xref: /openbmc/linux/sound/soc/codecs/sta32x.c (revision c8af4658)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Codec driver for ST STA32x 2.1-channel high-efficiency digital audio system
4  *
5  * Copyright: 2011 Raumfeld GmbH
6  * Author: Johannes Stezenbach <js@sig21.net>
7  *
8  * based on code from:
9  *	Wolfson Microelectronics PLC.
10  *	  Mark Brown <broonie@opensource.wolfsonmicro.com>
11  *	Freescale Semiconductor, Inc.
12  *	  Timur Tabi <timur@freescale.com>
13  */
14 
15 #define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
16 
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/init.h>
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/pm.h>
23 #include <linux/i2c.h>
24 #include <linux/of_device.h>
25 #include <linux/of_gpio.h>
26 #include <linux/regmap.h>
27 #include <linux/regulator/consumer.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/slab.h>
30 #include <linux/workqueue.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/soc.h>
35 #include <sound/soc-dapm.h>
36 #include <sound/initval.h>
37 #include <sound/tlv.h>
38 
39 #include <sound/sta32x.h>
40 #include "sta32x.h"
41 
42 #define STA32X_RATES (SNDRV_PCM_RATE_32000 | \
43 		      SNDRV_PCM_RATE_44100 | \
44 		      SNDRV_PCM_RATE_48000 | \
45 		      SNDRV_PCM_RATE_88200 | \
46 		      SNDRV_PCM_RATE_96000 | \
47 		      SNDRV_PCM_RATE_176400 | \
48 		      SNDRV_PCM_RATE_192000)
49 
50 #define STA32X_FORMATS \
51 	(SNDRV_PCM_FMTBIT_S16_LE  | SNDRV_PCM_FMTBIT_S18_3LE | \
52 	 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_3LE | \
53 	 SNDRV_PCM_FMTBIT_S24_LE  | SNDRV_PCM_FMTBIT_S32_LE)
54 
55 /* Power-up register defaults */
56 static const struct reg_default sta32x_regs[] = {
57 	{  0x0, 0x63 },
58 	{  0x1, 0x80 },
59 	{  0x2, 0xc2 },
60 	{  0x3, 0x40 },
61 	{  0x4, 0xc2 },
62 	{  0x5, 0x5c },
63 	{  0x6, 0x10 },
64 	{  0x7, 0xff },
65 	{  0x8, 0x60 },
66 	{  0x9, 0x60 },
67 	{  0xa, 0x60 },
68 	{  0xb, 0x80 },
69 	{  0xc, 0x00 },
70 	{  0xd, 0x00 },
71 	{  0xe, 0x00 },
72 	{  0xf, 0x40 },
73 	{ 0x10, 0x80 },
74 	{ 0x11, 0x77 },
75 	{ 0x12, 0x6a },
76 	{ 0x13, 0x69 },
77 	{ 0x14, 0x6a },
78 	{ 0x15, 0x69 },
79 	{ 0x16, 0x00 },
80 	{ 0x17, 0x00 },
81 	{ 0x18, 0x00 },
82 	{ 0x19, 0x00 },
83 	{ 0x1a, 0x00 },
84 	{ 0x1b, 0x00 },
85 	{ 0x1c, 0x00 },
86 	{ 0x1d, 0x00 },
87 	{ 0x1e, 0x00 },
88 	{ 0x1f, 0x00 },
89 	{ 0x20, 0x00 },
90 	{ 0x21, 0x00 },
91 	{ 0x22, 0x00 },
92 	{ 0x23, 0x00 },
93 	{ 0x24, 0x00 },
94 	{ 0x25, 0x00 },
95 	{ 0x26, 0x00 },
96 	{ 0x27, 0x2d },
97 	{ 0x28, 0xc0 },
98 	{ 0x2b, 0x00 },
99 	{ 0x2c, 0x0c },
100 };
101 
102 static const struct regmap_range sta32x_write_regs_range[] = {
103 	regmap_reg_range(STA32X_CONFA,  STA32X_FDRC2),
104 };
105 
106 static const struct regmap_range sta32x_read_regs_range[] = {
107 	regmap_reg_range(STA32X_CONFA,  STA32X_FDRC2),
108 };
109 
110 static const struct regmap_range sta32x_volatile_regs_range[] = {
111 	regmap_reg_range(STA32X_CFADDR2, STA32X_CFUD),
112 };
113 
114 static const struct regmap_access_table sta32x_write_regs = {
115 	.yes_ranges =	sta32x_write_regs_range,
116 	.n_yes_ranges =	ARRAY_SIZE(sta32x_write_regs_range),
117 };
118 
119 static const struct regmap_access_table sta32x_read_regs = {
120 	.yes_ranges =	sta32x_read_regs_range,
121 	.n_yes_ranges =	ARRAY_SIZE(sta32x_read_regs_range),
122 };
123 
124 static const struct regmap_access_table sta32x_volatile_regs = {
125 	.yes_ranges =	sta32x_volatile_regs_range,
126 	.n_yes_ranges =	ARRAY_SIZE(sta32x_volatile_regs_range),
127 };
128 
129 /* regulator power supply names */
130 static const char *sta32x_supply_names[] = {
131 	"Vdda",	/* analog supply, 3.3VV */
132 	"Vdd3",	/* digital supply, 3.3V */
133 	"Vcc"	/* power amp spply, 10V - 36V */
134 };
135 
136 /* codec private data */
137 struct sta32x_priv {
138 	struct regmap *regmap;
139 	struct clk *xti_clk;
140 	struct regulator_bulk_data supplies[ARRAY_SIZE(sta32x_supply_names)];
141 	struct snd_soc_component *component;
142 	struct sta32x_platform_data *pdata;
143 
144 	unsigned int mclk;
145 	unsigned int format;
146 
147 	u32 coef_shadow[STA32X_COEF_COUNT];
148 	struct delayed_work watchdog_work;
149 	int shutdown;
150 	struct gpio_desc *gpiod_nreset;
151 	struct mutex coeff_lock;
152 };
153 
154 static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12700, 50, 1);
155 static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
156 static const DECLARE_TLV_DB_SCALE(tone_tlv, -120, 200, 0);
157 
158 static const char *sta32x_drc_ac[] = {
159 	"Anti-Clipping", "Dynamic Range Compression" };
160 static const char *sta32x_auto_eq_mode[] = {
161 	"User", "Preset", "Loudness" };
162 static const char *sta32x_auto_gc_mode[] = {
163 	"User", "AC no clipping", "AC limited clipping (10%)",
164 	"DRC nighttime listening mode" };
165 static const char *sta32x_auto_xo_mode[] = {
166 	"User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz", "200Hz",
167 	"220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz", "340Hz", "360Hz" };
168 static const char *sta32x_preset_eq_mode[] = {
169 	"Flat", "Rock", "Soft Rock", "Jazz", "Classical", "Dance", "Pop", "Soft",
170 	"Hard", "Party", "Vocal", "Hip-Hop", "Dialog", "Bass-boost #1",
171 	"Bass-boost #2", "Bass-boost #3", "Loudness 1", "Loudness 2",
172 	"Loudness 3", "Loudness 4", "Loudness 5", "Loudness 6", "Loudness 7",
173 	"Loudness 8", "Loudness 9", "Loudness 10", "Loudness 11", "Loudness 12",
174 	"Loudness 13", "Loudness 14", "Loudness 15", "Loudness 16" };
175 static const char *sta32x_limiter_select[] = {
176 	"Limiter Disabled", "Limiter #1", "Limiter #2" };
177 static const char *sta32x_limiter_attack_rate[] = {
178 	"3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
179 	"0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
180 	"0.0645", "0.0564", "0.0501", "0.0451" };
181 static const char *sta32x_limiter_release_rate[] = {
182 	"0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
183 	"0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
184 	"0.0134", "0.0117", "0.0110", "0.0104" };
185 static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_attack_tlv,
186 	0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
187 	8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
188 );
189 
190 static DECLARE_TLV_DB_RANGE(sta32x_limiter_ac_release_tlv,
191 	0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
192 	1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
193 	2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
194 	3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
195 	8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
196 );
197 
198 static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_attack_tlv,
199 	0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
200 	8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
201 	14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
202 );
203 
204 static DECLARE_TLV_DB_RANGE(sta32x_limiter_drc_release_tlv,
205 	0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
206 	1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
207 	3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
208 	5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
209 	13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
210 );
211 
212 static SOC_ENUM_SINGLE_DECL(sta32x_drc_ac_enum,
213 			    STA32X_CONFD, STA32X_CONFD_DRC_SHIFT,
214 			    sta32x_drc_ac);
215 static SOC_ENUM_SINGLE_DECL(sta32x_auto_eq_enum,
216 			    STA32X_AUTO1, STA32X_AUTO1_AMEQ_SHIFT,
217 			    sta32x_auto_eq_mode);
218 static SOC_ENUM_SINGLE_DECL(sta32x_auto_gc_enum,
219 			    STA32X_AUTO1, STA32X_AUTO1_AMGC_SHIFT,
220 			    sta32x_auto_gc_mode);
221 static SOC_ENUM_SINGLE_DECL(sta32x_auto_xo_enum,
222 			    STA32X_AUTO2, STA32X_AUTO2_XO_SHIFT,
223 			    sta32x_auto_xo_mode);
224 static SOC_ENUM_SINGLE_DECL(sta32x_preset_eq_enum,
225 			    STA32X_AUTO3, STA32X_AUTO3_PEQ_SHIFT,
226 			    sta32x_preset_eq_mode);
227 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch1_enum,
228 			    STA32X_C1CFG, STA32X_CxCFG_LS_SHIFT,
229 			    sta32x_limiter_select);
230 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch2_enum,
231 			    STA32X_C2CFG, STA32X_CxCFG_LS_SHIFT,
232 			    sta32x_limiter_select);
233 static SOC_ENUM_SINGLE_DECL(sta32x_limiter_ch3_enum,
234 			    STA32X_C3CFG, STA32X_CxCFG_LS_SHIFT,
235 			    sta32x_limiter_select);
236 static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_attack_rate_enum,
237 			    STA32X_L1AR, STA32X_LxA_SHIFT,
238 			    sta32x_limiter_attack_rate);
239 static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_attack_rate_enum,
240 			    STA32X_L2AR, STA32X_LxA_SHIFT,
241 			    sta32x_limiter_attack_rate);
242 static SOC_ENUM_SINGLE_DECL(sta32x_limiter1_release_rate_enum,
243 			    STA32X_L1AR, STA32X_LxR_SHIFT,
244 			    sta32x_limiter_release_rate);
245 static SOC_ENUM_SINGLE_DECL(sta32x_limiter2_release_rate_enum,
246 			    STA32X_L2AR, STA32X_LxR_SHIFT,
247 			    sta32x_limiter_release_rate);
248 
249 /* byte array controls for setting biquad, mixer, scaling coefficients;
250  * for biquads all five coefficients need to be set in one go,
251  * mixer and pre/postscale coefs can be set individually;
252  * each coef is 24bit, the bytes are ordered in the same way
253  * as given in the STA32x data sheet (big endian; b1, b2, a1, a2, b0)
254  */
255 
sta32x_coefficient_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)256 static int sta32x_coefficient_info(struct snd_kcontrol *kcontrol,
257 				   struct snd_ctl_elem_info *uinfo)
258 {
259 	int numcoef = kcontrol->private_value >> 16;
260 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
261 	uinfo->count = 3 * numcoef;
262 	return 0;
263 }
264 
sta32x_coefficient_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)265 static int sta32x_coefficient_get(struct snd_kcontrol *kcontrol,
266 				  struct snd_ctl_elem_value *ucontrol)
267 {
268 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
269 	struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
270 	int numcoef = kcontrol->private_value >> 16;
271 	int index = kcontrol->private_value & 0xffff;
272 	unsigned int cfud, val;
273 	int i, ret = 0;
274 
275 	mutex_lock(&sta32x->coeff_lock);
276 
277 	/* preserve reserved bits in STA32X_CFUD */
278 	regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
279 	cfud &= 0xf0;
280 	/*
281 	 * chip documentation does not say if the bits are self clearing,
282 	 * so do it explicitly
283 	 */
284 	regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
285 
286 	regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
287 	if (numcoef == 1) {
288 		regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x04);
289 	} else if (numcoef == 5) {
290 		regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x08);
291 	} else {
292 		ret = -EINVAL;
293 		goto exit_unlock;
294 	}
295 
296 	for (i = 0; i < 3 * numcoef; i++) {
297 		regmap_read(sta32x->regmap, STA32X_B1CF1 + i, &val);
298 		ucontrol->value.bytes.data[i] = val;
299 	}
300 
301 exit_unlock:
302 	mutex_unlock(&sta32x->coeff_lock);
303 
304 	return ret;
305 }
306 
sta32x_coefficient_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)307 static int sta32x_coefficient_put(struct snd_kcontrol *kcontrol,
308 				  struct snd_ctl_elem_value *ucontrol)
309 {
310 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
311 	struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
312 	int numcoef = kcontrol->private_value >> 16;
313 	int index = kcontrol->private_value & 0xffff;
314 	unsigned int cfud;
315 	int i;
316 
317 	/* preserve reserved bits in STA32X_CFUD */
318 	regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
319 	cfud &= 0xf0;
320 	/*
321 	 * chip documentation does not say if the bits are self clearing,
322 	 * so do it explicitly
323 	 */
324 	regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
325 
326 	regmap_write(sta32x->regmap, STA32X_CFADDR2, index);
327 	for (i = 0; i < numcoef && (index + i < STA32X_COEF_COUNT); i++)
328 		sta32x->coef_shadow[index + i] =
329 			  (ucontrol->value.bytes.data[3 * i] << 16)
330 			| (ucontrol->value.bytes.data[3 * i + 1] << 8)
331 			| (ucontrol->value.bytes.data[3 * i + 2]);
332 	for (i = 0; i < 3 * numcoef; i++)
333 		regmap_write(sta32x->regmap, STA32X_B1CF1 + i,
334 			     ucontrol->value.bytes.data[i]);
335 	if (numcoef == 1)
336 		regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
337 	else if (numcoef == 5)
338 		regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x02);
339 	else
340 		return -EINVAL;
341 
342 	return 0;
343 }
344 
sta32x_sync_coef_shadow(struct snd_soc_component * component)345 static int sta32x_sync_coef_shadow(struct snd_soc_component *component)
346 {
347 	struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
348 	unsigned int cfud;
349 	int i;
350 
351 	/* preserve reserved bits in STA32X_CFUD */
352 	regmap_read(sta32x->regmap, STA32X_CFUD, &cfud);
353 	cfud &= 0xf0;
354 
355 	for (i = 0; i < STA32X_COEF_COUNT; i++) {
356 		regmap_write(sta32x->regmap, STA32X_CFADDR2, i);
357 		regmap_write(sta32x->regmap, STA32X_B1CF1,
358 			     (sta32x->coef_shadow[i] >> 16) & 0xff);
359 		regmap_write(sta32x->regmap, STA32X_B1CF2,
360 			     (sta32x->coef_shadow[i] >> 8) & 0xff);
361 		regmap_write(sta32x->regmap, STA32X_B1CF3,
362 			     (sta32x->coef_shadow[i]) & 0xff);
363 		/*
364 		 * chip documentation does not say if the bits are
365 		 * self-clearing, so do it explicitly
366 		 */
367 		regmap_write(sta32x->regmap, STA32X_CFUD, cfud);
368 		regmap_write(sta32x->regmap, STA32X_CFUD, cfud | 0x01);
369 	}
370 	return 0;
371 }
372 
sta32x_cache_sync(struct snd_soc_component * component)373 static int sta32x_cache_sync(struct snd_soc_component *component)
374 {
375 	struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
376 	unsigned int mute;
377 	int rc;
378 
379 	/* mute during register sync */
380 	regmap_read(sta32x->regmap, STA32X_MMUTE, &mute);
381 	regmap_write(sta32x->regmap, STA32X_MMUTE, mute | STA32X_MMUTE_MMUTE);
382 	sta32x_sync_coef_shadow(component);
383 	rc = regcache_sync(sta32x->regmap);
384 	regmap_write(sta32x->regmap, STA32X_MMUTE, mute);
385 	return rc;
386 }
387 
388 /* work around ESD issue where sta32x resets and loses all configuration */
sta32x_watchdog(struct work_struct * work)389 static void sta32x_watchdog(struct work_struct *work)
390 {
391 	struct sta32x_priv *sta32x = container_of(work, struct sta32x_priv,
392 						  watchdog_work.work);
393 	struct snd_soc_component *component = sta32x->component;
394 	unsigned int confa, confa_cached;
395 
396 	/* check if sta32x has reset itself */
397 	confa_cached = snd_soc_component_read(component, STA32X_CONFA);
398 	regcache_cache_bypass(sta32x->regmap, true);
399 	confa = snd_soc_component_read(component, STA32X_CONFA);
400 	regcache_cache_bypass(sta32x->regmap, false);
401 	if (confa != confa_cached) {
402 		regcache_mark_dirty(sta32x->regmap);
403 		sta32x_cache_sync(component);
404 	}
405 
406 	if (!sta32x->shutdown)
407 		queue_delayed_work(system_power_efficient_wq,
408 				   &sta32x->watchdog_work,
409 				   round_jiffies_relative(HZ));
410 }
411 
sta32x_watchdog_start(struct sta32x_priv * sta32x)412 static void sta32x_watchdog_start(struct sta32x_priv *sta32x)
413 {
414 	if (sta32x->pdata->needs_esd_watchdog) {
415 		sta32x->shutdown = 0;
416 		queue_delayed_work(system_power_efficient_wq,
417 				   &sta32x->watchdog_work,
418 				   round_jiffies_relative(HZ));
419 	}
420 }
421 
sta32x_watchdog_stop(struct sta32x_priv * sta32x)422 static void sta32x_watchdog_stop(struct sta32x_priv *sta32x)
423 {
424 	if (sta32x->pdata->needs_esd_watchdog) {
425 		sta32x->shutdown = 1;
426 		cancel_delayed_work_sync(&sta32x->watchdog_work);
427 	}
428 }
429 
430 #define SINGLE_COEF(xname, index) \
431 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
432 	.info = sta32x_coefficient_info, \
433 	.get = sta32x_coefficient_get,\
434 	.put = sta32x_coefficient_put, \
435 	.private_value = index | (1 << 16) }
436 
437 #define BIQUAD_COEFS(xname, index) \
438 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
439 	.info = sta32x_coefficient_info, \
440 	.get = sta32x_coefficient_get,\
441 	.put = sta32x_coefficient_put, \
442 	.private_value = index | (5 << 16) }
443 
444 static const struct snd_kcontrol_new sta32x_snd_controls[] = {
445 SOC_SINGLE_TLV("Master Volume", STA32X_MVOL, 0, 0xff, 1, mvol_tlv),
446 SOC_SINGLE("Master Switch", STA32X_MMUTE, 0, 1, 1),
447 SOC_SINGLE("Ch1 Switch", STA32X_MMUTE, 1, 1, 1),
448 SOC_SINGLE("Ch2 Switch", STA32X_MMUTE, 2, 1, 1),
449 SOC_SINGLE("Ch3 Switch", STA32X_MMUTE, 3, 1, 1),
450 SOC_SINGLE_TLV("Ch1 Volume", STA32X_C1VOL, 0, 0xff, 1, chvol_tlv),
451 SOC_SINGLE_TLV("Ch2 Volume", STA32X_C2VOL, 0, 0xff, 1, chvol_tlv),
452 SOC_SINGLE_TLV("Ch3 Volume", STA32X_C3VOL, 0, 0xff, 1, chvol_tlv),
453 SOC_SINGLE("De-emphasis Filter Switch", STA32X_CONFD, STA32X_CONFD_DEMP_SHIFT, 1, 0),
454 SOC_ENUM("Compressor/Limiter Switch", sta32x_drc_ac_enum),
455 SOC_SINGLE("Miami Mode Switch", STA32X_CONFD, STA32X_CONFD_MME_SHIFT, 1, 0),
456 SOC_SINGLE("Zero Cross Switch", STA32X_CONFE, STA32X_CONFE_ZCE_SHIFT, 1, 0),
457 SOC_SINGLE("Soft Ramp Switch", STA32X_CONFE, STA32X_CONFE_SVE_SHIFT, 1, 0),
458 SOC_SINGLE("Auto-Mute Switch", STA32X_CONFF, STA32X_CONFF_IDE_SHIFT, 1, 0),
459 SOC_ENUM("Automode EQ", sta32x_auto_eq_enum),
460 SOC_ENUM("Automode GC", sta32x_auto_gc_enum),
461 SOC_ENUM("Automode XO", sta32x_auto_xo_enum),
462 SOC_ENUM("Preset EQ", sta32x_preset_eq_enum),
463 SOC_SINGLE("Ch1 Tone Control Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
464 SOC_SINGLE("Ch2 Tone Control Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_TCB_SHIFT, 1, 0),
465 SOC_SINGLE("Ch1 EQ Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
466 SOC_SINGLE("Ch2 EQ Bypass Switch", STA32X_C2CFG, STA32X_CxCFG_EQBP_SHIFT, 1, 0),
467 SOC_SINGLE("Ch1 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
468 SOC_SINGLE("Ch2 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
469 SOC_SINGLE("Ch3 Master Volume Bypass Switch", STA32X_C1CFG, STA32X_CxCFG_VBP_SHIFT, 1, 0),
470 SOC_ENUM("Ch1 Limiter Select", sta32x_limiter_ch1_enum),
471 SOC_ENUM("Ch2 Limiter Select", sta32x_limiter_ch2_enum),
472 SOC_ENUM("Ch3 Limiter Select", sta32x_limiter_ch3_enum),
473 SOC_SINGLE_TLV("Bass Tone Control", STA32X_TONE, STA32X_TONE_BTC_SHIFT, 15, 0, tone_tlv),
474 SOC_SINGLE_TLV("Treble Tone Control", STA32X_TONE, STA32X_TONE_TTC_SHIFT, 15, 0, tone_tlv),
475 SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta32x_limiter1_attack_rate_enum),
476 SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta32x_limiter2_attack_rate_enum),
477 SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta32x_limiter1_release_rate_enum),
478 SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta32x_limiter2_release_rate_enum),
479 
480 /* depending on mode, the attack/release thresholds have
481  * two different enum definitions; provide both
482  */
483 SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
484 	       16, 0, sta32x_limiter_ac_attack_tlv),
485 SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
486 	       16, 0, sta32x_limiter_ac_attack_tlv),
487 SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
488 	       16, 0, sta32x_limiter_ac_release_tlv),
489 SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
490 	       16, 0, sta32x_limiter_ac_release_tlv),
491 SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxA_SHIFT,
492 	       16, 0, sta32x_limiter_drc_attack_tlv),
493 SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxA_SHIFT,
494 	       16, 0, sta32x_limiter_drc_attack_tlv),
495 SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)", STA32X_L1ATRT, STA32X_LxR_SHIFT,
496 	       16, 0, sta32x_limiter_drc_release_tlv),
497 SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)", STA32X_L2ATRT, STA32X_LxR_SHIFT,
498 	       16, 0, sta32x_limiter_drc_release_tlv),
499 
500 BIQUAD_COEFS("Ch1 - Biquad 1", 0),
501 BIQUAD_COEFS("Ch1 - Biquad 2", 5),
502 BIQUAD_COEFS("Ch1 - Biquad 3", 10),
503 BIQUAD_COEFS("Ch1 - Biquad 4", 15),
504 BIQUAD_COEFS("Ch2 - Biquad 1", 20),
505 BIQUAD_COEFS("Ch2 - Biquad 2", 25),
506 BIQUAD_COEFS("Ch2 - Biquad 3", 30),
507 BIQUAD_COEFS("Ch2 - Biquad 4", 35),
508 BIQUAD_COEFS("High-pass", 40),
509 BIQUAD_COEFS("Low-pass", 45),
510 SINGLE_COEF("Ch1 - Prescale", 50),
511 SINGLE_COEF("Ch2 - Prescale", 51),
512 SINGLE_COEF("Ch1 - Postscale", 52),
513 SINGLE_COEF("Ch2 - Postscale", 53),
514 SINGLE_COEF("Ch3 - Postscale", 54),
515 SINGLE_COEF("Thermal warning - Postscale", 55),
516 SINGLE_COEF("Ch1 - Mix 1", 56),
517 SINGLE_COEF("Ch1 - Mix 2", 57),
518 SINGLE_COEF("Ch2 - Mix 1", 58),
519 SINGLE_COEF("Ch2 - Mix 2", 59),
520 SINGLE_COEF("Ch3 - Mix 1", 60),
521 SINGLE_COEF("Ch3 - Mix 2", 61),
522 };
523 
524 static const struct snd_soc_dapm_widget sta32x_dapm_widgets[] = {
525 SND_SOC_DAPM_DAC("DAC", "Playback", SND_SOC_NOPM, 0, 0),
526 SND_SOC_DAPM_OUTPUT("LEFT"),
527 SND_SOC_DAPM_OUTPUT("RIGHT"),
528 SND_SOC_DAPM_OUTPUT("SUB"),
529 };
530 
531 static const struct snd_soc_dapm_route sta32x_dapm_routes[] = {
532 	{ "LEFT", NULL, "DAC" },
533 	{ "RIGHT", NULL, "DAC" },
534 	{ "SUB", NULL, "DAC" },
535 };
536 
537 /* MCLK interpolation ratio per fs */
538 static struct {
539 	int fs;
540 	int ir;
541 } interpolation_ratios[] = {
542 	{ 32000, 0 },
543 	{ 44100, 0 },
544 	{ 48000, 0 },
545 	{ 88200, 1 },
546 	{ 96000, 1 },
547 	{ 176400, 2 },
548 	{ 192000, 2 },
549 };
550 
551 /* MCLK to fs clock ratios */
552 static int mcs_ratio_table[3][7] = {
553 	{ 768, 512, 384, 256, 128, 576, 0 },
554 	{ 384, 256, 192, 128,  64,   0 },
555 	{ 384, 256, 192, 128,  64,   0 },
556 };
557 
558 /**
559  * sta32x_set_dai_sysclk - configure MCLK
560  * @codec_dai: the codec DAI
561  * @clk_id: the clock ID (ignored)
562  * @freq: the MCLK input frequency
563  * @dir: the clock direction (ignored)
564  *
565  * The value of MCLK is used to determine which sample rates are supported
566  * by the STA32X, based on the mclk_ratios table.
567  *
568  * This function must be called by the machine driver's 'startup' function,
569  * otherwise the list of supported sample rates will not be available in
570  * time for ALSA.
571  *
572  * For setups with variable MCLKs, pass 0 as 'freq' argument. This will cause
573  * theoretically possible sample rates to be enabled. Call it again with a
574  * proper value set one the external clock is set (most probably you would do
575  * that from a machine's driver 'hw_param' hook.
576  */
sta32x_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)577 static int sta32x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
578 		int clk_id, unsigned int freq, int dir)
579 {
580 	struct snd_soc_component *component = codec_dai->component;
581 	struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
582 
583 	dev_dbg(component->dev, "mclk=%u\n", freq);
584 	sta32x->mclk = freq;
585 
586 	return 0;
587 }
588 
589 /**
590  * sta32x_set_dai_fmt - configure the codec for the selected audio format
591  * @codec_dai: the codec DAI
592  * @fmt: a SND_SOC_DAIFMT_x value indicating the data format
593  *
594  * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
595  * codec accordingly.
596  */
sta32x_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)597 static int sta32x_set_dai_fmt(struct snd_soc_dai *codec_dai,
598 			      unsigned int fmt)
599 {
600 	struct snd_soc_component *component = codec_dai->component;
601 	struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
602 	u8 confb = 0;
603 
604 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
605 	case SND_SOC_DAIFMT_CBC_CFC:
606 		break;
607 	default:
608 		return -EINVAL;
609 	}
610 
611 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
612 	case SND_SOC_DAIFMT_I2S:
613 	case SND_SOC_DAIFMT_RIGHT_J:
614 	case SND_SOC_DAIFMT_LEFT_J:
615 		sta32x->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
616 		break;
617 	default:
618 		return -EINVAL;
619 	}
620 
621 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
622 	case SND_SOC_DAIFMT_NB_NF:
623 		confb |= STA32X_CONFB_C2IM;
624 		break;
625 	case SND_SOC_DAIFMT_NB_IF:
626 		confb |= STA32X_CONFB_C1IM;
627 		break;
628 	default:
629 		return -EINVAL;
630 	}
631 
632 	return regmap_update_bits(sta32x->regmap, STA32X_CONFB,
633 				  STA32X_CONFB_C1IM | STA32X_CONFB_C2IM, confb);
634 }
635 
636 /**
637  * sta32x_hw_params - program the STA32X with the given hardware parameters.
638  * @substream: the audio stream
639  * @params: the hardware parameters to set
640  * @dai: the SOC DAI (ignored)
641  *
642  * This function programs the hardware with the values provided.
643  * Specifically, the sample rate and the data format.
644  */
sta32x_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)645 static int sta32x_hw_params(struct snd_pcm_substream *substream,
646 			    struct snd_pcm_hw_params *params,
647 			    struct snd_soc_dai *dai)
648 {
649 	struct snd_soc_component *component = dai->component;
650 	struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
651 	int i, mcs = -EINVAL, ir = -EINVAL;
652 	unsigned int confa, confb;
653 	unsigned int rate, ratio;
654 	int ret;
655 
656 	if (!sta32x->mclk) {
657 		dev_err(component->dev,
658 			"sta32x->mclk is unset. Unable to determine ratio\n");
659 		return -EIO;
660 	}
661 
662 	rate = params_rate(params);
663 	ratio = sta32x->mclk / rate;
664 	dev_dbg(component->dev, "rate: %u, ratio: %u\n", rate, ratio);
665 
666 	for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
667 		if (interpolation_ratios[i].fs == rate) {
668 			ir = interpolation_ratios[i].ir;
669 			break;
670 		}
671 	}
672 
673 	if (ir < 0) {
674 		dev_err(component->dev, "Unsupported samplerate: %u\n", rate);
675 		return -EINVAL;
676 	}
677 
678 	for (i = 0; i < 6; i++) {
679 		if (mcs_ratio_table[ir][i] == ratio) {
680 			mcs = i;
681 			break;
682 		}
683 	}
684 
685 	if (mcs < 0) {
686 		dev_err(component->dev, "Unresolvable ratio: %u\n", ratio);
687 		return -EINVAL;
688 	}
689 
690 	confa = (ir << STA32X_CONFA_IR_SHIFT) |
691 		(mcs << STA32X_CONFA_MCS_SHIFT);
692 	confb = 0;
693 
694 	switch (params_width(params)) {
695 	case 24:
696 		dev_dbg(component->dev, "24bit\n");
697 		fallthrough;
698 	case 32:
699 		dev_dbg(component->dev, "24bit or 32bit\n");
700 		switch (sta32x->format) {
701 		case SND_SOC_DAIFMT_I2S:
702 			confb |= 0x0;
703 			break;
704 		case SND_SOC_DAIFMT_LEFT_J:
705 			confb |= 0x1;
706 			break;
707 		case SND_SOC_DAIFMT_RIGHT_J:
708 			confb |= 0x2;
709 			break;
710 		}
711 
712 		break;
713 	case 20:
714 		dev_dbg(component->dev, "20bit\n");
715 		switch (sta32x->format) {
716 		case SND_SOC_DAIFMT_I2S:
717 			confb |= 0x4;
718 			break;
719 		case SND_SOC_DAIFMT_LEFT_J:
720 			confb |= 0x5;
721 			break;
722 		case SND_SOC_DAIFMT_RIGHT_J:
723 			confb |= 0x6;
724 			break;
725 		}
726 
727 		break;
728 	case 18:
729 		dev_dbg(component->dev, "18bit\n");
730 		switch (sta32x->format) {
731 		case SND_SOC_DAIFMT_I2S:
732 			confb |= 0x8;
733 			break;
734 		case SND_SOC_DAIFMT_LEFT_J:
735 			confb |= 0x9;
736 			break;
737 		case SND_SOC_DAIFMT_RIGHT_J:
738 			confb |= 0xa;
739 			break;
740 		}
741 
742 		break;
743 	case 16:
744 		dev_dbg(component->dev, "16bit\n");
745 		switch (sta32x->format) {
746 		case SND_SOC_DAIFMT_I2S:
747 			confb |= 0x0;
748 			break;
749 		case SND_SOC_DAIFMT_LEFT_J:
750 			confb |= 0xd;
751 			break;
752 		case SND_SOC_DAIFMT_RIGHT_J:
753 			confb |= 0xe;
754 			break;
755 		}
756 
757 		break;
758 	default:
759 		return -EINVAL;
760 	}
761 
762 	ret = regmap_update_bits(sta32x->regmap, STA32X_CONFA,
763 				 STA32X_CONFA_MCS_MASK | STA32X_CONFA_IR_MASK,
764 				 confa);
765 	if (ret < 0)
766 		return ret;
767 
768 	ret = regmap_update_bits(sta32x->regmap, STA32X_CONFB,
769 				 STA32X_CONFB_SAI_MASK | STA32X_CONFB_SAIFB,
770 				 confb);
771 	if (ret < 0)
772 		return ret;
773 
774 	return 0;
775 }
776 
sta32x_startup_sequence(struct sta32x_priv * sta32x)777 static int sta32x_startup_sequence(struct sta32x_priv *sta32x)
778 {
779 	if (sta32x->gpiod_nreset) {
780 		gpiod_set_value(sta32x->gpiod_nreset, 0);
781 		mdelay(1);
782 		gpiod_set_value(sta32x->gpiod_nreset, 1);
783 		mdelay(1);
784 	}
785 
786 	return 0;
787 }
788 
789 /**
790  * sta32x_set_bias_level - DAPM callback
791  * @component: the component device
792  * @level: DAPM power level
793  *
794  * This is called by ALSA to put the component into low power mode
795  * or to wake it up.  If the component is powered off completely
796  * all registers must be restored after power on.
797  */
sta32x_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)798 static int sta32x_set_bias_level(struct snd_soc_component *component,
799 				 enum snd_soc_bias_level level)
800 {
801 	int ret;
802 	struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
803 
804 	dev_dbg(component->dev, "level = %d\n", level);
805 	switch (level) {
806 	case SND_SOC_BIAS_ON:
807 		break;
808 
809 	case SND_SOC_BIAS_PREPARE:
810 		/* Full power on */
811 		regmap_update_bits(sta32x->regmap, STA32X_CONFF,
812 				    STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
813 				    STA32X_CONFF_PWDN | STA32X_CONFF_EAPD);
814 		break;
815 
816 	case SND_SOC_BIAS_STANDBY:
817 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
818 			ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
819 						    sta32x->supplies);
820 			if (ret != 0) {
821 				dev_err(component->dev,
822 					"Failed to enable supplies: %d\n", ret);
823 				return ret;
824 			}
825 
826 			sta32x_startup_sequence(sta32x);
827 			sta32x_cache_sync(component);
828 			sta32x_watchdog_start(sta32x);
829 		}
830 
831 		/* Power down */
832 		regmap_update_bits(sta32x->regmap, STA32X_CONFF,
833 				   STA32X_CONFF_PWDN | STA32X_CONFF_EAPD,
834 				   0);
835 
836 		break;
837 
838 	case SND_SOC_BIAS_OFF:
839 		/* The chip runs through the power down sequence for us. */
840 		regmap_update_bits(sta32x->regmap, STA32X_CONFF,
841 				   STA32X_CONFF_PWDN | STA32X_CONFF_EAPD, 0);
842 		msleep(300);
843 		sta32x_watchdog_stop(sta32x);
844 
845 		gpiod_set_value(sta32x->gpiod_nreset, 0);
846 
847 		regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies),
848 				       sta32x->supplies);
849 		break;
850 	}
851 	return 0;
852 }
853 
854 static const struct snd_soc_dai_ops sta32x_dai_ops = {
855 	.hw_params	= sta32x_hw_params,
856 	.set_sysclk	= sta32x_set_dai_sysclk,
857 	.set_fmt	= sta32x_set_dai_fmt,
858 };
859 
860 static struct snd_soc_dai_driver sta32x_dai = {
861 	.name = "sta32x-hifi",
862 	.playback = {
863 		.stream_name = "Playback",
864 		.channels_min = 2,
865 		.channels_max = 2,
866 		.rates = STA32X_RATES,
867 		.formats = STA32X_FORMATS,
868 	},
869 	.ops = &sta32x_dai_ops,
870 };
871 
sta32x_probe(struct snd_soc_component * component)872 static int sta32x_probe(struct snd_soc_component *component)
873 {
874 	struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
875 	struct sta32x_platform_data *pdata = sta32x->pdata;
876 	int i, ret = 0, thermal = 0;
877 
878 	sta32x->component = component;
879 
880 	if (sta32x->xti_clk) {
881 		ret = clk_prepare_enable(sta32x->xti_clk);
882 		if (ret != 0) {
883 			dev_err(component->dev,
884 				"Failed to enable clock: %d\n", ret);
885 			return ret;
886 		}
887 	}
888 
889 	ret = regulator_bulk_enable(ARRAY_SIZE(sta32x->supplies),
890 				    sta32x->supplies);
891 	if (ret != 0) {
892 		dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
893 		goto err_clk_disable_unprepare;
894 	}
895 
896 	ret = sta32x_startup_sequence(sta32x);
897 	if (ret < 0) {
898 		dev_err(component->dev, "Failed to startup device\n");
899 		goto err_regulator_bulk_disable;
900 	}
901 
902 	/* CONFA */
903 	if (!pdata->thermal_warning_recovery)
904 		thermal |= STA32X_CONFA_TWAB;
905 	if (!pdata->thermal_warning_adjustment)
906 		thermal |= STA32X_CONFA_TWRB;
907 	if (!pdata->fault_detect_recovery)
908 		thermal |= STA32X_CONFA_FDRB;
909 	regmap_update_bits(sta32x->regmap, STA32X_CONFA,
910 			   STA32X_CONFA_TWAB | STA32X_CONFA_TWRB |
911 			   STA32X_CONFA_FDRB,
912 			   thermal);
913 
914 	/* CONFC */
915 	regmap_update_bits(sta32x->regmap, STA32X_CONFC,
916 			   STA32X_CONFC_CSZ_MASK,
917 			   pdata->drop_compensation_ns
918 				<< STA32X_CONFC_CSZ_SHIFT);
919 
920 	/* CONFE */
921 	regmap_update_bits(sta32x->regmap, STA32X_CONFE,
922 			   STA32X_CONFE_MPCV,
923 			   pdata->max_power_use_mpcc ?
924 				STA32X_CONFE_MPCV : 0);
925 	regmap_update_bits(sta32x->regmap, STA32X_CONFE,
926 			   STA32X_CONFE_MPC,
927 			   pdata->max_power_correction ?
928 				STA32X_CONFE_MPC : 0);
929 	regmap_update_bits(sta32x->regmap, STA32X_CONFE,
930 			   STA32X_CONFE_AME,
931 			   pdata->am_reduction_mode ?
932 				STA32X_CONFE_AME : 0);
933 	regmap_update_bits(sta32x->regmap, STA32X_CONFE,
934 			   STA32X_CONFE_PWMS,
935 			   pdata->odd_pwm_speed_mode ?
936 				STA32X_CONFE_PWMS : 0);
937 
938 	/*  CONFF */
939 	regmap_update_bits(sta32x->regmap, STA32X_CONFF,
940 			   STA32X_CONFF_IDE,
941 			   pdata->invalid_input_detect_mute ?
942 				STA32X_CONFF_IDE : 0);
943 
944 	/* select output configuration  */
945 	regmap_update_bits(sta32x->regmap, STA32X_CONFF,
946 			   STA32X_CONFF_OCFG_MASK,
947 			   pdata->output_conf
948 				<< STA32X_CONFF_OCFG_SHIFT);
949 
950 	/* channel to output mapping */
951 	regmap_update_bits(sta32x->regmap, STA32X_C1CFG,
952 			   STA32X_CxCFG_OM_MASK,
953 			   pdata->ch1_output_mapping
954 				<< STA32X_CxCFG_OM_SHIFT);
955 	regmap_update_bits(sta32x->regmap, STA32X_C2CFG,
956 			   STA32X_CxCFG_OM_MASK,
957 			   pdata->ch2_output_mapping
958 				<< STA32X_CxCFG_OM_SHIFT);
959 	regmap_update_bits(sta32x->regmap, STA32X_C3CFG,
960 			   STA32X_CxCFG_OM_MASK,
961 			   pdata->ch3_output_mapping
962 				<< STA32X_CxCFG_OM_SHIFT);
963 
964 	/* initialize coefficient shadow RAM with reset values */
965 	for (i = 4; i <= 49; i += 5)
966 		sta32x->coef_shadow[i] = 0x400000;
967 	for (i = 50; i <= 54; i++)
968 		sta32x->coef_shadow[i] = 0x7fffff;
969 	sta32x->coef_shadow[55] = 0x5a9df7;
970 	sta32x->coef_shadow[56] = 0x7fffff;
971 	sta32x->coef_shadow[59] = 0x7fffff;
972 	sta32x->coef_shadow[60] = 0x400000;
973 	sta32x->coef_shadow[61] = 0x400000;
974 
975 	if (sta32x->pdata->needs_esd_watchdog)
976 		INIT_DELAYED_WORK(&sta32x->watchdog_work, sta32x_watchdog);
977 
978 	snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
979 	/* Bias level configuration will have done an extra enable */
980 	regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
981 
982 	return 0;
983 
984 err_regulator_bulk_disable:
985 	regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
986 err_clk_disable_unprepare:
987 	if (sta32x->xti_clk)
988 		clk_disable_unprepare(sta32x->xti_clk);
989 	return ret;
990 }
991 
sta32x_remove(struct snd_soc_component * component)992 static void sta32x_remove(struct snd_soc_component *component)
993 {
994 	struct sta32x_priv *sta32x = snd_soc_component_get_drvdata(component);
995 
996 	sta32x_watchdog_stop(sta32x);
997 	regulator_bulk_disable(ARRAY_SIZE(sta32x->supplies), sta32x->supplies);
998 
999 	if (sta32x->xti_clk)
1000 		clk_disable_unprepare(sta32x->xti_clk);
1001 }
1002 
1003 static const struct snd_soc_component_driver sta32x_component = {
1004 	.probe			= sta32x_probe,
1005 	.remove			= sta32x_remove,
1006 	.set_bias_level		= sta32x_set_bias_level,
1007 	.controls		= sta32x_snd_controls,
1008 	.num_controls		= ARRAY_SIZE(sta32x_snd_controls),
1009 	.dapm_widgets		= sta32x_dapm_widgets,
1010 	.num_dapm_widgets	= ARRAY_SIZE(sta32x_dapm_widgets),
1011 	.dapm_routes		= sta32x_dapm_routes,
1012 	.num_dapm_routes	= ARRAY_SIZE(sta32x_dapm_routes),
1013 	.suspend_bias_off	= 1,
1014 	.idle_bias_on		= 1,
1015 	.use_pmdown_time	= 1,
1016 	.endianness		= 1,
1017 };
1018 
1019 static const struct regmap_config sta32x_regmap = {
1020 	.reg_bits =		8,
1021 	.val_bits =		8,
1022 	.max_register =		STA32X_FDRC2,
1023 	.reg_defaults =		sta32x_regs,
1024 	.num_reg_defaults =	ARRAY_SIZE(sta32x_regs),
1025 	.cache_type =		REGCACHE_MAPLE,
1026 	.wr_table =		&sta32x_write_regs,
1027 	.rd_table =		&sta32x_read_regs,
1028 	.volatile_table =	&sta32x_volatile_regs,
1029 };
1030 
1031 #ifdef CONFIG_OF
1032 static const struct of_device_id st32x_dt_ids[] = {
1033 	{ .compatible = "st,sta32x", },
1034 	{ }
1035 };
1036 MODULE_DEVICE_TABLE(of, st32x_dt_ids);
1037 
sta32x_probe_dt(struct device * dev,struct sta32x_priv * sta32x)1038 static int sta32x_probe_dt(struct device *dev, struct sta32x_priv *sta32x)
1039 {
1040 	struct device_node *np = dev->of_node;
1041 	struct sta32x_platform_data *pdata;
1042 	u16 tmp;
1043 
1044 	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1045 	if (!pdata)
1046 		return -ENOMEM;
1047 
1048 	of_property_read_u8(np, "st,output-conf",
1049 			    &pdata->output_conf);
1050 	of_property_read_u8(np, "st,ch1-output-mapping",
1051 			    &pdata->ch1_output_mapping);
1052 	of_property_read_u8(np, "st,ch2-output-mapping",
1053 			    &pdata->ch2_output_mapping);
1054 	of_property_read_u8(np, "st,ch3-output-mapping",
1055 			    &pdata->ch3_output_mapping);
1056 
1057 	pdata->fault_detect_recovery =
1058 		of_property_read_bool(np, "st,fault-detect-recovery");
1059 	pdata->thermal_warning_recovery =
1060 		of_property_read_bool(np, "st,thermal-warning-recovery");
1061 	pdata->thermal_warning_adjustment =
1062 		of_property_read_bool(np, "st,thermal-warning-adjustment");
1063 	pdata->needs_esd_watchdog =
1064 		of_property_read_bool(np, "st,needs_esd_watchdog");
1065 
1066 	tmp = 140;
1067 	of_property_read_u16(np, "st,drop-compensation-ns", &tmp);
1068 	pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20;
1069 
1070 	/* CONFE */
1071 	pdata->max_power_use_mpcc =
1072 		of_property_read_bool(np, "st,max-power-use-mpcc");
1073 	pdata->max_power_correction =
1074 		of_property_read_bool(np, "st,max-power-correction");
1075 	pdata->am_reduction_mode =
1076 		of_property_read_bool(np, "st,am-reduction-mode");
1077 	pdata->odd_pwm_speed_mode =
1078 		of_property_read_bool(np, "st,odd-pwm-speed-mode");
1079 
1080 	/* CONFF */
1081 	pdata->invalid_input_detect_mute =
1082 		of_property_read_bool(np, "st,invalid-input-detect-mute");
1083 
1084 	sta32x->pdata = pdata;
1085 
1086 	return 0;
1087 }
1088 #endif
1089 
sta32x_i2c_probe(struct i2c_client * i2c)1090 static int sta32x_i2c_probe(struct i2c_client *i2c)
1091 {
1092 	struct device *dev = &i2c->dev;
1093 	struct sta32x_priv *sta32x;
1094 	int ret, i;
1095 
1096 	sta32x = devm_kzalloc(&i2c->dev, sizeof(struct sta32x_priv),
1097 			      GFP_KERNEL);
1098 	if (!sta32x)
1099 		return -ENOMEM;
1100 
1101 	mutex_init(&sta32x->coeff_lock);
1102 	sta32x->pdata = dev_get_platdata(dev);
1103 
1104 #ifdef CONFIG_OF
1105 	if (dev->of_node) {
1106 		ret = sta32x_probe_dt(dev, sta32x);
1107 		if (ret < 0)
1108 			return ret;
1109 	}
1110 #endif
1111 
1112 	/* Clock */
1113 	sta32x->xti_clk = devm_clk_get(dev, "xti");
1114 	if (IS_ERR(sta32x->xti_clk)) {
1115 		ret = PTR_ERR(sta32x->xti_clk);
1116 
1117 		if (ret == -EPROBE_DEFER)
1118 			return ret;
1119 
1120 		sta32x->xti_clk = NULL;
1121 	}
1122 
1123 	/* GPIOs */
1124 	sta32x->gpiod_nreset = devm_gpiod_get_optional(dev, "reset",
1125 						       GPIOD_OUT_LOW);
1126 	if (IS_ERR(sta32x->gpiod_nreset))
1127 		return PTR_ERR(sta32x->gpiod_nreset);
1128 
1129 	/* regulators */
1130 	for (i = 0; i < ARRAY_SIZE(sta32x->supplies); i++)
1131 		sta32x->supplies[i].supply = sta32x_supply_names[i];
1132 
1133 	ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(sta32x->supplies),
1134 				      sta32x->supplies);
1135 	if (ret != 0) {
1136 		dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
1137 		return ret;
1138 	}
1139 
1140 	sta32x->regmap = devm_regmap_init_i2c(i2c, &sta32x_regmap);
1141 	if (IS_ERR(sta32x->regmap)) {
1142 		ret = PTR_ERR(sta32x->regmap);
1143 		dev_err(dev, "Failed to init regmap: %d\n", ret);
1144 		return ret;
1145 	}
1146 
1147 	i2c_set_clientdata(i2c, sta32x);
1148 
1149 	ret = devm_snd_soc_register_component(dev, &sta32x_component,
1150 					      &sta32x_dai, 1);
1151 	if (ret < 0)
1152 		dev_err(dev, "Failed to register component (%d)\n", ret);
1153 
1154 	return ret;
1155 }
1156 
1157 static const struct i2c_device_id sta32x_i2c_id[] = {
1158 	{ "sta326", 0 },
1159 	{ "sta328", 0 },
1160 	{ "sta329", 0 },
1161 	{ }
1162 };
1163 MODULE_DEVICE_TABLE(i2c, sta32x_i2c_id);
1164 
1165 static struct i2c_driver sta32x_i2c_driver = {
1166 	.driver = {
1167 		.name = "sta32x",
1168 		.of_match_table = of_match_ptr(st32x_dt_ids),
1169 	},
1170 	.probe = sta32x_i2c_probe,
1171 	.id_table = sta32x_i2c_id,
1172 };
1173 
1174 module_i2c_driver(sta32x_i2c_driver);
1175 
1176 MODULE_DESCRIPTION("ASoC STA32X driver");
1177 MODULE_AUTHOR("Johannes Stezenbach <js@sig21.net>");
1178 MODULE_LICENSE("GPL");
1179