xref: /openbmc/linux/sound/soc/codecs/sta350.c (revision 87256942)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Codec driver for ST STA350 2.1-channel high-efficiency digital audio system
4  *
5  * Copyright: 2014 Raumfeld GmbH
6  * Author: Sven Brandau <info@brandau.biz>
7  *
8  * based on code from:
9  *	Raumfeld GmbH
10  *	  Johannes Stezenbach <js@sig21.net>
11  *	Wolfson Microelectronics PLC.
12  *	  Mark Brown <broonie@opensource.wolfsonmicro.com>
13  *	Freescale Semiconductor, Inc.
14  *	  Timur Tabi <timur@freescale.com>
15  */
16 
17 #define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d: " fmt, __func__, __LINE__
18 
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/init.h>
22 #include <linux/delay.h>
23 #include <linux/pm.h>
24 #include <linux/i2c.h>
25 #include <linux/of_device.h>
26 #include <linux/of_gpio.h>
27 #include <linux/regmap.h>
28 #include <linux/regulator/consumer.h>
29 #include <linux/gpio/consumer.h>
30 #include <linux/slab.h>
31 #include <sound/core.h>
32 #include <sound/pcm.h>
33 #include <sound/pcm_params.h>
34 #include <sound/soc.h>
35 #include <sound/soc-dapm.h>
36 #include <sound/initval.h>
37 #include <sound/tlv.h>
38 
39 #include <sound/sta350.h>
40 #include "sta350.h"
41 
42 #define STA350_RATES (SNDRV_PCM_RATE_32000 | \
43 		      SNDRV_PCM_RATE_44100 | \
44 		      SNDRV_PCM_RATE_48000 | \
45 		      SNDRV_PCM_RATE_88200 | \
46 		      SNDRV_PCM_RATE_96000 | \
47 		      SNDRV_PCM_RATE_176400 | \
48 		      SNDRV_PCM_RATE_192000)
49 
50 #define STA350_FORMATS \
51 	(SNDRV_PCM_FMTBIT_S16_LE  | SNDRV_PCM_FMTBIT_S18_3LE | \
52 	 SNDRV_PCM_FMTBIT_S20_3LE | SNDRV_PCM_FMTBIT_S24_3LE | \
53 	 SNDRV_PCM_FMTBIT_S24_LE  | SNDRV_PCM_FMTBIT_S32_LE)
54 
55 /* Power-up register defaults */
56 static const struct reg_default sta350_regs[] = {
57 	{  0x0, 0x63 },
58 	{  0x1, 0x80 },
59 	{  0x2, 0xdf },
60 	{  0x3, 0x40 },
61 	{  0x4, 0xc2 },
62 	{  0x5, 0x5c },
63 	{  0x6, 0x00 },
64 	{  0x7, 0xff },
65 	{  0x8, 0x60 },
66 	{  0x9, 0x60 },
67 	{  0xa, 0x60 },
68 	{  0xb, 0x00 },
69 	{  0xc, 0x00 },
70 	{  0xd, 0x00 },
71 	{  0xe, 0x00 },
72 	{  0xf, 0x40 },
73 	{ 0x10, 0x80 },
74 	{ 0x11, 0x77 },
75 	{ 0x12, 0x6a },
76 	{ 0x13, 0x69 },
77 	{ 0x14, 0x6a },
78 	{ 0x15, 0x69 },
79 	{ 0x16, 0x00 },
80 	{ 0x17, 0x00 },
81 	{ 0x18, 0x00 },
82 	{ 0x19, 0x00 },
83 	{ 0x1a, 0x00 },
84 	{ 0x1b, 0x00 },
85 	{ 0x1c, 0x00 },
86 	{ 0x1d, 0x00 },
87 	{ 0x1e, 0x00 },
88 	{ 0x1f, 0x00 },
89 	{ 0x20, 0x00 },
90 	{ 0x21, 0x00 },
91 	{ 0x22, 0x00 },
92 	{ 0x23, 0x00 },
93 	{ 0x24, 0x00 },
94 	{ 0x25, 0x00 },
95 	{ 0x26, 0x00 },
96 	{ 0x27, 0x2a },
97 	{ 0x28, 0xc0 },
98 	{ 0x29, 0xf3 },
99 	{ 0x2a, 0x33 },
100 	{ 0x2b, 0x00 },
101 	{ 0x2c, 0x0c },
102 	{ 0x31, 0x00 },
103 	{ 0x36, 0x00 },
104 	{ 0x37, 0x00 },
105 	{ 0x38, 0x00 },
106 	{ 0x39, 0x01 },
107 	{ 0x3a, 0xee },
108 	{ 0x3b, 0xff },
109 	{ 0x3c, 0x7e },
110 	{ 0x3d, 0xc0 },
111 	{ 0x3e, 0x26 },
112 	{ 0x3f, 0x00 },
113 	{ 0x48, 0x00 },
114 	{ 0x49, 0x00 },
115 	{ 0x4a, 0x00 },
116 	{ 0x4b, 0x04 },
117 	{ 0x4c, 0x00 },
118 };
119 
120 static const struct regmap_range sta350_write_regs_range[] = {
121 	regmap_reg_range(STA350_CONFA,  STA350_AUTO2),
122 	regmap_reg_range(STA350_C1CFG,  STA350_FDRC2),
123 	regmap_reg_range(STA350_EQCFG,  STA350_EVOLRES),
124 	regmap_reg_range(STA350_NSHAPE, STA350_MISC2),
125 };
126 
127 static const struct regmap_range sta350_read_regs_range[] = {
128 	regmap_reg_range(STA350_CONFA,  STA350_AUTO2),
129 	regmap_reg_range(STA350_C1CFG,  STA350_STATUS),
130 	regmap_reg_range(STA350_EQCFG,  STA350_EVOLRES),
131 	regmap_reg_range(STA350_NSHAPE, STA350_MISC2),
132 };
133 
134 static const struct regmap_range sta350_volatile_regs_range[] = {
135 	regmap_reg_range(STA350_CFADDR2, STA350_CFUD),
136 	regmap_reg_range(STA350_STATUS,  STA350_STATUS),
137 };
138 
139 static const struct regmap_access_table sta350_write_regs = {
140 	.yes_ranges =	sta350_write_regs_range,
141 	.n_yes_ranges =	ARRAY_SIZE(sta350_write_regs_range),
142 };
143 
144 static const struct regmap_access_table sta350_read_regs = {
145 	.yes_ranges =	sta350_read_regs_range,
146 	.n_yes_ranges =	ARRAY_SIZE(sta350_read_regs_range),
147 };
148 
149 static const struct regmap_access_table sta350_volatile_regs = {
150 	.yes_ranges =	sta350_volatile_regs_range,
151 	.n_yes_ranges =	ARRAY_SIZE(sta350_volatile_regs_range),
152 };
153 
154 /* regulator power supply names */
155 static const char * const sta350_supply_names[] = {
156 	"vdd-dig",	/* digital supply, 3.3V */
157 	"vdd-pll",	/* pll supply, 3.3V */
158 	"vcc"		/* power amp supply, 5V - 26V */
159 };
160 
161 /* codec private data */
162 struct sta350_priv {
163 	struct regmap *regmap;
164 	struct regulator_bulk_data supplies[ARRAY_SIZE(sta350_supply_names)];
165 	struct sta350_platform_data *pdata;
166 
167 	unsigned int mclk;
168 	unsigned int format;
169 
170 	u32 coef_shadow[STA350_COEF_COUNT];
171 	int shutdown;
172 
173 	struct gpio_desc *gpiod_nreset;
174 	struct gpio_desc *gpiod_power_down;
175 
176 	struct mutex coeff_lock;
177 };
178 
179 static const DECLARE_TLV_DB_SCALE(mvol_tlv, -12750, 50, 1);
180 static const DECLARE_TLV_DB_SCALE(chvol_tlv, -7950, 50, 1);
181 static const DECLARE_TLV_DB_SCALE(tone_tlv, -1200, 200, 0);
182 
183 static const char * const sta350_drc_ac[] = {
184 	"Anti-Clipping", "Dynamic Range Compression"
185 };
186 static const char * const sta350_auto_gc_mode[] = {
187 	"User", "AC no clipping", "AC limited clipping (10%)",
188 	"DRC nighttime listening mode"
189 };
190 static const char * const sta350_auto_xo_mode[] = {
191 	"User", "80Hz", "100Hz", "120Hz", "140Hz", "160Hz", "180Hz",
192 	"200Hz", "220Hz", "240Hz", "260Hz", "280Hz", "300Hz", "320Hz",
193 	"340Hz", "360Hz"
194 };
195 static const char * const sta350_binary_output[] = {
196 	"FFX 3-state output - normal operation", "Binary output"
197 };
198 static const char * const sta350_limiter_select[] = {
199 	"Limiter Disabled", "Limiter #1", "Limiter #2"
200 };
201 static const char * const sta350_limiter_attack_rate[] = {
202 	"3.1584", "2.7072", "2.2560", "1.8048", "1.3536", "0.9024",
203 	"0.4512", "0.2256", "0.1504", "0.1123", "0.0902", "0.0752",
204 	"0.0645", "0.0564", "0.0501", "0.0451"
205 };
206 static const char * const sta350_limiter_release_rate[] = {
207 	"0.5116", "0.1370", "0.0744", "0.0499", "0.0360", "0.0299",
208 	"0.0264", "0.0208", "0.0198", "0.0172", "0.0147", "0.0137",
209 	"0.0134", "0.0117", "0.0110", "0.0104"
210 };
211 static const char * const sta350_noise_shaper_type[] = {
212 	"Third order", "Fourth order"
213 };
214 
215 static DECLARE_TLV_DB_RANGE(sta350_limiter_ac_attack_tlv,
216 	0, 7, TLV_DB_SCALE_ITEM(-1200, 200, 0),
217 	8, 16, TLV_DB_SCALE_ITEM(300, 100, 0),
218 );
219 
220 static DECLARE_TLV_DB_RANGE(sta350_limiter_ac_release_tlv,
221 	0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
222 	1, 1, TLV_DB_SCALE_ITEM(-2900, 0, 0),
223 	2, 2, TLV_DB_SCALE_ITEM(-2000, 0, 0),
224 	3, 8, TLV_DB_SCALE_ITEM(-1400, 200, 0),
225 	8, 16, TLV_DB_SCALE_ITEM(-700, 100, 0),
226 );
227 
228 static DECLARE_TLV_DB_RANGE(sta350_limiter_drc_attack_tlv,
229 	0, 7, TLV_DB_SCALE_ITEM(-3100, 200, 0),
230 	8, 13, TLV_DB_SCALE_ITEM(-1600, 100, 0),
231 	14, 16, TLV_DB_SCALE_ITEM(-1000, 300, 0),
232 );
233 
234 static DECLARE_TLV_DB_RANGE(sta350_limiter_drc_release_tlv,
235 	0, 0, TLV_DB_SCALE_ITEM(TLV_DB_GAIN_MUTE, 0, 0),
236 	1, 2, TLV_DB_SCALE_ITEM(-3800, 200, 0),
237 	3, 4, TLV_DB_SCALE_ITEM(-3300, 200, 0),
238 	5, 12, TLV_DB_SCALE_ITEM(-3000, 200, 0),
239 	13, 16, TLV_DB_SCALE_ITEM(-1500, 300, 0),
240 );
241 
242 static SOC_ENUM_SINGLE_DECL(sta350_drc_ac_enum,
243 			    STA350_CONFD, STA350_CONFD_DRC_SHIFT,
244 			    sta350_drc_ac);
245 static SOC_ENUM_SINGLE_DECL(sta350_noise_shaper_enum,
246 			    STA350_CONFE, STA350_CONFE_NSBW_SHIFT,
247 			    sta350_noise_shaper_type);
248 static SOC_ENUM_SINGLE_DECL(sta350_auto_gc_enum,
249 			    STA350_AUTO1, STA350_AUTO1_AMGC_SHIFT,
250 			    sta350_auto_gc_mode);
251 static SOC_ENUM_SINGLE_DECL(sta350_auto_xo_enum,
252 			    STA350_AUTO2, STA350_AUTO2_XO_SHIFT,
253 			    sta350_auto_xo_mode);
254 static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch1_enum,
255 			    STA350_C1CFG, STA350_CxCFG_BO_SHIFT,
256 			    sta350_binary_output);
257 static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch2_enum,
258 			    STA350_C2CFG, STA350_CxCFG_BO_SHIFT,
259 			    sta350_binary_output);
260 static SOC_ENUM_SINGLE_DECL(sta350_binary_output_ch3_enum,
261 			    STA350_C3CFG, STA350_CxCFG_BO_SHIFT,
262 			    sta350_binary_output);
263 static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch1_enum,
264 			    STA350_C1CFG, STA350_CxCFG_LS_SHIFT,
265 			    sta350_limiter_select);
266 static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch2_enum,
267 			    STA350_C2CFG, STA350_CxCFG_LS_SHIFT,
268 			    sta350_limiter_select);
269 static SOC_ENUM_SINGLE_DECL(sta350_limiter_ch3_enum,
270 			    STA350_C3CFG, STA350_CxCFG_LS_SHIFT,
271 			    sta350_limiter_select);
272 static SOC_ENUM_SINGLE_DECL(sta350_limiter1_attack_rate_enum,
273 			    STA350_L1AR, STA350_LxA_SHIFT,
274 			    sta350_limiter_attack_rate);
275 static SOC_ENUM_SINGLE_DECL(sta350_limiter2_attack_rate_enum,
276 			    STA350_L2AR, STA350_LxA_SHIFT,
277 			    sta350_limiter_attack_rate);
278 static SOC_ENUM_SINGLE_DECL(sta350_limiter1_release_rate_enum,
279 			    STA350_L1AR, STA350_LxR_SHIFT,
280 			    sta350_limiter_release_rate);
281 static SOC_ENUM_SINGLE_DECL(sta350_limiter2_release_rate_enum,
282 			    STA350_L2AR, STA350_LxR_SHIFT,
283 			    sta350_limiter_release_rate);
284 
285 /*
286  * byte array controls for setting biquad, mixer, scaling coefficients;
287  * for biquads all five coefficients need to be set in one go,
288  * mixer and pre/postscale coefs can be set individually;
289  * each coef is 24bit, the bytes are ordered in the same way
290  * as given in the STA350 data sheet (big endian; b1, b2, a1, a2, b0)
291  */
292 
sta350_coefficient_info(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_info * uinfo)293 static int sta350_coefficient_info(struct snd_kcontrol *kcontrol,
294 				   struct snd_ctl_elem_info *uinfo)
295 {
296 	int numcoef = kcontrol->private_value >> 16;
297 	uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
298 	uinfo->count = 3 * numcoef;
299 	return 0;
300 }
301 
sta350_coefficient_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)302 static int sta350_coefficient_get(struct snd_kcontrol *kcontrol,
303 				  struct snd_ctl_elem_value *ucontrol)
304 {
305 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
306 	struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
307 	int numcoef = kcontrol->private_value >> 16;
308 	int index = kcontrol->private_value & 0xffff;
309 	unsigned int cfud, val;
310 	int i, ret = 0;
311 
312 	mutex_lock(&sta350->coeff_lock);
313 
314 	/* preserve reserved bits in STA350_CFUD */
315 	regmap_read(sta350->regmap, STA350_CFUD, &cfud);
316 	cfud &= 0xf0;
317 	/*
318 	 * chip documentation does not say if the bits are self clearing,
319 	 * so do it explicitly
320 	 */
321 	regmap_write(sta350->regmap, STA350_CFUD, cfud);
322 
323 	regmap_write(sta350->regmap, STA350_CFADDR2, index);
324 	if (numcoef == 1) {
325 		regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x04);
326 	} else if (numcoef == 5) {
327 		regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x08);
328 	} else {
329 		ret = -EINVAL;
330 		goto exit_unlock;
331 	}
332 
333 	for (i = 0; i < 3 * numcoef; i++) {
334 		regmap_read(sta350->regmap, STA350_B1CF1 + i, &val);
335 		ucontrol->value.bytes.data[i] = val;
336 	}
337 
338 exit_unlock:
339 	mutex_unlock(&sta350->coeff_lock);
340 
341 	return ret;
342 }
343 
sta350_coefficient_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)344 static int sta350_coefficient_put(struct snd_kcontrol *kcontrol,
345 				  struct snd_ctl_elem_value *ucontrol)
346 {
347 	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
348 	struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
349 	int numcoef = kcontrol->private_value >> 16;
350 	int index = kcontrol->private_value & 0xffff;
351 	unsigned int cfud;
352 	int i;
353 
354 	/* preserve reserved bits in STA350_CFUD */
355 	regmap_read(sta350->regmap, STA350_CFUD, &cfud);
356 	cfud &= 0xf0;
357 	/*
358 	 * chip documentation does not say if the bits are self clearing,
359 	 * so do it explicitly
360 	 */
361 	regmap_write(sta350->regmap, STA350_CFUD, cfud);
362 
363 	regmap_write(sta350->regmap, STA350_CFADDR2, index);
364 	for (i = 0; i < numcoef && (index + i < STA350_COEF_COUNT); i++)
365 		sta350->coef_shadow[index + i] =
366 			  (ucontrol->value.bytes.data[3 * i] << 16)
367 			| (ucontrol->value.bytes.data[3 * i + 1] << 8)
368 			| (ucontrol->value.bytes.data[3 * i + 2]);
369 	for (i = 0; i < 3 * numcoef; i++)
370 		regmap_write(sta350->regmap, STA350_B1CF1 + i,
371 			     ucontrol->value.bytes.data[i]);
372 	if (numcoef == 1)
373 		regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x01);
374 	else if (numcoef == 5)
375 		regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x02);
376 	else
377 		return -EINVAL;
378 
379 	return 0;
380 }
381 
sta350_sync_coef_shadow(struct snd_soc_component * component)382 static int sta350_sync_coef_shadow(struct snd_soc_component *component)
383 {
384 	struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
385 	unsigned int cfud;
386 	int i;
387 
388 	/* preserve reserved bits in STA350_CFUD */
389 	regmap_read(sta350->regmap, STA350_CFUD, &cfud);
390 	cfud &= 0xf0;
391 
392 	for (i = 0; i < STA350_COEF_COUNT; i++) {
393 		regmap_write(sta350->regmap, STA350_CFADDR2, i);
394 		regmap_write(sta350->regmap, STA350_B1CF1,
395 			     (sta350->coef_shadow[i] >> 16) & 0xff);
396 		regmap_write(sta350->regmap, STA350_B1CF2,
397 			     (sta350->coef_shadow[i] >> 8) & 0xff);
398 		regmap_write(sta350->regmap, STA350_B1CF3,
399 			     (sta350->coef_shadow[i]) & 0xff);
400 		/*
401 		 * chip documentation does not say if the bits are
402 		 * self-clearing, so do it explicitly
403 		 */
404 		regmap_write(sta350->regmap, STA350_CFUD, cfud);
405 		regmap_write(sta350->regmap, STA350_CFUD, cfud | 0x01);
406 	}
407 	return 0;
408 }
409 
sta350_cache_sync(struct snd_soc_component * component)410 static int sta350_cache_sync(struct snd_soc_component *component)
411 {
412 	struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
413 	unsigned int mute;
414 	int rc;
415 
416 	/* mute during register sync */
417 	regmap_read(sta350->regmap, STA350_CFUD, &mute);
418 	regmap_write(sta350->regmap, STA350_MMUTE, mute | STA350_MMUTE_MMUTE);
419 	sta350_sync_coef_shadow(component);
420 	rc = regcache_sync(sta350->regmap);
421 	regmap_write(sta350->regmap, STA350_MMUTE, mute);
422 	return rc;
423 }
424 
425 #define SINGLE_COEF(xname, index) \
426 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
427 	.info = sta350_coefficient_info, \
428 	.get = sta350_coefficient_get,\
429 	.put = sta350_coefficient_put, \
430 	.private_value = index | (1 << 16) }
431 
432 #define BIQUAD_COEFS(xname, index) \
433 {	.iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
434 	.info = sta350_coefficient_info, \
435 	.get = sta350_coefficient_get,\
436 	.put = sta350_coefficient_put, \
437 	.private_value = index | (5 << 16) }
438 
439 static const struct snd_kcontrol_new sta350_snd_controls[] = {
440 SOC_SINGLE_TLV("Master Volume", STA350_MVOL, 0, 0xff, 1, mvol_tlv),
441 /* VOL */
442 SOC_SINGLE_TLV("Ch1 Volume", STA350_C1VOL, 0, 0xff, 1, chvol_tlv),
443 SOC_SINGLE_TLV("Ch2 Volume", STA350_C2VOL, 0, 0xff, 1, chvol_tlv),
444 SOC_SINGLE_TLV("Ch3 Volume", STA350_C3VOL, 0, 0xff, 1, chvol_tlv),
445 /* CONFD */
446 SOC_SINGLE("High Pass Filter Bypass Switch",
447 	   STA350_CONFD, STA350_CONFD_HPB_SHIFT, 1, 1),
448 SOC_SINGLE("De-emphasis Filter Switch",
449 	   STA350_CONFD, STA350_CONFD_DEMP_SHIFT, 1, 0),
450 SOC_SINGLE("DSP Bypass Switch",
451 	   STA350_CONFD, STA350_CONFD_DSPB_SHIFT, 1, 0),
452 SOC_SINGLE("Post-scale Link Switch",
453 	   STA350_CONFD, STA350_CONFD_PSL_SHIFT, 1, 0),
454 SOC_SINGLE("Biquad Coefficient Link Switch",
455 	   STA350_CONFD, STA350_CONFD_BQL_SHIFT, 1, 0),
456 SOC_ENUM("Compressor/Limiter Switch", sta350_drc_ac_enum),
457 SOC_ENUM("Noise Shaper Bandwidth", sta350_noise_shaper_enum),
458 SOC_SINGLE("Zero-detect Mute Enable Switch",
459 	   STA350_CONFD, STA350_CONFD_ZDE_SHIFT, 1, 0),
460 SOC_SINGLE("Submix Mode Switch",
461 	   STA350_CONFD, STA350_CONFD_SME_SHIFT, 1, 0),
462 /* CONFE */
463 SOC_SINGLE("Zero Cross Switch", STA350_CONFE, STA350_CONFE_ZCE_SHIFT, 1, 0),
464 SOC_SINGLE("Soft Ramp Switch", STA350_CONFE, STA350_CONFE_SVE_SHIFT, 1, 0),
465 /* MUTE */
466 SOC_SINGLE("Master Switch", STA350_MMUTE, STA350_MMUTE_MMUTE_SHIFT, 1, 1),
467 SOC_SINGLE("Ch1 Switch", STA350_MMUTE, STA350_MMUTE_C1M_SHIFT, 1, 1),
468 SOC_SINGLE("Ch2 Switch", STA350_MMUTE, STA350_MMUTE_C2M_SHIFT, 1, 1),
469 SOC_SINGLE("Ch3 Switch", STA350_MMUTE, STA350_MMUTE_C3M_SHIFT, 1, 1),
470 /* AUTOx */
471 SOC_ENUM("Automode GC", sta350_auto_gc_enum),
472 SOC_ENUM("Automode XO", sta350_auto_xo_enum),
473 /* CxCFG */
474 SOC_SINGLE("Ch1 Tone Control Bypass Switch",
475 	   STA350_C1CFG, STA350_CxCFG_TCB_SHIFT, 1, 0),
476 SOC_SINGLE("Ch2 Tone Control Bypass Switch",
477 	   STA350_C2CFG, STA350_CxCFG_TCB_SHIFT, 1, 0),
478 SOC_SINGLE("Ch1 EQ Bypass Switch",
479 	   STA350_C1CFG, STA350_CxCFG_EQBP_SHIFT, 1, 0),
480 SOC_SINGLE("Ch2 EQ Bypass Switch",
481 	   STA350_C2CFG, STA350_CxCFG_EQBP_SHIFT, 1, 0),
482 SOC_SINGLE("Ch1 Master Volume Bypass Switch",
483 	   STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0),
484 SOC_SINGLE("Ch2 Master Volume Bypass Switch",
485 	   STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0),
486 SOC_SINGLE("Ch3 Master Volume Bypass Switch",
487 	   STA350_C1CFG, STA350_CxCFG_VBP_SHIFT, 1, 0),
488 SOC_ENUM("Ch1 Binary Output Select", sta350_binary_output_ch1_enum),
489 SOC_ENUM("Ch2 Binary Output Select", sta350_binary_output_ch2_enum),
490 SOC_ENUM("Ch3 Binary Output Select", sta350_binary_output_ch3_enum),
491 SOC_ENUM("Ch1 Limiter Select", sta350_limiter_ch1_enum),
492 SOC_ENUM("Ch2 Limiter Select", sta350_limiter_ch2_enum),
493 SOC_ENUM("Ch3 Limiter Select", sta350_limiter_ch3_enum),
494 /* TONE */
495 SOC_SINGLE_RANGE_TLV("Bass Tone Control Volume",
496 		     STA350_TONE, STA350_TONE_BTC_SHIFT, 1, 13, 0, tone_tlv),
497 SOC_SINGLE_RANGE_TLV("Treble Tone Control Volume",
498 		     STA350_TONE, STA350_TONE_TTC_SHIFT, 1, 13, 0, tone_tlv),
499 SOC_ENUM("Limiter1 Attack Rate (dB/ms)", sta350_limiter1_attack_rate_enum),
500 SOC_ENUM("Limiter2 Attack Rate (dB/ms)", sta350_limiter2_attack_rate_enum),
501 SOC_ENUM("Limiter1 Release Rate (dB/ms)", sta350_limiter1_release_rate_enum),
502 SOC_ENUM("Limiter2 Release Rate (dB/ms)", sta350_limiter2_release_rate_enum),
503 
504 /*
505  * depending on mode, the attack/release thresholds have
506  * two different enum definitions; provide both
507  */
508 SOC_SINGLE_TLV("Limiter1 Attack Threshold (AC Mode)",
509 	       STA350_L1ATRT, STA350_LxA_SHIFT,
510 	       16, 0, sta350_limiter_ac_attack_tlv),
511 SOC_SINGLE_TLV("Limiter2 Attack Threshold (AC Mode)",
512 	       STA350_L2ATRT, STA350_LxA_SHIFT,
513 	       16, 0, sta350_limiter_ac_attack_tlv),
514 SOC_SINGLE_TLV("Limiter1 Release Threshold (AC Mode)",
515 	       STA350_L1ATRT, STA350_LxR_SHIFT,
516 	       16, 0, sta350_limiter_ac_release_tlv),
517 SOC_SINGLE_TLV("Limiter2 Release Threshold (AC Mode)",
518 	       STA350_L2ATRT, STA350_LxR_SHIFT,
519 	       16, 0, sta350_limiter_ac_release_tlv),
520 SOC_SINGLE_TLV("Limiter1 Attack Threshold (DRC Mode)",
521 	       STA350_L1ATRT, STA350_LxA_SHIFT,
522 	       16, 0, sta350_limiter_drc_attack_tlv),
523 SOC_SINGLE_TLV("Limiter2 Attack Threshold (DRC Mode)",
524 	       STA350_L2ATRT, STA350_LxA_SHIFT,
525 	       16, 0, sta350_limiter_drc_attack_tlv),
526 SOC_SINGLE_TLV("Limiter1 Release Threshold (DRC Mode)",
527 	       STA350_L1ATRT, STA350_LxR_SHIFT,
528 	       16, 0, sta350_limiter_drc_release_tlv),
529 SOC_SINGLE_TLV("Limiter2 Release Threshold (DRC Mode)",
530 	       STA350_L2ATRT, STA350_LxR_SHIFT,
531 	       16, 0, sta350_limiter_drc_release_tlv),
532 
533 BIQUAD_COEFS("Ch1 - Biquad 1", 0),
534 BIQUAD_COEFS("Ch1 - Biquad 2", 5),
535 BIQUAD_COEFS("Ch1 - Biquad 3", 10),
536 BIQUAD_COEFS("Ch1 - Biquad 4", 15),
537 BIQUAD_COEFS("Ch2 - Biquad 1", 20),
538 BIQUAD_COEFS("Ch2 - Biquad 2", 25),
539 BIQUAD_COEFS("Ch2 - Biquad 3", 30),
540 BIQUAD_COEFS("Ch2 - Biquad 4", 35),
541 BIQUAD_COEFS("High-pass", 40),
542 BIQUAD_COEFS("Low-pass", 45),
543 SINGLE_COEF("Ch1 - Prescale", 50),
544 SINGLE_COEF("Ch2 - Prescale", 51),
545 SINGLE_COEF("Ch1 - Postscale", 52),
546 SINGLE_COEF("Ch2 - Postscale", 53),
547 SINGLE_COEF("Ch3 - Postscale", 54),
548 SINGLE_COEF("Thermal warning - Postscale", 55),
549 SINGLE_COEF("Ch1 - Mix 1", 56),
550 SINGLE_COEF("Ch1 - Mix 2", 57),
551 SINGLE_COEF("Ch2 - Mix 1", 58),
552 SINGLE_COEF("Ch2 - Mix 2", 59),
553 SINGLE_COEF("Ch3 - Mix 1", 60),
554 SINGLE_COEF("Ch3 - Mix 2", 61),
555 };
556 
557 static const struct snd_soc_dapm_widget sta350_dapm_widgets[] = {
558 SND_SOC_DAPM_DAC("DAC", NULL, SND_SOC_NOPM, 0, 0),
559 SND_SOC_DAPM_OUTPUT("LEFT"),
560 SND_SOC_DAPM_OUTPUT("RIGHT"),
561 SND_SOC_DAPM_OUTPUT("SUB"),
562 };
563 
564 static const struct snd_soc_dapm_route sta350_dapm_routes[] = {
565 	{ "LEFT", NULL, "DAC" },
566 	{ "RIGHT", NULL, "DAC" },
567 	{ "SUB", NULL, "DAC" },
568 	{ "DAC", NULL, "Playback" },
569 };
570 
571 /* MCLK interpolation ratio per fs */
572 static struct {
573 	int fs;
574 	int ir;
575 } interpolation_ratios[] = {
576 	{ 32000, 0 },
577 	{ 44100, 0 },
578 	{ 48000, 0 },
579 	{ 88200, 1 },
580 	{ 96000, 1 },
581 	{ 176400, 2 },
582 	{ 192000, 2 },
583 };
584 
585 /* MCLK to fs clock ratios */
586 static int mcs_ratio_table[3][6] = {
587 	{ 768, 512, 384, 256, 128, 576 },
588 	{ 384, 256, 192, 128,  64,   0 },
589 	{ 192, 128,  96,  64,  32,   0 },
590 };
591 
592 /**
593  * sta350_set_dai_sysclk - configure MCLK
594  * @codec_dai: the codec DAI
595  * @clk_id: the clock ID (ignored)
596  * @freq: the MCLK input frequency
597  * @dir: the clock direction (ignored)
598  *
599  * The value of MCLK is used to determine which sample rates are supported
600  * by the STA350, based on the mcs_ratio_table.
601  *
602  * This function must be called by the machine driver's 'startup' function,
603  * otherwise the list of supported sample rates will not be available in
604  * time for ALSA.
605  */
sta350_set_dai_sysclk(struct snd_soc_dai * codec_dai,int clk_id,unsigned int freq,int dir)606 static int sta350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
607 				 int clk_id, unsigned int freq, int dir)
608 {
609 	struct snd_soc_component *component = codec_dai->component;
610 	struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
611 
612 	dev_dbg(component->dev, "mclk=%u\n", freq);
613 	sta350->mclk = freq;
614 
615 	return 0;
616 }
617 
618 /**
619  * sta350_set_dai_fmt - configure the codec for the selected audio format
620  * @codec_dai: the codec DAI
621  * @fmt: a SND_SOC_DAIFMT_x value indicating the data format
622  *
623  * This function takes a bitmask of SND_SOC_DAIFMT_x bits and programs the
624  * codec accordingly.
625  */
sta350_set_dai_fmt(struct snd_soc_dai * codec_dai,unsigned int fmt)626 static int sta350_set_dai_fmt(struct snd_soc_dai *codec_dai,
627 			      unsigned int fmt)
628 {
629 	struct snd_soc_component *component = codec_dai->component;
630 	struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
631 	unsigned int confb = 0;
632 
633 	switch (fmt & SND_SOC_DAIFMT_CLOCK_PROVIDER_MASK) {
634 	case SND_SOC_DAIFMT_CBC_CFC:
635 		break;
636 	default:
637 		return -EINVAL;
638 	}
639 
640 	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
641 	case SND_SOC_DAIFMT_I2S:
642 	case SND_SOC_DAIFMT_RIGHT_J:
643 	case SND_SOC_DAIFMT_LEFT_J:
644 		sta350->format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
645 		break;
646 	default:
647 		return -EINVAL;
648 	}
649 
650 	switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
651 	case SND_SOC_DAIFMT_NB_NF:
652 		confb |= STA350_CONFB_C2IM;
653 		break;
654 	case SND_SOC_DAIFMT_NB_IF:
655 		confb |= STA350_CONFB_C1IM;
656 		break;
657 	default:
658 		return -EINVAL;
659 	}
660 
661 	return regmap_update_bits(sta350->regmap, STA350_CONFB,
662 				  STA350_CONFB_C1IM | STA350_CONFB_C2IM, confb);
663 }
664 
665 /**
666  * sta350_hw_params - program the STA350 with the given hardware parameters.
667  * @substream: the audio stream
668  * @params: the hardware parameters to set
669  * @dai: the SOC DAI (ignored)
670  *
671  * This function programs the hardware with the values provided.
672  * Specifically, the sample rate and the data format.
673  */
sta350_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)674 static int sta350_hw_params(struct snd_pcm_substream *substream,
675 			    struct snd_pcm_hw_params *params,
676 			    struct snd_soc_dai *dai)
677 {
678 	struct snd_soc_component *component = dai->component;
679 	struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
680 	int i, mcs = -EINVAL, ir = -EINVAL;
681 	unsigned int confa, confb;
682 	unsigned int rate, ratio;
683 	int ret;
684 
685 	if (!sta350->mclk) {
686 		dev_err(component->dev,
687 			"sta350->mclk is unset. Unable to determine ratio\n");
688 		return -EIO;
689 	}
690 
691 	rate = params_rate(params);
692 	ratio = sta350->mclk / rate;
693 	dev_dbg(component->dev, "rate: %u, ratio: %u\n", rate, ratio);
694 
695 	for (i = 0; i < ARRAY_SIZE(interpolation_ratios); i++) {
696 		if (interpolation_ratios[i].fs == rate) {
697 			ir = interpolation_ratios[i].ir;
698 			break;
699 		}
700 	}
701 
702 	if (ir < 0) {
703 		dev_err(component->dev, "Unsupported samplerate: %u\n", rate);
704 		return -EINVAL;
705 	}
706 
707 	for (i = 0; i < 6; i++) {
708 		if (mcs_ratio_table[ir][i] == ratio) {
709 			mcs = i;
710 			break;
711 		}
712 	}
713 
714 	if (mcs < 0) {
715 		dev_err(component->dev, "Unresolvable ratio: %u\n", ratio);
716 		return -EINVAL;
717 	}
718 
719 	confa = (ir << STA350_CONFA_IR_SHIFT) |
720 		(mcs << STA350_CONFA_MCS_SHIFT);
721 	confb = 0;
722 
723 	switch (params_width(params)) {
724 	case 24:
725 		dev_dbg(component->dev, "24bit\n");
726 		fallthrough;
727 	case 32:
728 		dev_dbg(component->dev, "24bit or 32bit\n");
729 		switch (sta350->format) {
730 		case SND_SOC_DAIFMT_I2S:
731 			confb |= 0x0;
732 			break;
733 		case SND_SOC_DAIFMT_LEFT_J:
734 			confb |= 0x1;
735 			break;
736 		case SND_SOC_DAIFMT_RIGHT_J:
737 			confb |= 0x2;
738 			break;
739 		}
740 
741 		break;
742 	case 20:
743 		dev_dbg(component->dev, "20bit\n");
744 		switch (sta350->format) {
745 		case SND_SOC_DAIFMT_I2S:
746 			confb |= 0x4;
747 			break;
748 		case SND_SOC_DAIFMT_LEFT_J:
749 			confb |= 0x5;
750 			break;
751 		case SND_SOC_DAIFMT_RIGHT_J:
752 			confb |= 0x6;
753 			break;
754 		}
755 
756 		break;
757 	case 18:
758 		dev_dbg(component->dev, "18bit\n");
759 		switch (sta350->format) {
760 		case SND_SOC_DAIFMT_I2S:
761 			confb |= 0x8;
762 			break;
763 		case SND_SOC_DAIFMT_LEFT_J:
764 			confb |= 0x9;
765 			break;
766 		case SND_SOC_DAIFMT_RIGHT_J:
767 			confb |= 0xa;
768 			break;
769 		}
770 
771 		break;
772 	case 16:
773 		dev_dbg(component->dev, "16bit\n");
774 		switch (sta350->format) {
775 		case SND_SOC_DAIFMT_I2S:
776 			confb |= 0x0;
777 			break;
778 		case SND_SOC_DAIFMT_LEFT_J:
779 			confb |= 0xd;
780 			break;
781 		case SND_SOC_DAIFMT_RIGHT_J:
782 			confb |= 0xe;
783 			break;
784 		}
785 
786 		break;
787 	default:
788 		return -EINVAL;
789 	}
790 
791 	ret = regmap_update_bits(sta350->regmap, STA350_CONFA,
792 				 STA350_CONFA_MCS_MASK | STA350_CONFA_IR_MASK,
793 				 confa);
794 	if (ret < 0)
795 		return ret;
796 
797 	ret = regmap_update_bits(sta350->regmap, STA350_CONFB,
798 				 STA350_CONFB_SAI_MASK | STA350_CONFB_SAIFB,
799 				 confb);
800 	if (ret < 0)
801 		return ret;
802 
803 	return 0;
804 }
805 
sta350_startup_sequence(struct sta350_priv * sta350)806 static int sta350_startup_sequence(struct sta350_priv *sta350)
807 {
808 	if (sta350->gpiod_power_down)
809 		gpiod_set_value(sta350->gpiod_power_down, 1);
810 
811 	if (sta350->gpiod_nreset) {
812 		gpiod_set_value(sta350->gpiod_nreset, 0);
813 		mdelay(1);
814 		gpiod_set_value(sta350->gpiod_nreset, 1);
815 		mdelay(1);
816 	}
817 
818 	return 0;
819 }
820 
821 /**
822  * sta350_set_bias_level - DAPM callback
823  * @component: the component device
824  * @level: DAPM power level
825  *
826  * This is called by ALSA to put the component into low power mode
827  * or to wake it up.  If the component is powered off completely
828  * all registers must be restored after power on.
829  */
sta350_set_bias_level(struct snd_soc_component * component,enum snd_soc_bias_level level)830 static int sta350_set_bias_level(struct snd_soc_component *component,
831 				 enum snd_soc_bias_level level)
832 {
833 	struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
834 	int ret;
835 
836 	dev_dbg(component->dev, "level = %d\n", level);
837 	switch (level) {
838 	case SND_SOC_BIAS_ON:
839 		break;
840 
841 	case SND_SOC_BIAS_PREPARE:
842 		/* Full power on */
843 		regmap_update_bits(sta350->regmap, STA350_CONFF,
844 				   STA350_CONFF_PWDN | STA350_CONFF_EAPD,
845 				   STA350_CONFF_PWDN | STA350_CONFF_EAPD);
846 		break;
847 
848 	case SND_SOC_BIAS_STANDBY:
849 		if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF) {
850 			ret = regulator_bulk_enable(
851 				ARRAY_SIZE(sta350->supplies),
852 				sta350->supplies);
853 			if (ret < 0) {
854 				dev_err(component->dev,
855 					"Failed to enable supplies: %d\n",
856 					ret);
857 				return ret;
858 			}
859 			sta350_startup_sequence(sta350);
860 			sta350_cache_sync(component);
861 		}
862 
863 		/* Power down */
864 		regmap_update_bits(sta350->regmap, STA350_CONFF,
865 				   STA350_CONFF_PWDN | STA350_CONFF_EAPD,
866 				   0);
867 
868 		break;
869 
870 	case SND_SOC_BIAS_OFF:
871 		/* The chip runs through the power down sequence for us */
872 		regmap_update_bits(sta350->regmap, STA350_CONFF,
873 				   STA350_CONFF_PWDN | STA350_CONFF_EAPD, 0);
874 
875 		/* power down: low */
876 		if (sta350->gpiod_power_down)
877 			gpiod_set_value(sta350->gpiod_power_down, 0);
878 
879 		if (sta350->gpiod_nreset)
880 			gpiod_set_value(sta350->gpiod_nreset, 0);
881 
882 		regulator_bulk_disable(ARRAY_SIZE(sta350->supplies),
883 				       sta350->supplies);
884 		break;
885 	}
886 	return 0;
887 }
888 
889 static const struct snd_soc_dai_ops sta350_dai_ops = {
890 	.hw_params	= sta350_hw_params,
891 	.set_sysclk	= sta350_set_dai_sysclk,
892 	.set_fmt	= sta350_set_dai_fmt,
893 };
894 
895 static struct snd_soc_dai_driver sta350_dai = {
896 	.name = "sta350-hifi",
897 	.playback = {
898 		.stream_name = "Playback",
899 		.channels_min = 2,
900 		.channels_max = 2,
901 		.rates = STA350_RATES,
902 		.formats = STA350_FORMATS,
903 	},
904 	.ops = &sta350_dai_ops,
905 };
906 
sta350_probe(struct snd_soc_component * component)907 static int sta350_probe(struct snd_soc_component *component)
908 {
909 	struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
910 	struct sta350_platform_data *pdata = sta350->pdata;
911 	int i, ret = 0, thermal = 0;
912 
913 	ret = regulator_bulk_enable(ARRAY_SIZE(sta350->supplies),
914 				    sta350->supplies);
915 	if (ret < 0) {
916 		dev_err(component->dev, "Failed to enable supplies: %d\n", ret);
917 		return ret;
918 	}
919 
920 	ret = sta350_startup_sequence(sta350);
921 	if (ret < 0) {
922 		dev_err(component->dev, "Failed to startup device\n");
923 		return ret;
924 	}
925 
926 	/* CONFA */
927 	if (!pdata->thermal_warning_recovery)
928 		thermal |= STA350_CONFA_TWAB;
929 	if (!pdata->thermal_warning_adjustment)
930 		thermal |= STA350_CONFA_TWRB;
931 	if (!pdata->fault_detect_recovery)
932 		thermal |= STA350_CONFA_FDRB;
933 	regmap_update_bits(sta350->regmap, STA350_CONFA,
934 			   STA350_CONFA_TWAB | STA350_CONFA_TWRB |
935 			   STA350_CONFA_FDRB,
936 			   thermal);
937 
938 	/* CONFC */
939 	regmap_update_bits(sta350->regmap, STA350_CONFC,
940 			   STA350_CONFC_OM_MASK,
941 			   pdata->ffx_power_output_mode
942 				<< STA350_CONFC_OM_SHIFT);
943 	regmap_update_bits(sta350->regmap, STA350_CONFC,
944 			   STA350_CONFC_CSZ_MASK,
945 			   pdata->drop_compensation_ns
946 				<< STA350_CONFC_CSZ_SHIFT);
947 	regmap_update_bits(sta350->regmap,
948 			   STA350_CONFC,
949 			   STA350_CONFC_OCRB,
950 			   pdata->oc_warning_adjustment ?
951 				STA350_CONFC_OCRB : 0);
952 
953 	/* CONFE */
954 	regmap_update_bits(sta350->regmap, STA350_CONFE,
955 			   STA350_CONFE_MPCV,
956 			   pdata->max_power_use_mpcc ?
957 				STA350_CONFE_MPCV : 0);
958 	regmap_update_bits(sta350->regmap, STA350_CONFE,
959 			   STA350_CONFE_MPC,
960 			   pdata->max_power_correction ?
961 				STA350_CONFE_MPC : 0);
962 	regmap_update_bits(sta350->regmap, STA350_CONFE,
963 			   STA350_CONFE_AME,
964 			   pdata->am_reduction_mode ?
965 				STA350_CONFE_AME : 0);
966 	regmap_update_bits(sta350->regmap, STA350_CONFE,
967 			   STA350_CONFE_PWMS,
968 			   pdata->odd_pwm_speed_mode ?
969 				STA350_CONFE_PWMS : 0);
970 	regmap_update_bits(sta350->regmap, STA350_CONFE,
971 			   STA350_CONFE_DCCV,
972 			   pdata->distortion_compensation ?
973 				STA350_CONFE_DCCV : 0);
974 	/*  CONFF */
975 	regmap_update_bits(sta350->regmap, STA350_CONFF,
976 			   STA350_CONFF_IDE,
977 			   pdata->invalid_input_detect_mute ?
978 				STA350_CONFF_IDE : 0);
979 	regmap_update_bits(sta350->regmap, STA350_CONFF,
980 			   STA350_CONFF_OCFG_MASK,
981 			   pdata->output_conf
982 				<< STA350_CONFF_OCFG_SHIFT);
983 
984 	/* channel to output mapping */
985 	regmap_update_bits(sta350->regmap, STA350_C1CFG,
986 			   STA350_CxCFG_OM_MASK,
987 			   pdata->ch1_output_mapping
988 				<< STA350_CxCFG_OM_SHIFT);
989 	regmap_update_bits(sta350->regmap, STA350_C2CFG,
990 			   STA350_CxCFG_OM_MASK,
991 			   pdata->ch2_output_mapping
992 				<< STA350_CxCFG_OM_SHIFT);
993 	regmap_update_bits(sta350->regmap, STA350_C3CFG,
994 			   STA350_CxCFG_OM_MASK,
995 			   pdata->ch3_output_mapping
996 				<< STA350_CxCFG_OM_SHIFT);
997 
998 	/* miscellaneous registers */
999 	regmap_update_bits(sta350->regmap, STA350_MISC1,
1000 			   STA350_MISC1_CPWMEN,
1001 			   pdata->activate_mute_output ?
1002 				STA350_MISC1_CPWMEN : 0);
1003 	regmap_update_bits(sta350->regmap, STA350_MISC1,
1004 			   STA350_MISC1_BRIDGOFF,
1005 			   pdata->bridge_immediate_off ?
1006 				STA350_MISC1_BRIDGOFF : 0);
1007 	regmap_update_bits(sta350->regmap, STA350_MISC1,
1008 			   STA350_MISC1_NSHHPEN,
1009 			   pdata->noise_shape_dc_cut ?
1010 				STA350_MISC1_NSHHPEN : 0);
1011 	regmap_update_bits(sta350->regmap, STA350_MISC1,
1012 			   STA350_MISC1_RPDNEN,
1013 			   pdata->powerdown_master_vol ?
1014 				STA350_MISC1_RPDNEN: 0);
1015 
1016 	regmap_update_bits(sta350->regmap, STA350_MISC2,
1017 			   STA350_MISC2_PNDLSL_MASK,
1018 			   pdata->powerdown_delay_divider
1019 				<< STA350_MISC2_PNDLSL_SHIFT);
1020 
1021 	/* initialize coefficient shadow RAM with reset values */
1022 	for (i = 4; i <= 49; i += 5)
1023 		sta350->coef_shadow[i] = 0x400000;
1024 	for (i = 50; i <= 54; i++)
1025 		sta350->coef_shadow[i] = 0x7fffff;
1026 	sta350->coef_shadow[55] = 0x5a9df7;
1027 	sta350->coef_shadow[56] = 0x7fffff;
1028 	sta350->coef_shadow[59] = 0x7fffff;
1029 	sta350->coef_shadow[60] = 0x400000;
1030 	sta350->coef_shadow[61] = 0x400000;
1031 
1032 	snd_soc_component_force_bias_level(component, SND_SOC_BIAS_STANDBY);
1033 	/* Bias level configuration will have done an extra enable */
1034 	regulator_bulk_disable(ARRAY_SIZE(sta350->supplies), sta350->supplies);
1035 
1036 	return 0;
1037 }
1038 
sta350_remove(struct snd_soc_component * component)1039 static void sta350_remove(struct snd_soc_component *component)
1040 {
1041 	struct sta350_priv *sta350 = snd_soc_component_get_drvdata(component);
1042 
1043 	regulator_bulk_disable(ARRAY_SIZE(sta350->supplies), sta350->supplies);
1044 }
1045 
1046 static const struct snd_soc_component_driver sta350_component = {
1047 	.probe			= sta350_probe,
1048 	.remove			= sta350_remove,
1049 	.set_bias_level		= sta350_set_bias_level,
1050 	.controls		= sta350_snd_controls,
1051 	.num_controls		= ARRAY_SIZE(sta350_snd_controls),
1052 	.dapm_widgets		= sta350_dapm_widgets,
1053 	.num_dapm_widgets	= ARRAY_SIZE(sta350_dapm_widgets),
1054 	.dapm_routes		= sta350_dapm_routes,
1055 	.num_dapm_routes	= ARRAY_SIZE(sta350_dapm_routes),
1056 	.suspend_bias_off	= 1,
1057 	.idle_bias_on		= 1,
1058 	.use_pmdown_time	= 1,
1059 	.endianness		= 1,
1060 };
1061 
1062 static const struct regmap_config sta350_regmap = {
1063 	.reg_bits =		8,
1064 	.val_bits =		8,
1065 	.max_register =		STA350_MISC2,
1066 	.reg_defaults =		sta350_regs,
1067 	.num_reg_defaults =	ARRAY_SIZE(sta350_regs),
1068 	.cache_type =		REGCACHE_MAPLE,
1069 	.wr_table =		&sta350_write_regs,
1070 	.rd_table =		&sta350_read_regs,
1071 	.volatile_table =	&sta350_volatile_regs,
1072 };
1073 
1074 #ifdef CONFIG_OF
1075 static const struct of_device_id st350_dt_ids[] = {
1076 	{ .compatible = "st,sta350", },
1077 	{ }
1078 };
1079 MODULE_DEVICE_TABLE(of, st350_dt_ids);
1080 
1081 static const char * const sta350_ffx_modes[] = {
1082 	[STA350_FFX_PM_DROP_COMP]		= "drop-compensation",
1083 	[STA350_FFX_PM_TAPERED_COMP]		= "tapered-compensation",
1084 	[STA350_FFX_PM_FULL_POWER]		= "full-power-mode",
1085 	[STA350_FFX_PM_VARIABLE_DROP_COMP]	= "variable-drop-compensation",
1086 };
1087 
sta350_probe_dt(struct device * dev,struct sta350_priv * sta350)1088 static int sta350_probe_dt(struct device *dev, struct sta350_priv *sta350)
1089 {
1090 	struct device_node *np = dev->of_node;
1091 	struct sta350_platform_data *pdata;
1092 	const char *ffx_power_mode;
1093 	u16 tmp;
1094 	u8 tmp8;
1095 
1096 	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
1097 	if (!pdata)
1098 		return -ENOMEM;
1099 
1100 	of_property_read_u8(np, "st,output-conf",
1101 			    &pdata->output_conf);
1102 	of_property_read_u8(np, "st,ch1-output-mapping",
1103 			    &pdata->ch1_output_mapping);
1104 	of_property_read_u8(np, "st,ch2-output-mapping",
1105 			    &pdata->ch2_output_mapping);
1106 	of_property_read_u8(np, "st,ch3-output-mapping",
1107 			    &pdata->ch3_output_mapping);
1108 
1109 	pdata->thermal_warning_recovery =
1110 		of_property_read_bool(np, "st,thermal-warning-recovery");
1111 	pdata->thermal_warning_adjustment =
1112 		of_property_read_bool(np, "st,thermal-warning-adjustment");
1113 	pdata->fault_detect_recovery =
1114 		of_property_read_bool(np, "st,fault-detect-recovery");
1115 
1116 	pdata->ffx_power_output_mode = STA350_FFX_PM_VARIABLE_DROP_COMP;
1117 	if (!of_property_read_string(np, "st,ffx-power-output-mode",
1118 				     &ffx_power_mode)) {
1119 		int i, mode = -EINVAL;
1120 
1121 		for (i = 0; i < ARRAY_SIZE(sta350_ffx_modes); i++)
1122 			if (!strcasecmp(ffx_power_mode, sta350_ffx_modes[i]))
1123 				mode = i;
1124 
1125 		if (mode < 0)
1126 			dev_warn(dev, "Unsupported ffx output mode: %s\n",
1127 				 ffx_power_mode);
1128 		else
1129 			pdata->ffx_power_output_mode = mode;
1130 	}
1131 
1132 	tmp = 140;
1133 	of_property_read_u16(np, "st,drop-compensation-ns", &tmp);
1134 	pdata->drop_compensation_ns = clamp_t(u16, tmp, 0, 300) / 20;
1135 
1136 	pdata->oc_warning_adjustment =
1137 		of_property_read_bool(np, "st,overcurrent-warning-adjustment");
1138 
1139 	/* CONFE */
1140 	pdata->max_power_use_mpcc =
1141 		of_property_read_bool(np, "st,max-power-use-mpcc");
1142 	pdata->max_power_correction =
1143 		of_property_read_bool(np, "st,max-power-correction");
1144 	pdata->am_reduction_mode =
1145 		of_property_read_bool(np, "st,am-reduction-mode");
1146 	pdata->odd_pwm_speed_mode =
1147 		of_property_read_bool(np, "st,odd-pwm-speed-mode");
1148 	pdata->distortion_compensation =
1149 		of_property_read_bool(np, "st,distortion-compensation");
1150 
1151 	/* CONFF */
1152 	pdata->invalid_input_detect_mute =
1153 		of_property_read_bool(np, "st,invalid-input-detect-mute");
1154 
1155 	/* MISC */
1156 	pdata->activate_mute_output =
1157 		of_property_read_bool(np, "st,activate-mute-output");
1158 	pdata->bridge_immediate_off =
1159 		of_property_read_bool(np, "st,bridge-immediate-off");
1160 	pdata->noise_shape_dc_cut =
1161 		of_property_read_bool(np, "st,noise-shape-dc-cut");
1162 	pdata->powerdown_master_vol =
1163 		of_property_read_bool(np, "st,powerdown-master-volume");
1164 
1165 	if (!of_property_read_u8(np, "st,powerdown-delay-divider", &tmp8)) {
1166 		if (is_power_of_2(tmp8) && tmp8 >= 1 && tmp8 <= 128)
1167 			pdata->powerdown_delay_divider = ilog2(tmp8);
1168 		else
1169 			dev_warn(dev, "Unsupported powerdown delay divider %d\n",
1170 				 tmp8);
1171 	}
1172 
1173 	sta350->pdata = pdata;
1174 
1175 	return 0;
1176 }
1177 #endif
1178 
sta350_i2c_probe(struct i2c_client * i2c)1179 static int sta350_i2c_probe(struct i2c_client *i2c)
1180 {
1181 	struct device *dev = &i2c->dev;
1182 	struct sta350_priv *sta350;
1183 	int ret, i;
1184 
1185 	sta350 = devm_kzalloc(dev, sizeof(struct sta350_priv), GFP_KERNEL);
1186 	if (!sta350)
1187 		return -ENOMEM;
1188 
1189 	mutex_init(&sta350->coeff_lock);
1190 	sta350->pdata = dev_get_platdata(dev);
1191 
1192 #ifdef CONFIG_OF
1193 	if (dev->of_node) {
1194 		ret = sta350_probe_dt(dev, sta350);
1195 		if (ret < 0)
1196 			return ret;
1197 	}
1198 #endif
1199 
1200 	/* GPIOs */
1201 	sta350->gpiod_nreset = devm_gpiod_get_optional(dev, "reset",
1202 						       GPIOD_OUT_LOW);
1203 	if (IS_ERR(sta350->gpiod_nreset))
1204 		return PTR_ERR(sta350->gpiod_nreset);
1205 
1206 	sta350->gpiod_power_down = devm_gpiod_get_optional(dev, "power-down",
1207 							   GPIOD_OUT_LOW);
1208 	if (IS_ERR(sta350->gpiod_power_down))
1209 		return PTR_ERR(sta350->gpiod_power_down);
1210 
1211 	/* regulators */
1212 	for (i = 0; i < ARRAY_SIZE(sta350->supplies); i++)
1213 		sta350->supplies[i].supply = sta350_supply_names[i];
1214 
1215 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(sta350->supplies),
1216 				      sta350->supplies);
1217 	if (ret < 0) {
1218 		dev_err(dev, "Failed to request supplies: %d\n", ret);
1219 		return ret;
1220 	}
1221 
1222 	sta350->regmap = devm_regmap_init_i2c(i2c, &sta350_regmap);
1223 	if (IS_ERR(sta350->regmap)) {
1224 		ret = PTR_ERR(sta350->regmap);
1225 		dev_err(dev, "Failed to init regmap: %d\n", ret);
1226 		return ret;
1227 	}
1228 
1229 	i2c_set_clientdata(i2c, sta350);
1230 
1231 	ret = devm_snd_soc_register_component(dev, &sta350_component, &sta350_dai, 1);
1232 	if (ret < 0)
1233 		dev_err(dev, "Failed to register component (%d)\n", ret);
1234 
1235 	return ret;
1236 }
1237 
sta350_i2c_remove(struct i2c_client * client)1238 static void sta350_i2c_remove(struct i2c_client *client)
1239 {}
1240 
1241 static const struct i2c_device_id sta350_i2c_id[] = {
1242 	{ "sta350", 0 },
1243 	{ }
1244 };
1245 MODULE_DEVICE_TABLE(i2c, sta350_i2c_id);
1246 
1247 static struct i2c_driver sta350_i2c_driver = {
1248 	.driver = {
1249 		.name = "sta350",
1250 		.of_match_table = of_match_ptr(st350_dt_ids),
1251 	},
1252 	.probe =    sta350_i2c_probe,
1253 	.remove =   sta350_i2c_remove,
1254 	.id_table = sta350_i2c_id,
1255 };
1256 
1257 module_i2c_driver(sta350_i2c_driver);
1258 
1259 MODULE_DESCRIPTION("ASoC STA350 driver");
1260 MODULE_AUTHOR("Sven Brandau <info@brandau.biz>");
1261 MODULE_LICENSE("GPL");
1262