1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Host side test driver to test endpoint functionality
4 *
5 * Copyright (C) 2017 Texas Instruments
6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
7 */
8
9 #include <linux/crc32.h>
10 #include <linux/delay.h>
11 #include <linux/fs.h>
12 #include <linux/io.h>
13 #include <linux/interrupt.h>
14 #include <linux/irq.h>
15 #include <linux/miscdevice.h>
16 #include <linux/module.h>
17 #include <linux/mutex.h>
18 #include <linux/random.h>
19 #include <linux/slab.h>
20 #include <linux/uaccess.h>
21 #include <linux/pci.h>
22 #include <linux/pci_ids.h>
23
24 #include <linux/pci_regs.h>
25
26 #include <uapi/linux/pcitest.h>
27
28 #define DRV_MODULE_NAME "pci-endpoint-test"
29
30 #define IRQ_TYPE_UNDEFINED -1
31 #define IRQ_TYPE_LEGACY 0
32 #define IRQ_TYPE_MSI 1
33 #define IRQ_TYPE_MSIX 2
34
35 #define PCI_ENDPOINT_TEST_MAGIC 0x0
36
37 #define PCI_ENDPOINT_TEST_COMMAND 0x4
38 #define COMMAND_RAISE_LEGACY_IRQ BIT(0)
39 #define COMMAND_RAISE_MSI_IRQ BIT(1)
40 #define COMMAND_RAISE_MSIX_IRQ BIT(2)
41 #define COMMAND_READ BIT(3)
42 #define COMMAND_WRITE BIT(4)
43 #define COMMAND_COPY BIT(5)
44
45 #define PCI_ENDPOINT_TEST_STATUS 0x8
46 #define STATUS_READ_SUCCESS BIT(0)
47 #define STATUS_READ_FAIL BIT(1)
48 #define STATUS_WRITE_SUCCESS BIT(2)
49 #define STATUS_WRITE_FAIL BIT(3)
50 #define STATUS_COPY_SUCCESS BIT(4)
51 #define STATUS_COPY_FAIL BIT(5)
52 #define STATUS_IRQ_RAISED BIT(6)
53 #define STATUS_SRC_ADDR_INVALID BIT(7)
54 #define STATUS_DST_ADDR_INVALID BIT(8)
55
56 #define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR 0x0c
57 #define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR 0x10
58
59 #define PCI_ENDPOINT_TEST_LOWER_DST_ADDR 0x14
60 #define PCI_ENDPOINT_TEST_UPPER_DST_ADDR 0x18
61
62 #define PCI_ENDPOINT_TEST_SIZE 0x1c
63 #define PCI_ENDPOINT_TEST_CHECKSUM 0x20
64
65 #define PCI_ENDPOINT_TEST_IRQ_TYPE 0x24
66 #define PCI_ENDPOINT_TEST_IRQ_NUMBER 0x28
67
68 #define PCI_ENDPOINT_TEST_FLAGS 0x2c
69 #define FLAG_USE_DMA BIT(0)
70
71 #define PCI_DEVICE_ID_TI_AM654 0xb00c
72 #define PCI_DEVICE_ID_TI_J7200 0xb00f
73 #define PCI_DEVICE_ID_TI_AM64 0xb010
74 #define PCI_DEVICE_ID_TI_J721S2 0xb013
75 #define PCI_DEVICE_ID_LS1088A 0x80c0
76 #define PCI_DEVICE_ID_IMX8 0x0808
77
78 #define is_am654_pci_dev(pdev) \
79 ((pdev)->device == PCI_DEVICE_ID_TI_AM654)
80
81 #define PCI_DEVICE_ID_RENESAS_R8A774A1 0x0028
82 #define PCI_DEVICE_ID_RENESAS_R8A774B1 0x002b
83 #define PCI_DEVICE_ID_RENESAS_R8A774C0 0x002d
84 #define PCI_DEVICE_ID_RENESAS_R8A774E1 0x0025
85 #define PCI_DEVICE_ID_RENESAS_R8A779F0 0x0031
86
87 static DEFINE_IDA(pci_endpoint_test_ida);
88
89 #define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
90 miscdev)
91
92 static bool no_msi;
93 module_param(no_msi, bool, 0444);
94 MODULE_PARM_DESC(no_msi, "Disable MSI interrupt in pci_endpoint_test");
95
96 static int irq_type = IRQ_TYPE_MSI;
97 module_param(irq_type, int, 0444);
98 MODULE_PARM_DESC(irq_type, "IRQ mode selection in pci_endpoint_test (0 - Legacy, 1 - MSI, 2 - MSI-X)");
99
100 enum pci_barno {
101 BAR_0,
102 BAR_1,
103 BAR_2,
104 BAR_3,
105 BAR_4,
106 BAR_5,
107 };
108
109 struct pci_endpoint_test {
110 struct pci_dev *pdev;
111 void __iomem *base;
112 void __iomem *bar[PCI_STD_NUM_BARS];
113 struct completion irq_raised;
114 int last_irq;
115 int num_irqs;
116 int irq_type;
117 /* mutex to protect the ioctls */
118 struct mutex mutex;
119 struct miscdevice miscdev;
120 enum pci_barno test_reg_bar;
121 size_t alignment;
122 const char *name;
123 };
124
125 struct pci_endpoint_test_data {
126 enum pci_barno test_reg_bar;
127 size_t alignment;
128 int irq_type;
129 };
130
pci_endpoint_test_readl(struct pci_endpoint_test * test,u32 offset)131 static inline u32 pci_endpoint_test_readl(struct pci_endpoint_test *test,
132 u32 offset)
133 {
134 return readl(test->base + offset);
135 }
136
pci_endpoint_test_writel(struct pci_endpoint_test * test,u32 offset,u32 value)137 static inline void pci_endpoint_test_writel(struct pci_endpoint_test *test,
138 u32 offset, u32 value)
139 {
140 writel(value, test->base + offset);
141 }
142
pci_endpoint_test_bar_readl(struct pci_endpoint_test * test,int bar,int offset)143 static inline u32 pci_endpoint_test_bar_readl(struct pci_endpoint_test *test,
144 int bar, int offset)
145 {
146 return readl(test->bar[bar] + offset);
147 }
148
pci_endpoint_test_bar_writel(struct pci_endpoint_test * test,int bar,u32 offset,u32 value)149 static inline void pci_endpoint_test_bar_writel(struct pci_endpoint_test *test,
150 int bar, u32 offset, u32 value)
151 {
152 writel(value, test->bar[bar] + offset);
153 }
154
pci_endpoint_test_irqhandler(int irq,void * dev_id)155 static irqreturn_t pci_endpoint_test_irqhandler(int irq, void *dev_id)
156 {
157 struct pci_endpoint_test *test = dev_id;
158 u32 reg;
159
160 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
161 if (reg & STATUS_IRQ_RAISED) {
162 test->last_irq = irq;
163 complete(&test->irq_raised);
164 }
165
166 return IRQ_HANDLED;
167 }
168
pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test * test)169 static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test)
170 {
171 struct pci_dev *pdev = test->pdev;
172
173 pci_free_irq_vectors(pdev);
174 test->irq_type = IRQ_TYPE_UNDEFINED;
175 }
176
pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test * test,int type)177 static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test,
178 int type)
179 {
180 int irq = -1;
181 struct pci_dev *pdev = test->pdev;
182 struct device *dev = &pdev->dev;
183 bool res = true;
184
185 switch (type) {
186 case IRQ_TYPE_LEGACY:
187 irq = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
188 if (irq < 0)
189 dev_err(dev, "Failed to get Legacy interrupt\n");
190 break;
191 case IRQ_TYPE_MSI:
192 irq = pci_alloc_irq_vectors(pdev, 1, 32, PCI_IRQ_MSI);
193 if (irq < 0)
194 dev_err(dev, "Failed to get MSI interrupts\n");
195 break;
196 case IRQ_TYPE_MSIX:
197 irq = pci_alloc_irq_vectors(pdev, 1, 2048, PCI_IRQ_MSIX);
198 if (irq < 0)
199 dev_err(dev, "Failed to get MSI-X interrupts\n");
200 break;
201 default:
202 dev_err(dev, "Invalid IRQ type selected\n");
203 }
204
205 if (irq < 0) {
206 irq = 0;
207 res = false;
208 }
209
210 test->irq_type = type;
211 test->num_irqs = irq;
212
213 return res;
214 }
215
pci_endpoint_test_release_irq(struct pci_endpoint_test * test)216 static void pci_endpoint_test_release_irq(struct pci_endpoint_test *test)
217 {
218 int i;
219 struct pci_dev *pdev = test->pdev;
220 struct device *dev = &pdev->dev;
221
222 for (i = 0; i < test->num_irqs; i++)
223 devm_free_irq(dev, pci_irq_vector(pdev, i), test);
224
225 test->num_irqs = 0;
226 }
227
pci_endpoint_test_request_irq(struct pci_endpoint_test * test)228 static bool pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
229 {
230 int i;
231 int err;
232 struct pci_dev *pdev = test->pdev;
233 struct device *dev = &pdev->dev;
234
235 for (i = 0; i < test->num_irqs; i++) {
236 err = devm_request_irq(dev, pci_irq_vector(pdev, i),
237 pci_endpoint_test_irqhandler,
238 IRQF_SHARED, test->name, test);
239 if (err)
240 goto fail;
241 }
242
243 return true;
244
245 fail:
246 switch (test->irq_type) {
247 case IRQ_TYPE_LEGACY:
248 dev_err(dev, "Failed to request IRQ %d for Legacy\n",
249 pci_irq_vector(pdev, i));
250 break;
251 case IRQ_TYPE_MSI:
252 dev_err(dev, "Failed to request IRQ %d for MSI %d\n",
253 pci_irq_vector(pdev, i),
254 i + 1);
255 break;
256 case IRQ_TYPE_MSIX:
257 dev_err(dev, "Failed to request IRQ %d for MSI-X %d\n",
258 pci_irq_vector(pdev, i),
259 i + 1);
260 break;
261 }
262
263 test->num_irqs = i;
264 pci_endpoint_test_release_irq(test);
265
266 return false;
267 }
268
pci_endpoint_test_bar(struct pci_endpoint_test * test,enum pci_barno barno)269 static bool pci_endpoint_test_bar(struct pci_endpoint_test *test,
270 enum pci_barno barno)
271 {
272 int j;
273 u32 val;
274 int size;
275 struct pci_dev *pdev = test->pdev;
276
277 if (!test->bar[barno])
278 return false;
279
280 size = pci_resource_len(pdev, barno);
281
282 if (barno == test->test_reg_bar)
283 size = 0x4;
284
285 for (j = 0; j < size; j += 4)
286 pci_endpoint_test_bar_writel(test, barno, j, 0xA0A0A0A0);
287
288 for (j = 0; j < size; j += 4) {
289 val = pci_endpoint_test_bar_readl(test, barno, j);
290 if (val != 0xA0A0A0A0)
291 return false;
292 }
293
294 return true;
295 }
296
pci_endpoint_test_legacy_irq(struct pci_endpoint_test * test)297 static bool pci_endpoint_test_legacy_irq(struct pci_endpoint_test *test)
298 {
299 u32 val;
300
301 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
302 IRQ_TYPE_LEGACY);
303 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 0);
304 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
305 COMMAND_RAISE_LEGACY_IRQ);
306 val = wait_for_completion_timeout(&test->irq_raised,
307 msecs_to_jiffies(1000));
308 if (!val)
309 return false;
310
311 return true;
312 }
313
pci_endpoint_test_msi_irq(struct pci_endpoint_test * test,u16 msi_num,bool msix)314 static bool pci_endpoint_test_msi_irq(struct pci_endpoint_test *test,
315 u16 msi_num, bool msix)
316 {
317 u32 val;
318 struct pci_dev *pdev = test->pdev;
319
320 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE,
321 msix ? IRQ_TYPE_MSIX : IRQ_TYPE_MSI);
322 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, msi_num);
323 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
324 msix ? COMMAND_RAISE_MSIX_IRQ :
325 COMMAND_RAISE_MSI_IRQ);
326 val = wait_for_completion_timeout(&test->irq_raised,
327 msecs_to_jiffies(1000));
328 if (!val)
329 return false;
330
331 return pci_irq_vector(pdev, msi_num - 1) == test->last_irq;
332 }
333
pci_endpoint_test_validate_xfer_params(struct device * dev,struct pci_endpoint_test_xfer_param * param,size_t alignment)334 static int pci_endpoint_test_validate_xfer_params(struct device *dev,
335 struct pci_endpoint_test_xfer_param *param, size_t alignment)
336 {
337 if (!param->size) {
338 dev_dbg(dev, "Data size is zero\n");
339 return -EINVAL;
340 }
341
342 if (param->size > SIZE_MAX - alignment) {
343 dev_dbg(dev, "Maximum transfer data size exceeded\n");
344 return -EINVAL;
345 }
346
347 return 0;
348 }
349
pci_endpoint_test_copy(struct pci_endpoint_test * test,unsigned long arg)350 static bool pci_endpoint_test_copy(struct pci_endpoint_test *test,
351 unsigned long arg)
352 {
353 struct pci_endpoint_test_xfer_param param;
354 bool ret = false;
355 void *src_addr;
356 void *dst_addr;
357 u32 flags = 0;
358 bool use_dma;
359 size_t size;
360 dma_addr_t src_phys_addr;
361 dma_addr_t dst_phys_addr;
362 struct pci_dev *pdev = test->pdev;
363 struct device *dev = &pdev->dev;
364 void *orig_src_addr;
365 dma_addr_t orig_src_phys_addr;
366 void *orig_dst_addr;
367 dma_addr_t orig_dst_phys_addr;
368 size_t offset;
369 size_t alignment = test->alignment;
370 int irq_type = test->irq_type;
371 u32 src_crc32;
372 u32 dst_crc32;
373 int err;
374
375 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
376 if (err) {
377 dev_err(dev, "Failed to get transfer param\n");
378 return false;
379 }
380
381 err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment);
382 if (err)
383 return false;
384
385 size = param.size;
386
387 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
388 if (use_dma)
389 flags |= FLAG_USE_DMA;
390
391 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
392 dev_err(dev, "Invalid IRQ type option\n");
393 goto err;
394 }
395
396 orig_src_addr = kzalloc(size + alignment, GFP_KERNEL);
397 if (!orig_src_addr) {
398 dev_err(dev, "Failed to allocate source buffer\n");
399 ret = false;
400 goto err;
401 }
402
403 get_random_bytes(orig_src_addr, size + alignment);
404 orig_src_phys_addr = dma_map_single(dev, orig_src_addr,
405 size + alignment, DMA_TO_DEVICE);
406 if (dma_mapping_error(dev, orig_src_phys_addr)) {
407 dev_err(dev, "failed to map source buffer address\n");
408 ret = false;
409 goto err_src_phys_addr;
410 }
411
412 if (alignment && !IS_ALIGNED(orig_src_phys_addr, alignment)) {
413 src_phys_addr = PTR_ALIGN(orig_src_phys_addr, alignment);
414 offset = src_phys_addr - orig_src_phys_addr;
415 src_addr = orig_src_addr + offset;
416 } else {
417 src_phys_addr = orig_src_phys_addr;
418 src_addr = orig_src_addr;
419 }
420
421 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
422 lower_32_bits(src_phys_addr));
423
424 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
425 upper_32_bits(src_phys_addr));
426
427 src_crc32 = crc32_le(~0, src_addr, size);
428
429 orig_dst_addr = kzalloc(size + alignment, GFP_KERNEL);
430 if (!orig_dst_addr) {
431 dev_err(dev, "Failed to allocate destination address\n");
432 ret = false;
433 goto err_dst_addr;
434 }
435
436 orig_dst_phys_addr = dma_map_single(dev, orig_dst_addr,
437 size + alignment, DMA_FROM_DEVICE);
438 if (dma_mapping_error(dev, orig_dst_phys_addr)) {
439 dev_err(dev, "failed to map destination buffer address\n");
440 ret = false;
441 goto err_dst_phys_addr;
442 }
443
444 if (alignment && !IS_ALIGNED(orig_dst_phys_addr, alignment)) {
445 dst_phys_addr = PTR_ALIGN(orig_dst_phys_addr, alignment);
446 offset = dst_phys_addr - orig_dst_phys_addr;
447 dst_addr = orig_dst_addr + offset;
448 } else {
449 dst_phys_addr = orig_dst_phys_addr;
450 dst_addr = orig_dst_addr;
451 }
452
453 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
454 lower_32_bits(dst_phys_addr));
455 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
456 upper_32_bits(dst_phys_addr));
457
458 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE,
459 size);
460
461 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
462 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
463 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
464 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
465 COMMAND_COPY);
466
467 wait_for_completion(&test->irq_raised);
468
469 dma_unmap_single(dev, orig_dst_phys_addr, size + alignment,
470 DMA_FROM_DEVICE);
471
472 dst_crc32 = crc32_le(~0, dst_addr, size);
473 if (dst_crc32 == src_crc32)
474 ret = true;
475
476 err_dst_phys_addr:
477 kfree(orig_dst_addr);
478
479 err_dst_addr:
480 dma_unmap_single(dev, orig_src_phys_addr, size + alignment,
481 DMA_TO_DEVICE);
482
483 err_src_phys_addr:
484 kfree(orig_src_addr);
485
486 err:
487 return ret;
488 }
489
pci_endpoint_test_write(struct pci_endpoint_test * test,unsigned long arg)490 static bool pci_endpoint_test_write(struct pci_endpoint_test *test,
491 unsigned long arg)
492 {
493 struct pci_endpoint_test_xfer_param param;
494 bool ret = false;
495 u32 flags = 0;
496 bool use_dma;
497 u32 reg;
498 void *addr;
499 dma_addr_t phys_addr;
500 struct pci_dev *pdev = test->pdev;
501 struct device *dev = &pdev->dev;
502 void *orig_addr;
503 dma_addr_t orig_phys_addr;
504 size_t offset;
505 size_t alignment = test->alignment;
506 int irq_type = test->irq_type;
507 size_t size;
508 u32 crc32;
509 int err;
510
511 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
512 if (err != 0) {
513 dev_err(dev, "Failed to get transfer param\n");
514 return false;
515 }
516
517 err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment);
518 if (err)
519 return false;
520
521 size = param.size;
522
523 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
524 if (use_dma)
525 flags |= FLAG_USE_DMA;
526
527 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
528 dev_err(dev, "Invalid IRQ type option\n");
529 goto err;
530 }
531
532 orig_addr = kzalloc(size + alignment, GFP_KERNEL);
533 if (!orig_addr) {
534 dev_err(dev, "Failed to allocate address\n");
535 ret = false;
536 goto err;
537 }
538
539 get_random_bytes(orig_addr, size + alignment);
540
541 orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
542 DMA_TO_DEVICE);
543 if (dma_mapping_error(dev, orig_phys_addr)) {
544 dev_err(dev, "failed to map source buffer address\n");
545 ret = false;
546 goto err_phys_addr;
547 }
548
549 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
550 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
551 offset = phys_addr - orig_phys_addr;
552 addr = orig_addr + offset;
553 } else {
554 phys_addr = orig_phys_addr;
555 addr = orig_addr;
556 }
557
558 crc32 = crc32_le(~0, addr, size);
559 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_CHECKSUM,
560 crc32);
561
562 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_SRC_ADDR,
563 lower_32_bits(phys_addr));
564 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_SRC_ADDR,
565 upper_32_bits(phys_addr));
566
567 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
568
569 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
570 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
571 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
572 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
573 COMMAND_READ);
574
575 wait_for_completion(&test->irq_raised);
576
577 reg = pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_STATUS);
578 if (reg & STATUS_READ_SUCCESS)
579 ret = true;
580
581 dma_unmap_single(dev, orig_phys_addr, size + alignment,
582 DMA_TO_DEVICE);
583
584 err_phys_addr:
585 kfree(orig_addr);
586
587 err:
588 return ret;
589 }
590
pci_endpoint_test_read(struct pci_endpoint_test * test,unsigned long arg)591 static bool pci_endpoint_test_read(struct pci_endpoint_test *test,
592 unsigned long arg)
593 {
594 struct pci_endpoint_test_xfer_param param;
595 bool ret = false;
596 u32 flags = 0;
597 bool use_dma;
598 size_t size;
599 void *addr;
600 dma_addr_t phys_addr;
601 struct pci_dev *pdev = test->pdev;
602 struct device *dev = &pdev->dev;
603 void *orig_addr;
604 dma_addr_t orig_phys_addr;
605 size_t offset;
606 size_t alignment = test->alignment;
607 int irq_type = test->irq_type;
608 u32 crc32;
609 int err;
610
611 err = copy_from_user(¶m, (void __user *)arg, sizeof(param));
612 if (err) {
613 dev_err(dev, "Failed to get transfer param\n");
614 return false;
615 }
616
617 err = pci_endpoint_test_validate_xfer_params(dev, ¶m, alignment);
618 if (err)
619 return false;
620
621 size = param.size;
622
623 use_dma = !!(param.flags & PCITEST_FLAGS_USE_DMA);
624 if (use_dma)
625 flags |= FLAG_USE_DMA;
626
627 if (irq_type < IRQ_TYPE_LEGACY || irq_type > IRQ_TYPE_MSIX) {
628 dev_err(dev, "Invalid IRQ type option\n");
629 goto err;
630 }
631
632 orig_addr = kzalloc(size + alignment, GFP_KERNEL);
633 if (!orig_addr) {
634 dev_err(dev, "Failed to allocate destination address\n");
635 ret = false;
636 goto err;
637 }
638
639 orig_phys_addr = dma_map_single(dev, orig_addr, size + alignment,
640 DMA_FROM_DEVICE);
641 if (dma_mapping_error(dev, orig_phys_addr)) {
642 dev_err(dev, "failed to map source buffer address\n");
643 ret = false;
644 goto err_phys_addr;
645 }
646
647 if (alignment && !IS_ALIGNED(orig_phys_addr, alignment)) {
648 phys_addr = PTR_ALIGN(orig_phys_addr, alignment);
649 offset = phys_addr - orig_phys_addr;
650 addr = orig_addr + offset;
651 } else {
652 phys_addr = orig_phys_addr;
653 addr = orig_addr;
654 }
655
656 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_LOWER_DST_ADDR,
657 lower_32_bits(phys_addr));
658 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_UPPER_DST_ADDR,
659 upper_32_bits(phys_addr));
660
661 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_SIZE, size);
662
663 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_FLAGS, flags);
664 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_TYPE, irq_type);
665 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_IRQ_NUMBER, 1);
666 pci_endpoint_test_writel(test, PCI_ENDPOINT_TEST_COMMAND,
667 COMMAND_WRITE);
668
669 wait_for_completion(&test->irq_raised);
670
671 dma_unmap_single(dev, orig_phys_addr, size + alignment,
672 DMA_FROM_DEVICE);
673
674 crc32 = crc32_le(~0, addr, size);
675 if (crc32 == pci_endpoint_test_readl(test, PCI_ENDPOINT_TEST_CHECKSUM))
676 ret = true;
677
678 err_phys_addr:
679 kfree(orig_addr);
680 err:
681 return ret;
682 }
683
pci_endpoint_test_clear_irq(struct pci_endpoint_test * test)684 static bool pci_endpoint_test_clear_irq(struct pci_endpoint_test *test)
685 {
686 pci_endpoint_test_release_irq(test);
687 pci_endpoint_test_free_irq_vectors(test);
688 return true;
689 }
690
pci_endpoint_test_set_irq(struct pci_endpoint_test * test,int req_irq_type)691 static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test,
692 int req_irq_type)
693 {
694 struct pci_dev *pdev = test->pdev;
695 struct device *dev = &pdev->dev;
696
697 if (req_irq_type < IRQ_TYPE_LEGACY || req_irq_type > IRQ_TYPE_MSIX) {
698 dev_err(dev, "Invalid IRQ type option\n");
699 return false;
700 }
701
702 if (test->irq_type == req_irq_type)
703 return true;
704
705 pci_endpoint_test_release_irq(test);
706 pci_endpoint_test_free_irq_vectors(test);
707
708 if (!pci_endpoint_test_alloc_irq_vectors(test, req_irq_type))
709 goto err;
710
711 if (!pci_endpoint_test_request_irq(test))
712 goto err;
713
714 irq_type = test->irq_type;
715 return true;
716
717 err:
718 pci_endpoint_test_free_irq_vectors(test);
719 return false;
720 }
721
pci_endpoint_test_ioctl(struct file * file,unsigned int cmd,unsigned long arg)722 static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
723 unsigned long arg)
724 {
725 int ret = -EINVAL;
726 enum pci_barno bar;
727 struct pci_endpoint_test *test = to_endpoint_test(file->private_data);
728 struct pci_dev *pdev = test->pdev;
729
730 mutex_lock(&test->mutex);
731
732 reinit_completion(&test->irq_raised);
733 test->last_irq = -ENODATA;
734
735 switch (cmd) {
736 case PCITEST_BAR:
737 bar = arg;
738 if (bar > BAR_5)
739 goto ret;
740 if (is_am654_pci_dev(pdev) && bar == BAR_0)
741 goto ret;
742 ret = pci_endpoint_test_bar(test, bar);
743 break;
744 case PCITEST_LEGACY_IRQ:
745 ret = pci_endpoint_test_legacy_irq(test);
746 break;
747 case PCITEST_MSI:
748 case PCITEST_MSIX:
749 ret = pci_endpoint_test_msi_irq(test, arg, cmd == PCITEST_MSIX);
750 break;
751 case PCITEST_WRITE:
752 ret = pci_endpoint_test_write(test, arg);
753 break;
754 case PCITEST_READ:
755 ret = pci_endpoint_test_read(test, arg);
756 break;
757 case PCITEST_COPY:
758 ret = pci_endpoint_test_copy(test, arg);
759 break;
760 case PCITEST_SET_IRQTYPE:
761 ret = pci_endpoint_test_set_irq(test, arg);
762 break;
763 case PCITEST_GET_IRQTYPE:
764 ret = irq_type;
765 break;
766 case PCITEST_CLEAR_IRQ:
767 ret = pci_endpoint_test_clear_irq(test);
768 break;
769 }
770
771 ret:
772 mutex_unlock(&test->mutex);
773 return ret;
774 }
775
776 static const struct file_operations pci_endpoint_test_fops = {
777 .owner = THIS_MODULE,
778 .unlocked_ioctl = pci_endpoint_test_ioctl,
779 };
780
pci_endpoint_test_probe(struct pci_dev * pdev,const struct pci_device_id * ent)781 static int pci_endpoint_test_probe(struct pci_dev *pdev,
782 const struct pci_device_id *ent)
783 {
784 int err;
785 int id;
786 char name[24];
787 enum pci_barno bar;
788 void __iomem *base;
789 struct device *dev = &pdev->dev;
790 struct pci_endpoint_test *test;
791 struct pci_endpoint_test_data *data;
792 enum pci_barno test_reg_bar = BAR_0;
793 struct miscdevice *misc_device;
794
795 if (pci_is_bridge(pdev))
796 return -ENODEV;
797
798 test = devm_kzalloc(dev, sizeof(*test), GFP_KERNEL);
799 if (!test)
800 return -ENOMEM;
801
802 test->test_reg_bar = 0;
803 test->alignment = 0;
804 test->pdev = pdev;
805 test->irq_type = IRQ_TYPE_UNDEFINED;
806
807 if (no_msi)
808 irq_type = IRQ_TYPE_LEGACY;
809
810 data = (struct pci_endpoint_test_data *)ent->driver_data;
811 if (data) {
812 test_reg_bar = data->test_reg_bar;
813 test->test_reg_bar = test_reg_bar;
814 test->alignment = data->alignment;
815 irq_type = data->irq_type;
816 }
817
818 init_completion(&test->irq_raised);
819 mutex_init(&test->mutex);
820
821 if ((dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(48)) != 0) &&
822 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)) != 0) {
823 dev_err(dev, "Cannot set DMA mask\n");
824 return -EINVAL;
825 }
826
827 err = pci_enable_device(pdev);
828 if (err) {
829 dev_err(dev, "Cannot enable PCI device\n");
830 return err;
831 }
832
833 err = pci_request_regions(pdev, DRV_MODULE_NAME);
834 if (err) {
835 dev_err(dev, "Cannot obtain PCI resources\n");
836 goto err_disable_pdev;
837 }
838
839 pci_set_master(pdev);
840
841 if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type)) {
842 err = -EINVAL;
843 goto err_disable_irq;
844 }
845
846 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
847 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
848 base = pci_ioremap_bar(pdev, bar);
849 if (!base) {
850 dev_err(dev, "Failed to read BAR%d\n", bar);
851 WARN_ON(bar == test_reg_bar);
852 }
853 test->bar[bar] = base;
854 }
855 }
856
857 test->base = test->bar[test_reg_bar];
858 if (!test->base) {
859 err = -ENOMEM;
860 dev_err(dev, "Cannot perform PCI test without BAR%d\n",
861 test_reg_bar);
862 goto err_iounmap;
863 }
864
865 pci_set_drvdata(pdev, test);
866
867 id = ida_simple_get(&pci_endpoint_test_ida, 0, 0, GFP_KERNEL);
868 if (id < 0) {
869 err = id;
870 dev_err(dev, "Unable to get id\n");
871 goto err_iounmap;
872 }
873
874 snprintf(name, sizeof(name), DRV_MODULE_NAME ".%d", id);
875 test->name = kstrdup(name, GFP_KERNEL);
876 if (!test->name) {
877 err = -ENOMEM;
878 goto err_ida_remove;
879 }
880
881 if (!pci_endpoint_test_request_irq(test)) {
882 err = -EINVAL;
883 goto err_kfree_test_name;
884 }
885
886 misc_device = &test->miscdev;
887 misc_device->minor = MISC_DYNAMIC_MINOR;
888 misc_device->name = kstrdup(name, GFP_KERNEL);
889 if (!misc_device->name) {
890 err = -ENOMEM;
891 goto err_release_irq;
892 }
893 misc_device->parent = &pdev->dev;
894 misc_device->fops = &pci_endpoint_test_fops;
895
896 err = misc_register(misc_device);
897 if (err) {
898 dev_err(dev, "Failed to register device\n");
899 goto err_kfree_name;
900 }
901
902 return 0;
903
904 err_kfree_name:
905 kfree(misc_device->name);
906
907 err_release_irq:
908 pci_endpoint_test_release_irq(test);
909
910 err_kfree_test_name:
911 kfree(test->name);
912
913 err_ida_remove:
914 ida_simple_remove(&pci_endpoint_test_ida, id);
915
916 err_iounmap:
917 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
918 if (test->bar[bar])
919 pci_iounmap(pdev, test->bar[bar]);
920 }
921
922 err_disable_irq:
923 pci_endpoint_test_free_irq_vectors(test);
924 pci_release_regions(pdev);
925
926 err_disable_pdev:
927 pci_disable_device(pdev);
928
929 return err;
930 }
931
pci_endpoint_test_remove(struct pci_dev * pdev)932 static void pci_endpoint_test_remove(struct pci_dev *pdev)
933 {
934 int id;
935 enum pci_barno bar;
936 struct pci_endpoint_test *test = pci_get_drvdata(pdev);
937 struct miscdevice *misc_device = &test->miscdev;
938
939 if (sscanf(misc_device->name, DRV_MODULE_NAME ".%d", &id) != 1)
940 return;
941 if (id < 0)
942 return;
943
944 pci_endpoint_test_release_irq(test);
945 pci_endpoint_test_free_irq_vectors(test);
946
947 misc_deregister(&test->miscdev);
948 kfree(misc_device->name);
949 kfree(test->name);
950 ida_simple_remove(&pci_endpoint_test_ida, id);
951 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
952 if (test->bar[bar])
953 pci_iounmap(pdev, test->bar[bar]);
954 }
955
956 pci_release_regions(pdev);
957 pci_disable_device(pdev);
958 }
959
960 static const struct pci_endpoint_test_data default_data = {
961 .test_reg_bar = BAR_0,
962 .alignment = SZ_4K,
963 .irq_type = IRQ_TYPE_MSI,
964 };
965
966 static const struct pci_endpoint_test_data am654_data = {
967 .test_reg_bar = BAR_2,
968 .alignment = SZ_64K,
969 .irq_type = IRQ_TYPE_MSI,
970 };
971
972 static const struct pci_endpoint_test_data j721e_data = {
973 .alignment = 256,
974 .irq_type = IRQ_TYPE_MSI,
975 };
976
977 static const struct pci_device_id pci_endpoint_test_tbl[] = {
978 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x),
979 .driver_data = (kernel_ulong_t)&default_data,
980 },
981 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x),
982 .driver_data = (kernel_ulong_t)&default_data,
983 },
984 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0),
985 .driver_data = (kernel_ulong_t)&default_data,
986 },
987 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_IMX8),},
988 { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, PCI_DEVICE_ID_LS1088A),
989 .driver_data = (kernel_ulong_t)&default_data,
990 },
991 { PCI_DEVICE_DATA(SYNOPSYS, EDDA, NULL) },
992 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM654),
993 .driver_data = (kernel_ulong_t)&am654_data
994 },
995 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774A1),},
996 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774B1),},
997 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774C0),},
998 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A774E1),},
999 { PCI_DEVICE(PCI_VENDOR_ID_RENESAS, PCI_DEVICE_ID_RENESAS_R8A779F0),
1000 .driver_data = (kernel_ulong_t)&default_data,
1001 },
1002 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721E),
1003 .driver_data = (kernel_ulong_t)&j721e_data,
1004 },
1005 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J7200),
1006 .driver_data = (kernel_ulong_t)&j721e_data,
1007 },
1008 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_AM64),
1009 .driver_data = (kernel_ulong_t)&j721e_data,
1010 },
1011 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_J721S2),
1012 .driver_data = (kernel_ulong_t)&j721e_data,
1013 },
1014 { }
1015 };
1016 MODULE_DEVICE_TABLE(pci, pci_endpoint_test_tbl);
1017
1018 static struct pci_driver pci_endpoint_test_driver = {
1019 .name = DRV_MODULE_NAME,
1020 .id_table = pci_endpoint_test_tbl,
1021 .probe = pci_endpoint_test_probe,
1022 .remove = pci_endpoint_test_remove,
1023 .sriov_configure = pci_sriov_configure_simple,
1024 };
1025 module_pci_driver(pci_endpoint_test_driver);
1026
1027 MODULE_DESCRIPTION("PCI ENDPOINT TEST HOST DRIVER");
1028 MODULE_AUTHOR("Kishon Vijay Abraham I <kishon@ti.com>");
1029 MODULE_LICENSE("GPL v2");
1030