1 // SPDX-License-Identifier: GPL-2.0
2 #include <linux/kernel.h>
3 #include <linux/pgtable.h>
4
5 #include <linux/string.h>
6 #include <linux/bitops.h>
7 #include <linux/smp.h>
8 #include <linux/sched.h>
9 #include <linux/sched/clock.h>
10 #include <linux/semaphore.h>
11 #include <linux/thread_info.h>
12 #include <linux/init.h>
13 #include <linux/uaccess.h>
14 #include <linux/workqueue.h>
15 #include <linux/delay.h>
16 #include <linux/cpuhotplug.h>
17
18 #include <asm/cpufeature.h>
19 #include <asm/msr.h>
20 #include <asm/bugs.h>
21 #include <asm/cpu.h>
22 #include <asm/intel-family.h>
23 #include <asm/microcode.h>
24 #include <asm/hwcap2.h>
25 #include <asm/elf.h>
26 #include <asm/cpu_device_id.h>
27 #include <asm/cmdline.h>
28 #include <asm/traps.h>
29 #include <asm/resctrl.h>
30 #include <asm/numa.h>
31 #include <asm/thermal.h>
32
33 #ifdef CONFIG_X86_64
34 #include <linux/topology.h>
35 #endif
36
37 #include "cpu.h"
38
39 #ifdef CONFIG_X86_LOCAL_APIC
40 #include <asm/mpspec.h>
41 #include <asm/apic.h>
42 #endif
43
44 enum split_lock_detect_state {
45 sld_off = 0,
46 sld_warn,
47 sld_fatal,
48 sld_ratelimit,
49 };
50
51 /*
52 * Default to sld_off because most systems do not support split lock detection.
53 * sld_state_setup() will switch this to sld_warn on systems that support
54 * split lock/bus lock detect, unless there is a command line override.
55 */
56 static enum split_lock_detect_state sld_state __ro_after_init = sld_off;
57 static u64 msr_test_ctrl_cache __ro_after_init;
58
59 /*
60 * With a name like MSR_TEST_CTL it should go without saying, but don't touch
61 * MSR_TEST_CTL unless the CPU is one of the whitelisted models. Writing it
62 * on CPUs that do not support SLD can cause fireworks, even when writing '0'.
63 */
64 static bool cpu_model_supports_sld __ro_after_init;
65
66 /*
67 * Processors which have self-snooping capability can handle conflicting
68 * memory type across CPUs by snooping its own cache. However, there exists
69 * CPU models in which having conflicting memory types still leads to
70 * unpredictable behavior, machine check errors, or hangs. Clear this
71 * feature to prevent its use on machines with known erratas.
72 */
check_memory_type_self_snoop_errata(struct cpuinfo_x86 * c)73 static void check_memory_type_self_snoop_errata(struct cpuinfo_x86 *c)
74 {
75 switch (c->x86_vfm) {
76 case INTEL_CORE_YONAH:
77 case INTEL_CORE2_MEROM:
78 case INTEL_CORE2_MEROM_L:
79 case INTEL_CORE2_PENRYN:
80 case INTEL_CORE2_DUNNINGTON:
81 case INTEL_NEHALEM:
82 case INTEL_NEHALEM_G:
83 case INTEL_NEHALEM_EP:
84 case INTEL_NEHALEM_EX:
85 case INTEL_WESTMERE:
86 case INTEL_WESTMERE_EP:
87 case INTEL_SANDYBRIDGE:
88 setup_clear_cpu_cap(X86_FEATURE_SELFSNOOP);
89 }
90 }
91
92 static bool ring3mwait_disabled __read_mostly;
93
ring3mwait_disable(char * __unused)94 static int __init ring3mwait_disable(char *__unused)
95 {
96 ring3mwait_disabled = true;
97 return 1;
98 }
99 __setup("ring3mwait=disable", ring3mwait_disable);
100
probe_xeon_phi_r3mwait(struct cpuinfo_x86 * c)101 static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
102 {
103 /*
104 * Ring 3 MONITOR/MWAIT feature cannot be detected without
105 * cpu model and family comparison.
106 */
107 if (c->x86 != 6)
108 return;
109 switch (c->x86_vfm) {
110 case INTEL_XEON_PHI_KNL:
111 case INTEL_XEON_PHI_KNM:
112 break;
113 default:
114 return;
115 }
116
117 if (ring3mwait_disabled)
118 return;
119
120 set_cpu_cap(c, X86_FEATURE_RING3MWAIT);
121 this_cpu_or(msr_misc_features_shadow,
122 1UL << MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT);
123
124 if (c == &boot_cpu_data)
125 ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
126 }
127
128 /*
129 * Early microcode releases for the Spectre v2 mitigation were broken.
130 * Information taken from;
131 * - https://newsroom.intel.com/wp-content/uploads/sites/11/2018/03/microcode-update-guidance.pdf
132 * - https://kb.vmware.com/s/article/52345
133 * - Microcode revisions observed in the wild
134 * - Release note from 20180108 microcode release
135 */
136 struct sku_microcode {
137 u32 vfm;
138 u8 stepping;
139 u32 microcode;
140 };
141 static const struct sku_microcode spectre_bad_microcodes[] = {
142 { INTEL_KABYLAKE, 0x0B, 0x80 },
143 { INTEL_KABYLAKE, 0x0A, 0x80 },
144 { INTEL_KABYLAKE, 0x09, 0x80 },
145 { INTEL_KABYLAKE_L, 0x0A, 0x80 },
146 { INTEL_KABYLAKE_L, 0x09, 0x80 },
147 { INTEL_SKYLAKE_X, 0x03, 0x0100013e },
148 { INTEL_SKYLAKE_X, 0x04, 0x0200003c },
149 { INTEL_BROADWELL, 0x04, 0x28 },
150 { INTEL_BROADWELL_G, 0x01, 0x1b },
151 { INTEL_BROADWELL_D, 0x02, 0x14 },
152 { INTEL_BROADWELL_D, 0x03, 0x07000011 },
153 { INTEL_BROADWELL_X, 0x01, 0x0b000025 },
154 { INTEL_HASWELL_L, 0x01, 0x21 },
155 { INTEL_HASWELL_G, 0x01, 0x18 },
156 { INTEL_HASWELL, 0x03, 0x23 },
157 { INTEL_HASWELL_X, 0x02, 0x3b },
158 { INTEL_HASWELL_X, 0x04, 0x10 },
159 { INTEL_IVYBRIDGE_X, 0x04, 0x42a },
160 /* Observed in the wild */
161 { INTEL_SANDYBRIDGE_X, 0x06, 0x61b },
162 { INTEL_SANDYBRIDGE_X, 0x07, 0x712 },
163 };
164
bad_spectre_microcode(struct cpuinfo_x86 * c)165 static bool bad_spectre_microcode(struct cpuinfo_x86 *c)
166 {
167 int i;
168
169 /*
170 * We know that the hypervisor lie to us on the microcode version so
171 * we may as well hope that it is running the correct version.
172 */
173 if (cpu_has(c, X86_FEATURE_HYPERVISOR))
174 return false;
175
176 for (i = 0; i < ARRAY_SIZE(spectre_bad_microcodes); i++) {
177 if (c->x86_vfm == spectre_bad_microcodes[i].vfm &&
178 c->x86_stepping == spectre_bad_microcodes[i].stepping)
179 return (c->microcode <= spectre_bad_microcodes[i].microcode);
180 }
181 return false;
182 }
183
184 #define MSR_IA32_TME_ACTIVATE 0x982
185
186 /* Helpers to access TME_ACTIVATE MSR */
187 #define TME_ACTIVATE_LOCKED(x) (x & 0x1)
188 #define TME_ACTIVATE_ENABLED(x) (x & 0x2)
189
190 #define TME_ACTIVATE_POLICY(x) ((x >> 4) & 0xf) /* Bits 7:4 */
191 #define TME_ACTIVATE_POLICY_AES_XTS_128 0
192
193 #define TME_ACTIVATE_KEYID_BITS(x) ((x >> 32) & 0xf) /* Bits 35:32 */
194
195 #define TME_ACTIVATE_CRYPTO_ALGS(x) ((x >> 48) & 0xffff) /* Bits 63:48 */
196 #define TME_ACTIVATE_CRYPTO_AES_XTS_128 1
197
198 /* Values for mktme_status (SW only construct) */
199 #define MKTME_ENABLED 0
200 #define MKTME_DISABLED 1
201 #define MKTME_UNINITIALIZED 2
202 static int mktme_status = MKTME_UNINITIALIZED;
203
detect_tme_early(struct cpuinfo_x86 * c)204 static void detect_tme_early(struct cpuinfo_x86 *c)
205 {
206 u64 tme_activate, tme_policy, tme_crypto_algs;
207 int keyid_bits = 0, nr_keyids = 0;
208 static u64 tme_activate_cpu0 = 0;
209
210 rdmsrl(MSR_IA32_TME_ACTIVATE, tme_activate);
211
212 if (mktme_status != MKTME_UNINITIALIZED) {
213 if (tme_activate != tme_activate_cpu0) {
214 /* Broken BIOS? */
215 pr_err_once("x86/tme: configuration is inconsistent between CPUs\n");
216 pr_err_once("x86/tme: MKTME is not usable\n");
217 mktme_status = MKTME_DISABLED;
218
219 /* Proceed. We may need to exclude bits from x86_phys_bits. */
220 }
221 } else {
222 tme_activate_cpu0 = tme_activate;
223 }
224
225 if (!TME_ACTIVATE_LOCKED(tme_activate) || !TME_ACTIVATE_ENABLED(tme_activate)) {
226 pr_info_once("x86/tme: not enabled by BIOS\n");
227 mktme_status = MKTME_DISABLED;
228 return;
229 }
230
231 if (mktme_status != MKTME_UNINITIALIZED)
232 goto detect_keyid_bits;
233
234 pr_info("x86/tme: enabled by BIOS\n");
235
236 tme_policy = TME_ACTIVATE_POLICY(tme_activate);
237 if (tme_policy != TME_ACTIVATE_POLICY_AES_XTS_128)
238 pr_warn("x86/tme: Unknown policy is active: %#llx\n", tme_policy);
239
240 tme_crypto_algs = TME_ACTIVATE_CRYPTO_ALGS(tme_activate);
241 if (!(tme_crypto_algs & TME_ACTIVATE_CRYPTO_AES_XTS_128)) {
242 pr_err("x86/mktme: No known encryption algorithm is supported: %#llx\n",
243 tme_crypto_algs);
244 mktme_status = MKTME_DISABLED;
245 }
246 detect_keyid_bits:
247 keyid_bits = TME_ACTIVATE_KEYID_BITS(tme_activate);
248 nr_keyids = (1UL << keyid_bits) - 1;
249 if (nr_keyids) {
250 pr_info_once("x86/mktme: enabled by BIOS\n");
251 pr_info_once("x86/mktme: %d KeyIDs available\n", nr_keyids);
252 } else {
253 pr_info_once("x86/mktme: disabled by BIOS\n");
254 }
255
256 if (mktme_status == MKTME_UNINITIALIZED) {
257 /* MKTME is usable */
258 mktme_status = MKTME_ENABLED;
259 }
260
261 /*
262 * KeyID bits effectively lower the number of physical address
263 * bits. Update cpuinfo_x86::x86_phys_bits accordingly.
264 */
265 c->x86_phys_bits -= keyid_bits;
266 }
267
early_init_intel(struct cpuinfo_x86 * c)268 static void early_init_intel(struct cpuinfo_x86 *c)
269 {
270 u64 misc_enable;
271
272 /* Unmask CPUID levels if masked: */
273 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
274 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
275 MSR_IA32_MISC_ENABLE_LIMIT_CPUID_BIT) > 0) {
276 c->cpuid_level = cpuid_eax(0);
277 get_cpu_cap(c);
278 }
279 }
280
281 if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
282 (c->x86 == 0x6 && c->x86_model >= 0x0e))
283 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
284
285 if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
286 c->microcode = intel_get_microcode_revision();
287
288 /* Now if any of them are set, check the blacklist and clear the lot */
289 if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
290 cpu_has(c, X86_FEATURE_INTEL_STIBP) ||
291 cpu_has(c, X86_FEATURE_IBRS) || cpu_has(c, X86_FEATURE_IBPB) ||
292 cpu_has(c, X86_FEATURE_STIBP)) && bad_spectre_microcode(c)) {
293 pr_warn("Intel Spectre v2 broken microcode detected; disabling Speculation Control\n");
294 setup_clear_cpu_cap(X86_FEATURE_IBRS);
295 setup_clear_cpu_cap(X86_FEATURE_IBPB);
296 setup_clear_cpu_cap(X86_FEATURE_STIBP);
297 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL);
298 setup_clear_cpu_cap(X86_FEATURE_MSR_SPEC_CTRL);
299 setup_clear_cpu_cap(X86_FEATURE_INTEL_STIBP);
300 setup_clear_cpu_cap(X86_FEATURE_SSBD);
301 setup_clear_cpu_cap(X86_FEATURE_SPEC_CTRL_SSBD);
302 }
303
304 /*
305 * Atom erratum AAE44/AAF40/AAG38/AAH41:
306 *
307 * A race condition between speculative fetches and invalidating
308 * a large page. This is worked around in microcode, but we
309 * need the microcode to have already been loaded... so if it is
310 * not, recommend a BIOS update and disable large pages.
311 */
312 if (c->x86_vfm == INTEL_ATOM_BONNELL && c->x86_stepping <= 2 &&
313 c->microcode < 0x20e) {
314 pr_warn("Atom PSE erratum detected, BIOS microcode update recommended\n");
315 clear_cpu_cap(c, X86_FEATURE_PSE);
316 }
317
318 #ifdef CONFIG_X86_64
319 set_cpu_cap(c, X86_FEATURE_SYSENTER32);
320 #else
321 /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
322 if (c->x86 == 15 && c->x86_cache_alignment == 64)
323 c->x86_cache_alignment = 128;
324 #endif
325
326 /* CPUID workaround for 0F33/0F34 CPU */
327 if (c->x86 == 0xF && c->x86_model == 0x3
328 && (c->x86_stepping == 0x3 || c->x86_stepping == 0x4))
329 c->x86_phys_bits = 36;
330
331 /*
332 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
333 * with P/T states and does not stop in deep C-states.
334 *
335 * It is also reliable across cores and sockets. (but not across
336 * cabinets - we turn it off in that case explicitly.)
337 */
338 if (c->x86_power & (1 << 8)) {
339 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
340 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
341 }
342
343 /* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
344 switch (c->x86_vfm) {
345 case INTEL_ATOM_SALTWELL_MID:
346 case INTEL_ATOM_SALTWELL_TABLET:
347 case INTEL_ATOM_SILVERMONT_MID:
348 case INTEL_ATOM_AIRMONT_NP:
349 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
350 break;
351 }
352
353 /*
354 * There is a known erratum on Pentium III and Core Solo
355 * and Core Duo CPUs.
356 * " Page with PAT set to WC while associated MTRR is UC
357 * may consolidate to UC "
358 * Because of this erratum, it is better to stick with
359 * setting WC in MTRR rather than using PAT on these CPUs.
360 *
361 * Enable PAT WC only on P4, Core 2 or later CPUs.
362 */
363 if (c->x86 == 6 && c->x86_model < 15)
364 clear_cpu_cap(c, X86_FEATURE_PAT);
365
366 /*
367 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
368 * clear the fast string and enhanced fast string CPU capabilities.
369 */
370 if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
371 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
372 if (!(misc_enable & MSR_IA32_MISC_ENABLE_FAST_STRING)) {
373 pr_info("Disabled fast string operations\n");
374 setup_clear_cpu_cap(X86_FEATURE_REP_GOOD);
375 setup_clear_cpu_cap(X86_FEATURE_ERMS);
376 }
377 }
378
379 /*
380 * Intel Quark Core DevMan_001.pdf section 6.4.11
381 * "The operating system also is required to invalidate (i.e., flush)
382 * the TLB when any changes are made to any of the page table entries.
383 * The operating system must reload CR3 to cause the TLB to be flushed"
384 *
385 * As a result, boot_cpu_has(X86_FEATURE_PGE) in arch/x86/include/asm/tlbflush.h
386 * should be false so that __flush_tlb_all() causes CR3 instead of CR4.PGE
387 * to be modified.
388 */
389 if (c->x86_vfm == INTEL_QUARK_X1000) {
390 pr_info("Disabling PGE capability bit\n");
391 setup_clear_cpu_cap(X86_FEATURE_PGE);
392 }
393
394 if (c->cpuid_level >= 0x00000001) {
395 u32 eax, ebx, ecx, edx;
396
397 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
398 /*
399 * If HTT (EDX[28]) is set EBX[16:23] contain the number of
400 * apicids which are reserved per package. Store the resulting
401 * shift value for the package management code.
402 */
403 if (edx & (1U << 28))
404 c->x86_coreid_bits = get_count_order((ebx >> 16) & 0xff);
405 }
406
407 check_memory_type_self_snoop_errata(c);
408
409 /*
410 * Get the number of SMT siblings early from the extended topology
411 * leaf, if available. Otherwise try the legacy SMT detection.
412 */
413 if (detect_extended_topology_early(c) < 0)
414 detect_ht_early(c);
415
416 /*
417 * Adjust the number of physical bits early because it affects the
418 * valid bits of the MTRR mask registers.
419 */
420 if (cpu_has(c, X86_FEATURE_TME))
421 detect_tme_early(c);
422 }
423
bsp_init_intel(struct cpuinfo_x86 * c)424 static void bsp_init_intel(struct cpuinfo_x86 *c)
425 {
426 resctrl_cpu_detect(c);
427 }
428
429 #ifdef CONFIG_X86_32
430 /*
431 * Early probe support logic for ppro memory erratum #50
432 *
433 * This is called before we do cpu ident work
434 */
435
ppro_with_ram_bug(void)436 int ppro_with_ram_bug(void)
437 {
438 /* Uses data from early_cpu_detect now */
439 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
440 boot_cpu_data.x86 == 6 &&
441 boot_cpu_data.x86_model == 1 &&
442 boot_cpu_data.x86_stepping < 8) {
443 pr_info("Pentium Pro with Errata#50 detected. Taking evasive action.\n");
444 return 1;
445 }
446 return 0;
447 }
448
intel_smp_check(struct cpuinfo_x86 * c)449 static void intel_smp_check(struct cpuinfo_x86 *c)
450 {
451 /* calling is from identify_secondary_cpu() ? */
452 if (!c->cpu_index)
453 return;
454
455 /*
456 * Mask B, Pentium, but not Pentium MMX
457 */
458 if (c->x86 == 5 &&
459 c->x86_stepping >= 1 && c->x86_stepping <= 4 &&
460 c->x86_model <= 3) {
461 /*
462 * Remember we have B step Pentia with bugs
463 */
464 WARN_ONCE(1, "WARNING: SMP operation may be unreliable"
465 "with B stepping processors.\n");
466 }
467 }
468
469 static int forcepae;
forcepae_setup(char * __unused)470 static int __init forcepae_setup(char *__unused)
471 {
472 forcepae = 1;
473 return 1;
474 }
475 __setup("forcepae", forcepae_setup);
476
intel_workarounds(struct cpuinfo_x86 * c)477 static void intel_workarounds(struct cpuinfo_x86 *c)
478 {
479 #ifdef CONFIG_X86_F00F_BUG
480 /*
481 * All models of Pentium and Pentium with MMX technology CPUs
482 * have the F0 0F bug, which lets nonprivileged users lock up the
483 * system. Announce that the fault handler will be checking for it.
484 * The Quark is also family 5, but does not have the same bug.
485 */
486 clear_cpu_bug(c, X86_BUG_F00F);
487 if (c->x86 == 5 && c->x86_model < 9) {
488 static int f00f_workaround_enabled;
489
490 set_cpu_bug(c, X86_BUG_F00F);
491 if (!f00f_workaround_enabled) {
492 pr_notice("Intel Pentium with F0 0F bug - workaround enabled.\n");
493 f00f_workaround_enabled = 1;
494 }
495 }
496 #endif
497
498 /*
499 * SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until
500 * model 3 mask 3
501 */
502 if ((c->x86<<8 | c->x86_model<<4 | c->x86_stepping) < 0x633)
503 clear_cpu_cap(c, X86_FEATURE_SEP);
504
505 /*
506 * PAE CPUID issue: many Pentium M report no PAE but may have a
507 * functionally usable PAE implementation.
508 * Forcefully enable PAE if kernel parameter "forcepae" is present.
509 */
510 if (forcepae) {
511 pr_warn("PAE forced!\n");
512 set_cpu_cap(c, X86_FEATURE_PAE);
513 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_NOW_UNRELIABLE);
514 }
515
516 /*
517 * P4 Xeon erratum 037 workaround.
518 * Hardware prefetcher may cause stale data to be loaded into the cache.
519 */
520 if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_stepping == 1)) {
521 if (msr_set_bit(MSR_IA32_MISC_ENABLE,
522 MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
523 pr_info("CPU: C0 stepping P4 Xeon detected.\n");
524 pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
525 }
526 }
527
528 /*
529 * See if we have a good local APIC by checking for buggy Pentia,
530 * i.e. all B steppings and the C2 stepping of P54C when using their
531 * integrated APIC (see 11AP erratum in "Pentium Processor
532 * Specification Update").
533 */
534 if (boot_cpu_has(X86_FEATURE_APIC) && (c->x86<<8 | c->x86_model<<4) == 0x520 &&
535 (c->x86_stepping < 0x6 || c->x86_stepping == 0xb))
536 set_cpu_bug(c, X86_BUG_11AP);
537
538
539 #ifdef CONFIG_X86_INTEL_USERCOPY
540 /*
541 * Set up the preferred alignment for movsl bulk memory moves
542 */
543 switch (c->x86) {
544 case 4: /* 486: untested */
545 break;
546 case 5: /* Old Pentia: untested */
547 break;
548 case 6: /* PII/PIII only like movsl with 8-byte alignment */
549 movsl_mask.mask = 7;
550 break;
551 case 15: /* P4 is OK down to 8-byte alignment */
552 movsl_mask.mask = 7;
553 break;
554 }
555 #endif
556
557 intel_smp_check(c);
558 }
559 #else
intel_workarounds(struct cpuinfo_x86 * c)560 static void intel_workarounds(struct cpuinfo_x86 *c)
561 {
562 }
563 #endif
564
srat_detect_node(struct cpuinfo_x86 * c)565 static void srat_detect_node(struct cpuinfo_x86 *c)
566 {
567 #ifdef CONFIG_NUMA
568 unsigned node;
569 int cpu = smp_processor_id();
570
571 /* Don't do the funky fallback heuristics the AMD version employs
572 for now. */
573 node = numa_cpu_node(cpu);
574 if (node == NUMA_NO_NODE || !node_online(node)) {
575 /* reuse the value from init_cpu_to_node() */
576 node = cpu_to_node(cpu);
577 }
578 numa_set_node(cpu, node);
579 #endif
580 }
581
init_cpuid_fault(struct cpuinfo_x86 * c)582 static void init_cpuid_fault(struct cpuinfo_x86 *c)
583 {
584 u64 msr;
585
586 if (!rdmsrl_safe(MSR_PLATFORM_INFO, &msr)) {
587 if (msr & MSR_PLATFORM_INFO_CPUID_FAULT)
588 set_cpu_cap(c, X86_FEATURE_CPUID_FAULT);
589 }
590 }
591
init_intel_misc_features(struct cpuinfo_x86 * c)592 static void init_intel_misc_features(struct cpuinfo_x86 *c)
593 {
594 u64 msr;
595
596 if (rdmsrl_safe(MSR_MISC_FEATURES_ENABLES, &msr))
597 return;
598
599 /* Clear all MISC features */
600 this_cpu_write(msr_misc_features_shadow, 0);
601
602 /* Check features and update capabilities and shadow control bits */
603 init_cpuid_fault(c);
604 probe_xeon_phi_r3mwait(c);
605
606 msr = this_cpu_read(msr_misc_features_shadow);
607 wrmsrl(MSR_MISC_FEATURES_ENABLES, msr);
608 }
609
610 static void split_lock_init(void);
611 static void bus_lock_init(void);
612
init_intel(struct cpuinfo_x86 * c)613 static void init_intel(struct cpuinfo_x86 *c)
614 {
615 early_init_intel(c);
616
617 intel_workarounds(c);
618
619 /*
620 * Detect the extended topology information if available. This
621 * will reinitialise the initial_apicid which will be used
622 * in init_intel_cacheinfo()
623 */
624 detect_extended_topology(c);
625
626 if (!cpu_has(c, X86_FEATURE_XTOPOLOGY)) {
627 /*
628 * let's use the legacy cpuid vector 0x1 and 0x4 for topology
629 * detection.
630 */
631 detect_num_cpu_cores(c);
632 #ifdef CONFIG_X86_32
633 detect_ht(c);
634 #endif
635 }
636
637 init_intel_cacheinfo(c);
638
639 if (c->cpuid_level > 9) {
640 unsigned eax = cpuid_eax(10);
641 /* Check for version and the number of counters */
642 if ((eax & 0xff) && (((eax>>8) & 0xff) > 1))
643 set_cpu_cap(c, X86_FEATURE_ARCH_PERFMON);
644 }
645
646 if (cpu_has(c, X86_FEATURE_XMM2))
647 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
648
649 if (boot_cpu_has(X86_FEATURE_DS)) {
650 unsigned int l1, l2;
651
652 rdmsr(MSR_IA32_MISC_ENABLE, l1, l2);
653 if (!(l1 & MSR_IA32_MISC_ENABLE_BTS_UNAVAIL))
654 set_cpu_cap(c, X86_FEATURE_BTS);
655 if (!(l1 & MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL))
656 set_cpu_cap(c, X86_FEATURE_PEBS);
657 }
658
659 if (boot_cpu_has(X86_FEATURE_CLFLUSH) &&
660 (c->x86_vfm == INTEL_CORE2_DUNNINGTON ||
661 c->x86_vfm == INTEL_NEHALEM_EX ||
662 c->x86_vfm == INTEL_WESTMERE_EX))
663 set_cpu_bug(c, X86_BUG_CLFLUSH_MONITOR);
664
665 if (boot_cpu_has(X86_FEATURE_MWAIT) &&
666 (c->x86_vfm == INTEL_ATOM_GOLDMONT ||
667 c->x86_vfm == INTEL_LUNARLAKE_M))
668 set_cpu_bug(c, X86_BUG_MONITOR);
669
670 #ifdef CONFIG_X86_64
671 if (c->x86 == 15)
672 c->x86_cache_alignment = c->x86_clflush_size * 2;
673 if (c->x86 == 6)
674 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
675 #else
676 /*
677 * Names for the Pentium II/Celeron processors
678 * detectable only by also checking the cache size.
679 * Dixon is NOT a Celeron.
680 */
681 if (c->x86 == 6) {
682 unsigned int l2 = c->x86_cache_size;
683 char *p = NULL;
684
685 switch (c->x86_model) {
686 case 5:
687 if (l2 == 0)
688 p = "Celeron (Covington)";
689 else if (l2 == 256)
690 p = "Mobile Pentium II (Dixon)";
691 break;
692
693 case 6:
694 if (l2 == 128)
695 p = "Celeron (Mendocino)";
696 else if (c->x86_stepping == 0 || c->x86_stepping == 5)
697 p = "Celeron-A";
698 break;
699
700 case 8:
701 if (l2 == 128)
702 p = "Celeron (Coppermine)";
703 break;
704 }
705
706 if (p)
707 strcpy(c->x86_model_id, p);
708 }
709
710 if (c->x86 == 15)
711 set_cpu_cap(c, X86_FEATURE_P4);
712 if (c->x86 == 6)
713 set_cpu_cap(c, X86_FEATURE_P3);
714 #endif
715
716 /* Work around errata */
717 srat_detect_node(c);
718
719 init_ia32_feat_ctl(c);
720
721 init_intel_misc_features(c);
722
723 split_lock_init();
724 bus_lock_init();
725
726 intel_init_thermal(c);
727 }
728
729 #ifdef CONFIG_X86_32
intel_size_cache(struct cpuinfo_x86 * c,unsigned int size)730 static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
731 {
732 /*
733 * Intel PIII Tualatin. This comes in two flavours.
734 * One has 256kb of cache, the other 512. We have no way
735 * to determine which, so we use a boottime override
736 * for the 512kb model, and assume 256 otherwise.
737 */
738 if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
739 size = 256;
740
741 /*
742 * Intel Quark SoC X1000 contains a 4-way set associative
743 * 16K cache with a 16 byte cache line and 256 lines per tag
744 */
745 if ((c->x86 == 5) && (c->x86_model == 9))
746 size = 16;
747 return size;
748 }
749 #endif
750
751 #define TLB_INST_4K 0x01
752 #define TLB_INST_4M 0x02
753 #define TLB_INST_2M_4M 0x03
754
755 #define TLB_INST_ALL 0x05
756 #define TLB_INST_1G 0x06
757
758 #define TLB_DATA_4K 0x11
759 #define TLB_DATA_4M 0x12
760 #define TLB_DATA_2M_4M 0x13
761 #define TLB_DATA_4K_4M 0x14
762
763 #define TLB_DATA_1G 0x16
764 #define TLB_DATA_1G_2M_4M 0x17
765
766 #define TLB_DATA0_4K 0x21
767 #define TLB_DATA0_4M 0x22
768 #define TLB_DATA0_2M_4M 0x23
769
770 #define STLB_4K 0x41
771 #define STLB_4K_2M 0x42
772
773 /*
774 * All of leaf 0x2's one-byte TLB descriptors implies the same number of
775 * entries for their respective TLB types. The 0x63 descriptor is an
776 * exception: it implies 4 dTLB entries for 1GB pages 32 dTLB entries
777 * for 2MB or 4MB pages. Encode descriptor 0x63 dTLB entry count for
778 * 2MB/4MB pages here, as its count for dTLB 1GB pages is already at the
779 * intel_tlb_table[] mapping.
780 */
781 #define TLB_0x63_2M_4M_ENTRIES 32
782
783 static const struct _tlb_table intel_tlb_table[] = {
784 { 0x01, TLB_INST_4K, 32, " TLB_INST 4 KByte pages, 4-way set associative" },
785 { 0x02, TLB_INST_4M, 2, " TLB_INST 4 MByte pages, full associative" },
786 { 0x03, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way set associative" },
787 { 0x04, TLB_DATA_4M, 8, " TLB_DATA 4 MByte pages, 4-way set associative" },
788 { 0x05, TLB_DATA_4M, 32, " TLB_DATA 4 MByte pages, 4-way set associative" },
789 { 0x0b, TLB_INST_4M, 4, " TLB_INST 4 MByte pages, 4-way set associative" },
790 { 0x4f, TLB_INST_4K, 32, " TLB_INST 4 KByte pages" },
791 { 0x50, TLB_INST_ALL, 64, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
792 { 0x51, TLB_INST_ALL, 128, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
793 { 0x52, TLB_INST_ALL, 256, " TLB_INST 4 KByte and 2-MByte or 4-MByte pages" },
794 { 0x55, TLB_INST_2M_4M, 7, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
795 { 0x56, TLB_DATA0_4M, 16, " TLB_DATA0 4 MByte pages, 4-way set associative" },
796 { 0x57, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, 4-way associative" },
797 { 0x59, TLB_DATA0_4K, 16, " TLB_DATA0 4 KByte pages, fully associative" },
798 { 0x5a, TLB_DATA0_2M_4M, 32, " TLB_DATA0 2-MByte or 4 MByte pages, 4-way set associative" },
799 { 0x5b, TLB_DATA_4K_4M, 64, " TLB_DATA 4 KByte and 4 MByte pages" },
800 { 0x5c, TLB_DATA_4K_4M, 128, " TLB_DATA 4 KByte and 4 MByte pages" },
801 { 0x5d, TLB_DATA_4K_4M, 256, " TLB_DATA 4 KByte and 4 MByte pages" },
802 { 0x61, TLB_INST_4K, 48, " TLB_INST 4 KByte pages, full associative" },
803 { 0x63, TLB_DATA_1G_2M_4M, 4, " TLB_DATA 1 GByte pages, 4-way set associative"
804 " (plus 32 entries TLB_DATA 2 MByte or 4 MByte pages, not encoded here)" },
805 { 0x6b, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 8-way associative" },
806 { 0x6c, TLB_DATA_2M_4M, 128, " TLB_DATA 2 MByte or 4 MByte pages, 8-way associative" },
807 { 0x6d, TLB_DATA_1G, 16, " TLB_DATA 1 GByte pages, fully associative" },
808 { 0x76, TLB_INST_2M_4M, 8, " TLB_INST 2-MByte or 4-MByte pages, fully associative" },
809 { 0xb0, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 4-way set associative" },
810 { 0xb1, TLB_INST_2M_4M, 4, " TLB_INST 2M pages, 4-way, 8 entries or 4M pages, 4-way entries" },
811 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
812 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
813 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
814 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
815 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
816 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
817 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
818 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
819 { 0xc2, TLB_DATA_2M_4M, 16, " TLB_DATA 2 MByte/4MByte pages, 4-way associative" },
820 { 0xca, STLB_4K, 512, " STLB 4 KByte pages, 4-way associative" },
821 { 0x00, 0, 0 }
822 };
823
intel_tlb_lookup(const unsigned char desc)824 static void intel_tlb_lookup(const unsigned char desc)
825 {
826 unsigned char k;
827 if (desc == 0)
828 return;
829
830 /* look up this descriptor in the table */
831 for (k = 0; intel_tlb_table[k].descriptor != desc &&
832 intel_tlb_table[k].descriptor != 0; k++)
833 ;
834
835 if (intel_tlb_table[k].tlb_type == 0)
836 return;
837
838 switch (intel_tlb_table[k].tlb_type) {
839 case STLB_4K:
840 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
841 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
842 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
843 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
844 break;
845 case STLB_4K_2M:
846 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
847 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
848 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
849 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
850 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
851 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
852 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
853 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
854 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
855 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
856 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
857 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
858 break;
859 case TLB_INST_ALL:
860 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
861 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
862 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
863 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
864 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
865 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
866 break;
867 case TLB_INST_4K:
868 if (tlb_lli_4k[ENTRIES] < intel_tlb_table[k].entries)
869 tlb_lli_4k[ENTRIES] = intel_tlb_table[k].entries;
870 break;
871 case TLB_INST_4M:
872 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
873 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
874 break;
875 case TLB_INST_2M_4M:
876 if (tlb_lli_2m[ENTRIES] < intel_tlb_table[k].entries)
877 tlb_lli_2m[ENTRIES] = intel_tlb_table[k].entries;
878 if (tlb_lli_4m[ENTRIES] < intel_tlb_table[k].entries)
879 tlb_lli_4m[ENTRIES] = intel_tlb_table[k].entries;
880 break;
881 case TLB_DATA_4K:
882 case TLB_DATA0_4K:
883 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
884 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
885 break;
886 case TLB_DATA_4M:
887 case TLB_DATA0_4M:
888 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
889 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
890 break;
891 case TLB_DATA_2M_4M:
892 case TLB_DATA0_2M_4M:
893 if (tlb_lld_2m[ENTRIES] < intel_tlb_table[k].entries)
894 tlb_lld_2m[ENTRIES] = intel_tlb_table[k].entries;
895 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
896 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
897 break;
898 case TLB_DATA_4K_4M:
899 if (tlb_lld_4k[ENTRIES] < intel_tlb_table[k].entries)
900 tlb_lld_4k[ENTRIES] = intel_tlb_table[k].entries;
901 if (tlb_lld_4m[ENTRIES] < intel_tlb_table[k].entries)
902 tlb_lld_4m[ENTRIES] = intel_tlb_table[k].entries;
903 break;
904 case TLB_DATA_1G_2M_4M:
905 if (tlb_lld_2m[ENTRIES] < TLB_0x63_2M_4M_ENTRIES)
906 tlb_lld_2m[ENTRIES] = TLB_0x63_2M_4M_ENTRIES;
907 if (tlb_lld_4m[ENTRIES] < TLB_0x63_2M_4M_ENTRIES)
908 tlb_lld_4m[ENTRIES] = TLB_0x63_2M_4M_ENTRIES;
909 fallthrough;
910 case TLB_DATA_1G:
911 if (tlb_lld_1g[ENTRIES] < intel_tlb_table[k].entries)
912 tlb_lld_1g[ENTRIES] = intel_tlb_table[k].entries;
913 break;
914 }
915 }
916
intel_detect_tlb(struct cpuinfo_x86 * c)917 static void intel_detect_tlb(struct cpuinfo_x86 *c)
918 {
919 int i, j, n;
920 unsigned int regs[4];
921 unsigned char *desc = (unsigned char *)regs;
922
923 if (c->cpuid_level < 2)
924 return;
925
926 /* Number of times to iterate */
927 n = cpuid_eax(2) & 0xFF;
928
929 for (i = 0 ; i < n ; i++) {
930 cpuid(2, ®s[0], ®s[1], ®s[2], ®s[3]);
931
932 /* If bit 31 is set, this is an unknown format */
933 for (j = 0 ; j < 4 ; j++)
934 if (regs[j] & (1 << 31))
935 regs[j] = 0;
936
937 /* Byte 0 is level count, not a descriptor */
938 for (j = 1 ; j < 16 ; j++)
939 intel_tlb_lookup(desc[j]);
940 }
941 }
942
943 static const struct cpu_dev intel_cpu_dev = {
944 .c_vendor = "Intel",
945 .c_ident = { "GenuineIntel" },
946 #ifdef CONFIG_X86_32
947 .legacy_models = {
948 { .family = 4, .model_names =
949 {
950 [0] = "486 DX-25/33",
951 [1] = "486 DX-50",
952 [2] = "486 SX",
953 [3] = "486 DX/2",
954 [4] = "486 SL",
955 [5] = "486 SX/2",
956 [7] = "486 DX/2-WB",
957 [8] = "486 DX/4",
958 [9] = "486 DX/4-WB"
959 }
960 },
961 { .family = 5, .model_names =
962 {
963 [0] = "Pentium 60/66 A-step",
964 [1] = "Pentium 60/66",
965 [2] = "Pentium 75 - 200",
966 [3] = "OverDrive PODP5V83",
967 [4] = "Pentium MMX",
968 [7] = "Mobile Pentium 75 - 200",
969 [8] = "Mobile Pentium MMX",
970 [9] = "Quark SoC X1000",
971 }
972 },
973 { .family = 6, .model_names =
974 {
975 [0] = "Pentium Pro A-step",
976 [1] = "Pentium Pro",
977 [3] = "Pentium II (Klamath)",
978 [4] = "Pentium II (Deschutes)",
979 [5] = "Pentium II (Deschutes)",
980 [6] = "Mobile Pentium II",
981 [7] = "Pentium III (Katmai)",
982 [8] = "Pentium III (Coppermine)",
983 [10] = "Pentium III (Cascades)",
984 [11] = "Pentium III (Tualatin)",
985 }
986 },
987 { .family = 15, .model_names =
988 {
989 [0] = "Pentium 4 (Unknown)",
990 [1] = "Pentium 4 (Willamette)",
991 [2] = "Pentium 4 (Northwood)",
992 [4] = "Pentium 4 (Foster)",
993 [5] = "Pentium 4 (Foster)",
994 }
995 },
996 },
997 .legacy_cache_size = intel_size_cache,
998 #endif
999 .c_detect_tlb = intel_detect_tlb,
1000 .c_early_init = early_init_intel,
1001 .c_bsp_init = bsp_init_intel,
1002 .c_init = init_intel,
1003 .c_x86_vendor = X86_VENDOR_INTEL,
1004 };
1005
1006 cpu_dev_register(intel_cpu_dev);
1007
1008 #undef pr_fmt
1009 #define pr_fmt(fmt) "x86/split lock detection: " fmt
1010
1011 static const struct {
1012 const char *option;
1013 enum split_lock_detect_state state;
1014 } sld_options[] __initconst = {
1015 { "off", sld_off },
1016 { "warn", sld_warn },
1017 { "fatal", sld_fatal },
1018 { "ratelimit:", sld_ratelimit },
1019 };
1020
1021 static struct ratelimit_state bld_ratelimit;
1022
1023 static unsigned int sysctl_sld_mitigate = 1;
1024 static DEFINE_SEMAPHORE(buslock_sem, 1);
1025
1026 #ifdef CONFIG_PROC_SYSCTL
1027 static struct ctl_table sld_sysctls[] = {
1028 {
1029 .procname = "split_lock_mitigate",
1030 .data = &sysctl_sld_mitigate,
1031 .maxlen = sizeof(unsigned int),
1032 .mode = 0644,
1033 .proc_handler = proc_douintvec_minmax,
1034 .extra1 = SYSCTL_ZERO,
1035 .extra2 = SYSCTL_ONE,
1036 },
1037 {}
1038 };
1039
sld_mitigate_sysctl_init(void)1040 static int __init sld_mitigate_sysctl_init(void)
1041 {
1042 register_sysctl_init("kernel", sld_sysctls);
1043 return 0;
1044 }
1045
1046 late_initcall(sld_mitigate_sysctl_init);
1047 #endif
1048
match_option(const char * arg,int arglen,const char * opt)1049 static inline bool match_option(const char *arg, int arglen, const char *opt)
1050 {
1051 int len = strlen(opt), ratelimit;
1052
1053 if (strncmp(arg, opt, len))
1054 return false;
1055
1056 /*
1057 * Min ratelimit is 1 bus lock/sec.
1058 * Max ratelimit is 1000 bus locks/sec.
1059 */
1060 if (sscanf(arg, "ratelimit:%d", &ratelimit) == 1 &&
1061 ratelimit > 0 && ratelimit <= 1000) {
1062 ratelimit_state_init(&bld_ratelimit, HZ, ratelimit);
1063 ratelimit_set_flags(&bld_ratelimit, RATELIMIT_MSG_ON_RELEASE);
1064 return true;
1065 }
1066
1067 return len == arglen;
1068 }
1069
split_lock_verify_msr(bool on)1070 static bool split_lock_verify_msr(bool on)
1071 {
1072 u64 ctrl, tmp;
1073
1074 if (rdmsrl_safe(MSR_TEST_CTRL, &ctrl))
1075 return false;
1076 if (on)
1077 ctrl |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1078 else
1079 ctrl &= ~MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1080 if (wrmsrl_safe(MSR_TEST_CTRL, ctrl))
1081 return false;
1082 rdmsrl(MSR_TEST_CTRL, tmp);
1083 return ctrl == tmp;
1084 }
1085
sld_state_setup(void)1086 static void __init sld_state_setup(void)
1087 {
1088 enum split_lock_detect_state state = sld_warn;
1089 char arg[20];
1090 int i, ret;
1091
1092 if (!boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1093 !boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1094 return;
1095
1096 ret = cmdline_find_option(boot_command_line, "split_lock_detect",
1097 arg, sizeof(arg));
1098 if (ret >= 0) {
1099 for (i = 0; i < ARRAY_SIZE(sld_options); i++) {
1100 if (match_option(arg, ret, sld_options[i].option)) {
1101 state = sld_options[i].state;
1102 break;
1103 }
1104 }
1105 }
1106 sld_state = state;
1107 }
1108
__split_lock_setup(void)1109 static void __init __split_lock_setup(void)
1110 {
1111 if (!split_lock_verify_msr(false)) {
1112 pr_info("MSR access failed: Disabled\n");
1113 return;
1114 }
1115
1116 rdmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1117
1118 if (!split_lock_verify_msr(true)) {
1119 pr_info("MSR access failed: Disabled\n");
1120 return;
1121 }
1122
1123 /* Restore the MSR to its cached value. */
1124 wrmsrl(MSR_TEST_CTRL, msr_test_ctrl_cache);
1125
1126 setup_force_cpu_cap(X86_FEATURE_SPLIT_LOCK_DETECT);
1127 }
1128
1129 /*
1130 * MSR_TEST_CTRL is per core, but we treat it like a per CPU MSR. Locking
1131 * is not implemented as one thread could undo the setting of the other
1132 * thread immediately after dropping the lock anyway.
1133 */
sld_update_msr(bool on)1134 static void sld_update_msr(bool on)
1135 {
1136 u64 test_ctrl_val = msr_test_ctrl_cache;
1137
1138 if (on)
1139 test_ctrl_val |= MSR_TEST_CTRL_SPLIT_LOCK_DETECT;
1140
1141 wrmsrl(MSR_TEST_CTRL, test_ctrl_val);
1142 }
1143
split_lock_init(void)1144 static void split_lock_init(void)
1145 {
1146 /*
1147 * #DB for bus lock handles ratelimit and #AC for split lock is
1148 * disabled.
1149 */
1150 if (sld_state == sld_ratelimit) {
1151 split_lock_verify_msr(false);
1152 return;
1153 }
1154
1155 if (cpu_model_supports_sld)
1156 split_lock_verify_msr(sld_state != sld_off);
1157 }
1158
__split_lock_reenable_unlock(struct work_struct * work)1159 static void __split_lock_reenable_unlock(struct work_struct *work)
1160 {
1161 sld_update_msr(true);
1162 up(&buslock_sem);
1163 }
1164
1165 static DECLARE_DELAYED_WORK(sl_reenable_unlock, __split_lock_reenable_unlock);
1166
__split_lock_reenable(struct work_struct * work)1167 static void __split_lock_reenable(struct work_struct *work)
1168 {
1169 sld_update_msr(true);
1170 }
1171 /*
1172 * In order for each CPU to schedule its delayed work independently of the
1173 * others, delayed work struct must be per-CPU. This is not required when
1174 * sysctl_sld_mitigate is enabled because of the semaphore that limits
1175 * the number of simultaneously scheduled delayed works to 1.
1176 */
1177 static DEFINE_PER_CPU(struct delayed_work, sl_reenable);
1178
1179 /*
1180 * If a CPU goes offline with pending delayed work to re-enable split lock
1181 * detection then the delayed work will be executed on some other CPU. That
1182 * handles releasing the buslock_sem, but because it executes on a
1183 * different CPU probably won't re-enable split lock detection. This is a
1184 * problem on HT systems since the sibling CPU on the same core may then be
1185 * left running with split lock detection disabled.
1186 *
1187 * Unconditionally re-enable detection here.
1188 */
splitlock_cpu_offline(unsigned int cpu)1189 static int splitlock_cpu_offline(unsigned int cpu)
1190 {
1191 sld_update_msr(true);
1192
1193 return 0;
1194 }
1195
split_lock_warn(unsigned long ip)1196 static void split_lock_warn(unsigned long ip)
1197 {
1198 struct delayed_work *work = NULL;
1199 int cpu;
1200
1201 if (!current->reported_split_lock)
1202 pr_warn_ratelimited("#AC: %s/%d took a split_lock trap at address: 0x%lx\n",
1203 current->comm, current->pid, ip);
1204 current->reported_split_lock = 1;
1205
1206 if (sysctl_sld_mitigate) {
1207 /*
1208 * misery factor #1:
1209 * sleep 10ms before trying to execute split lock.
1210 */
1211 if (msleep_interruptible(10) > 0)
1212 return;
1213 /*
1214 * Misery factor #2:
1215 * only allow one buslocked disabled core at a time.
1216 */
1217 if (down_interruptible(&buslock_sem) == -EINTR)
1218 return;
1219 work = &sl_reenable_unlock;
1220 }
1221
1222 cpu = get_cpu();
1223
1224 if (!work) {
1225 work = this_cpu_ptr(&sl_reenable);
1226 /* Deferred initialization of per-CPU struct */
1227 if (!work->work.func)
1228 INIT_DELAYED_WORK(work, __split_lock_reenable);
1229 }
1230
1231 schedule_delayed_work_on(cpu, work, 2);
1232
1233 /* Disable split lock detection on this CPU to make progress */
1234 sld_update_msr(false);
1235 put_cpu();
1236 }
1237
handle_guest_split_lock(unsigned long ip)1238 bool handle_guest_split_lock(unsigned long ip)
1239 {
1240 if (sld_state == sld_warn) {
1241 split_lock_warn(ip);
1242 return true;
1243 }
1244
1245 pr_warn_once("#AC: %s/%d %s split_lock trap at address: 0x%lx\n",
1246 current->comm, current->pid,
1247 sld_state == sld_fatal ? "fatal" : "bogus", ip);
1248
1249 current->thread.error_code = 0;
1250 current->thread.trap_nr = X86_TRAP_AC;
1251 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1252 return false;
1253 }
1254 EXPORT_SYMBOL_GPL(handle_guest_split_lock);
1255
bus_lock_init(void)1256 static void bus_lock_init(void)
1257 {
1258 u64 val;
1259
1260 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1261 return;
1262
1263 rdmsrl(MSR_IA32_DEBUGCTLMSR, val);
1264
1265 if ((boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) &&
1266 (sld_state == sld_warn || sld_state == sld_fatal)) ||
1267 sld_state == sld_off) {
1268 /*
1269 * Warn and fatal are handled by #AC for split lock if #AC for
1270 * split lock is supported.
1271 */
1272 val &= ~DEBUGCTLMSR_BUS_LOCK_DETECT;
1273 } else {
1274 val |= DEBUGCTLMSR_BUS_LOCK_DETECT;
1275 }
1276
1277 wrmsrl(MSR_IA32_DEBUGCTLMSR, val);
1278 }
1279
handle_user_split_lock(struct pt_regs * regs,long error_code)1280 bool handle_user_split_lock(struct pt_regs *regs, long error_code)
1281 {
1282 if ((regs->flags & X86_EFLAGS_AC) || sld_state == sld_fatal)
1283 return false;
1284 split_lock_warn(regs->ip);
1285 return true;
1286 }
1287
handle_bus_lock(struct pt_regs * regs)1288 void handle_bus_lock(struct pt_regs *regs)
1289 {
1290 switch (sld_state) {
1291 case sld_off:
1292 break;
1293 case sld_ratelimit:
1294 /* Enforce no more than bld_ratelimit bus locks/sec. */
1295 while (!__ratelimit(&bld_ratelimit))
1296 msleep(20);
1297 /* Warn on the bus lock. */
1298 fallthrough;
1299 case sld_warn:
1300 pr_warn_ratelimited("#DB: %s/%d took a bus_lock trap at address: 0x%lx\n",
1301 current->comm, current->pid, regs->ip);
1302 break;
1303 case sld_fatal:
1304 force_sig_fault(SIGBUS, BUS_ADRALN, NULL);
1305 break;
1306 }
1307 }
1308
1309 /*
1310 * CPU models that are known to have the per-core split-lock detection
1311 * feature even though they do not enumerate IA32_CORE_CAPABILITIES.
1312 */
1313 static const struct x86_cpu_id split_lock_cpu_ids[] __initconst = {
1314 X86_MATCH_VFM(INTEL_ICELAKE_X, 0),
1315 X86_MATCH_VFM(INTEL_ICELAKE_L, 0),
1316 X86_MATCH_VFM(INTEL_ICELAKE_D, 0),
1317 {}
1318 };
1319
split_lock_setup(struct cpuinfo_x86 * c)1320 static void __init split_lock_setup(struct cpuinfo_x86 *c)
1321 {
1322 const struct x86_cpu_id *m;
1323 u64 ia32_core_caps;
1324
1325 if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
1326 return;
1327
1328 /* Check for CPUs that have support but do not enumerate it: */
1329 m = x86_match_cpu(split_lock_cpu_ids);
1330 if (m)
1331 goto supported;
1332
1333 if (!cpu_has(c, X86_FEATURE_CORE_CAPABILITIES))
1334 return;
1335
1336 /*
1337 * Not all bits in MSR_IA32_CORE_CAPS are architectural, but
1338 * MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT is. All CPUs that set
1339 * it have split lock detection.
1340 */
1341 rdmsrl(MSR_IA32_CORE_CAPS, ia32_core_caps);
1342 if (ia32_core_caps & MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT)
1343 goto supported;
1344
1345 /* CPU is not in the model list and does not have the MSR bit: */
1346 return;
1347
1348 supported:
1349 cpu_model_supports_sld = true;
1350 __split_lock_setup();
1351 }
1352
sld_state_show(void)1353 static void sld_state_show(void)
1354 {
1355 if (!boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT) &&
1356 !boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT))
1357 return;
1358
1359 switch (sld_state) {
1360 case sld_off:
1361 pr_info("disabled\n");
1362 break;
1363 case sld_warn:
1364 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1365 pr_info("#AC: crashing the kernel on kernel split_locks and warning on user-space split_locks\n");
1366 if (cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
1367 "x86/splitlock", NULL, splitlock_cpu_offline) < 0)
1368 pr_warn("No splitlock CPU offline handler\n");
1369 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1370 pr_info("#DB: warning on user-space bus_locks\n");
1371 }
1372 break;
1373 case sld_fatal:
1374 if (boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT)) {
1375 pr_info("#AC: crashing the kernel on kernel split_locks and sending SIGBUS on user-space split_locks\n");
1376 } else if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT)) {
1377 pr_info("#DB: sending SIGBUS on user-space bus_locks%s\n",
1378 boot_cpu_has(X86_FEATURE_SPLIT_LOCK_DETECT) ?
1379 " from non-WB" : "");
1380 }
1381 break;
1382 case sld_ratelimit:
1383 if (boot_cpu_has(X86_FEATURE_BUS_LOCK_DETECT))
1384 pr_info("#DB: setting system wide bus lock rate limit to %u/sec\n", bld_ratelimit.burst);
1385 break;
1386 }
1387 }
1388
sld_setup(struct cpuinfo_x86 * c)1389 void __init sld_setup(struct cpuinfo_x86 *c)
1390 {
1391 split_lock_setup(c);
1392 sld_state_setup();
1393 sld_state_show();
1394 }
1395
1396 #define X86_HYBRID_CPU_TYPE_ID_SHIFT 24
1397
1398 /**
1399 * get_this_hybrid_cpu_type() - Get the type of this hybrid CPU
1400 *
1401 * Returns the CPU type [31:24] (i.e., Atom or Core) of a CPU in
1402 * a hybrid processor. If the processor is not hybrid, returns 0.
1403 */
get_this_hybrid_cpu_type(void)1404 u8 get_this_hybrid_cpu_type(void)
1405 {
1406 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
1407 return 0;
1408
1409 return cpuid_eax(0x0000001a) >> X86_HYBRID_CPU_TYPE_ID_SHIFT;
1410 }
1411