1 /*
2 * ASPEED SoC family
3 *
4 * Andrew Jeffery <andrew@aj.id.au>
5 *
6 * Copyright 2016 IBM Corp.
7 *
8 * This code is licensed under the GPL version 2 or later. See
9 * the COPYING file in the top-level directory.
10 */
11
12 #ifndef ASPEED_SOC_H
13 #define ASPEED_SOC_H
14
15 #include "hw/cpu/a15mpcore.h"
16 #include "hw/arm/armv7m.h"
17 #include "hw/intc/aspeed_vic.h"
18 #include "hw/intc/aspeed_intc.h"
19 #include "hw/misc/aspeed_scu.h"
20 #include "hw/adc/aspeed_adc.h"
21 #include "hw/misc/aspeed_gfx.h"
22 #include "hw/misc/aspeed_sdmc.h"
23 #include "hw/misc/aspeed_xdma.h"
24 #include "hw/timer/aspeed_timer.h"
25 #include "hw/rtc/aspeed_rtc.h"
26 #include "hw/misc/aspeed_ibt.h"
27 #include "hw/i2c/aspeed_i2c.h"
28 #include "hw/i3c/aspeed_i3c.h"
29 #include "hw/ssi/aspeed_smc.h"
30 #include "hw/misc/aspeed_hace.h"
31 #include "hw/misc/aspeed_sbc.h"
32 #include "hw/misc/aspeed_sli.h"
33 #include "hw/misc/aspeed_pwm.h"
34 #include "hw/watchdog/wdt_aspeed.h"
35 #include "hw/net/ftgmac100.h"
36 #include "target/arm/cpu.h"
37 #include "hw/gpio/aspeed_gpio.h"
38 #include "hw/sd/aspeed_sdhci.h"
39 #include "hw/usb/hcd-ehci.h"
40 #include "qom/object.h"
41 #include "hw/misc/aspeed_lpc.h"
42 #include "hw/misc/unimp.h"
43 #include "hw/pci-host/aspeed_pcie.h"
44 #include "hw/misc/aspeed_peci.h"
45 #include "hw/fsi/aspeed_apb2opb.h"
46 #include "hw/char/serial-mm.h"
47 #include "hw/intc/arm_gicv3.h"
48
49 #define ASPEED_SPIS_NUM 3
50 #define ASPEED_EHCIS_NUM 4
51 #define ASPEED_WDTS_NUM 8
52 #define ASPEED_CPUS_NUM 4
53 #define ASPEED_MACS_NUM 4
54 #define ASPEED_UARTS_NUM 13
55 #define ASPEED_JTAG_NUM 2
56 #define ASPEED_PCIE_NUM 3
57
58 struct AspeedSoCState {
59 DeviceState parent;
60
61 MemoryRegion *memory;
62 MemoryRegion *dram_mr;
63 MemoryRegion dram_container;
64 MemoryRegion sram;
65 MemoryRegion spi_boot_container;
66 MemoryRegion spi_boot;
67 MemoryRegion vbootrom;
68 AddressSpace dram_as;
69 AspeedRtcState rtc;
70 AspeedTimerCtrlState timerctrl;
71 AspeedIBTState ibt;
72 AspeedI2CState i2c;
73 AspeedI3CState i3c;
74 AspeedSCUState scu;
75 AspeedSCUState scuio;
76 AspeedHACEState hace;
77 AspeedXDMAState xdma;
78 AspeedADCState adc;
79 AspeedSMCState fmc;
80 AspeedSMCState spi[ASPEED_SPIS_NUM];
81 EHCISysBusState ehci[ASPEED_EHCIS_NUM];
82 AspeedSBCState sbc;
83 AspeedSLIState sli;
84 AspeedSLIState sliio;
85 MemoryRegion secsram;
86 UnimplementedDeviceState sbc_unimplemented;
87 AspeedSDMCState sdmc;
88 AspeedWDTState wdt[ASPEED_WDTS_NUM];
89 FTGMAC100State ftgmac100[ASPEED_MACS_NUM];
90 AspeedMiiState mii[ASPEED_MACS_NUM];
91 AspeedGPIOState gpio;
92 AspeedGPIOState gpio_1_8v;
93 AspeedSDHCIState sdhci;
94 AspeedSDHCIState emmc;
95 AspeedLPCState lpc;
96 AspeedPCIECfgState pcie[ASPEED_PCIE_NUM];
97 AspeedPCIEPhyState pcie_phy[ASPEED_PCIE_NUM];
98 AspeedPECIState peci;
99 AspeedGFXState gfx;
100 SerialMM uart[ASPEED_UARTS_NUM];
101 Clock *sysclk;
102 UnimplementedDeviceState iomem;
103 UnimplementedDeviceState iomem0;
104 UnimplementedDeviceState iomem1;
105 UnimplementedDeviceState video;
106 UnimplementedDeviceState emmc_boot_controller;
107 UnimplementedDeviceState dpmcu;
108 AspeedPWMState pwm;
109 UnimplementedDeviceState espi;
110 UnimplementedDeviceState udc;
111 UnimplementedDeviceState sgpiom;
112 UnimplementedDeviceState ltpi;
113 UnimplementedDeviceState jtag[ASPEED_JTAG_NUM];
114 AspeedAPB2OPBState fsi[2];
115 };
116
117 #define TYPE_ASPEED_SOC "aspeed-soc"
118 OBJECT_DECLARE_TYPE(AspeedSoCState, AspeedSoCClass, ASPEED_SOC)
119
120 struct Aspeed2400SoCState {
121 AspeedSoCState parent;
122
123 ARMCPU cpu[ASPEED_CPUS_NUM];
124 AspeedVICState vic;
125 };
126
127 #define TYPE_ASPEED2400_SOC "aspeed2400-soc"
128 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2400SoCState, ASPEED2400_SOC)
129
130 struct Aspeed2600SoCState {
131 AspeedSoCState parent;
132
133 A15MPPrivState a7mpcore;
134 ARMCPU cpu[ASPEED_CPUS_NUM]; /* XXX belong to a7mpcore */
135 };
136
137 #define TYPE_ASPEED2600_SOC "aspeed2600-soc"
138 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed2600SoCState, ASPEED2600_SOC)
139
140 struct Aspeed27x0SSPSoCState {
141 AspeedSoCState parent;
142 AspeedINTCState intc[2];
143 UnimplementedDeviceState ipc[2];
144 UnimplementedDeviceState scuio;
145 MemoryRegion memory;
146 MemoryRegion sram_mr_alias;
147 MemoryRegion scu_mr_alias;
148 MemoryRegion sdram_remap1_alias;
149 MemoryRegion sdram_remap2_alias;
150
151 ARMv7MState armv7m;
152 };
153
154 #define TYPE_ASPEED27X0SSP_SOC "aspeed27x0ssp-soc"
155 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SSPSoCState, ASPEED27X0SSP_SOC)
156
157 struct Aspeed27x0TSPSoCState {
158 AspeedSoCState parent;
159 AspeedINTCState intc[2];
160 UnimplementedDeviceState ipc[2];
161 UnimplementedDeviceState scuio;
162 MemoryRegion memory;
163 MemoryRegion sram_mr_alias;
164 MemoryRegion scu_mr_alias;
165 MemoryRegion sdram_remap_alias;
166
167 ARMv7MState armv7m;
168 };
169
170 #define TYPE_ASPEED27X0TSP_SOC "aspeed27x0tsp-soc"
171 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0TSPSoCState, ASPEED27X0TSP_SOC)
172
173 struct Aspeed27x0SoCState {
174 AspeedSoCState parent;
175
176 ARMCPU cpu[ASPEED_CPUS_NUM];
177 AspeedINTCState intc[2];
178 GICv3State gic;
179 MemoryRegion dram_empty;
180
181 Aspeed27x0SSPSoCState ssp;
182 Aspeed27x0TSPSoCState tsp;
183 };
184
185 #define TYPE_ASPEED27X0_SOC "aspeed27x0-soc"
186 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed27x0SoCState, ASPEED27X0_SOC)
187
188 struct Aspeed10x0SoCState {
189 AspeedSoCState parent;
190
191 ARMv7MState armv7m;
192 };
193
194 #define TYPE_ASPEED10X0_SOC "aspeed10x0-soc"
195 OBJECT_DECLARE_SIMPLE_TYPE(Aspeed10x0SoCState, ASPEED10X0_SOC)
196
197 struct AspeedSoCClass {
198 DeviceClass parent_class;
199
200 /** valid_cpu_types: NULL terminated array of a single CPU type. */
201 const char * const *valid_cpu_types;
202 uint32_t silicon_rev;
203 uint64_t sram_size;
204 uint64_t secsram_size;
205 int pcie_num;
206 int spis_num;
207 int ehcis_num;
208 int wdts_num;
209 int macs_num;
210 int uarts_num;
211 int uarts_base;
212 const int *irqmap;
213 const hwaddr *memmap;
214 uint32_t num_cpus;
215 qemu_irq (*get_irq)(AspeedSoCState *s, int dev);
216 bool (*boot_from_emmc)(AspeedSoCState *s);
217 };
218
219 const char *aspeed_soc_cpu_type(AspeedSoCClass *sc);
220
221 enum {
222 ASPEED_DEV_VBOOTROM,
223 ASPEED_DEV_SPI_BOOT,
224 ASPEED_DEV_IOMEM,
225 ASPEED_DEV_IOMEM0,
226 ASPEED_DEV_IOMEM1,
227 ASPEED_DEV_LTPI,
228 ASPEED_DEV_UART0,
229 ASPEED_DEV_UART1,
230 ASPEED_DEV_UART2,
231 ASPEED_DEV_UART3,
232 ASPEED_DEV_UART4,
233 ASPEED_DEV_UART5,
234 ASPEED_DEV_UART6,
235 ASPEED_DEV_UART7,
236 ASPEED_DEV_UART8,
237 ASPEED_DEV_UART9,
238 ASPEED_DEV_UART10,
239 ASPEED_DEV_UART11,
240 ASPEED_DEV_UART12,
241 ASPEED_DEV_UART13,
242 ASPEED_DEV_VUART,
243 ASPEED_DEV_FMC,
244 ASPEED_DEV_SPI0,
245 ASPEED_DEV_SPI1,
246 ASPEED_DEV_SPI2,
247 ASPEED_DEV_EHCI1,
248 ASPEED_DEV_EHCI2,
249 ASPEED_DEV_EHCI3,
250 ASPEED_DEV_EHCI4,
251 ASPEED_DEV_VIC,
252 ASPEED_DEV_INTC,
253 ASPEED_DEV_INTCIO,
254 ASPEED_DEV_SDMC,
255 ASPEED_DEV_SCU,
256 ASPEED_DEV_ADC,
257 ASPEED_DEV_SBC,
258 ASPEED_DEV_SECSRAM,
259 ASPEED_DEV_EMMC_BC,
260 ASPEED_DEV_VIDEO,
261 ASPEED_DEV_SRAM,
262 ASPEED_DEV_SDHCI,
263 ASPEED_DEV_GPIO,
264 ASPEED_DEV_GPIO_1_8V,
265 ASPEED_DEV_RTC,
266 ASPEED_DEV_TIMER1,
267 ASPEED_DEV_TIMER2,
268 ASPEED_DEV_TIMER3,
269 ASPEED_DEV_TIMER4,
270 ASPEED_DEV_TIMER5,
271 ASPEED_DEV_TIMER6,
272 ASPEED_DEV_TIMER7,
273 ASPEED_DEV_TIMER8,
274 ASPEED_DEV_WDT,
275 ASPEED_DEV_PWM,
276 ASPEED_DEV_LPC,
277 ASPEED_DEV_IBT,
278 ASPEED_DEV_I2C,
279 ASPEED_DEV_PCIE0,
280 ASPEED_DEV_PCIE1,
281 ASPEED_DEV_PCIE2,
282 ASPEED_DEV_PCIE_PHY0,
283 ASPEED_DEV_PCIE_PHY1,
284 ASPEED_DEV_PCIE_PHY2,
285 ASPEED_DEV_PCIE_MMIO0,
286 ASPEED_DEV_PCIE_MMIO1,
287 ASPEED_DEV_PCIE_MMIO2,
288 ASPEED_DEV_PECI,
289 ASPEED_DEV_ETH1,
290 ASPEED_DEV_ETH2,
291 ASPEED_DEV_ETH3,
292 ASPEED_DEV_ETH4,
293 ASPEED_DEV_MII1,
294 ASPEED_DEV_MII2,
295 ASPEED_DEV_MII3,
296 ASPEED_DEV_MII4,
297 ASPEED_DEV_SDRAM,
298 ASPEED_DEV_XDMA,
299 ASPEED_DEV_EMMC,
300 ASPEED_DEV_KCS,
301 ASPEED_DEV_HACE,
302 ASPEED_DEV_GFX,
303 ASPEED_DEV_DPMCU,
304 ASPEED_DEV_DP,
305 ASPEED_DEV_I3C,
306 ASPEED_DEV_ESPI,
307 ASPEED_DEV_UDC,
308 ASPEED_DEV_SGPIOM,
309 ASPEED_DEV_JTAG0,
310 ASPEED_DEV_JTAG1,
311 ASPEED_DEV_FSI1,
312 ASPEED_DEV_FSI2,
313 ASPEED_DEV_SCUIO,
314 ASPEED_DEV_SLI,
315 ASPEED_DEV_SLIIO,
316 ASPEED_GIC_DIST,
317 ASPEED_GIC_REDIST,
318 ASPEED_DEV_IPC0,
319 ASPEED_DEV_IPC1,
320 };
321
322 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev);
323 bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp);
324 void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr);
325 bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp);
326 void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr);
327 void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
328 const char *name, hwaddr addr,
329 uint64_t size);
330 void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype,
331 unsigned int count, int unit0);
332
aspeed_uart_index(int uart_dev)333 static inline int aspeed_uart_index(int uart_dev)
334 {
335 return uart_dev - ASPEED_DEV_UART0;
336 }
337
aspeed_uart_first(AspeedSoCClass * sc)338 static inline int aspeed_uart_first(AspeedSoCClass *sc)
339 {
340 return aspeed_uart_index(sc->uarts_base);
341 }
342
aspeed_uart_last(AspeedSoCClass * sc)343 static inline int aspeed_uart_last(AspeedSoCClass *sc)
344 {
345 return aspeed_uart_first(sc) + sc->uarts_num - 1;
346 }
347
348 #endif /* ASPEED_SOC_H */
349