xref: /openbmc/linux/drivers/spi/spi-mt65xx.c (revision 62b1f837)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  * Author: Leilk Liu <leilk.liu@mediatek.com>
5  */
6 
7 #include <linux/clk.h>
8 #include <linux/device.h>
9 #include <linux/err.h>
10 #include <linux/interrupt.h>
11 #include <linux/io.h>
12 #include <linux/ioport.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/platform_device.h>
17 #include <linux/platform_data/spi-mt65xx.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/spi/spi.h>
20 #include <linux/spi/spi-mem.h>
21 #include <linux/dma-mapping.h>
22 
23 #define SPI_CFG0_REG			0x0000
24 #define SPI_CFG1_REG			0x0004
25 #define SPI_TX_SRC_REG			0x0008
26 #define SPI_RX_DST_REG			0x000c
27 #define SPI_TX_DATA_REG			0x0010
28 #define SPI_RX_DATA_REG			0x0014
29 #define SPI_CMD_REG			0x0018
30 #define SPI_STATUS0_REG			0x001c
31 #define SPI_PAD_SEL_REG			0x0024
32 #define SPI_CFG2_REG			0x0028
33 #define SPI_TX_SRC_REG_64		0x002c
34 #define SPI_RX_DST_REG_64		0x0030
35 #define SPI_CFG3_IPM_REG		0x0040
36 
37 #define SPI_CFG0_SCK_HIGH_OFFSET	0
38 #define SPI_CFG0_SCK_LOW_OFFSET		8
39 #define SPI_CFG0_CS_HOLD_OFFSET		16
40 #define SPI_CFG0_CS_SETUP_OFFSET	24
41 #define SPI_ADJUST_CFG0_CS_HOLD_OFFSET	0
42 #define SPI_ADJUST_CFG0_CS_SETUP_OFFSET	16
43 
44 #define SPI_CFG1_CS_IDLE_OFFSET		0
45 #define SPI_CFG1_PACKET_LOOP_OFFSET	8
46 #define SPI_CFG1_PACKET_LENGTH_OFFSET	16
47 #define SPI_CFG1_GET_TICK_DLY_OFFSET	29
48 #define SPI_CFG1_GET_TICK_DLY_OFFSET_V1	30
49 
50 #define SPI_CFG1_GET_TICK_DLY_MASK	0xe0000000
51 #define SPI_CFG1_GET_TICK_DLY_MASK_V1	0xc0000000
52 
53 #define SPI_CFG1_CS_IDLE_MASK		0xff
54 #define SPI_CFG1_PACKET_LOOP_MASK	0xff00
55 #define SPI_CFG1_PACKET_LENGTH_MASK	0x3ff0000
56 #define SPI_CFG1_IPM_PACKET_LENGTH_MASK	GENMASK(31, 16)
57 #define SPI_CFG2_SCK_HIGH_OFFSET	0
58 #define SPI_CFG2_SCK_LOW_OFFSET		16
59 
60 #define SPI_CMD_ACT			BIT(0)
61 #define SPI_CMD_RESUME			BIT(1)
62 #define SPI_CMD_RST			BIT(2)
63 #define SPI_CMD_PAUSE_EN		BIT(4)
64 #define SPI_CMD_DEASSERT		BIT(5)
65 #define SPI_CMD_SAMPLE_SEL		BIT(6)
66 #define SPI_CMD_CS_POL			BIT(7)
67 #define SPI_CMD_CPHA			BIT(8)
68 #define SPI_CMD_CPOL			BIT(9)
69 #define SPI_CMD_RX_DMA			BIT(10)
70 #define SPI_CMD_TX_DMA			BIT(11)
71 #define SPI_CMD_TXMSBF			BIT(12)
72 #define SPI_CMD_RXMSBF			BIT(13)
73 #define SPI_CMD_RX_ENDIAN		BIT(14)
74 #define SPI_CMD_TX_ENDIAN		BIT(15)
75 #define SPI_CMD_FINISH_IE		BIT(16)
76 #define SPI_CMD_PAUSE_IE		BIT(17)
77 #define SPI_CMD_IPM_NONIDLE_MODE	BIT(19)
78 #define SPI_CMD_IPM_SPIM_LOOP		BIT(21)
79 #define SPI_CMD_IPM_GET_TICKDLY_OFFSET	22
80 
81 #define SPI_CMD_IPM_GET_TICKDLY_MASK	GENMASK(24, 22)
82 
83 #define PIN_MODE_CFG(x)	((x) / 2)
84 
85 #define SPI_CFG3_IPM_HALF_DUPLEX_DIR	BIT(2)
86 #define SPI_CFG3_IPM_HALF_DUPLEX_EN	BIT(3)
87 #define SPI_CFG3_IPM_XMODE_EN		BIT(4)
88 #define SPI_CFG3_IPM_NODATA_FLAG	BIT(5)
89 #define SPI_CFG3_IPM_CMD_BYTELEN_OFFSET	8
90 #define SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET 12
91 
92 #define SPI_CFG3_IPM_CMD_PIN_MODE_MASK	GENMASK(1, 0)
93 #define SPI_CFG3_IPM_CMD_BYTELEN_MASK	GENMASK(11, 8)
94 #define SPI_CFG3_IPM_ADDR_BYTELEN_MASK	GENMASK(15, 12)
95 
96 #define MT8173_SPI_MAX_PAD_SEL		3
97 
98 #define MTK_SPI_PAUSE_INT_STATUS	0x2
99 
100 #define MTK_SPI_MAX_FIFO_SIZE		32U
101 #define MTK_SPI_PACKET_SIZE		1024
102 #define MTK_SPI_IPM_PACKET_SIZE		SZ_64K
103 #define MTK_SPI_IPM_PACKET_LOOP		SZ_256
104 
105 #define MTK_SPI_IDLE			0
106 #define MTK_SPI_PAUSED			1
107 
108 #define MTK_SPI_32BITS_MASK		(0xffffffff)
109 
110 #define DMA_ADDR_EXT_BITS		(36)
111 #define DMA_ADDR_DEF_BITS		(32)
112 
113 /**
114  * struct mtk_spi_compatible - device data structure
115  * @need_pad_sel:	Enable pad (pins) selection in SPI controller
116  * @must_tx:		Must explicitly send dummy TX bytes to do RX only transfer
117  * @enhance_timing:	Enable adjusting cfg register to enhance time accuracy
118  * @dma_ext:		DMA address extension supported
119  * @no_need_unprepare:	Don't unprepare the SPI clk during runtime
120  * @ipm_design:		Adjust/extend registers to support IPM design IP features
121  */
122 struct mtk_spi_compatible {
123 	bool need_pad_sel;
124 	bool must_tx;
125 	bool enhance_timing;
126 	bool dma_ext;
127 	bool no_need_unprepare;
128 	bool ipm_design;
129 };
130 
131 /**
132  * struct mtk_spi - SPI driver instance
133  * @base:		Start address of the SPI controller registers
134  * @state:		SPI controller state
135  * @pad_num:		Number of pad_sel entries
136  * @pad_sel:		Groups of pins to select
137  * @parent_clk:		Parent of sel_clk
138  * @sel_clk:		SPI master mux clock
139  * @spi_clk:		Peripheral clock
140  * @spi_hclk:		AHB bus clock
141  * @cur_transfer:	Currently processed SPI transfer
142  * @xfer_len:		Number of bytes to transfer
143  * @num_xfered:		Number of transferred bytes
144  * @tx_sgl:		TX transfer scatterlist
145  * @rx_sgl:		RX transfer scatterlist
146  * @tx_sgl_len:		Size of TX DMA transfer
147  * @rx_sgl_len:		Size of RX DMA transfer
148  * @dev_comp:		Device data structure
149  * @spi_clk_hz:		Current SPI clock in Hz
150  * @spimem_done:	SPI-MEM operation completion
151  * @use_spimem:		Enables SPI-MEM
152  * @dev:		Device pointer
153  * @tx_dma:		DMA start for SPI-MEM TX
154  * @rx_dma:		DMA start for SPI-MEM RX
155  */
156 struct mtk_spi {
157 	void __iomem *base;
158 	u32 state;
159 	int pad_num;
160 	u32 *pad_sel;
161 	struct clk *parent_clk, *sel_clk, *spi_clk, *spi_hclk;
162 	struct spi_transfer *cur_transfer;
163 	u32 xfer_len;
164 	u32 num_xfered;
165 	struct scatterlist *tx_sgl, *rx_sgl;
166 	u32 tx_sgl_len, rx_sgl_len;
167 	const struct mtk_spi_compatible *dev_comp;
168 	u32 spi_clk_hz;
169 	struct completion spimem_done;
170 	bool use_spimem;
171 	struct device *dev;
172 	dma_addr_t tx_dma;
173 	dma_addr_t rx_dma;
174 };
175 
176 static const struct mtk_spi_compatible mtk_common_compat;
177 
178 static const struct mtk_spi_compatible mt2712_compat = {
179 	.must_tx = true,
180 };
181 
182 static const struct mtk_spi_compatible mtk_ipm_compat = {
183 	.enhance_timing = true,
184 	.dma_ext = true,
185 	.ipm_design = true,
186 };
187 
188 static const struct mtk_spi_compatible mt6765_compat = {
189 	.need_pad_sel = true,
190 	.must_tx = true,
191 	.enhance_timing = true,
192 	.dma_ext = true,
193 };
194 
195 static const struct mtk_spi_compatible mt7622_compat = {
196 	.must_tx = true,
197 	.enhance_timing = true,
198 };
199 
200 static const struct mtk_spi_compatible mt8173_compat = {
201 	.need_pad_sel = true,
202 	.must_tx = true,
203 };
204 
205 static const struct mtk_spi_compatible mt8183_compat = {
206 	.need_pad_sel = true,
207 	.must_tx = true,
208 	.enhance_timing = true,
209 };
210 
211 static const struct mtk_spi_compatible mt6893_compat = {
212 	.need_pad_sel = true,
213 	.must_tx = true,
214 	.enhance_timing = true,
215 	.dma_ext = true,
216 	.no_need_unprepare = true,
217 };
218 
219 /*
220  * A piece of default chip info unless the platform
221  * supplies it.
222  */
223 static const struct mtk_chip_config mtk_default_chip_info = {
224 	.sample_sel = 0,
225 	.tick_delay = 0,
226 };
227 
228 static const struct of_device_id mtk_spi_of_match[] = {
229 	{ .compatible = "mediatek,spi-ipm",
230 		.data = (void *)&mtk_ipm_compat,
231 	},
232 	{ .compatible = "mediatek,mt2701-spi",
233 		.data = (void *)&mtk_common_compat,
234 	},
235 	{ .compatible = "mediatek,mt2712-spi",
236 		.data = (void *)&mt2712_compat,
237 	},
238 	{ .compatible = "mediatek,mt6589-spi",
239 		.data = (void *)&mtk_common_compat,
240 	},
241 	{ .compatible = "mediatek,mt6765-spi",
242 		.data = (void *)&mt6765_compat,
243 	},
244 	{ .compatible = "mediatek,mt7622-spi",
245 		.data = (void *)&mt7622_compat,
246 	},
247 	{ .compatible = "mediatek,mt7629-spi",
248 		.data = (void *)&mt7622_compat,
249 	},
250 	{ .compatible = "mediatek,mt8135-spi",
251 		.data = (void *)&mtk_common_compat,
252 	},
253 	{ .compatible = "mediatek,mt8173-spi",
254 		.data = (void *)&mt8173_compat,
255 	},
256 	{ .compatible = "mediatek,mt8183-spi",
257 		.data = (void *)&mt8183_compat,
258 	},
259 	{ .compatible = "mediatek,mt8192-spi",
260 		.data = (void *)&mt6765_compat,
261 	},
262 	{ .compatible = "mediatek,mt6893-spi",
263 		.data = (void *)&mt6893_compat,
264 	},
265 	{}
266 };
267 MODULE_DEVICE_TABLE(of, mtk_spi_of_match);
268 
mtk_spi_reset(struct mtk_spi * mdata)269 static void mtk_spi_reset(struct mtk_spi *mdata)
270 {
271 	u32 reg_val;
272 
273 	/* set the software reset bit in SPI_CMD_REG. */
274 	reg_val = readl(mdata->base + SPI_CMD_REG);
275 	reg_val |= SPI_CMD_RST;
276 	writel(reg_val, mdata->base + SPI_CMD_REG);
277 
278 	reg_val = readl(mdata->base + SPI_CMD_REG);
279 	reg_val &= ~SPI_CMD_RST;
280 	writel(reg_val, mdata->base + SPI_CMD_REG);
281 }
282 
mtk_spi_set_hw_cs_timing(struct spi_device * spi)283 static int mtk_spi_set_hw_cs_timing(struct spi_device *spi)
284 {
285 	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
286 	struct spi_delay *cs_setup = &spi->cs_setup;
287 	struct spi_delay *cs_hold = &spi->cs_hold;
288 	struct spi_delay *cs_inactive = &spi->cs_inactive;
289 	u32 setup, hold, inactive;
290 	u32 reg_val;
291 	int delay;
292 
293 	delay = spi_delay_to_ns(cs_setup, NULL);
294 	if (delay < 0)
295 		return delay;
296 	setup = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
297 
298 	delay = spi_delay_to_ns(cs_hold, NULL);
299 	if (delay < 0)
300 		return delay;
301 	hold = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
302 
303 	delay = spi_delay_to_ns(cs_inactive, NULL);
304 	if (delay < 0)
305 		return delay;
306 	inactive = (delay * DIV_ROUND_UP(mdata->spi_clk_hz, 1000000)) / 1000;
307 
308 	if (hold || setup) {
309 		reg_val = readl(mdata->base + SPI_CFG0_REG);
310 		if (mdata->dev_comp->enhance_timing) {
311 			if (hold) {
312 				hold = min_t(u32, hold, 0x10000);
313 				reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
314 				reg_val |= (((hold - 1) & 0xffff)
315 					<< SPI_ADJUST_CFG0_CS_HOLD_OFFSET);
316 			}
317 			if (setup) {
318 				setup = min_t(u32, setup, 0x10000);
319 				reg_val &= ~(0xffff << SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
320 				reg_val |= (((setup - 1) & 0xffff)
321 					<< SPI_ADJUST_CFG0_CS_SETUP_OFFSET);
322 			}
323 		} else {
324 			if (hold) {
325 				hold = min_t(u32, hold, 0x100);
326 				reg_val &= ~(0xff << SPI_CFG0_CS_HOLD_OFFSET);
327 				reg_val |= (((hold - 1) & 0xff) << SPI_CFG0_CS_HOLD_OFFSET);
328 			}
329 			if (setup) {
330 				setup = min_t(u32, setup, 0x100);
331 				reg_val &= ~(0xff << SPI_CFG0_CS_SETUP_OFFSET);
332 				reg_val |= (((setup - 1) & 0xff)
333 					<< SPI_CFG0_CS_SETUP_OFFSET);
334 			}
335 		}
336 		writel(reg_val, mdata->base + SPI_CFG0_REG);
337 	}
338 
339 	if (inactive) {
340 		inactive = min_t(u32, inactive, 0x100);
341 		reg_val = readl(mdata->base + SPI_CFG1_REG);
342 		reg_val &= ~SPI_CFG1_CS_IDLE_MASK;
343 		reg_val |= (((inactive - 1) & 0xff) << SPI_CFG1_CS_IDLE_OFFSET);
344 		writel(reg_val, mdata->base + SPI_CFG1_REG);
345 	}
346 
347 	return 0;
348 }
349 
mtk_spi_hw_init(struct spi_master * master,struct spi_device * spi)350 static int mtk_spi_hw_init(struct spi_master *master,
351 			   struct spi_device *spi)
352 {
353 	u16 cpha, cpol;
354 	u32 reg_val;
355 	struct mtk_chip_config *chip_config = spi->controller_data;
356 	struct mtk_spi *mdata = spi_master_get_devdata(master);
357 
358 	cpha = spi->mode & SPI_CPHA ? 1 : 0;
359 	cpol = spi->mode & SPI_CPOL ? 1 : 0;
360 
361 	reg_val = readl(mdata->base + SPI_CMD_REG);
362 	if (mdata->dev_comp->ipm_design) {
363 		/* SPI transfer without idle time until packet length done */
364 		reg_val |= SPI_CMD_IPM_NONIDLE_MODE;
365 		if (spi->mode & SPI_LOOP)
366 			reg_val |= SPI_CMD_IPM_SPIM_LOOP;
367 		else
368 			reg_val &= ~SPI_CMD_IPM_SPIM_LOOP;
369 	}
370 
371 	if (cpha)
372 		reg_val |= SPI_CMD_CPHA;
373 	else
374 		reg_val &= ~SPI_CMD_CPHA;
375 	if (cpol)
376 		reg_val |= SPI_CMD_CPOL;
377 	else
378 		reg_val &= ~SPI_CMD_CPOL;
379 
380 	/* set the mlsbx and mlsbtx */
381 	if (spi->mode & SPI_LSB_FIRST) {
382 		reg_val &= ~SPI_CMD_TXMSBF;
383 		reg_val &= ~SPI_CMD_RXMSBF;
384 	} else {
385 		reg_val |= SPI_CMD_TXMSBF;
386 		reg_val |= SPI_CMD_RXMSBF;
387 	}
388 
389 	/* set the tx/rx endian */
390 #ifdef __LITTLE_ENDIAN
391 	reg_val &= ~SPI_CMD_TX_ENDIAN;
392 	reg_val &= ~SPI_CMD_RX_ENDIAN;
393 #else
394 	reg_val |= SPI_CMD_TX_ENDIAN;
395 	reg_val |= SPI_CMD_RX_ENDIAN;
396 #endif
397 
398 	if (mdata->dev_comp->enhance_timing) {
399 		/* set CS polarity */
400 		if (spi->mode & SPI_CS_HIGH)
401 			reg_val |= SPI_CMD_CS_POL;
402 		else
403 			reg_val &= ~SPI_CMD_CS_POL;
404 
405 		if (chip_config->sample_sel)
406 			reg_val |= SPI_CMD_SAMPLE_SEL;
407 		else
408 			reg_val &= ~SPI_CMD_SAMPLE_SEL;
409 	}
410 
411 	/* set finish and pause interrupt always enable */
412 	reg_val |= SPI_CMD_FINISH_IE | SPI_CMD_PAUSE_IE;
413 
414 	/* disable dma mode */
415 	reg_val &= ~(SPI_CMD_TX_DMA | SPI_CMD_RX_DMA);
416 
417 	/* disable deassert mode */
418 	reg_val &= ~SPI_CMD_DEASSERT;
419 
420 	writel(reg_val, mdata->base + SPI_CMD_REG);
421 
422 	/* pad select */
423 	if (mdata->dev_comp->need_pad_sel)
424 		writel(mdata->pad_sel[spi_get_chipselect(spi, 0)],
425 		       mdata->base + SPI_PAD_SEL_REG);
426 
427 	/* tick delay */
428 	if (mdata->dev_comp->enhance_timing) {
429 		if (mdata->dev_comp->ipm_design) {
430 			reg_val = readl(mdata->base + SPI_CMD_REG);
431 			reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK;
432 			reg_val |= ((chip_config->tick_delay & 0x7)
433 				    << SPI_CMD_IPM_GET_TICKDLY_OFFSET);
434 			writel(reg_val, mdata->base + SPI_CMD_REG);
435 		} else {
436 			reg_val = readl(mdata->base + SPI_CFG1_REG);
437 			reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK;
438 			reg_val |= ((chip_config->tick_delay & 0x7)
439 				    << SPI_CFG1_GET_TICK_DLY_OFFSET);
440 			writel(reg_val, mdata->base + SPI_CFG1_REG);
441 		}
442 	} else {
443 		reg_val = readl(mdata->base + SPI_CFG1_REG);
444 		reg_val &= ~SPI_CFG1_GET_TICK_DLY_MASK_V1;
445 		reg_val |= ((chip_config->tick_delay & 0x3)
446 			    << SPI_CFG1_GET_TICK_DLY_OFFSET_V1);
447 		writel(reg_val, mdata->base + SPI_CFG1_REG);
448 	}
449 
450 	/* set hw cs timing */
451 	mtk_spi_set_hw_cs_timing(spi);
452 	return 0;
453 }
454 
mtk_spi_prepare_message(struct spi_master * master,struct spi_message * msg)455 static int mtk_spi_prepare_message(struct spi_master *master,
456 				   struct spi_message *msg)
457 {
458 	return mtk_spi_hw_init(master, msg->spi);
459 }
460 
mtk_spi_set_cs(struct spi_device * spi,bool enable)461 static void mtk_spi_set_cs(struct spi_device *spi, bool enable)
462 {
463 	u32 reg_val;
464 	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
465 
466 	if (spi->mode & SPI_CS_HIGH)
467 		enable = !enable;
468 
469 	reg_val = readl(mdata->base + SPI_CMD_REG);
470 	if (!enable) {
471 		reg_val |= SPI_CMD_PAUSE_EN;
472 		writel(reg_val, mdata->base + SPI_CMD_REG);
473 	} else {
474 		reg_val &= ~SPI_CMD_PAUSE_EN;
475 		writel(reg_val, mdata->base + SPI_CMD_REG);
476 		mdata->state = MTK_SPI_IDLE;
477 		mtk_spi_reset(mdata);
478 	}
479 }
480 
mtk_spi_prepare_transfer(struct spi_master * master,u32 speed_hz)481 static void mtk_spi_prepare_transfer(struct spi_master *master,
482 				     u32 speed_hz)
483 {
484 	u32 div, sck_time, reg_val;
485 	struct mtk_spi *mdata = spi_master_get_devdata(master);
486 
487 	if (speed_hz < mdata->spi_clk_hz / 2)
488 		div = DIV_ROUND_UP(mdata->spi_clk_hz, speed_hz);
489 	else
490 		div = 1;
491 
492 	sck_time = (div + 1) / 2;
493 
494 	if (mdata->dev_comp->enhance_timing) {
495 		reg_val = readl(mdata->base + SPI_CFG2_REG);
496 		reg_val &= ~(0xffff << SPI_CFG2_SCK_HIGH_OFFSET);
497 		reg_val |= (((sck_time - 1) & 0xffff)
498 			   << SPI_CFG2_SCK_HIGH_OFFSET);
499 		reg_val &= ~(0xffff << SPI_CFG2_SCK_LOW_OFFSET);
500 		reg_val |= (((sck_time - 1) & 0xffff)
501 			   << SPI_CFG2_SCK_LOW_OFFSET);
502 		writel(reg_val, mdata->base + SPI_CFG2_REG);
503 	} else {
504 		reg_val = readl(mdata->base + SPI_CFG0_REG);
505 		reg_val &= ~(0xff << SPI_CFG0_SCK_HIGH_OFFSET);
506 		reg_val |= (((sck_time - 1) & 0xff)
507 			   << SPI_CFG0_SCK_HIGH_OFFSET);
508 		reg_val &= ~(0xff << SPI_CFG0_SCK_LOW_OFFSET);
509 		reg_val |= (((sck_time - 1) & 0xff) << SPI_CFG0_SCK_LOW_OFFSET);
510 		writel(reg_val, mdata->base + SPI_CFG0_REG);
511 	}
512 }
513 
mtk_spi_setup_packet(struct spi_master * master)514 static void mtk_spi_setup_packet(struct spi_master *master)
515 {
516 	u32 packet_size, packet_loop, reg_val;
517 	struct mtk_spi *mdata = spi_master_get_devdata(master);
518 
519 	if (mdata->dev_comp->ipm_design)
520 		packet_size = min_t(u32,
521 				    mdata->xfer_len,
522 				    MTK_SPI_IPM_PACKET_SIZE);
523 	else
524 		packet_size = min_t(u32,
525 				    mdata->xfer_len,
526 				    MTK_SPI_PACKET_SIZE);
527 
528 	packet_loop = mdata->xfer_len / packet_size;
529 
530 	reg_val = readl(mdata->base + SPI_CFG1_REG);
531 	if (mdata->dev_comp->ipm_design)
532 		reg_val &= ~SPI_CFG1_IPM_PACKET_LENGTH_MASK;
533 	else
534 		reg_val &= ~SPI_CFG1_PACKET_LENGTH_MASK;
535 	reg_val |= (packet_size - 1) << SPI_CFG1_PACKET_LENGTH_OFFSET;
536 	reg_val &= ~SPI_CFG1_PACKET_LOOP_MASK;
537 	reg_val |= (packet_loop - 1) << SPI_CFG1_PACKET_LOOP_OFFSET;
538 	writel(reg_val, mdata->base + SPI_CFG1_REG);
539 }
540 
mtk_spi_enable_transfer(struct spi_master * master)541 static void mtk_spi_enable_transfer(struct spi_master *master)
542 {
543 	u32 cmd;
544 	struct mtk_spi *mdata = spi_master_get_devdata(master);
545 
546 	cmd = readl(mdata->base + SPI_CMD_REG);
547 	if (mdata->state == MTK_SPI_IDLE)
548 		cmd |= SPI_CMD_ACT;
549 	else
550 		cmd |= SPI_CMD_RESUME;
551 	writel(cmd, mdata->base + SPI_CMD_REG);
552 }
553 
mtk_spi_get_mult_delta(struct mtk_spi * mdata,u32 xfer_len)554 static int mtk_spi_get_mult_delta(struct mtk_spi *mdata, u32 xfer_len)
555 {
556 	u32 mult_delta = 0;
557 
558 	if (mdata->dev_comp->ipm_design) {
559 		if (xfer_len > MTK_SPI_IPM_PACKET_SIZE)
560 			mult_delta = xfer_len % MTK_SPI_IPM_PACKET_SIZE;
561 	} else {
562 		if (xfer_len > MTK_SPI_PACKET_SIZE)
563 			mult_delta = xfer_len % MTK_SPI_PACKET_SIZE;
564 	}
565 
566 	return mult_delta;
567 }
568 
mtk_spi_update_mdata_len(struct spi_master * master)569 static void mtk_spi_update_mdata_len(struct spi_master *master)
570 {
571 	int mult_delta;
572 	struct mtk_spi *mdata = spi_master_get_devdata(master);
573 
574 	if (mdata->tx_sgl_len && mdata->rx_sgl_len) {
575 		if (mdata->tx_sgl_len > mdata->rx_sgl_len) {
576 			mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len);
577 			mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
578 			mdata->rx_sgl_len = mult_delta;
579 			mdata->tx_sgl_len -= mdata->xfer_len;
580 		} else {
581 			mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len);
582 			mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
583 			mdata->tx_sgl_len = mult_delta;
584 			mdata->rx_sgl_len -= mdata->xfer_len;
585 		}
586 	} else if (mdata->tx_sgl_len) {
587 		mult_delta = mtk_spi_get_mult_delta(mdata, mdata->tx_sgl_len);
588 		mdata->xfer_len = mdata->tx_sgl_len - mult_delta;
589 		mdata->tx_sgl_len = mult_delta;
590 	} else if (mdata->rx_sgl_len) {
591 		mult_delta = mtk_spi_get_mult_delta(mdata, mdata->rx_sgl_len);
592 		mdata->xfer_len = mdata->rx_sgl_len - mult_delta;
593 		mdata->rx_sgl_len = mult_delta;
594 	}
595 }
596 
mtk_spi_setup_dma_addr(struct spi_master * master,struct spi_transfer * xfer)597 static void mtk_spi_setup_dma_addr(struct spi_master *master,
598 				   struct spi_transfer *xfer)
599 {
600 	struct mtk_spi *mdata = spi_master_get_devdata(master);
601 
602 	if (mdata->tx_sgl) {
603 		writel((u32)(xfer->tx_dma & MTK_SPI_32BITS_MASK),
604 		       mdata->base + SPI_TX_SRC_REG);
605 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
606 		if (mdata->dev_comp->dma_ext)
607 			writel((u32)(xfer->tx_dma >> 32),
608 			       mdata->base + SPI_TX_SRC_REG_64);
609 #endif
610 	}
611 
612 	if (mdata->rx_sgl) {
613 		writel((u32)(xfer->rx_dma & MTK_SPI_32BITS_MASK),
614 		       mdata->base + SPI_RX_DST_REG);
615 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
616 		if (mdata->dev_comp->dma_ext)
617 			writel((u32)(xfer->rx_dma >> 32),
618 			       mdata->base + SPI_RX_DST_REG_64);
619 #endif
620 	}
621 }
622 
mtk_spi_fifo_transfer(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)623 static int mtk_spi_fifo_transfer(struct spi_master *master,
624 				 struct spi_device *spi,
625 				 struct spi_transfer *xfer)
626 {
627 	int cnt, remainder;
628 	u32 reg_val;
629 	struct mtk_spi *mdata = spi_master_get_devdata(master);
630 
631 	mdata->cur_transfer = xfer;
632 	mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, xfer->len);
633 	mdata->num_xfered = 0;
634 	mtk_spi_prepare_transfer(master, xfer->speed_hz);
635 	mtk_spi_setup_packet(master);
636 
637 	if (xfer->tx_buf) {
638 		cnt = xfer->len / 4;
639 		iowrite32_rep(mdata->base + SPI_TX_DATA_REG, xfer->tx_buf, cnt);
640 		remainder = xfer->len % 4;
641 		if (remainder > 0) {
642 			reg_val = 0;
643 			memcpy(&reg_val, xfer->tx_buf + (cnt * 4), remainder);
644 			writel(reg_val, mdata->base + SPI_TX_DATA_REG);
645 		}
646 	}
647 
648 	mtk_spi_enable_transfer(master);
649 
650 	return 1;
651 }
652 
mtk_spi_dma_transfer(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)653 static int mtk_spi_dma_transfer(struct spi_master *master,
654 				struct spi_device *spi,
655 				struct spi_transfer *xfer)
656 {
657 	int cmd;
658 	struct mtk_spi *mdata = spi_master_get_devdata(master);
659 
660 	mdata->tx_sgl = NULL;
661 	mdata->rx_sgl = NULL;
662 	mdata->tx_sgl_len = 0;
663 	mdata->rx_sgl_len = 0;
664 	mdata->cur_transfer = xfer;
665 	mdata->num_xfered = 0;
666 
667 	mtk_spi_prepare_transfer(master, xfer->speed_hz);
668 
669 	cmd = readl(mdata->base + SPI_CMD_REG);
670 	if (xfer->tx_buf)
671 		cmd |= SPI_CMD_TX_DMA;
672 	if (xfer->rx_buf)
673 		cmd |= SPI_CMD_RX_DMA;
674 	writel(cmd, mdata->base + SPI_CMD_REG);
675 
676 	if (xfer->tx_buf)
677 		mdata->tx_sgl = xfer->tx_sg.sgl;
678 	if (xfer->rx_buf)
679 		mdata->rx_sgl = xfer->rx_sg.sgl;
680 
681 	if (mdata->tx_sgl) {
682 		xfer->tx_dma = sg_dma_address(mdata->tx_sgl);
683 		mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
684 	}
685 	if (mdata->rx_sgl) {
686 		xfer->rx_dma = sg_dma_address(mdata->rx_sgl);
687 		mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
688 	}
689 
690 	mtk_spi_update_mdata_len(master);
691 	mtk_spi_setup_packet(master);
692 	mtk_spi_setup_dma_addr(master, xfer);
693 	mtk_spi_enable_transfer(master);
694 
695 	return 1;
696 }
697 
mtk_spi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)698 static int mtk_spi_transfer_one(struct spi_master *master,
699 				struct spi_device *spi,
700 				struct spi_transfer *xfer)
701 {
702 	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
703 	u32 reg_val = 0;
704 
705 	/* prepare xfer direction and duplex mode */
706 	if (mdata->dev_comp->ipm_design) {
707 		if (!xfer->tx_buf || !xfer->rx_buf) {
708 			reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
709 			if (xfer->rx_buf)
710 				reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
711 		}
712 		writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
713 	}
714 
715 	if (master->can_dma(master, spi, xfer))
716 		return mtk_spi_dma_transfer(master, spi, xfer);
717 	else
718 		return mtk_spi_fifo_transfer(master, spi, xfer);
719 }
720 
mtk_spi_can_dma(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)721 static bool mtk_spi_can_dma(struct spi_master *master,
722 			    struct spi_device *spi,
723 			    struct spi_transfer *xfer)
724 {
725 	/* Buffers for DMA transactions must be 4-byte aligned */
726 	return (xfer->len > MTK_SPI_MAX_FIFO_SIZE &&
727 		(unsigned long)xfer->tx_buf % 4 == 0 &&
728 		(unsigned long)xfer->rx_buf % 4 == 0);
729 }
730 
mtk_spi_setup(struct spi_device * spi)731 static int mtk_spi_setup(struct spi_device *spi)
732 {
733 	struct mtk_spi *mdata = spi_master_get_devdata(spi->master);
734 
735 	if (!spi->controller_data)
736 		spi->controller_data = (void *)&mtk_default_chip_info;
737 
738 	if (mdata->dev_comp->need_pad_sel && spi_get_csgpiod(spi, 0))
739 		/* CS de-asserted, gpiolib will handle inversion */
740 		gpiod_direction_output(spi_get_csgpiod(spi, 0), 0);
741 
742 	return 0;
743 }
744 
mtk_spi_interrupt(int irq,void * dev_id)745 static irqreturn_t mtk_spi_interrupt(int irq, void *dev_id)
746 {
747 	u32 cmd, reg_val, cnt, remainder, len;
748 	struct spi_master *master = dev_id;
749 	struct mtk_spi *mdata = spi_master_get_devdata(master);
750 	struct spi_transfer *trans = mdata->cur_transfer;
751 
752 	reg_val = readl(mdata->base + SPI_STATUS0_REG);
753 	if (reg_val & MTK_SPI_PAUSE_INT_STATUS)
754 		mdata->state = MTK_SPI_PAUSED;
755 	else
756 		mdata->state = MTK_SPI_IDLE;
757 
758 	/* SPI-MEM ops */
759 	if (mdata->use_spimem) {
760 		complete(&mdata->spimem_done);
761 		return IRQ_HANDLED;
762 	}
763 
764 	if (!master->can_dma(master, NULL, trans)) {
765 		if (trans->rx_buf) {
766 			cnt = mdata->xfer_len / 4;
767 			ioread32_rep(mdata->base + SPI_RX_DATA_REG,
768 				     trans->rx_buf + mdata->num_xfered, cnt);
769 			remainder = mdata->xfer_len % 4;
770 			if (remainder > 0) {
771 				reg_val = readl(mdata->base + SPI_RX_DATA_REG);
772 				memcpy(trans->rx_buf +
773 					mdata->num_xfered +
774 					(cnt * 4),
775 					&reg_val,
776 					remainder);
777 			}
778 		}
779 
780 		mdata->num_xfered += mdata->xfer_len;
781 		if (mdata->num_xfered == trans->len) {
782 			spi_finalize_current_transfer(master);
783 			return IRQ_HANDLED;
784 		}
785 
786 		len = trans->len - mdata->num_xfered;
787 		mdata->xfer_len = min(MTK_SPI_MAX_FIFO_SIZE, len);
788 		mtk_spi_setup_packet(master);
789 
790 		if (trans->tx_buf) {
791 			cnt = mdata->xfer_len / 4;
792 			iowrite32_rep(mdata->base + SPI_TX_DATA_REG,
793 					trans->tx_buf + mdata->num_xfered, cnt);
794 
795 			remainder = mdata->xfer_len % 4;
796 			if (remainder > 0) {
797 				reg_val = 0;
798 				memcpy(&reg_val,
799 					trans->tx_buf + (cnt * 4) + mdata->num_xfered,
800 					remainder);
801 				writel(reg_val, mdata->base + SPI_TX_DATA_REG);
802 			}
803 		}
804 
805 		mtk_spi_enable_transfer(master);
806 
807 		return IRQ_HANDLED;
808 	}
809 
810 	if (mdata->tx_sgl)
811 		trans->tx_dma += mdata->xfer_len;
812 	if (mdata->rx_sgl)
813 		trans->rx_dma += mdata->xfer_len;
814 
815 	if (mdata->tx_sgl && (mdata->tx_sgl_len == 0)) {
816 		mdata->tx_sgl = sg_next(mdata->tx_sgl);
817 		if (mdata->tx_sgl) {
818 			trans->tx_dma = sg_dma_address(mdata->tx_sgl);
819 			mdata->tx_sgl_len = sg_dma_len(mdata->tx_sgl);
820 		}
821 	}
822 	if (mdata->rx_sgl && (mdata->rx_sgl_len == 0)) {
823 		mdata->rx_sgl = sg_next(mdata->rx_sgl);
824 		if (mdata->rx_sgl) {
825 			trans->rx_dma = sg_dma_address(mdata->rx_sgl);
826 			mdata->rx_sgl_len = sg_dma_len(mdata->rx_sgl);
827 		}
828 	}
829 
830 	if (!mdata->tx_sgl && !mdata->rx_sgl) {
831 		/* spi disable dma */
832 		cmd = readl(mdata->base + SPI_CMD_REG);
833 		cmd &= ~SPI_CMD_TX_DMA;
834 		cmd &= ~SPI_CMD_RX_DMA;
835 		writel(cmd, mdata->base + SPI_CMD_REG);
836 
837 		spi_finalize_current_transfer(master);
838 		return IRQ_HANDLED;
839 	}
840 
841 	mtk_spi_update_mdata_len(master);
842 	mtk_spi_setup_packet(master);
843 	mtk_spi_setup_dma_addr(master, trans);
844 	mtk_spi_enable_transfer(master);
845 
846 	return IRQ_HANDLED;
847 }
848 
mtk_spi_mem_adjust_op_size(struct spi_mem * mem,struct spi_mem_op * op)849 static int mtk_spi_mem_adjust_op_size(struct spi_mem *mem,
850 				      struct spi_mem_op *op)
851 {
852 	int opcode_len;
853 
854 	if (op->data.dir != SPI_MEM_NO_DATA) {
855 		opcode_len = 1 + op->addr.nbytes + op->dummy.nbytes;
856 		if (opcode_len + op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
857 			op->data.nbytes = MTK_SPI_IPM_PACKET_SIZE - opcode_len;
858 			/* force data buffer dma-aligned. */
859 			op->data.nbytes -= op->data.nbytes % 4;
860 		}
861 	}
862 
863 	return 0;
864 }
865 
mtk_spi_mem_supports_op(struct spi_mem * mem,const struct spi_mem_op * op)866 static bool mtk_spi_mem_supports_op(struct spi_mem *mem,
867 				    const struct spi_mem_op *op)
868 {
869 	if (!spi_mem_default_supports_op(mem, op))
870 		return false;
871 
872 	if (op->addr.nbytes && op->dummy.nbytes &&
873 	    op->addr.buswidth != op->dummy.buswidth)
874 		return false;
875 
876 	if (op->addr.nbytes + op->dummy.nbytes > 16)
877 		return false;
878 
879 	if (op->data.nbytes > MTK_SPI_IPM_PACKET_SIZE) {
880 		if (op->data.nbytes / MTK_SPI_IPM_PACKET_SIZE >
881 		    MTK_SPI_IPM_PACKET_LOOP ||
882 		    op->data.nbytes % MTK_SPI_IPM_PACKET_SIZE != 0)
883 			return false;
884 	}
885 
886 	return true;
887 }
888 
mtk_spi_mem_setup_dma_xfer(struct spi_master * master,const struct spi_mem_op * op)889 static void mtk_spi_mem_setup_dma_xfer(struct spi_master *master,
890 				       const struct spi_mem_op *op)
891 {
892 	struct mtk_spi *mdata = spi_master_get_devdata(master);
893 
894 	writel((u32)(mdata->tx_dma & MTK_SPI_32BITS_MASK),
895 	       mdata->base + SPI_TX_SRC_REG);
896 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
897 	if (mdata->dev_comp->dma_ext)
898 		writel((u32)(mdata->tx_dma >> 32),
899 		       mdata->base + SPI_TX_SRC_REG_64);
900 #endif
901 
902 	if (op->data.dir == SPI_MEM_DATA_IN) {
903 		writel((u32)(mdata->rx_dma & MTK_SPI_32BITS_MASK),
904 		       mdata->base + SPI_RX_DST_REG);
905 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
906 		if (mdata->dev_comp->dma_ext)
907 			writel((u32)(mdata->rx_dma >> 32),
908 			       mdata->base + SPI_RX_DST_REG_64);
909 #endif
910 	}
911 }
912 
mtk_spi_transfer_wait(struct spi_mem * mem,const struct spi_mem_op * op)913 static int mtk_spi_transfer_wait(struct spi_mem *mem,
914 				 const struct spi_mem_op *op)
915 {
916 	struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
917 	/*
918 	 * For each byte we wait for 8 cycles of the SPI clock.
919 	 * Since speed is defined in Hz and we want milliseconds,
920 	 * so it should be 8 * 1000.
921 	 */
922 	u64 ms = 8000LL;
923 
924 	if (op->data.dir == SPI_MEM_NO_DATA)
925 		ms *= 32; /* prevent we may get 0 for short transfers. */
926 	else
927 		ms *= op->data.nbytes;
928 	ms = div_u64(ms, mem->spi->max_speed_hz);
929 	ms += ms + 1000; /* 1s tolerance */
930 
931 	if (ms > UINT_MAX)
932 		ms = UINT_MAX;
933 
934 	if (!wait_for_completion_timeout(&mdata->spimem_done,
935 					 msecs_to_jiffies(ms))) {
936 		dev_err(mdata->dev, "spi-mem transfer timeout\n");
937 		return -ETIMEDOUT;
938 	}
939 
940 	return 0;
941 }
942 
mtk_spi_mem_exec_op(struct spi_mem * mem,const struct spi_mem_op * op)943 static int mtk_spi_mem_exec_op(struct spi_mem *mem,
944 			       const struct spi_mem_op *op)
945 {
946 	struct mtk_spi *mdata = spi_master_get_devdata(mem->spi->master);
947 	u32 reg_val, nio, tx_size;
948 	char *tx_tmp_buf, *rx_tmp_buf;
949 	int ret = 0;
950 
951 	mdata->use_spimem = true;
952 	reinit_completion(&mdata->spimem_done);
953 
954 	mtk_spi_reset(mdata);
955 	mtk_spi_hw_init(mem->spi->master, mem->spi);
956 	mtk_spi_prepare_transfer(mem->spi->master, mem->spi->max_speed_hz);
957 
958 	reg_val = readl(mdata->base + SPI_CFG3_IPM_REG);
959 	/* opcode byte len */
960 	reg_val &= ~SPI_CFG3_IPM_CMD_BYTELEN_MASK;
961 	reg_val |= 1 << SPI_CFG3_IPM_CMD_BYTELEN_OFFSET;
962 
963 	/* addr & dummy byte len */
964 	reg_val &= ~SPI_CFG3_IPM_ADDR_BYTELEN_MASK;
965 	if (op->addr.nbytes || op->dummy.nbytes)
966 		reg_val |= (op->addr.nbytes + op->dummy.nbytes) <<
967 			    SPI_CFG3_IPM_ADDR_BYTELEN_OFFSET;
968 
969 	/* data byte len */
970 	if (op->data.dir == SPI_MEM_NO_DATA) {
971 		reg_val |= SPI_CFG3_IPM_NODATA_FLAG;
972 		writel(0, mdata->base + SPI_CFG1_REG);
973 	} else {
974 		reg_val &= ~SPI_CFG3_IPM_NODATA_FLAG;
975 		mdata->xfer_len = op->data.nbytes;
976 		mtk_spi_setup_packet(mem->spi->master);
977 	}
978 
979 	if (op->addr.nbytes || op->dummy.nbytes) {
980 		if (op->addr.buswidth == 1 || op->dummy.buswidth == 1)
981 			reg_val |= SPI_CFG3_IPM_XMODE_EN;
982 		else
983 			reg_val &= ~SPI_CFG3_IPM_XMODE_EN;
984 	}
985 
986 	if (op->addr.buswidth == 2 ||
987 	    op->dummy.buswidth == 2 ||
988 	    op->data.buswidth == 2)
989 		nio = 2;
990 	else if (op->addr.buswidth == 4 ||
991 		 op->dummy.buswidth == 4 ||
992 		 op->data.buswidth == 4)
993 		nio = 4;
994 	else
995 		nio = 1;
996 
997 	reg_val &= ~SPI_CFG3_IPM_CMD_PIN_MODE_MASK;
998 	reg_val |= PIN_MODE_CFG(nio);
999 
1000 	reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_EN;
1001 	if (op->data.dir == SPI_MEM_DATA_IN)
1002 		reg_val |= SPI_CFG3_IPM_HALF_DUPLEX_DIR;
1003 	else
1004 		reg_val &= ~SPI_CFG3_IPM_HALF_DUPLEX_DIR;
1005 	writel(reg_val, mdata->base + SPI_CFG3_IPM_REG);
1006 
1007 	tx_size = 1 + op->addr.nbytes + op->dummy.nbytes;
1008 	if (op->data.dir == SPI_MEM_DATA_OUT)
1009 		tx_size += op->data.nbytes;
1010 
1011 	tx_size = max_t(u32, tx_size, 32);
1012 
1013 	tx_tmp_buf = kzalloc(tx_size, GFP_KERNEL | GFP_DMA);
1014 	if (!tx_tmp_buf) {
1015 		mdata->use_spimem = false;
1016 		return -ENOMEM;
1017 	}
1018 
1019 	tx_tmp_buf[0] = op->cmd.opcode;
1020 
1021 	if (op->addr.nbytes) {
1022 		int i;
1023 
1024 		for (i = 0; i < op->addr.nbytes; i++)
1025 			tx_tmp_buf[i + 1] = op->addr.val >>
1026 					(8 * (op->addr.nbytes - i - 1));
1027 	}
1028 
1029 	if (op->dummy.nbytes)
1030 		memset(tx_tmp_buf + op->addr.nbytes + 1,
1031 		       0xff,
1032 		       op->dummy.nbytes);
1033 
1034 	if (op->data.nbytes && op->data.dir == SPI_MEM_DATA_OUT)
1035 		memcpy(tx_tmp_buf + op->dummy.nbytes + op->addr.nbytes + 1,
1036 		       op->data.buf.out,
1037 		       op->data.nbytes);
1038 
1039 	mdata->tx_dma = dma_map_single(mdata->dev, tx_tmp_buf,
1040 				       tx_size, DMA_TO_DEVICE);
1041 	if (dma_mapping_error(mdata->dev, mdata->tx_dma)) {
1042 		ret = -ENOMEM;
1043 		goto err_exit;
1044 	}
1045 
1046 	if (op->data.dir == SPI_MEM_DATA_IN) {
1047 		if (!IS_ALIGNED((size_t)op->data.buf.in, 4)) {
1048 			rx_tmp_buf = kzalloc(op->data.nbytes,
1049 					     GFP_KERNEL | GFP_DMA);
1050 			if (!rx_tmp_buf) {
1051 				ret = -ENOMEM;
1052 				goto unmap_tx_dma;
1053 			}
1054 		} else {
1055 			rx_tmp_buf = op->data.buf.in;
1056 		}
1057 
1058 		mdata->rx_dma = dma_map_single(mdata->dev,
1059 					       rx_tmp_buf,
1060 					       op->data.nbytes,
1061 					       DMA_FROM_DEVICE);
1062 		if (dma_mapping_error(mdata->dev, mdata->rx_dma)) {
1063 			ret = -ENOMEM;
1064 			goto kfree_rx_tmp_buf;
1065 		}
1066 	}
1067 
1068 	reg_val = readl(mdata->base + SPI_CMD_REG);
1069 	reg_val |= SPI_CMD_TX_DMA;
1070 	if (op->data.dir == SPI_MEM_DATA_IN)
1071 		reg_val |= SPI_CMD_RX_DMA;
1072 	writel(reg_val, mdata->base + SPI_CMD_REG);
1073 
1074 	mtk_spi_mem_setup_dma_xfer(mem->spi->master, op);
1075 
1076 	mtk_spi_enable_transfer(mem->spi->master);
1077 
1078 	/* Wait for the interrupt. */
1079 	ret = mtk_spi_transfer_wait(mem, op);
1080 	if (ret)
1081 		goto unmap_rx_dma;
1082 
1083 	/* spi disable dma */
1084 	reg_val = readl(mdata->base + SPI_CMD_REG);
1085 	reg_val &= ~SPI_CMD_TX_DMA;
1086 	if (op->data.dir == SPI_MEM_DATA_IN)
1087 		reg_val &= ~SPI_CMD_RX_DMA;
1088 	writel(reg_val, mdata->base + SPI_CMD_REG);
1089 
1090 unmap_rx_dma:
1091 	if (op->data.dir == SPI_MEM_DATA_IN) {
1092 		dma_unmap_single(mdata->dev, mdata->rx_dma,
1093 				 op->data.nbytes, DMA_FROM_DEVICE);
1094 		if (!IS_ALIGNED((size_t)op->data.buf.in, 4))
1095 			memcpy(op->data.buf.in, rx_tmp_buf, op->data.nbytes);
1096 	}
1097 kfree_rx_tmp_buf:
1098 	if (op->data.dir == SPI_MEM_DATA_IN &&
1099 	    !IS_ALIGNED((size_t)op->data.buf.in, 4))
1100 		kfree(rx_tmp_buf);
1101 unmap_tx_dma:
1102 	dma_unmap_single(mdata->dev, mdata->tx_dma,
1103 			 tx_size, DMA_TO_DEVICE);
1104 err_exit:
1105 	kfree(tx_tmp_buf);
1106 	mdata->use_spimem = false;
1107 
1108 	return ret;
1109 }
1110 
1111 static const struct spi_controller_mem_ops mtk_spi_mem_ops = {
1112 	.adjust_op_size = mtk_spi_mem_adjust_op_size,
1113 	.supports_op = mtk_spi_mem_supports_op,
1114 	.exec_op = mtk_spi_mem_exec_op,
1115 };
1116 
mtk_spi_probe(struct platform_device * pdev)1117 static int mtk_spi_probe(struct platform_device *pdev)
1118 {
1119 	struct device *dev = &pdev->dev;
1120 	struct spi_master *master;
1121 	struct mtk_spi *mdata;
1122 	int i, irq, ret, addr_bits;
1123 
1124 	master = devm_spi_alloc_master(dev, sizeof(*mdata));
1125 	if (!master)
1126 		return dev_err_probe(dev, -ENOMEM, "failed to alloc spi master\n");
1127 
1128 	master->auto_runtime_pm = true;
1129 	master->dev.of_node = dev->of_node;
1130 	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
1131 
1132 	master->set_cs = mtk_spi_set_cs;
1133 	master->prepare_message = mtk_spi_prepare_message;
1134 	master->transfer_one = mtk_spi_transfer_one;
1135 	master->can_dma = mtk_spi_can_dma;
1136 	master->setup = mtk_spi_setup;
1137 	master->set_cs_timing = mtk_spi_set_hw_cs_timing;
1138 	master->use_gpio_descriptors = true;
1139 
1140 	mdata = spi_master_get_devdata(master);
1141 	mdata->dev_comp = device_get_match_data(dev);
1142 
1143 	if (mdata->dev_comp->enhance_timing)
1144 		master->mode_bits |= SPI_CS_HIGH;
1145 
1146 	if (mdata->dev_comp->must_tx)
1147 		master->flags = SPI_CONTROLLER_MUST_TX;
1148 	if (mdata->dev_comp->ipm_design)
1149 		master->mode_bits |= SPI_LOOP | SPI_RX_DUAL | SPI_TX_DUAL |
1150 				     SPI_RX_QUAD | SPI_TX_QUAD;
1151 
1152 	if (mdata->dev_comp->ipm_design) {
1153 		mdata->dev = dev;
1154 		master->mem_ops = &mtk_spi_mem_ops;
1155 		init_completion(&mdata->spimem_done);
1156 	}
1157 
1158 	if (mdata->dev_comp->need_pad_sel) {
1159 		mdata->pad_num = of_property_count_u32_elems(dev->of_node,
1160 			"mediatek,pad-select");
1161 		if (mdata->pad_num < 0)
1162 			return dev_err_probe(dev, -EINVAL,
1163 				"No 'mediatek,pad-select' property\n");
1164 
1165 		mdata->pad_sel = devm_kmalloc_array(dev, mdata->pad_num,
1166 						    sizeof(u32), GFP_KERNEL);
1167 		if (!mdata->pad_sel)
1168 			return -ENOMEM;
1169 
1170 		for (i = 0; i < mdata->pad_num; i++) {
1171 			of_property_read_u32_index(dev->of_node,
1172 						   "mediatek,pad-select",
1173 						   i, &mdata->pad_sel[i]);
1174 			if (mdata->pad_sel[i] > MT8173_SPI_MAX_PAD_SEL)
1175 				return dev_err_probe(dev, -EINVAL,
1176 						     "wrong pad-sel[%d]: %u\n",
1177 						     i, mdata->pad_sel[i]);
1178 		}
1179 	}
1180 
1181 	platform_set_drvdata(pdev, master);
1182 	mdata->base = devm_platform_ioremap_resource(pdev, 0);
1183 	if (IS_ERR(mdata->base))
1184 		return PTR_ERR(mdata->base);
1185 
1186 	irq = platform_get_irq(pdev, 0);
1187 	if (irq < 0)
1188 		return irq;
1189 
1190 	if (!dev->dma_mask)
1191 		dev->dma_mask = &dev->coherent_dma_mask;
1192 
1193 	if (mdata->dev_comp->ipm_design)
1194 		dma_set_max_seg_size(dev, SZ_16M);
1195 	else
1196 		dma_set_max_seg_size(dev, SZ_256K);
1197 
1198 	mdata->parent_clk = devm_clk_get(dev, "parent-clk");
1199 	if (IS_ERR(mdata->parent_clk))
1200 		return dev_err_probe(dev, PTR_ERR(mdata->parent_clk),
1201 				     "failed to get parent-clk\n");
1202 
1203 	mdata->sel_clk = devm_clk_get(dev, "sel-clk");
1204 	if (IS_ERR(mdata->sel_clk))
1205 		return dev_err_probe(dev, PTR_ERR(mdata->sel_clk), "failed to get sel-clk\n");
1206 
1207 	mdata->spi_clk = devm_clk_get(dev, "spi-clk");
1208 	if (IS_ERR(mdata->spi_clk))
1209 		return dev_err_probe(dev, PTR_ERR(mdata->spi_clk), "failed to get spi-clk\n");
1210 
1211 	mdata->spi_hclk = devm_clk_get_optional(dev, "hclk");
1212 	if (IS_ERR(mdata->spi_hclk))
1213 		return dev_err_probe(dev, PTR_ERR(mdata->spi_hclk), "failed to get hclk\n");
1214 
1215 	ret = clk_set_parent(mdata->sel_clk, mdata->parent_clk);
1216 	if (ret < 0)
1217 		return dev_err_probe(dev, ret, "failed to clk_set_parent\n");
1218 
1219 	ret = clk_prepare_enable(mdata->spi_hclk);
1220 	if (ret < 0)
1221 		return dev_err_probe(dev, ret, "failed to enable hclk\n");
1222 
1223 	ret = clk_prepare_enable(mdata->spi_clk);
1224 	if (ret < 0) {
1225 		clk_disable_unprepare(mdata->spi_hclk);
1226 		return dev_err_probe(dev, ret, "failed to enable spi_clk\n");
1227 	}
1228 
1229 	mdata->spi_clk_hz = clk_get_rate(mdata->spi_clk);
1230 
1231 	if (mdata->dev_comp->no_need_unprepare) {
1232 		clk_disable(mdata->spi_clk);
1233 		clk_disable(mdata->spi_hclk);
1234 	} else {
1235 		clk_disable_unprepare(mdata->spi_clk);
1236 		clk_disable_unprepare(mdata->spi_hclk);
1237 	}
1238 
1239 	if (mdata->dev_comp->need_pad_sel) {
1240 		if (mdata->pad_num != master->num_chipselect)
1241 			return dev_err_probe(dev, -EINVAL,
1242 				"pad_num does not match num_chipselect(%d != %d)\n",
1243 				mdata->pad_num, master->num_chipselect);
1244 
1245 		if (!master->cs_gpiods && master->num_chipselect > 1)
1246 			return dev_err_probe(dev, -EINVAL,
1247 				"cs_gpios not specified and num_chipselect > 1\n");
1248 	}
1249 
1250 	if (mdata->dev_comp->dma_ext)
1251 		addr_bits = DMA_ADDR_EXT_BITS;
1252 	else
1253 		addr_bits = DMA_ADDR_DEF_BITS;
1254 	ret = dma_set_mask(dev, DMA_BIT_MASK(addr_bits));
1255 	if (ret)
1256 		dev_notice(dev, "SPI dma_set_mask(%d) failed, ret:%d\n",
1257 			   addr_bits, ret);
1258 
1259 	ret = devm_request_irq(dev, irq, mtk_spi_interrupt,
1260 			       IRQF_TRIGGER_NONE, dev_name(dev), master);
1261 	if (ret)
1262 		return dev_err_probe(dev, ret, "failed to register irq\n");
1263 
1264 	pm_runtime_enable(dev);
1265 
1266 	ret = devm_spi_register_master(dev, master);
1267 	if (ret) {
1268 		pm_runtime_disable(dev);
1269 		return dev_err_probe(dev, ret, "failed to register master\n");
1270 	}
1271 
1272 	return 0;
1273 }
1274 
mtk_spi_remove(struct platform_device * pdev)1275 static void mtk_spi_remove(struct platform_device *pdev)
1276 {
1277 	struct spi_master *master = platform_get_drvdata(pdev);
1278 	struct mtk_spi *mdata = spi_master_get_devdata(master);
1279 	int ret;
1280 
1281 	if (mdata->use_spimem && !completion_done(&mdata->spimem_done))
1282 		complete(&mdata->spimem_done);
1283 
1284 	ret = pm_runtime_get_sync(&pdev->dev);
1285 	if (ret < 0) {
1286 		dev_warn(&pdev->dev, "Failed to resume hardware (%pe)\n", ERR_PTR(ret));
1287 	} else {
1288 		/*
1289 		 * If pm runtime resume failed, clks are disabled and
1290 		 * unprepared. So don't access the hardware and skip clk
1291 		 * unpreparing.
1292 		 */
1293 		mtk_spi_reset(mdata);
1294 
1295 		if (mdata->dev_comp->no_need_unprepare) {
1296 			clk_unprepare(mdata->spi_clk);
1297 			clk_unprepare(mdata->spi_hclk);
1298 		}
1299 	}
1300 
1301 	pm_runtime_put_noidle(&pdev->dev);
1302 	pm_runtime_disable(&pdev->dev);
1303 }
1304 
1305 #ifdef CONFIG_PM_SLEEP
mtk_spi_suspend(struct device * dev)1306 static int mtk_spi_suspend(struct device *dev)
1307 {
1308 	int ret;
1309 	struct spi_master *master = dev_get_drvdata(dev);
1310 	struct mtk_spi *mdata = spi_master_get_devdata(master);
1311 
1312 	ret = spi_master_suspend(master);
1313 	if (ret)
1314 		return ret;
1315 
1316 	if (!pm_runtime_suspended(dev)) {
1317 		clk_disable_unprepare(mdata->spi_clk);
1318 		clk_disable_unprepare(mdata->spi_hclk);
1319 	}
1320 
1321 	return 0;
1322 }
1323 
mtk_spi_resume(struct device * dev)1324 static int mtk_spi_resume(struct device *dev)
1325 {
1326 	int ret;
1327 	struct spi_master *master = dev_get_drvdata(dev);
1328 	struct mtk_spi *mdata = spi_master_get_devdata(master);
1329 
1330 	if (!pm_runtime_suspended(dev)) {
1331 		ret = clk_prepare_enable(mdata->spi_clk);
1332 		if (ret < 0) {
1333 			dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
1334 			return ret;
1335 		}
1336 
1337 		ret = clk_prepare_enable(mdata->spi_hclk);
1338 		if (ret < 0) {
1339 			dev_err(dev, "failed to enable spi_hclk (%d)\n", ret);
1340 			clk_disable_unprepare(mdata->spi_clk);
1341 			return ret;
1342 		}
1343 	}
1344 
1345 	ret = spi_master_resume(master);
1346 	if (ret < 0) {
1347 		clk_disable_unprepare(mdata->spi_clk);
1348 		clk_disable_unprepare(mdata->spi_hclk);
1349 	}
1350 
1351 	return ret;
1352 }
1353 #endif /* CONFIG_PM_SLEEP */
1354 
1355 #ifdef CONFIG_PM
mtk_spi_runtime_suspend(struct device * dev)1356 static int mtk_spi_runtime_suspend(struct device *dev)
1357 {
1358 	struct spi_master *master = dev_get_drvdata(dev);
1359 	struct mtk_spi *mdata = spi_master_get_devdata(master);
1360 
1361 	if (mdata->dev_comp->no_need_unprepare) {
1362 		clk_disable(mdata->spi_clk);
1363 		clk_disable(mdata->spi_hclk);
1364 	} else {
1365 		clk_disable_unprepare(mdata->spi_clk);
1366 		clk_disable_unprepare(mdata->spi_hclk);
1367 	}
1368 
1369 	return 0;
1370 }
1371 
mtk_spi_runtime_resume(struct device * dev)1372 static int mtk_spi_runtime_resume(struct device *dev)
1373 {
1374 	struct spi_master *master = dev_get_drvdata(dev);
1375 	struct mtk_spi *mdata = spi_master_get_devdata(master);
1376 	int ret;
1377 
1378 	if (mdata->dev_comp->no_need_unprepare) {
1379 		ret = clk_enable(mdata->spi_clk);
1380 		if (ret < 0) {
1381 			dev_err(dev, "failed to enable spi_clk (%d)\n", ret);
1382 			return ret;
1383 		}
1384 		ret = clk_enable(mdata->spi_hclk);
1385 		if (ret < 0) {
1386 			dev_err(dev, "failed to enable spi_hclk (%d)\n", ret);
1387 			clk_disable(mdata->spi_clk);
1388 			return ret;
1389 		}
1390 	} else {
1391 		ret = clk_prepare_enable(mdata->spi_clk);
1392 		if (ret < 0) {
1393 			dev_err(dev, "failed to prepare_enable spi_clk (%d)\n", ret);
1394 			return ret;
1395 		}
1396 
1397 		ret = clk_prepare_enable(mdata->spi_hclk);
1398 		if (ret < 0) {
1399 			dev_err(dev, "failed to prepare_enable spi_hclk (%d)\n", ret);
1400 			clk_disable_unprepare(mdata->spi_clk);
1401 			return ret;
1402 		}
1403 	}
1404 
1405 	return 0;
1406 }
1407 #endif /* CONFIG_PM */
1408 
1409 static const struct dev_pm_ops mtk_spi_pm = {
1410 	SET_SYSTEM_SLEEP_PM_OPS(mtk_spi_suspend, mtk_spi_resume)
1411 	SET_RUNTIME_PM_OPS(mtk_spi_runtime_suspend,
1412 			   mtk_spi_runtime_resume, NULL)
1413 };
1414 
1415 static struct platform_driver mtk_spi_driver = {
1416 	.driver = {
1417 		.name = "mtk-spi",
1418 		.pm	= &mtk_spi_pm,
1419 		.of_match_table = mtk_spi_of_match,
1420 	},
1421 	.probe = mtk_spi_probe,
1422 	.remove_new = mtk_spi_remove,
1423 };
1424 
1425 module_platform_driver(mtk_spi_driver);
1426 
1427 MODULE_DESCRIPTION("MTK SPI Controller driver");
1428 MODULE_AUTHOR("Leilk Liu <leilk.liu@mediatek.com>");
1429 MODULE_LICENSE("GPL v2");
1430 MODULE_ALIAS("platform:mtk-spi");
1431