1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2012 SAMSUNG Electronics
4 * Padmavathi Venna <padma.v@samsung.com>
5 */
6
7 #include <common.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <malloc.h>
11 #include <spi.h>
12 #include <fdtdec.h>
13 #include <asm/arch/clk.h>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/gpio.h>
17 #include <asm/arch/pinmux.h>
18 #include <asm/arch/spi.h>
19 #include <asm/io.h>
20
21 DECLARE_GLOBAL_DATA_PTR;
22
23 struct exynos_spi_platdata {
24 enum periph_id periph_id;
25 s32 frequency; /* Default clock frequency, -1 for none */
26 struct exynos_spi *regs;
27 uint deactivate_delay_us; /* Delay to wait after deactivate */
28 };
29
30 struct exynos_spi_priv {
31 struct exynos_spi *regs;
32 unsigned int freq; /* Default frequency */
33 unsigned int mode;
34 enum periph_id periph_id; /* Peripheral ID for this device */
35 unsigned int fifo_size;
36 int skip_preamble;
37 ulong last_transaction_us; /* Time of last transaction end */
38 };
39
40 /**
41 * Flush spi tx, rx fifos and reset the SPI controller
42 *
43 * @param regs Pointer to SPI registers
44 */
spi_flush_fifo(struct exynos_spi * regs)45 static void spi_flush_fifo(struct exynos_spi *regs)
46 {
47 clrsetbits_le32(®s->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
48 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
49 setbits_le32(®s->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
50 }
51
spi_get_fifo_levels(struct exynos_spi * regs,int * rx_lvl,int * tx_lvl)52 static void spi_get_fifo_levels(struct exynos_spi *regs,
53 int *rx_lvl, int *tx_lvl)
54 {
55 uint32_t spi_sts = readl(®s->spi_sts);
56
57 *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
58 *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
59 }
60
61 /**
62 * If there's something to transfer, do a software reset and set a
63 * transaction size.
64 *
65 * @param regs SPI peripheral registers
66 * @param count Number of bytes to transfer
67 * @param step Number of bytes to transfer in each packet (1 or 4)
68 */
spi_request_bytes(struct exynos_spi * regs,int count,int step)69 static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
70 {
71 debug("%s: regs=%p, count=%d, step=%d\n", __func__, regs, count, step);
72
73 /* For word address we need to swap bytes */
74 if (step == 4) {
75 setbits_le32(®s->mode_cfg,
76 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
77 count /= 4;
78 setbits_le32(®s->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN |
79 SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP |
80 SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP);
81 } else {
82 /* Select byte access and clear the swap configuration */
83 clrbits_le32(®s->mode_cfg,
84 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
85 writel(0, ®s->swap_cfg);
86 }
87
88 assert(count && count < (1 << 16));
89 setbits_le32(®s->ch_cfg, SPI_CH_RST);
90 clrbits_le32(®s->ch_cfg, SPI_CH_RST);
91
92 writel(count | SPI_PACKET_CNT_EN, ®s->pkt_cnt);
93 }
94
spi_rx_tx(struct exynos_spi_priv * priv,int todo,void ** dinp,void const ** doutp,unsigned long flags)95 static int spi_rx_tx(struct exynos_spi_priv *priv, int todo,
96 void **dinp, void const **doutp, unsigned long flags)
97 {
98 struct exynos_spi *regs = priv->regs;
99 uchar *rxp = *dinp;
100 const uchar *txp = *doutp;
101 int rx_lvl, tx_lvl;
102 uint out_bytes, in_bytes;
103 int toread;
104 unsigned start = get_timer(0);
105 int stopping;
106 int step;
107
108 out_bytes = in_bytes = todo;
109
110 stopping = priv->skip_preamble && (flags & SPI_XFER_END) &&
111 !(priv->mode & SPI_SLAVE);
112
113 /*
114 * Try to transfer words if we can. This helps read performance at
115 * SPI clock speeds above about 20MHz.
116 */
117 step = 1;
118 if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
119 !priv->skip_preamble)
120 step = 4;
121
122 /*
123 * If there's something to send, do a software reset and set a
124 * transaction size.
125 */
126 spi_request_bytes(regs, todo, step);
127
128 /*
129 * Bytes are transmitted/received in pairs. Wait to receive all the
130 * data because then transmission will be done as well.
131 */
132 toread = in_bytes;
133
134 while (in_bytes) {
135 int temp;
136
137 /* Keep the fifos full/empty. */
138 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
139
140 /*
141 * Don't completely fill the txfifo, since we don't want our
142 * rxfifo to overflow, and it may already contain data.
143 */
144 while (tx_lvl < priv->fifo_size/2 && out_bytes) {
145 if (!txp)
146 temp = -1;
147 else if (step == 4)
148 temp = *(uint32_t *)txp;
149 else
150 temp = *txp;
151 writel(temp, ®s->tx_data);
152 out_bytes -= step;
153 if (txp)
154 txp += step;
155 tx_lvl += step;
156 }
157 if (rx_lvl >= step) {
158 while (rx_lvl >= step) {
159 temp = readl(®s->rx_data);
160 if (priv->skip_preamble) {
161 if (temp == SPI_PREAMBLE_END_BYTE) {
162 priv->skip_preamble = 0;
163 stopping = 0;
164 }
165 } else {
166 if (rxp || stopping) {
167 if (step == 4)
168 *(uint32_t *)rxp = temp;
169 else
170 *rxp = temp;
171 rxp += step;
172 }
173 in_bytes -= step;
174 }
175 toread -= step;
176 rx_lvl -= step;
177 }
178 } else if (!toread) {
179 /*
180 * We have run out of input data, but haven't read
181 * enough bytes after the preamble yet. Read some more,
182 * and make sure that we transmit dummy bytes too, to
183 * keep things going.
184 */
185 assert(!out_bytes);
186 out_bytes = in_bytes;
187 toread = in_bytes;
188 txp = NULL;
189 spi_request_bytes(regs, toread, step);
190 }
191 if (priv->skip_preamble && get_timer(start) > 100) {
192 debug("SPI timeout: in_bytes=%d, out_bytes=%d, ",
193 in_bytes, out_bytes);
194 return -ETIMEDOUT;
195 }
196 }
197
198 *dinp = rxp;
199 *doutp = txp;
200
201 return 0;
202 }
203
204 /**
205 * Activate the CS by driving it LOW
206 *
207 * @param slave Pointer to spi_slave to which controller has to
208 * communicate with
209 */
spi_cs_activate(struct udevice * dev)210 static void spi_cs_activate(struct udevice *dev)
211 {
212 struct udevice *bus = dev->parent;
213 struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
214 struct exynos_spi_priv *priv = dev_get_priv(bus);
215
216 /* If it's too soon to do another transaction, wait */
217 if (pdata->deactivate_delay_us &&
218 priv->last_transaction_us) {
219 ulong delay_us; /* The delay completed so far */
220 delay_us = timer_get_us() - priv->last_transaction_us;
221 if (delay_us < pdata->deactivate_delay_us)
222 udelay(pdata->deactivate_delay_us - delay_us);
223 }
224
225 clrbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
226 debug("Activate CS, bus '%s'\n", bus->name);
227 priv->skip_preamble = priv->mode & SPI_PREAMBLE;
228 }
229
230 /**
231 * Deactivate the CS by driving it HIGH
232 *
233 * @param slave Pointer to spi_slave to which controller has to
234 * communicate with
235 */
spi_cs_deactivate(struct udevice * dev)236 static void spi_cs_deactivate(struct udevice *dev)
237 {
238 struct udevice *bus = dev->parent;
239 struct exynos_spi_platdata *pdata = dev_get_platdata(bus);
240 struct exynos_spi_priv *priv = dev_get_priv(bus);
241
242 setbits_le32(&priv->regs->cs_reg, SPI_SLAVE_SIG_INACT);
243
244 /* Remember time of this transaction so we can honour the bus delay */
245 if (pdata->deactivate_delay_us)
246 priv->last_transaction_us = timer_get_us();
247
248 debug("Deactivate CS, bus '%s'\n", bus->name);
249 }
250
exynos_spi_ofdata_to_platdata(struct udevice * bus)251 static int exynos_spi_ofdata_to_platdata(struct udevice *bus)
252 {
253 struct exynos_spi_platdata *plat = bus->platdata;
254 const void *blob = gd->fdt_blob;
255 int node = dev_of_offset(bus);
256
257 plat->regs = (struct exynos_spi *)devfdt_get_addr(bus);
258 plat->periph_id = pinmux_decode_periph_id(blob, node);
259
260 if (plat->periph_id == PERIPH_ID_NONE) {
261 debug("%s: Invalid peripheral ID %d\n", __func__,
262 plat->periph_id);
263 return -FDT_ERR_NOTFOUND;
264 }
265
266 /* Use 500KHz as a suitable default */
267 plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
268 500000);
269 plat->deactivate_delay_us = fdtdec_get_int(blob, node,
270 "spi-deactivate-delay", 0);
271 debug("%s: regs=%p, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
272 __func__, plat->regs, plat->periph_id, plat->frequency,
273 plat->deactivate_delay_us);
274
275 return 0;
276 }
277
exynos_spi_probe(struct udevice * bus)278 static int exynos_spi_probe(struct udevice *bus)
279 {
280 struct exynos_spi_platdata *plat = dev_get_platdata(bus);
281 struct exynos_spi_priv *priv = dev_get_priv(bus);
282
283 priv->regs = plat->regs;
284 if (plat->periph_id == PERIPH_ID_SPI1 ||
285 plat->periph_id == PERIPH_ID_SPI2)
286 priv->fifo_size = 64;
287 else
288 priv->fifo_size = 256;
289
290 priv->skip_preamble = 0;
291 priv->last_transaction_us = timer_get_us();
292 priv->freq = plat->frequency;
293 priv->periph_id = plat->periph_id;
294
295 return 0;
296 }
297
exynos_spi_claim_bus(struct udevice * dev)298 static int exynos_spi_claim_bus(struct udevice *dev)
299 {
300 struct udevice *bus = dev->parent;
301 struct exynos_spi_priv *priv = dev_get_priv(bus);
302
303 exynos_pinmux_config(priv->periph_id, PINMUX_FLAG_NONE);
304 spi_flush_fifo(priv->regs);
305
306 writel(SPI_FB_DELAY_180, &priv->regs->fb_clk);
307
308 return 0;
309 }
310
exynos_spi_release_bus(struct udevice * dev)311 static int exynos_spi_release_bus(struct udevice *dev)
312 {
313 struct udevice *bus = dev->parent;
314 struct exynos_spi_priv *priv = dev_get_priv(bus);
315
316 spi_flush_fifo(priv->regs);
317
318 return 0;
319 }
320
exynos_spi_xfer(struct udevice * dev,unsigned int bitlen,const void * dout,void * din,unsigned long flags)321 static int exynos_spi_xfer(struct udevice *dev, unsigned int bitlen,
322 const void *dout, void *din, unsigned long flags)
323 {
324 struct udevice *bus = dev->parent;
325 struct exynos_spi_priv *priv = dev_get_priv(bus);
326 int upto, todo;
327 int bytelen;
328 int ret = 0;
329
330 /* spi core configured to do 8 bit transfers */
331 if (bitlen % 8) {
332 debug("Non byte aligned SPI transfer.\n");
333 return -1;
334 }
335
336 /* Start the transaction, if necessary. */
337 if ((flags & SPI_XFER_BEGIN))
338 spi_cs_activate(dev);
339
340 /*
341 * Exynos SPI limits each transfer to 65535 transfers. To keep
342 * things simple, allow a maximum of 65532 bytes. We could allow
343 * more in word mode, but the performance difference is small.
344 */
345 bytelen = bitlen / 8;
346 for (upto = 0; !ret && upto < bytelen; upto += todo) {
347 todo = min(bytelen - upto, (1 << 16) - 4);
348 ret = spi_rx_tx(priv, todo, &din, &dout, flags);
349 if (ret)
350 break;
351 }
352
353 /* Stop the transaction, if necessary. */
354 if ((flags & SPI_XFER_END) && !(priv->mode & SPI_SLAVE)) {
355 spi_cs_deactivate(dev);
356 if (priv->skip_preamble) {
357 assert(!priv->skip_preamble);
358 debug("Failed to complete premable transaction\n");
359 ret = -1;
360 }
361 }
362
363 return ret;
364 }
365
exynos_spi_set_speed(struct udevice * bus,uint speed)366 static int exynos_spi_set_speed(struct udevice *bus, uint speed)
367 {
368 struct exynos_spi_platdata *plat = bus->platdata;
369 struct exynos_spi_priv *priv = dev_get_priv(bus);
370 int ret;
371
372 if (speed > plat->frequency)
373 speed = plat->frequency;
374 ret = set_spi_clk(priv->periph_id, speed);
375 if (ret)
376 return ret;
377 priv->freq = speed;
378 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
379
380 return 0;
381 }
382
exynos_spi_set_mode(struct udevice * bus,uint mode)383 static int exynos_spi_set_mode(struct udevice *bus, uint mode)
384 {
385 struct exynos_spi_priv *priv = dev_get_priv(bus);
386 uint32_t reg;
387
388 reg = readl(&priv->regs->ch_cfg);
389 reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
390
391 if (mode & SPI_CPHA)
392 reg |= SPI_CH_CPHA_B;
393
394 if (mode & SPI_CPOL)
395 reg |= SPI_CH_CPOL_L;
396
397 writel(reg, &priv->regs->ch_cfg);
398 priv->mode = mode;
399 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
400
401 return 0;
402 }
403
404 static const struct dm_spi_ops exynos_spi_ops = {
405 .claim_bus = exynos_spi_claim_bus,
406 .release_bus = exynos_spi_release_bus,
407 .xfer = exynos_spi_xfer,
408 .set_speed = exynos_spi_set_speed,
409 .set_mode = exynos_spi_set_mode,
410 /*
411 * cs_info is not needed, since we require all chip selects to be
412 * in the device tree explicitly
413 */
414 };
415
416 static const struct udevice_id exynos_spi_ids[] = {
417 { .compatible = "samsung,exynos-spi" },
418 { }
419 };
420
421 U_BOOT_DRIVER(exynos_spi) = {
422 .name = "exynos_spi",
423 .id = UCLASS_SPI,
424 .of_match = exynos_spi_ids,
425 .ops = &exynos_spi_ops,
426 .ofdata_to_platdata = exynos_spi_ofdata_to_platdata,
427 .platdata_auto_alloc_size = sizeof(struct exynos_spi_platdata),
428 .priv_auto_alloc_size = sizeof(struct exynos_spi_priv),
429 .probe = exynos_spi_probe,
430 };
431