1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Atmel DataFlash probing
4 *
5 * Copyright (C) 2004-2009, 2015 Freescale Semiconductor, Inc.
6 * Haikun Wang (haikun.wang@freescale.com)
7 */
8
9 #include <common.h>
10 #include <dm.h>
11 #include <errno.h>
12 #include <fdtdec.h>
13 #include <spi.h>
14 #include <spi_flash.h>
15 #include <div64.h>
16 #include <linux/err.h>
17 #include <linux/math64.h>
18
19 #include "sf_internal.h"
20
21 #define CMD_READ_ID 0x9f
22 /* reads can bypass the buffers */
23 #define OP_READ_CONTINUOUS 0xE8
24 #define OP_READ_PAGE 0xD2
25
26 /* group B requests can run even while status reports "busy" */
27 #define OP_READ_STATUS 0xD7 /* group B */
28
29 /* move data between host and buffer */
30 #define OP_READ_BUFFER1 0xD4 /* group B */
31 #define OP_READ_BUFFER2 0xD6 /* group B */
32 #define OP_WRITE_BUFFER1 0x84 /* group B */
33 #define OP_WRITE_BUFFER2 0x87 /* group B */
34
35 /* erasing flash */
36 #define OP_ERASE_PAGE 0x81
37 #define OP_ERASE_BLOCK 0x50
38
39 /* move data between buffer and flash */
40 #define OP_TRANSFER_BUF1 0x53
41 #define OP_TRANSFER_BUF2 0x55
42 #define OP_MREAD_BUFFER1 0xD4
43 #define OP_MREAD_BUFFER2 0xD6
44 #define OP_MWERASE_BUFFER1 0x83
45 #define OP_MWERASE_BUFFER2 0x86
46 #define OP_MWRITE_BUFFER1 0x88 /* sector must be pre-erased */
47 #define OP_MWRITE_BUFFER2 0x89 /* sector must be pre-erased */
48
49 /* write to buffer, then write-erase to flash */
50 #define OP_PROGRAM_VIA_BUF1 0x82
51 #define OP_PROGRAM_VIA_BUF2 0x85
52
53 /* compare buffer to flash */
54 #define OP_COMPARE_BUF1 0x60
55 #define OP_COMPARE_BUF2 0x61
56
57 /* read flash to buffer, then write-erase to flash */
58 #define OP_REWRITE_VIA_BUF1 0x58
59 #define OP_REWRITE_VIA_BUF2 0x59
60
61 /*
62 * newer chips report JEDEC manufacturer and device IDs; chip
63 * serial number and OTP bits; and per-sector writeprotect.
64 */
65 #define OP_READ_ID 0x9F
66 #define OP_READ_SECURITY 0x77
67 #define OP_WRITE_SECURITY_REVC 0x9A
68 #define OP_WRITE_SECURITY 0x9B /* revision D */
69
70 struct dataflash {
71 uint8_t command[16];
72 unsigned short page_offset; /* offset in flash address */
73 };
74
75 /* Return the status of the DataFlash device */
dataflash_status(struct spi_slave * spi)76 static inline int dataflash_status(struct spi_slave *spi)
77 {
78 int ret;
79 u8 status;
80 /*
81 * NOTE: at45db321c over 25 MHz wants to write
82 * a dummy byte after the opcode...
83 */
84 ret = spi_flash_cmd(spi, OP_READ_STATUS, &status, 1);
85 return ret ? -EIO : status;
86 }
87
88 /*
89 * Poll the DataFlash device until it is READY.
90 * This usually takes 5-20 msec or so; more for sector erase.
91 * ready: return > 0
92 */
dataflash_waitready(struct spi_slave * spi)93 static int dataflash_waitready(struct spi_slave *spi)
94 {
95 int status;
96 int timeout = 2 * CONFIG_SYS_HZ;
97 int timebase;
98
99 timebase = get_timer(0);
100 do {
101 status = dataflash_status(spi);
102 if (status < 0)
103 status = 0;
104
105 if (status & (1 << 7)) /* RDY/nBSY */
106 return status;
107
108 mdelay(3);
109 } while (get_timer(timebase) < timeout);
110
111 return -ETIME;
112 }
113
114 /* Erase pages of flash */
spi_dataflash_erase(struct udevice * dev,u32 offset,size_t len)115 static int spi_dataflash_erase(struct udevice *dev, u32 offset, size_t len)
116 {
117 struct dataflash *dataflash;
118 struct spi_flash *spi_flash;
119 struct spi_slave *spi;
120 unsigned blocksize;
121 uint8_t *command;
122 uint32_t rem;
123 int status;
124
125 dataflash = dev_get_priv(dev);
126 spi_flash = dev_get_uclass_priv(dev);
127 spi = spi_flash->spi;
128
129 blocksize = spi_flash->page_size << 3;
130
131 memset(dataflash->command, 0 , sizeof(dataflash->command));
132 command = dataflash->command;
133
134 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
135
136 div_u64_rem(len, spi_flash->page_size, &rem);
137 if (rem) {
138 printf("%s: len(0x%x) isn't the multiple of page size(0x%x)\n",
139 dev->name, len, spi_flash->page_size);
140 return -EINVAL;
141 }
142 div_u64_rem(offset, spi_flash->page_size, &rem);
143 if (rem) {
144 printf("%s: offset(0x%x) isn't the multiple of page size(0x%x)\n",
145 dev->name, offset, spi_flash->page_size);
146 return -EINVAL;
147 }
148
149 status = spi_claim_bus(spi);
150 if (status) {
151 debug("dataflash: unable to claim SPI bus\n");
152 return status;
153 }
154
155 while (len > 0) {
156 unsigned int pageaddr;
157 int do_block;
158 /*
159 * Calculate flash page address; use block erase (for speed) if
160 * we're at a block boundary and need to erase the whole block.
161 */
162 pageaddr = div_u64(offset, spi_flash->page_size);
163 do_block = (pageaddr & 0x7) == 0 && len >= blocksize;
164 pageaddr = pageaddr << dataflash->page_offset;
165
166 command[0] = do_block ? OP_ERASE_BLOCK : OP_ERASE_PAGE;
167 command[1] = (uint8_t)(pageaddr >> 16);
168 command[2] = (uint8_t)(pageaddr >> 8);
169 command[3] = 0;
170
171 debug("%s ERASE %s: (%x) %x %x %x [%d]\n",
172 dev->name, do_block ? "block" : "page",
173 command[0], command[1], command[2], command[3],
174 pageaddr);
175
176 status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
177 if (status < 0) {
178 debug("%s: erase send command error!\n", dev->name);
179 return -EIO;
180 }
181
182 status = dataflash_waitready(spi);
183 if (status < 0) {
184 debug("%s: erase waitready error!\n", dev->name);
185 return status;
186 }
187
188 if (do_block) {
189 offset += blocksize;
190 len -= blocksize;
191 } else {
192 offset += spi_flash->page_size;
193 len -= spi_flash->page_size;
194 }
195 }
196
197 spi_release_bus(spi);
198
199 return 0;
200 }
201
202 /*
203 * Read from the DataFlash device.
204 * offset : Start offset in flash device
205 * len : Amount to read
206 * buf : Buffer containing the data
207 */
spi_dataflash_read(struct udevice * dev,u32 offset,size_t len,void * buf)208 static int spi_dataflash_read(struct udevice *dev, u32 offset, size_t len,
209 void *buf)
210 {
211 struct dataflash *dataflash;
212 struct spi_flash *spi_flash;
213 struct spi_slave *spi;
214 unsigned int addr;
215 uint8_t *command;
216 int status;
217
218 dataflash = dev_get_priv(dev);
219 spi_flash = dev_get_uclass_priv(dev);
220 spi = spi_flash->spi;
221
222 memset(dataflash->command, 0 , sizeof(dataflash->command));
223 command = dataflash->command;
224
225 debug("%s: erase addr=0x%x len 0x%x\n", dev->name, offset, len);
226 debug("READ: (%x) %x %x %x\n",
227 command[0], command[1], command[2], command[3]);
228
229 /* Calculate flash page/byte address */
230 addr = (((unsigned)offset / spi_flash->page_size)
231 << dataflash->page_offset)
232 + ((unsigned)offset % spi_flash->page_size);
233
234 status = spi_claim_bus(spi);
235 if (status) {
236 debug("dataflash: unable to claim SPI bus\n");
237 return status;
238 }
239
240 /*
241 * Continuous read, max clock = f(car) which may be less than
242 * the peak rate available. Some chips support commands with
243 * fewer "don't care" bytes. Both buffers stay unchanged.
244 */
245 command[0] = OP_READ_CONTINUOUS;
246 command[1] = (uint8_t)(addr >> 16);
247 command[2] = (uint8_t)(addr >> 8);
248 command[3] = (uint8_t)(addr >> 0);
249
250 /* plus 4 "don't care" bytes, command len: 4 + 4 "don't care" bytes */
251 status = spi_flash_cmd_read(spi, command, 8, buf, len);
252
253 spi_release_bus(spi);
254
255 return status;
256 }
257
258 /*
259 * Write to the DataFlash device.
260 * offset : Start offset in flash device
261 * len : Amount to write
262 * buf : Buffer containing the data
263 */
spi_dataflash_write(struct udevice * dev,u32 offset,size_t len,const void * buf)264 int spi_dataflash_write(struct udevice *dev, u32 offset, size_t len,
265 const void *buf)
266 {
267 struct dataflash *dataflash;
268 struct spi_flash *spi_flash;
269 struct spi_slave *spi;
270 uint8_t *command;
271 unsigned int pageaddr, addr, to, writelen;
272 size_t remaining = len;
273 u_char *writebuf = (u_char *)buf;
274 int status = -EINVAL;
275
276 dataflash = dev_get_priv(dev);
277 spi_flash = dev_get_uclass_priv(dev);
278 spi = spi_flash->spi;
279
280 memset(dataflash->command, 0 , sizeof(dataflash->command));
281 command = dataflash->command;
282
283 debug("%s: write 0x%x..0x%x\n", dev->name, offset, (offset + len));
284
285 pageaddr = ((unsigned)offset / spi_flash->page_size);
286 to = ((unsigned)offset % spi_flash->page_size);
287 if (to + len > spi_flash->page_size)
288 writelen = spi_flash->page_size - to;
289 else
290 writelen = len;
291
292 status = spi_claim_bus(spi);
293 if (status) {
294 debug("dataflash: unable to claim SPI bus\n");
295 return status;
296 }
297
298 while (remaining > 0) {
299 debug("write @ %d:%d len=%d\n", pageaddr, to, writelen);
300
301 /*
302 * REVISIT:
303 * (a) each page in a sector must be rewritten at least
304 * once every 10K sibling erase/program operations.
305 * (b) for pages that are already erased, we could
306 * use WRITE+MWRITE not PROGRAM for ~30% speedup.
307 * (c) WRITE to buffer could be done while waiting for
308 * a previous MWRITE/MWERASE to complete ...
309 * (d) error handling here seems to be mostly missing.
310 *
311 * Two persistent bits per page, plus a per-sector counter,
312 * could support (a) and (b) ... we might consider using
313 * the second half of sector zero, which is just one block,
314 * to track that state. (On AT91, that sector should also
315 * support boot-from-DataFlash.)
316 */
317
318 addr = pageaddr << dataflash->page_offset;
319
320 /* (1) Maybe transfer partial page to Buffer1 */
321 if (writelen != spi_flash->page_size) {
322 command[0] = OP_TRANSFER_BUF1;
323 command[1] = (addr & 0x00FF0000) >> 16;
324 command[2] = (addr & 0x0000FF00) >> 8;
325 command[3] = 0;
326
327 debug("TRANSFER: (%x) %x %x %x\n",
328 command[0], command[1], command[2], command[3]);
329
330 status = spi_flash_cmd_write(spi, command, 4, NULL, 0);
331 if (status < 0) {
332 debug("%s: write(<pagesize) command error!\n",
333 dev->name);
334 return -EIO;
335 }
336
337 status = dataflash_waitready(spi);
338 if (status < 0) {
339 debug("%s: write(<pagesize) waitready error!\n",
340 dev->name);
341 return status;
342 }
343 }
344
345 /* (2) Program full page via Buffer1 */
346 addr += to;
347 command[0] = OP_PROGRAM_VIA_BUF1;
348 command[1] = (addr & 0x00FF0000) >> 16;
349 command[2] = (addr & 0x0000FF00) >> 8;
350 command[3] = (addr & 0x000000FF);
351
352 debug("PROGRAM: (%x) %x %x %x\n",
353 command[0], command[1], command[2], command[3]);
354
355 status = spi_flash_cmd_write(spi, command,
356 4, writebuf, writelen);
357 if (status < 0) {
358 debug("%s: write send command error!\n", dev->name);
359 return -EIO;
360 }
361
362 status = dataflash_waitready(spi);
363 if (status < 0) {
364 debug("%s: write waitready error!\n", dev->name);
365 return status;
366 }
367
368 #ifdef CONFIG_SPI_DATAFLASH_WRITE_VERIFY
369 /* (3) Compare to Buffer1 */
370 addr = pageaddr << dataflash->page_offset;
371 command[0] = OP_COMPARE_BUF1;
372 command[1] = (addr & 0x00FF0000) >> 16;
373 command[2] = (addr & 0x0000FF00) >> 8;
374 command[3] = 0;
375
376 debug("COMPARE: (%x) %x %x %x\n",
377 command[0], command[1], command[2], command[3]);
378
379 status = spi_flash_cmd_write(spi, command,
380 4, writebuf, writelen);
381 if (status < 0) {
382 debug("%s: write(compare) send command error!\n",
383 dev->name);
384 return -EIO;
385 }
386
387 status = dataflash_waitready(spi);
388
389 /* Check result of the compare operation */
390 if (status & (1 << 6)) {
391 printf("dataflash: write compare page %u, err %d\n",
392 pageaddr, status);
393 remaining = 0;
394 status = -EIO;
395 break;
396 } else {
397 status = 0;
398 }
399
400 #endif /* CONFIG_SPI_DATAFLASH_WRITE_VERIFY */
401 remaining = remaining - writelen;
402 pageaddr++;
403 to = 0;
404 writebuf += writelen;
405
406 if (remaining > spi_flash->page_size)
407 writelen = spi_flash->page_size;
408 else
409 writelen = remaining;
410 }
411
412 spi_release_bus(spi);
413
414 return 0;
415 }
416
add_dataflash(struct udevice * dev,char * name,int nr_pages,int pagesize,int pageoffset,char revision)417 static int add_dataflash(struct udevice *dev, char *name, int nr_pages,
418 int pagesize, int pageoffset, char revision)
419 {
420 struct spi_flash *spi_flash;
421 struct dataflash *dataflash;
422
423 dataflash = dev_get_priv(dev);
424 spi_flash = dev_get_uclass_priv(dev);
425
426 dataflash->page_offset = pageoffset;
427
428 spi_flash->name = name;
429 spi_flash->page_size = pagesize;
430 spi_flash->size = nr_pages * pagesize;
431 spi_flash->erase_size = pagesize;
432
433 #ifndef CONFIG_SPL_BUILD
434 printf("SPI DataFlash: Detected %s with page size ", spi_flash->name);
435 print_size(spi_flash->page_size, ", erase size ");
436 print_size(spi_flash->erase_size, ", total ");
437 print_size(spi_flash->size, "");
438 printf(", revision %c", revision);
439 puts("\n");
440 #endif
441
442 return 0;
443 }
444
445 struct data_flash_info {
446 char *name;
447
448 /*
449 * JEDEC id has a high byte of zero plus three data bytes:
450 * the manufacturer id, then a two byte device id.
451 */
452 uint32_t jedec_id;
453
454 /* The size listed here is what works with OP_ERASE_PAGE. */
455 unsigned nr_pages;
456 uint16_t pagesize;
457 uint16_t pageoffset;
458
459 uint16_t flags;
460 #define SUP_POW2PS 0x0002 /* supports 2^N byte pages */
461 #define IS_POW2PS 0x0001 /* uses 2^N byte pages */
462 };
463
464 static struct data_flash_info dataflash_data[] = {
465 /*
466 * NOTE: chips with SUP_POW2PS (rev D and up) need two entries,
467 * one with IS_POW2PS and the other without. The entry with the
468 * non-2^N byte page size can't name exact chip revisions without
469 * losing backwards compatibility for cmdlinepart.
470 *
471 * Those two entries have different name spelling format in order to
472 * show their difference obviously.
473 * The upper case refer to the chip isn't in normal 2^N bytes page-size
474 * mode.
475 * The lower case refer to the chip is in normal 2^N bytes page-size
476 * mode.
477 *
478 * These newer chips also support 128-byte security registers (with
479 * 64 bytes one-time-programmable) and software write-protection.
480 */
481 { "AT45DB011B", 0x1f2200, 512, 264, 9, SUP_POW2PS},
482 { "at45db011d", 0x1f2200, 512, 256, 8, SUP_POW2PS | IS_POW2PS},
483
484 { "AT45DB021B", 0x1f2300, 1024, 264, 9, SUP_POW2PS},
485 { "at45db021d", 0x1f2300, 1024, 256, 8, SUP_POW2PS | IS_POW2PS},
486
487 { "AT45DB041x", 0x1f2400, 2048, 264, 9, SUP_POW2PS},
488 { "at45db041d", 0x1f2400, 2048, 256, 8, SUP_POW2PS | IS_POW2PS},
489
490 { "AT45DB081B", 0x1f2500, 4096, 264, 9, SUP_POW2PS},
491 { "at45db081d", 0x1f2500, 4096, 256, 8, SUP_POW2PS | IS_POW2PS},
492
493 { "AT45DB161x", 0x1f2600, 4096, 528, 10, SUP_POW2PS},
494 { "at45db161d", 0x1f2600, 4096, 512, 9, SUP_POW2PS | IS_POW2PS},
495
496 { "AT45DB321x", 0x1f2700, 8192, 528, 10, 0}, /* rev C */
497
498 { "AT45DB321x", 0x1f2701, 8192, 528, 10, SUP_POW2PS},
499 { "at45db321d", 0x1f2701, 8192, 512, 9, SUP_POW2PS | IS_POW2PS},
500
501 { "AT45DB642x", 0x1f2800, 8192, 1056, 11, SUP_POW2PS},
502 { "at45db642d", 0x1f2800, 8192, 1024, 10, SUP_POW2PS | IS_POW2PS},
503 };
504
jedec_probe(struct spi_slave * spi)505 static struct data_flash_info *jedec_probe(struct spi_slave *spi)
506 {
507 int tmp;
508 uint8_t id[5];
509 uint32_t jedec;
510 struct data_flash_info *info;
511 int status;
512
513 /*
514 * JEDEC also defines an optional "extended device information"
515 * string for after vendor-specific data, after the three bytes
516 * we use here. Supporting some chips might require using it.
517 *
518 * If the vendor ID isn't Atmel's (0x1f), assume this call failed.
519 * That's not an error; only rev C and newer chips handle it, and
520 * only Atmel sells these chips.
521 */
522 tmp = spi_flash_cmd(spi, CMD_READ_ID, id, sizeof(id));
523 if (tmp < 0) {
524 printf("dataflash: error %d reading JEDEC ID\n", tmp);
525 return ERR_PTR(tmp);
526 }
527 if (id[0] != 0x1f)
528 return NULL;
529
530 jedec = id[0];
531 jedec = jedec << 8;
532 jedec |= id[1];
533 jedec = jedec << 8;
534 jedec |= id[2];
535
536 for (tmp = 0, info = dataflash_data;
537 tmp < ARRAY_SIZE(dataflash_data);
538 tmp++, info++) {
539 if (info->jedec_id == jedec) {
540 if (info->flags & SUP_POW2PS) {
541 status = dataflash_status(spi);
542 if (status < 0) {
543 debug("dataflash: status error %d\n",
544 status);
545 return NULL;
546 }
547 if (status & 0x1) {
548 if (info->flags & IS_POW2PS)
549 return info;
550 } else {
551 if (!(info->flags & IS_POW2PS))
552 return info;
553 }
554 } else {
555 return info;
556 }
557 }
558 }
559
560 /*
561 * Treat other chips as errors ... we won't know the right page
562 * size (it might be binary) even when we can tell which density
563 * class is involved (legacy chip id scheme).
564 */
565 printf("dataflash: JEDEC id %06x not handled\n", jedec);
566 return ERR_PTR(-ENODEV);
567 }
568
569 /*
570 * Detect and initialize DataFlash device, using JEDEC IDs on newer chips
571 * or else the ID code embedded in the status bits:
572 *
573 * Device Density ID code #Pages PageSize Offset
574 * AT45DB011B 1Mbit (128K) xx0011xx (0x0c) 512 264 9
575 * AT45DB021B 2Mbit (256K) xx0101xx (0x14) 1024 264 9
576 * AT45DB041B 4Mbit (512K) xx0111xx (0x1c) 2048 264 9
577 * AT45DB081B 8Mbit (1M) xx1001xx (0x24) 4096 264 9
578 * AT45DB0161B 16Mbit (2M) xx1011xx (0x2c) 4096 528 10
579 * AT45DB0321B 32Mbit (4M) xx1101xx (0x34) 8192 528 10
580 * AT45DB0642 64Mbit (8M) xx111xxx (0x3c) 8192 1056 11
581 * AT45DB1282 128Mbit (16M) xx0100xx (0x10) 16384 1056 11
582 */
spi_dataflash_probe(struct udevice * dev)583 static int spi_dataflash_probe(struct udevice *dev)
584 {
585 struct spi_slave *spi = dev_get_parent_priv(dev);
586 struct spi_flash *spi_flash;
587 struct data_flash_info *info;
588 int status;
589
590 spi_flash = dev_get_uclass_priv(dev);
591 spi_flash->spi = spi;
592 spi_flash->dev = dev;
593
594 status = spi_claim_bus(spi);
595 if (status)
596 return status;
597
598 /*
599 * Try to detect dataflash by JEDEC ID.
600 * If it succeeds we know we have either a C or D part.
601 * D will support power of 2 pagesize option.
602 * Both support the security register, though with different
603 * write procedures.
604 */
605 info = jedec_probe(spi);
606 if (IS_ERR(info))
607 goto err_jedec_probe;
608 if (info != NULL) {
609 status = add_dataflash(dev, info->name, info->nr_pages,
610 info->pagesize, info->pageoffset,
611 (info->flags & SUP_POW2PS) ? 'd' : 'c');
612 if (status < 0)
613 goto err_status;
614 }
615
616 /*
617 * Older chips support only legacy commands, identifing
618 * capacity using bits in the status byte.
619 */
620 status = dataflash_status(spi);
621 if (status <= 0 || status == 0xff) {
622 printf("dataflash: read status error %d\n", status);
623 if (status == 0 || status == 0xff)
624 status = -ENODEV;
625 goto err_jedec_probe;
626 }
627
628 /*
629 * if there's a device there, assume it's dataflash.
630 * board setup should have set spi->max_speed_max to
631 * match f(car) for continuous reads, mode 0 or 3.
632 */
633 switch (status & 0x3c) {
634 case 0x0c: /* 0 0 1 1 x x */
635 status = add_dataflash(dev, "AT45DB011B", 512, 264, 9, 0);
636 break;
637 case 0x14: /* 0 1 0 1 x x */
638 status = add_dataflash(dev, "AT45DB021B", 1024, 264, 9, 0);
639 break;
640 case 0x1c: /* 0 1 1 1 x x */
641 status = add_dataflash(dev, "AT45DB041x", 2048, 264, 9, 0);
642 break;
643 case 0x24: /* 1 0 0 1 x x */
644 status = add_dataflash(dev, "AT45DB081B", 4096, 264, 9, 0);
645 break;
646 case 0x2c: /* 1 0 1 1 x x */
647 status = add_dataflash(dev, "AT45DB161x", 4096, 528, 10, 0);
648 break;
649 case 0x34: /* 1 1 0 1 x x */
650 status = add_dataflash(dev, "AT45DB321x", 8192, 528, 10, 0);
651 break;
652 case 0x38: /* 1 1 1 x x x */
653 case 0x3c:
654 status = add_dataflash(dev, "AT45DB642x", 8192, 1056, 11, 0);
655 break;
656 /* obsolete AT45DB1282 not (yet?) supported */
657 default:
658 printf("dataflash: unsupported device (%x)\n", status & 0x3c);
659 status = -ENODEV;
660 goto err_status;
661 }
662
663 return status;
664
665 err_status:
666 spi_free_slave(spi);
667 err_jedec_probe:
668 spi_release_bus(spi);
669 return status;
670 }
671
672 static const struct dm_spi_flash_ops spi_dataflash_ops = {
673 .read = spi_dataflash_read,
674 .write = spi_dataflash_write,
675 .erase = spi_dataflash_erase,
676 };
677
678 static const struct udevice_id spi_dataflash_ids[] = {
679 { .compatible = "atmel,at45", },
680 { .compatible = "atmel,dataflash", },
681 { }
682 };
683
684 U_BOOT_DRIVER(spi_dataflash) = {
685 .name = "spi_dataflash",
686 .id = UCLASS_SPI_FLASH,
687 .of_match = spi_dataflash_ids,
688 .probe = spi_dataflash_probe,
689 .priv_auto_alloc_size = sizeof(struct dataflash),
690 .ops = &spi_dataflash_ops,
691 };
692