1 /*
2 * Sparc CPU init helpers
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/error.h"
22 #include "cpu.h"
23 #include "qemu/module.h"
24 #include "qemu/qemu-print.h"
25 #include "exec/exec-all.h"
26 #include "hw/qdev-properties.h"
27 #include "qapi/visitor.h"
28 #include "tcg/tcg.h"
29
30 //#define DEBUG_FEATURES
31
sparc_cpu_reset_hold(Object * obj,ResetType type)32 static void sparc_cpu_reset_hold(Object *obj, ResetType type)
33 {
34 CPUState *cs = CPU(obj);
35 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
36 CPUSPARCState *env = cpu_env(cs);
37
38 if (scc->parent_phases.hold) {
39 scc->parent_phases.hold(obj, type);
40 }
41
42 memset(env, 0, offsetof(CPUSPARCState, end_reset_fields));
43 env->cwp = 0;
44 #ifndef TARGET_SPARC64
45 env->wim = 1;
46 #endif
47 env->regwptr = env->regbase + (env->cwp * 16);
48 #if defined(CONFIG_USER_ONLY)
49 #ifdef TARGET_SPARC64
50 env->cleanwin = env->nwindows - 2;
51 env->cansave = env->nwindows - 2;
52 env->pstate = PS_RMO | PS_PEF | PS_IE;
53 env->asi = 0x82; /* Primary no-fault */
54 #endif
55 #else
56 #if !defined(TARGET_SPARC64)
57 env->psret = 0;
58 env->psrs = 1;
59 env->psrps = 1;
60 #endif
61 #ifdef TARGET_SPARC64
62 env->pstate = PS_PRIV | PS_RED | PS_PEF;
63 if (!cpu_has_hypervisor(env)) {
64 env->pstate |= PS_AG;
65 }
66 env->hpstate = cpu_has_hypervisor(env) ? HS_PRIV : 0;
67 env->tl = env->maxtl;
68 env->gl = 2;
69 cpu_tsptr(env)->tt = TT_POWER_ON_RESET;
70 env->lsu = 0;
71 #else
72 env->mmuregs[0] &= ~(MMU_E | MMU_NF);
73 env->mmuregs[0] |= env->def.mmu_bm;
74 #endif
75 env->pc = 0;
76 env->npc = env->pc + 4;
77 #endif
78 env->cache_control = 0;
79 }
80
81 #ifndef CONFIG_USER_ONLY
sparc_cpu_exec_interrupt(CPUState * cs,int interrupt_request)82 static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
83 {
84 if (interrupt_request & CPU_INTERRUPT_HARD) {
85 CPUSPARCState *env = cpu_env(cs);
86
87 if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) {
88 int pil = env->interrupt_index & 0xf;
89 int type = env->interrupt_index & 0xf0;
90
91 if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) {
92 cs->exception_index = env->interrupt_index;
93 sparc_cpu_do_interrupt(cs);
94 return true;
95 }
96 }
97 }
98 return false;
99 }
100 #endif /* !CONFIG_USER_ONLY */
101
cpu_sparc_disas_set_info(CPUState * cpu,disassemble_info * info)102 static void cpu_sparc_disas_set_info(CPUState *cpu, disassemble_info *info)
103 {
104 info->print_insn = print_insn_sparc;
105 #ifdef TARGET_SPARC64
106 info->mach = bfd_mach_sparc_v9b;
107 #endif
108 }
109
110 static void
cpu_add_feat_as_prop(const char * typename,const char * name,const char * val)111 cpu_add_feat_as_prop(const char *typename, const char *name, const char *val)
112 {
113 GlobalProperty *prop = g_new0(typeof(*prop), 1);
114 prop->driver = typename;
115 prop->property = g_strdup(name);
116 prop->value = g_strdup(val);
117 qdev_prop_register_global(prop);
118 }
119
120 /* Parse "+feature,-feature,feature=foo" CPU feature string */
sparc_cpu_parse_features(const char * typename,char * features,Error ** errp)121 static void sparc_cpu_parse_features(const char *typename, char *features,
122 Error **errp)
123 {
124 GList *l, *plus_features = NULL, *minus_features = NULL;
125 char *featurestr; /* Single 'key=value" string being parsed */
126 static bool cpu_globals_initialized;
127
128 if (cpu_globals_initialized) {
129 return;
130 }
131 cpu_globals_initialized = true;
132
133 if (!features) {
134 return;
135 }
136
137 for (featurestr = strtok(features, ",");
138 featurestr;
139 featurestr = strtok(NULL, ",")) {
140 const char *name;
141 const char *val = NULL;
142 char *eq = NULL;
143
144 /* Compatibility syntax: */
145 if (featurestr[0] == '+') {
146 plus_features = g_list_append(plus_features,
147 g_strdup(featurestr + 1));
148 continue;
149 } else if (featurestr[0] == '-') {
150 minus_features = g_list_append(minus_features,
151 g_strdup(featurestr + 1));
152 continue;
153 }
154
155 eq = strchr(featurestr, '=');
156 name = featurestr;
157 if (eq) {
158 *eq++ = 0;
159 val = eq;
160
161 /*
162 * Temporarily, only +feat/-feat will be supported
163 * for boolean properties until we remove the
164 * minus-overrides-plus semantics and just follow
165 * the order options appear on the command-line.
166 *
167 * TODO: warn if user is relying on minus-override-plus semantics
168 * TODO: remove minus-override-plus semantics after
169 * warning for a few releases
170 */
171 if (!strcasecmp(val, "on") ||
172 !strcasecmp(val, "off") ||
173 !strcasecmp(val, "true") ||
174 !strcasecmp(val, "false")) {
175 error_setg(errp, "Boolean properties in format %s=%s"
176 " are not supported", name, val);
177 return;
178 }
179 } else {
180 error_setg(errp, "Unsupported property format: %s", name);
181 return;
182 }
183 cpu_add_feat_as_prop(typename, name, val);
184 }
185
186 for (l = plus_features; l; l = l->next) {
187 const char *name = l->data;
188 cpu_add_feat_as_prop(typename, name, "on");
189 }
190 g_list_free_full(plus_features, g_free);
191
192 for (l = minus_features; l; l = l->next) {
193 const char *name = l->data;
194 cpu_add_feat_as_prop(typename, name, "off");
195 }
196 g_list_free_full(minus_features, g_free);
197 }
198
cpu_sparc_set_id(CPUSPARCState * env,unsigned int cpu)199 void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu)
200 {
201 #if !defined(TARGET_SPARC64)
202 env->mxccregs[7] = ((cpu + 8) & 0xf) << 24;
203 #endif
204 }
205
206 static const sparc_def_t sparc_defs[] = {
207 #ifdef TARGET_SPARC64
208 {
209 .name = "Fujitsu-Sparc64",
210 .iu_version = ((0x04ULL << 48) | (0x02ULL << 32) | (0ULL << 24)),
211 .fpu_version = 0x00000000,
212 .mmu_version = mmu_us_12,
213 .nwindows = 4,
214 .maxtl = 4,
215 .features = CPU_DEFAULT_FEATURES,
216 },
217 {
218 .name = "Fujitsu-Sparc64-III",
219 .iu_version = ((0x04ULL << 48) | (0x03ULL << 32) | (0ULL << 24)),
220 .fpu_version = 0x00000000,
221 .mmu_version = mmu_us_12,
222 .nwindows = 5,
223 .maxtl = 4,
224 .features = CPU_DEFAULT_FEATURES,
225 },
226 {
227 .name = "Fujitsu-Sparc64-IV",
228 .iu_version = ((0x04ULL << 48) | (0x04ULL << 32) | (0ULL << 24)),
229 .fpu_version = 0x00000000,
230 .mmu_version = mmu_us_12,
231 .nwindows = 8,
232 .maxtl = 5,
233 .features = CPU_DEFAULT_FEATURES,
234 },
235 {
236 .name = "Fujitsu-Sparc64-V",
237 .iu_version = ((0x04ULL << 48) | (0x05ULL << 32) | (0x51ULL << 24)),
238 .fpu_version = 0x00000000,
239 .mmu_version = mmu_us_12,
240 .nwindows = 8,
241 .maxtl = 5,
242 .features = CPU_DEFAULT_FEATURES,
243 },
244 {
245 .name = "TI-UltraSparc-I",
246 .iu_version = ((0x17ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
247 .fpu_version = 0x00000000,
248 .mmu_version = mmu_us_12,
249 .nwindows = 8,
250 .maxtl = 5,
251 .features = CPU_DEFAULT_FEATURES,
252 },
253 {
254 .name = "TI-UltraSparc-II",
255 .iu_version = ((0x17ULL << 48) | (0x11ULL << 32) | (0x20ULL << 24)),
256 .fpu_version = 0x00000000,
257 .mmu_version = mmu_us_12,
258 .nwindows = 8,
259 .maxtl = 5,
260 .features = CPU_DEFAULT_FEATURES,
261 },
262 {
263 .name = "TI-UltraSparc-IIi",
264 .iu_version = ((0x17ULL << 48) | (0x12ULL << 32) | (0x91ULL << 24)),
265 .fpu_version = 0x00000000,
266 .mmu_version = mmu_us_12,
267 .nwindows = 8,
268 .maxtl = 5,
269 .features = CPU_DEFAULT_FEATURES,
270 },
271 {
272 .name = "TI-UltraSparc-IIe",
273 .iu_version = ((0x17ULL << 48) | (0x13ULL << 32) | (0x14ULL << 24)),
274 .fpu_version = 0x00000000,
275 .mmu_version = mmu_us_12,
276 .nwindows = 8,
277 .maxtl = 5,
278 .features = CPU_DEFAULT_FEATURES,
279 },
280 {
281 .name = "Sun-UltraSparc-III",
282 .iu_version = ((0x3eULL << 48) | (0x14ULL << 32) | (0x34ULL << 24)),
283 .fpu_version = 0x00000000,
284 .mmu_version = mmu_us_12,
285 .nwindows = 8,
286 .maxtl = 5,
287 .features = CPU_DEFAULT_FEATURES,
288 },
289 {
290 .name = "Sun-UltraSparc-III-Cu",
291 .iu_version = ((0x3eULL << 48) | (0x15ULL << 32) | (0x41ULL << 24)),
292 .fpu_version = 0x00000000,
293 .mmu_version = mmu_us_3,
294 .nwindows = 8,
295 .maxtl = 5,
296 .features = CPU_DEFAULT_FEATURES,
297 },
298 {
299 .name = "Sun-UltraSparc-IIIi",
300 .iu_version = ((0x3eULL << 48) | (0x16ULL << 32) | (0x34ULL << 24)),
301 .fpu_version = 0x00000000,
302 .mmu_version = mmu_us_12,
303 .nwindows = 8,
304 .maxtl = 5,
305 .features = CPU_DEFAULT_FEATURES,
306 },
307 {
308 .name = "Sun-UltraSparc-IV",
309 .iu_version = ((0x3eULL << 48) | (0x18ULL << 32) | (0x31ULL << 24)),
310 .fpu_version = 0x00000000,
311 .mmu_version = mmu_us_4,
312 .nwindows = 8,
313 .maxtl = 5,
314 .features = CPU_DEFAULT_FEATURES,
315 },
316 {
317 .name = "Sun-UltraSparc-IV-plus",
318 .iu_version = ((0x3eULL << 48) | (0x19ULL << 32) | (0x22ULL << 24)),
319 .fpu_version = 0x00000000,
320 .mmu_version = mmu_us_12,
321 .nwindows = 8,
322 .maxtl = 5,
323 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_CMT,
324 },
325 {
326 .name = "Sun-UltraSparc-IIIi-plus",
327 .iu_version = ((0x3eULL << 48) | (0x22ULL << 32) | (0ULL << 24)),
328 .fpu_version = 0x00000000,
329 .mmu_version = mmu_us_3,
330 .nwindows = 8,
331 .maxtl = 5,
332 .features = CPU_DEFAULT_FEATURES,
333 },
334 {
335 .name = "Sun-UltraSparc-T1",
336 /* defined in sparc_ifu_fdp.v and ctu.h */
337 .iu_version = ((0x3eULL << 48) | (0x23ULL << 32) | (0x02ULL << 24)),
338 .fpu_version = 0x00000000,
339 .mmu_version = mmu_sun4v,
340 .nwindows = 8,
341 .maxtl = 6,
342 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
343 | CPU_FEATURE_GL,
344 },
345 {
346 .name = "Sun-UltraSparc-T2",
347 /* defined in tlu_asi_ctl.v and n2_revid_cust.v */
348 .iu_version = ((0x3eULL << 48) | (0x24ULL << 32) | (0x02ULL << 24)),
349 .fpu_version = 0x00000000,
350 .mmu_version = mmu_sun4v,
351 .nwindows = 8,
352 .maxtl = 6,
353 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_HYPV | CPU_FEATURE_CMT
354 | CPU_FEATURE_GL,
355 },
356 {
357 .name = "NEC-UltraSparc-I",
358 .iu_version = ((0x22ULL << 48) | (0x10ULL << 32) | (0x40ULL << 24)),
359 .fpu_version = 0x00000000,
360 .mmu_version = mmu_us_12,
361 .nwindows = 8,
362 .maxtl = 5,
363 .features = CPU_DEFAULT_FEATURES,
364 },
365 #else
366 {
367 .name = "Fujitsu-MB86904",
368 .iu_version = 0x04 << 24, /* Impl 0, ver 4 */
369 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
370 .mmu_version = 0x04 << 24, /* Impl 0, ver 4 */
371 .mmu_bm = 0x00004000,
372 .mmu_ctpr_mask = 0x00ffffc0,
373 .mmu_cxr_mask = 0x000000ff,
374 .mmu_sfsr_mask = 0x00016fff,
375 .mmu_trcr_mask = 0x00ffffff,
376 .nwindows = 8,
377 .features = CPU_DEFAULT_FEATURES,
378 },
379 {
380 .name = "Fujitsu-MB86907",
381 .iu_version = 0x05 << 24, /* Impl 0, ver 5 */
382 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
383 .mmu_version = 0x05 << 24, /* Impl 0, ver 5 */
384 .mmu_bm = 0x00004000,
385 .mmu_ctpr_mask = 0xffffffc0,
386 .mmu_cxr_mask = 0x000000ff,
387 .mmu_sfsr_mask = 0x00016fff,
388 .mmu_trcr_mask = 0xffffffff,
389 .nwindows = 8,
390 .features = CPU_DEFAULT_FEATURES,
391 },
392 {
393 .name = "TI-MicroSparc-I",
394 .iu_version = 0x41000000,
395 .fpu_version = 4 << FSR_VER_SHIFT,
396 .mmu_version = 0x41000000,
397 .mmu_bm = 0x00004000,
398 .mmu_ctpr_mask = 0x007ffff0,
399 .mmu_cxr_mask = 0x0000003f,
400 .mmu_sfsr_mask = 0x00016fff,
401 .mmu_trcr_mask = 0x0000003f,
402 .nwindows = 7,
403 .features = CPU_FEATURE_MUL | CPU_FEATURE_DIV,
404 },
405 {
406 .name = "TI-MicroSparc-II",
407 .iu_version = 0x42000000,
408 .fpu_version = 4 << FSR_VER_SHIFT,
409 .mmu_version = 0x02000000,
410 .mmu_bm = 0x00004000,
411 .mmu_ctpr_mask = 0x00ffffc0,
412 .mmu_cxr_mask = 0x000000ff,
413 .mmu_sfsr_mask = 0x00016fff,
414 .mmu_trcr_mask = 0x00ffffff,
415 .nwindows = 8,
416 .features = CPU_DEFAULT_FEATURES,
417 },
418 {
419 .name = "TI-MicroSparc-IIep",
420 .iu_version = 0x42000000,
421 .fpu_version = 4 << FSR_VER_SHIFT,
422 .mmu_version = 0x04000000,
423 .mmu_bm = 0x00004000,
424 .mmu_ctpr_mask = 0x00ffffc0,
425 .mmu_cxr_mask = 0x000000ff,
426 .mmu_sfsr_mask = 0x00016bff,
427 .mmu_trcr_mask = 0x00ffffff,
428 .nwindows = 8,
429 .features = CPU_DEFAULT_FEATURES,
430 },
431 {
432 .name = "TI-SuperSparc-40", /* STP1020NPGA */
433 .iu_version = 0x41000000, /* SuperSPARC 2.x */
434 .fpu_version = 0 << FSR_VER_SHIFT,
435 .mmu_version = 0x00000800, /* SuperSPARC 2.x, no MXCC */
436 .mmu_bm = 0x00002000,
437 .mmu_ctpr_mask = 0xffffffc0,
438 .mmu_cxr_mask = 0x0000ffff,
439 .mmu_sfsr_mask = 0xffffffff,
440 .mmu_trcr_mask = 0xffffffff,
441 .nwindows = 8,
442 .features = CPU_DEFAULT_FEATURES,
443 },
444 {
445 .name = "TI-SuperSparc-50", /* STP1020PGA */
446 .iu_version = 0x40000000, /* SuperSPARC 3.x */
447 .fpu_version = 0 << FSR_VER_SHIFT,
448 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
449 .mmu_bm = 0x00002000,
450 .mmu_ctpr_mask = 0xffffffc0,
451 .mmu_cxr_mask = 0x0000ffff,
452 .mmu_sfsr_mask = 0xffffffff,
453 .mmu_trcr_mask = 0xffffffff,
454 .nwindows = 8,
455 .features = CPU_DEFAULT_FEATURES,
456 },
457 {
458 .name = "TI-SuperSparc-51",
459 .iu_version = 0x40000000, /* SuperSPARC 3.x */
460 .fpu_version = 0 << FSR_VER_SHIFT,
461 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
462 .mmu_bm = 0x00002000,
463 .mmu_ctpr_mask = 0xffffffc0,
464 .mmu_cxr_mask = 0x0000ffff,
465 .mmu_sfsr_mask = 0xffffffff,
466 .mmu_trcr_mask = 0xffffffff,
467 .mxcc_version = 0x00000104,
468 .nwindows = 8,
469 .features = CPU_DEFAULT_FEATURES,
470 },
471 {
472 .name = "TI-SuperSparc-60", /* STP1020APGA */
473 .iu_version = 0x40000000, /* SuperSPARC 3.x */
474 .fpu_version = 0 << FSR_VER_SHIFT,
475 .mmu_version = 0x01000800, /* SuperSPARC 3.x, no MXCC */
476 .mmu_bm = 0x00002000,
477 .mmu_ctpr_mask = 0xffffffc0,
478 .mmu_cxr_mask = 0x0000ffff,
479 .mmu_sfsr_mask = 0xffffffff,
480 .mmu_trcr_mask = 0xffffffff,
481 .nwindows = 8,
482 .features = CPU_DEFAULT_FEATURES,
483 },
484 {
485 .name = "TI-SuperSparc-61",
486 .iu_version = 0x44000000, /* SuperSPARC 3.x */
487 .fpu_version = 0 << FSR_VER_SHIFT,
488 .mmu_version = 0x01000000, /* SuperSPARC 3.x, MXCC */
489 .mmu_bm = 0x00002000,
490 .mmu_ctpr_mask = 0xffffffc0,
491 .mmu_cxr_mask = 0x0000ffff,
492 .mmu_sfsr_mask = 0xffffffff,
493 .mmu_trcr_mask = 0xffffffff,
494 .mxcc_version = 0x00000104,
495 .nwindows = 8,
496 .features = CPU_DEFAULT_FEATURES,
497 },
498 {
499 .name = "TI-SuperSparc-II",
500 .iu_version = 0x40000000, /* SuperSPARC II 1.x */
501 .fpu_version = 0 << FSR_VER_SHIFT,
502 .mmu_version = 0x08000000, /* SuperSPARC II 1.x, MXCC */
503 .mmu_bm = 0x00002000,
504 .mmu_ctpr_mask = 0xffffffc0,
505 .mmu_cxr_mask = 0x0000ffff,
506 .mmu_sfsr_mask = 0xffffffff,
507 .mmu_trcr_mask = 0xffffffff,
508 .mxcc_version = 0x00000104,
509 .nwindows = 8,
510 .features = CPU_DEFAULT_FEATURES,
511 },
512 {
513 .name = "LEON2",
514 .iu_version = 0xf2000000,
515 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
516 .mmu_version = 0xf2000000,
517 .mmu_bm = 0x00004000,
518 .mmu_ctpr_mask = 0x007ffff0,
519 .mmu_cxr_mask = 0x0000003f,
520 .mmu_sfsr_mask = 0xffffffff,
521 .mmu_trcr_mask = 0xffffffff,
522 .nwindows = 8,
523 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
524 },
525 {
526 .name = "LEON3",
527 .iu_version = 0xf3000000,
528 .fpu_version = 4 << FSR_VER_SHIFT, /* FPU version 4 (Meiko) */
529 .mmu_version = 0xf3000000,
530 .mmu_bm = 0x00000000,
531 .mmu_ctpr_mask = 0xfffffffc,
532 .mmu_cxr_mask = 0x000000ff,
533 .mmu_sfsr_mask = 0xffffffff,
534 .mmu_trcr_mask = 0xffffffff,
535 .nwindows = 8,
536 .features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN |
537 CPU_FEATURE_ASR17 | CPU_FEATURE_CACHE_CTRL | CPU_FEATURE_POWERDOWN |
538 CPU_FEATURE_CASA,
539 },
540 #endif
541 };
542
543 /* This must match sparc_cpu_properties[]. */
544 static const char * const feature_name[] = {
545 [CPU_FEATURE_BIT_FLOAT128] = "float128",
546 #ifdef TARGET_SPARC64
547 [CPU_FEATURE_BIT_CMT] = "cmt",
548 [CPU_FEATURE_BIT_GL] = "gl",
549 [CPU_FEATURE_BIT_HYPV] = "hypv",
550 [CPU_FEATURE_BIT_VIS1] = "vis1",
551 [CPU_FEATURE_BIT_VIS2] = "vis2",
552 [CPU_FEATURE_BIT_FMAF] = "fmaf",
553 [CPU_FEATURE_BIT_VIS3] = "vis3",
554 [CPU_FEATURE_BIT_IMA] = "ima",
555 [CPU_FEATURE_BIT_VIS4] = "vis4",
556 #else
557 [CPU_FEATURE_BIT_MUL] = "mul",
558 [CPU_FEATURE_BIT_DIV] = "div",
559 [CPU_FEATURE_BIT_FSMULD] = "fsmuld",
560 #endif
561 };
562
print_features(uint32_t features,const char * prefix)563 static void print_features(uint32_t features, const char *prefix)
564 {
565 unsigned int i;
566
567 for (i = 0; i < ARRAY_SIZE(feature_name); i++) {
568 if (feature_name[i] && (features & (1 << i))) {
569 if (prefix) {
570 qemu_printf("%s", prefix);
571 }
572 qemu_printf("%s ", feature_name[i]);
573 }
574 }
575 }
576
sparc_cpu_list(void)577 void sparc_cpu_list(void)
578 {
579 unsigned int i;
580
581 qemu_printf("Available CPU types:\n");
582 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
583 qemu_printf(" %-20s (IU " TARGET_FMT_lx
584 " FPU %08x MMU %08x NWINS %d) ",
585 sparc_defs[i].name,
586 sparc_defs[i].iu_version,
587 sparc_defs[i].fpu_version,
588 sparc_defs[i].mmu_version,
589 sparc_defs[i].nwindows);
590 print_features(CPU_DEFAULT_FEATURES & ~sparc_defs[i].features, "-");
591 print_features(~CPU_DEFAULT_FEATURES & sparc_defs[i].features, "+");
592 qemu_printf("\n");
593 }
594 qemu_printf("Default CPU feature flags (use '-' to remove): ");
595 print_features(CPU_DEFAULT_FEATURES, NULL);
596 qemu_printf("\n");
597 qemu_printf("Available CPU feature flags (use '+' to add): ");
598 print_features(~CPU_DEFAULT_FEATURES, NULL);
599 qemu_printf("\n");
600 qemu_printf("Numerical features (use '=' to set): iu_version "
601 "fpu_version mmu_version nwindows\n");
602 }
603
cpu_print_cc(FILE * f,uint32_t cc)604 static void cpu_print_cc(FILE *f, uint32_t cc)
605 {
606 qemu_fprintf(f, "%c%c%c%c", cc & PSR_NEG ? 'N' : '-',
607 cc & PSR_ZERO ? 'Z' : '-', cc & PSR_OVF ? 'V' : '-',
608 cc & PSR_CARRY ? 'C' : '-');
609 }
610
611 #ifdef TARGET_SPARC64
612 #define REGS_PER_LINE 4
613 #else
614 #define REGS_PER_LINE 8
615 #endif
616
sparc_cpu_dump_state(CPUState * cs,FILE * f,int flags)617 static void sparc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
618 {
619 CPUSPARCState *env = cpu_env(cs);
620 int i, x;
621
622 qemu_fprintf(f, "pc: " TARGET_FMT_lx " npc: " TARGET_FMT_lx "\n", env->pc,
623 env->npc);
624
625 for (i = 0; i < 8; i++) {
626 if (i % REGS_PER_LINE == 0) {
627 qemu_fprintf(f, "%%g%d-%d:", i, i + REGS_PER_LINE - 1);
628 }
629 qemu_fprintf(f, " " TARGET_FMT_lx, env->gregs[i]);
630 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
631 qemu_fprintf(f, "\n");
632 }
633 }
634 for (x = 0; x < 3; x++) {
635 for (i = 0; i < 8; i++) {
636 if (i % REGS_PER_LINE == 0) {
637 qemu_fprintf(f, "%%%c%d-%d: ",
638 x == 0 ? 'o' : (x == 1 ? 'l' : 'i'),
639 i, i + REGS_PER_LINE - 1);
640 }
641 qemu_fprintf(f, TARGET_FMT_lx " ", env->regwptr[i + x * 8]);
642 if (i % REGS_PER_LINE == REGS_PER_LINE - 1) {
643 qemu_fprintf(f, "\n");
644 }
645 }
646 }
647
648 if (flags & CPU_DUMP_FPU) {
649 for (i = 0; i < TARGET_DPREGS; i++) {
650 if ((i & 3) == 0) {
651 qemu_fprintf(f, "%%f%02d: ", i * 2);
652 }
653 qemu_fprintf(f, " %016" PRIx64, env->fpr[i].ll);
654 if ((i & 3) == 3) {
655 qemu_fprintf(f, "\n");
656 }
657 }
658 }
659
660 #ifdef TARGET_SPARC64
661 qemu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate,
662 (unsigned)cpu_get_ccr(env));
663 cpu_print_cc(f, cpu_get_ccr(env) << PSR_CARRY_SHIFT);
664 qemu_fprintf(f, " xcc: ");
665 cpu_print_cc(f, cpu_get_ccr(env) << (PSR_CARRY_SHIFT - 4));
666 qemu_fprintf(f, ") asi: %02x tl: %d pil: %x gl: %d\n", env->asi, env->tl,
667 env->psrpil, env->gl);
668 qemu_fprintf(f, "tbr: " TARGET_FMT_lx " hpstate: " TARGET_FMT_lx " htba: "
669 TARGET_FMT_lx "\n", env->tbr, env->hpstate, env->htba);
670 qemu_fprintf(f, "cansave: %d canrestore: %d otherwin: %d wstate: %d "
671 "cleanwin: %d cwp: %d\n",
672 env->cansave, env->canrestore, env->otherwin, env->wstate,
673 env->cleanwin, env->nwindows - 1 - env->cwp);
674 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx " fprs: %016x\n",
675 cpu_get_fsr(env), env->y, env->fprs);
676
677 #else
678 qemu_fprintf(f, "psr: %08x (icc: ", cpu_get_psr(env));
679 cpu_print_cc(f, cpu_get_psr(env));
680 qemu_fprintf(f, " SPE: %c%c%c) wim: %08x\n", env->psrs ? 'S' : '-',
681 env->psrps ? 'P' : '-', env->psret ? 'E' : '-',
682 env->wim);
683 qemu_fprintf(f, "fsr: " TARGET_FMT_lx " y: " TARGET_FMT_lx "\n",
684 cpu_get_fsr(env), env->y);
685 #endif
686 qemu_fprintf(f, "\n");
687 }
688
sparc_cpu_set_pc(CPUState * cs,vaddr value)689 static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
690 {
691 SPARCCPU *cpu = SPARC_CPU(cs);
692
693 cpu->env.pc = value;
694 cpu->env.npc = value + 4;
695 }
696
sparc_cpu_get_pc(CPUState * cs)697 static vaddr sparc_cpu_get_pc(CPUState *cs)
698 {
699 SPARCCPU *cpu = SPARC_CPU(cs);
700
701 return cpu->env.pc;
702 }
703
sparc_cpu_synchronize_from_tb(CPUState * cs,const TranslationBlock * tb)704 static void sparc_cpu_synchronize_from_tb(CPUState *cs,
705 const TranslationBlock *tb)
706 {
707 SPARCCPU *cpu = SPARC_CPU(cs);
708
709 tcg_debug_assert(!tcg_cflags_has(cs, CF_PCREL));
710 cpu->env.pc = tb->pc;
711 cpu->env.npc = tb->cs_base;
712 }
713
sparc_cpu_has_work(CPUState * cs)714 static bool sparc_cpu_has_work(CPUState *cs)
715 {
716 return (cs->interrupt_request & CPU_INTERRUPT_HARD) &&
717 cpu_interrupts_enabled(cpu_env(cs));
718 }
719
sparc_cpu_mmu_index(CPUState * cs,bool ifetch)720 static int sparc_cpu_mmu_index(CPUState *cs, bool ifetch)
721 {
722 CPUSPARCState *env = cpu_env(cs);
723
724 #ifndef TARGET_SPARC64
725 if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
726 return MMU_PHYS_IDX;
727 } else {
728 return env->psrs;
729 }
730 #else
731 /* IMMU or DMMU disabled. */
732 if (ifetch
733 ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
734 : (env->lsu & DMMU_E) == 0) {
735 return MMU_PHYS_IDX;
736 } else if (cpu_hypervisor_mode(env)) {
737 return MMU_PHYS_IDX;
738 } else if (env->tl > 0) {
739 return MMU_NUCLEUS_IDX;
740 } else if (cpu_supervisor_mode(env)) {
741 return MMU_KERNEL_IDX;
742 } else {
743 return MMU_USER_IDX;
744 }
745 #endif
746 }
747
sparc_cpu_type_name(const char * cpu_model)748 static char *sparc_cpu_type_name(const char *cpu_model)
749 {
750 char *name = g_strdup_printf(SPARC_CPU_TYPE_NAME("%s"), cpu_model);
751 char *s = name;
752
753 /* SPARC cpu model names happen to have whitespaces,
754 * as type names shouldn't have spaces replace them with '-'
755 */
756 while ((s = strchr(s, ' '))) {
757 *s = '-';
758 }
759
760 return name;
761 }
762
sparc_cpu_class_by_name(const char * cpu_model)763 static ObjectClass *sparc_cpu_class_by_name(const char *cpu_model)
764 {
765 ObjectClass *oc;
766 char *typename;
767
768 typename = sparc_cpu_type_name(cpu_model);
769
770 /* Fix up legacy names with '+' in it */
771 if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV+"))) {
772 g_free(typename);
773 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IV-plus"));
774 } else if (g_str_equal(typename, SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi+"))) {
775 g_free(typename);
776 typename = g_strdup(SPARC_CPU_TYPE_NAME("Sun-UltraSparc-IIIi-plus"));
777 }
778
779 oc = object_class_by_name(typename);
780 g_free(typename);
781 return oc;
782 }
783
sparc_cpu_realizefn(DeviceState * dev,Error ** errp)784 static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
785 {
786 CPUState *cs = CPU(dev);
787 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev);
788 Error *local_err = NULL;
789 CPUSPARCState *env = cpu_env(cs);
790
791 #if defined(CONFIG_USER_ONLY)
792 /* We are emulating the kernel, which will trap and emulate float128. */
793 env->def.features |= CPU_FEATURE_FLOAT128;
794 #endif
795
796 env->version = env->def.iu_version;
797 env->nwindows = env->def.nwindows;
798 #if !defined(TARGET_SPARC64)
799 env->mmuregs[0] |= env->def.mmu_version;
800 cpu_sparc_set_id(env, 0);
801 env->mxccregs[7] |= env->def.mxcc_version;
802 #else
803 env->mmu_version = env->def.mmu_version;
804 env->maxtl = env->def.maxtl;
805 env->version |= env->def.maxtl << 8;
806 env->version |= env->def.nwindows - 1;
807 #endif
808 cpu_put_fsr(env, 0);
809
810 cpu_exec_realizefn(cs, &local_err);
811 if (local_err != NULL) {
812 error_propagate(errp, local_err);
813 return;
814 }
815
816 qemu_init_vcpu(cs);
817
818 scc->parent_realize(dev, errp);
819 }
820
sparc_cpu_initfn(Object * obj)821 static void sparc_cpu_initfn(Object *obj)
822 {
823 SPARCCPU *cpu = SPARC_CPU(obj);
824 SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(obj);
825 CPUSPARCState *env = &cpu->env;
826
827 if (scc->cpu_def) {
828 env->def = *scc->cpu_def;
829 }
830 }
831
sparc_get_nwindows(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)832 static void sparc_get_nwindows(Object *obj, Visitor *v, const char *name,
833 void *opaque, Error **errp)
834 {
835 SPARCCPU *cpu = SPARC_CPU(obj);
836 int64_t value = cpu->env.def.nwindows;
837
838 visit_type_int(v, name, &value, errp);
839 }
840
sparc_set_nwindows(Object * obj,Visitor * v,const char * name,void * opaque,Error ** errp)841 static void sparc_set_nwindows(Object *obj, Visitor *v, const char *name,
842 void *opaque, Error **errp)
843 {
844 const int64_t min = MIN_NWINDOWS;
845 const int64_t max = MAX_NWINDOWS;
846 SPARCCPU *cpu = SPARC_CPU(obj);
847 int64_t value;
848
849 if (!visit_type_int(v, name, &value, errp)) {
850 return;
851 }
852
853 if (value < min || value > max) {
854 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
855 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
856 object_get_typename(obj), name ? name : "null",
857 value, min, max);
858 return;
859 }
860 cpu->env.def.nwindows = value;
861 }
862
863 static PropertyInfo qdev_prop_nwindows = {
864 .name = "int",
865 .get = sparc_get_nwindows,
866 .set = sparc_set_nwindows,
867 };
868
869 /* This must match feature_name[]. */
870 static Property sparc_cpu_properties[] = {
871 DEFINE_PROP_BIT("float128", SPARCCPU, env.def.features,
872 CPU_FEATURE_BIT_FLOAT128, false),
873 #ifdef TARGET_SPARC64
874 DEFINE_PROP_BIT("cmt", SPARCCPU, env.def.features,
875 CPU_FEATURE_BIT_CMT, false),
876 DEFINE_PROP_BIT("gl", SPARCCPU, env.def.features,
877 CPU_FEATURE_BIT_GL, false),
878 DEFINE_PROP_BIT("hypv", SPARCCPU, env.def.features,
879 CPU_FEATURE_BIT_HYPV, false),
880 DEFINE_PROP_BIT("vis1", SPARCCPU, env.def.features,
881 CPU_FEATURE_BIT_VIS1, false),
882 DEFINE_PROP_BIT("vis2", SPARCCPU, env.def.features,
883 CPU_FEATURE_BIT_VIS2, false),
884 DEFINE_PROP_BIT("fmaf", SPARCCPU, env.def.features,
885 CPU_FEATURE_BIT_FMAF, false),
886 DEFINE_PROP_BIT("vis3", SPARCCPU, env.def.features,
887 CPU_FEATURE_BIT_VIS3, false),
888 DEFINE_PROP_BIT("ima", SPARCCPU, env.def.features,
889 CPU_FEATURE_BIT_IMA, false),
890 DEFINE_PROP_BIT("vis4", SPARCCPU, env.def.features,
891 CPU_FEATURE_BIT_VIS4, false),
892 #else
893 DEFINE_PROP_BIT("mul", SPARCCPU, env.def.features,
894 CPU_FEATURE_BIT_MUL, false),
895 DEFINE_PROP_BIT("div", SPARCCPU, env.def.features,
896 CPU_FEATURE_BIT_DIV, false),
897 DEFINE_PROP_BIT("fsmuld", SPARCCPU, env.def.features,
898 CPU_FEATURE_BIT_FSMULD, false),
899 #endif
900 DEFINE_PROP_UNSIGNED("iu-version", SPARCCPU, env.def.iu_version, 0,
901 qdev_prop_uint64, target_ulong),
902 DEFINE_PROP_UINT32("fpu-version", SPARCCPU, env.def.fpu_version, 0),
903 DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0),
904 DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows,
905 qdev_prop_nwindows, uint32_t),
906 DEFINE_PROP_END_OF_LIST()
907 };
908
909 #ifndef CONFIG_USER_ONLY
910 #include "hw/core/sysemu-cpu-ops.h"
911
912 static const struct SysemuCPUOps sparc_sysemu_ops = {
913 .get_phys_page_debug = sparc_cpu_get_phys_page_debug,
914 .legacy_vmsd = &vmstate_sparc_cpu,
915 };
916 #endif
917
918 #ifdef CONFIG_TCG
919 #include "hw/core/tcg-cpu-ops.h"
920
921 static const TCGCPUOps sparc_tcg_ops = {
922 .initialize = sparc_tcg_init,
923 .synchronize_from_tb = sparc_cpu_synchronize_from_tb,
924 .restore_state_to_opc = sparc_restore_state_to_opc,
925
926 #ifndef CONFIG_USER_ONLY
927 .tlb_fill = sparc_cpu_tlb_fill,
928 .cpu_exec_interrupt = sparc_cpu_exec_interrupt,
929 .cpu_exec_halt = sparc_cpu_has_work,
930 .do_interrupt = sparc_cpu_do_interrupt,
931 .do_transaction_failed = sparc_cpu_do_transaction_failed,
932 .do_unaligned_access = sparc_cpu_do_unaligned_access,
933 #endif /* !CONFIG_USER_ONLY */
934 };
935 #endif /* CONFIG_TCG */
936
sparc_cpu_class_init(ObjectClass * oc,void * data)937 static void sparc_cpu_class_init(ObjectClass *oc, void *data)
938 {
939 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
940 CPUClass *cc = CPU_CLASS(oc);
941 DeviceClass *dc = DEVICE_CLASS(oc);
942 ResettableClass *rc = RESETTABLE_CLASS(oc);
943
944 device_class_set_parent_realize(dc, sparc_cpu_realizefn,
945 &scc->parent_realize);
946 device_class_set_props(dc, sparc_cpu_properties);
947
948 resettable_class_set_parent_phases(rc, NULL, sparc_cpu_reset_hold, NULL,
949 &scc->parent_phases);
950
951 cc->class_by_name = sparc_cpu_class_by_name;
952 cc->parse_features = sparc_cpu_parse_features;
953 cc->has_work = sparc_cpu_has_work;
954 cc->mmu_index = sparc_cpu_mmu_index;
955 cc->dump_state = sparc_cpu_dump_state;
956 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
957 cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
958 #endif
959 cc->set_pc = sparc_cpu_set_pc;
960 cc->get_pc = sparc_cpu_get_pc;
961 cc->gdb_read_register = sparc_cpu_gdb_read_register;
962 cc->gdb_write_register = sparc_cpu_gdb_write_register;
963 #ifndef CONFIG_USER_ONLY
964 cc->sysemu_ops = &sparc_sysemu_ops;
965 #endif
966 cc->disas_set_info = cpu_sparc_disas_set_info;
967
968 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
969 cc->gdb_num_core_regs = 86;
970 #else
971 cc->gdb_num_core_regs = 72;
972 #endif
973 cc->tcg_ops = &sparc_tcg_ops;
974 }
975
976 static const TypeInfo sparc_cpu_type_info = {
977 .name = TYPE_SPARC_CPU,
978 .parent = TYPE_CPU,
979 .instance_size = sizeof(SPARCCPU),
980 .instance_align = __alignof(SPARCCPU),
981 .instance_init = sparc_cpu_initfn,
982 .abstract = true,
983 .class_size = sizeof(SPARCCPUClass),
984 .class_init = sparc_cpu_class_init,
985 };
986
sparc_cpu_cpudef_class_init(ObjectClass * oc,void * data)987 static void sparc_cpu_cpudef_class_init(ObjectClass *oc, void *data)
988 {
989 SPARCCPUClass *scc = SPARC_CPU_CLASS(oc);
990 scc->cpu_def = data;
991 }
992
sparc_register_cpudef_type(const struct sparc_def_t * def)993 static void sparc_register_cpudef_type(const struct sparc_def_t *def)
994 {
995 char *typename = sparc_cpu_type_name(def->name);
996 TypeInfo ti = {
997 .name = typename,
998 .parent = TYPE_SPARC_CPU,
999 .class_init = sparc_cpu_cpudef_class_init,
1000 .class_data = (void *)def,
1001 };
1002
1003 type_register(&ti);
1004 g_free(typename);
1005 }
1006
sparc_cpu_register_types(void)1007 static void sparc_cpu_register_types(void)
1008 {
1009 int i;
1010
1011 type_register_static(&sparc_cpu_type_info);
1012 for (i = 0; i < ARRAY_SIZE(sparc_defs); i++) {
1013 sparc_register_cpudef_type(&sparc_defs[i]);
1014 }
1015 }
1016
1017 type_init(sparc_cpu_register_types)
1018