1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2005, Intec Automation Inc.
4 * Copyright (C) 2014, Freescale Semiconductor, Inc.
5 */
6
7 #include <linux/bitfield.h>
8 #include <linux/device.h>
9 #include <linux/errno.h>
10 #include <linux/mtd/spi-nor.h>
11
12 #include "core.h"
13
14 /* flash_info mfr_flag. Used to clear sticky prorietary SR bits. */
15 #define USE_CLSR BIT(0)
16 #define USE_CLPEF BIT(1)
17
18 #define SPINOR_OP_CLSR 0x30 /* Clear status register 1 */
19 #define SPINOR_OP_CLPEF 0x82 /* Clear program/erase failure flags */
20 #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */
21 #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */
22 #define SPINOR_REG_CYPRESS_VREG 0x00800000
23 #define SPINOR_REG_CYPRESS_STR1 0x0
24 #define SPINOR_REG_CYPRESS_STR1V \
25 (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_STR1)
26 #define SPINOR_REG_CYPRESS_CFR1 0x2
27 #define SPINOR_REG_CYPRESS_CFR1_QUAD_EN BIT(1) /* Quad Enable */
28 #define SPINOR_REG_CYPRESS_CFR2 0x3
29 #define SPINOR_REG_CYPRESS_CFR2V \
30 (SPINOR_REG_CYPRESS_VREG + SPINOR_REG_CYPRESS_CFR2)
31 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK GENMASK(3, 0)
32 #define SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24 0xb
33 #define SPINOR_REG_CYPRESS_CFR2_ADRBYT BIT(7)
34 #define SPINOR_REG_CYPRESS_CFR3 0x4
35 #define SPINOR_REG_CYPRESS_CFR3_PGSZ BIT(4) /* Page size. */
36 #define SPINOR_REG_CYPRESS_CFR5 0x6
37 #define SPINOR_REG_CYPRESS_CFR5_BIT6 BIT(6)
38 #define SPINOR_REG_CYPRESS_CFR5_DDR BIT(1)
39 #define SPINOR_REG_CYPRESS_CFR5_OPI BIT(0)
40 #define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN \
41 (SPINOR_REG_CYPRESS_CFR5_BIT6 | SPINOR_REG_CYPRESS_CFR5_DDR | \
42 SPINOR_REG_CYPRESS_CFR5_OPI)
43 #define SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS SPINOR_REG_CYPRESS_CFR5_BIT6
44 #define SPINOR_OP_CYPRESS_RD_FAST 0xee
45 #define SPINOR_REG_CYPRESS_ARCFN 0x00000006
46
47 /* Cypress SPI NOR flash operations. */
48 #define CYPRESS_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \
49 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_WR_ANY_REG, 0), \
50 SPI_MEM_OP_ADDR(naddr, addr, 0), \
51 SPI_MEM_OP_NO_DUMMY, \
52 SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
53
54 #define CYPRESS_NOR_RD_ANY_REG_OP(naddr, addr, ndummy, buf) \
55 SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RD_ANY_REG, 0), \
56 SPI_MEM_OP_ADDR(naddr, addr, 0), \
57 SPI_MEM_OP_DUMMY(ndummy, 0), \
58 SPI_MEM_OP_DATA_IN(1, buf, 0))
59
60 #define SPANSION_OP(opcode) \
61 SPI_MEM_OP(SPI_MEM_OP_CMD(opcode, 0), \
62 SPI_MEM_OP_NO_ADDR, \
63 SPI_MEM_OP_NO_DUMMY, \
64 SPI_MEM_OP_NO_DATA)
65
66 /**
67 * struct spansion_nor_params - Spansion private parameters.
68 * @clsr: Clear Status Register or Clear Program and Erase Failure Flag
69 * opcode.
70 */
71 struct spansion_nor_params {
72 u8 clsr;
73 };
74
75 /**
76 * spansion_nor_clear_sr() - Clear the Status Register.
77 * @nor: pointer to 'struct spi_nor'.
78 */
spansion_nor_clear_sr(struct spi_nor * nor)79 static void spansion_nor_clear_sr(struct spi_nor *nor)
80 {
81 const struct spansion_nor_params *priv_params = nor->params->priv;
82 int ret;
83
84 if (nor->spimem) {
85 struct spi_mem_op op = SPANSION_OP(priv_params->clsr);
86
87 spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
88
89 ret = spi_mem_exec_op(nor->spimem, &op);
90 } else {
91 ret = spi_nor_controller_ops_write_reg(nor, SPINOR_OP_CLSR,
92 NULL, 0);
93 }
94
95 if (ret)
96 dev_dbg(nor->dev, "error %d clearing SR\n", ret);
97 }
98
cypress_nor_sr_ready_and_clear_reg(struct spi_nor * nor,u64 addr)99 static int cypress_nor_sr_ready_and_clear_reg(struct spi_nor *nor, u64 addr)
100 {
101 struct spi_nor_flash_parameter *params = nor->params;
102 struct spi_mem_op op =
103 CYPRESS_NOR_RD_ANY_REG_OP(params->addr_mode_nbytes, addr,
104 0, nor->bouncebuf);
105 int ret;
106
107 if (nor->reg_proto == SNOR_PROTO_8_8_8_DTR) {
108 op.addr.nbytes = nor->addr_nbytes;
109 op.dummy.nbytes = params->rdsr_dummy;
110 op.data.nbytes = 2;
111 }
112
113 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
114 if (ret)
115 return ret;
116
117 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
118 if (nor->bouncebuf[0] & SR_E_ERR)
119 dev_err(nor->dev, "Erase Error occurred\n");
120 else
121 dev_err(nor->dev, "Programming Error occurred\n");
122
123 spansion_nor_clear_sr(nor);
124
125 ret = spi_nor_write_disable(nor);
126 if (ret)
127 return ret;
128
129 return -EIO;
130 }
131
132 return !(nor->bouncebuf[0] & SR_WIP);
133 }
134 /**
135 * cypress_nor_sr_ready_and_clear() - Query the Status Register of each die by
136 * using Read Any Register command to see if the whole flash is ready for new
137 * commands and clear it if there are any errors.
138 * @nor: pointer to 'struct spi_nor'.
139 *
140 * Return: 1 if ready, 0 if not ready, -errno on errors.
141 */
cypress_nor_sr_ready_and_clear(struct spi_nor * nor)142 static int cypress_nor_sr_ready_and_clear(struct spi_nor *nor)
143 {
144 struct spi_nor_flash_parameter *params = nor->params;
145 u64 addr;
146 int ret;
147 u8 i;
148
149 for (i = 0; i < params->n_dice; i++) {
150 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_STR1;
151 ret = cypress_nor_sr_ready_and_clear_reg(nor, addr);
152 if (ret < 0)
153 return ret;
154 else if (ret == 0)
155 return 0;
156 }
157
158 return 1;
159 }
160
cypress_nor_set_memlat(struct spi_nor * nor,u64 addr)161 static int cypress_nor_set_memlat(struct spi_nor *nor, u64 addr)
162 {
163 struct spi_mem_op op;
164 u8 *buf = nor->bouncebuf;
165 int ret;
166 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
167
168 op = (struct spi_mem_op)
169 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0, buf);
170
171 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
172 if (ret)
173 return ret;
174
175 /* Use 24 dummy cycles for memory array reads. */
176 *buf &= ~SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK;
177 *buf |= FIELD_PREP(SPINOR_REG_CYPRESS_CFR2_MEMLAT_MASK,
178 SPINOR_REG_CYPRESS_CFR2_MEMLAT_11_24);
179 op = (struct spi_mem_op)
180 CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1, buf);
181
182 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
183 if (ret)
184 return ret;
185
186 nor->read_dummy = 24;
187
188 return 0;
189 }
190
cypress_nor_set_octal_dtr_bits(struct spi_nor * nor,u64 addr)191 static int cypress_nor_set_octal_dtr_bits(struct spi_nor *nor, u64 addr)
192 {
193 struct spi_mem_op op;
194 u8 *buf = nor->bouncebuf;
195
196 /* Set the octal and DTR enable bits. */
197 buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_EN;
198 op = (struct spi_mem_op)
199 CYPRESS_NOR_WR_ANY_REG_OP(nor->params->addr_mode_nbytes,
200 addr, 1, buf);
201
202 return spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
203 }
204
cypress_nor_octal_dtr_en(struct spi_nor * nor)205 static int cypress_nor_octal_dtr_en(struct spi_nor *nor)
206 {
207 const struct spi_nor_flash_parameter *params = nor->params;
208 u8 *buf = nor->bouncebuf;
209 u64 addr;
210 int i, ret;
211
212 for (i = 0; i < params->n_dice; i++) {
213 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR2;
214 ret = cypress_nor_set_memlat(nor, addr);
215 if (ret)
216 return ret;
217
218 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5;
219 ret = cypress_nor_set_octal_dtr_bits(nor, addr);
220 if (ret)
221 return ret;
222 }
223
224 /* Read flash ID to make sure the switch was successful. */
225 ret = spi_nor_read_id(nor, nor->addr_nbytes, 3, buf,
226 SNOR_PROTO_8_8_8_DTR);
227 if (ret) {
228 dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
229 return ret;
230 }
231
232 if (memcmp(buf, nor->info->id, nor->info->id_len))
233 return -EINVAL;
234
235 return 0;
236 }
237
cypress_nor_set_single_spi_bits(struct spi_nor * nor,u64 addr)238 static int cypress_nor_set_single_spi_bits(struct spi_nor *nor, u64 addr)
239 {
240 struct spi_mem_op op;
241 u8 *buf = nor->bouncebuf;
242
243 /*
244 * The register is 1-byte wide, but 1-byte transactions are not allowed
245 * in 8D-8D-8D mode. Since there is no register at the next location,
246 * just initialize the value to 0 and let the transaction go on.
247 */
248 buf[0] = SPINOR_REG_CYPRESS_CFR5_OCT_DTR_DS;
249 buf[1] = 0;
250 op = (struct spi_mem_op)
251 CYPRESS_NOR_WR_ANY_REG_OP(nor->addr_nbytes, addr, 2, buf);
252 return spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
253 }
254
cypress_nor_octal_dtr_dis(struct spi_nor * nor)255 static int cypress_nor_octal_dtr_dis(struct spi_nor *nor)
256 {
257 const struct spi_nor_flash_parameter *params = nor->params;
258 u8 *buf = nor->bouncebuf;
259 u64 addr;
260 int i, ret;
261
262 for (i = 0; i < params->n_dice; i++) {
263 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR5;
264 ret = cypress_nor_set_single_spi_bits(nor, addr);
265 if (ret)
266 return ret;
267 }
268
269 /* Read flash ID to make sure the switch was successful. */
270 ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
271 if (ret) {
272 dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
273 return ret;
274 }
275
276 if (memcmp(buf, nor->info->id, nor->info->id_len))
277 return -EINVAL;
278
279 return 0;
280 }
281
cypress_nor_quad_enable_volatile_reg(struct spi_nor * nor,u64 addr)282 static int cypress_nor_quad_enable_volatile_reg(struct spi_nor *nor, u64 addr)
283 {
284 struct spi_mem_op op;
285 u8 addr_mode_nbytes = nor->params->addr_mode_nbytes;
286 u8 cfr1v_written;
287 int ret;
288
289 op = (struct spi_mem_op)
290 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0,
291 nor->bouncebuf);
292
293 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
294 if (ret)
295 return ret;
296
297 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR1_QUAD_EN)
298 return 0;
299
300 /* Update the Quad Enable bit. */
301 nor->bouncebuf[0] |= SPINOR_REG_CYPRESS_CFR1_QUAD_EN;
302 op = (struct spi_mem_op)
303 CYPRESS_NOR_WR_ANY_REG_OP(addr_mode_nbytes, addr, 1,
304 nor->bouncebuf);
305 ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
306 if (ret)
307 return ret;
308
309 cfr1v_written = nor->bouncebuf[0];
310
311 /* Read back and check it. */
312 op = (struct spi_mem_op)
313 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode_nbytes, addr, 0,
314 nor->bouncebuf);
315 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
316 if (ret)
317 return ret;
318
319 if (nor->bouncebuf[0] != cfr1v_written) {
320 dev_err(nor->dev, "CFR1: Read back test failed\n");
321 return -EIO;
322 }
323
324 return 0;
325 }
326
327 /**
328 * cypress_nor_quad_enable_volatile() - enable Quad I/O mode in volatile
329 * register.
330 * @nor: pointer to a 'struct spi_nor'
331 *
332 * It is recommended to update volatile registers in the field application due
333 * to a risk of the non-volatile registers corruption by power interrupt. This
334 * function sets Quad Enable bit in CFR1 volatile. If users set the Quad Enable
335 * bit in the CFR1 non-volatile in advance (typically by a Flash programmer
336 * before mounting Flash on PCB), the Quad Enable bit in the CFR1 volatile is
337 * also set during Flash power-up.
338 *
339 * Return: 0 on success, -errno otherwise.
340 */
cypress_nor_quad_enable_volatile(struct spi_nor * nor)341 static int cypress_nor_quad_enable_volatile(struct spi_nor *nor)
342 {
343 struct spi_nor_flash_parameter *params = nor->params;
344 u64 addr;
345 u8 i;
346 int ret;
347
348 for (i = 0; i < params->n_dice; i++) {
349 addr = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR1;
350 ret = cypress_nor_quad_enable_volatile_reg(nor, addr);
351 if (ret)
352 return ret;
353 }
354
355 return 0;
356 }
357
358 /**
359 * cypress_nor_determine_addr_mode_by_sr1() - Determine current address mode
360 * (3 or 4-byte) by querying status
361 * register 1 (SR1).
362 * @nor: pointer to a 'struct spi_nor'
363 * @addr_mode: ponter to a buffer where we return the determined
364 * address mode.
365 *
366 * This function tries to determine current address mode by comparing SR1 value
367 * from RDSR1(no address), RDAR(3-byte address), and RDAR(4-byte address).
368 *
369 * Return: 0 on success, -errno otherwise.
370 */
cypress_nor_determine_addr_mode_by_sr1(struct spi_nor * nor,u8 * addr_mode)371 static int cypress_nor_determine_addr_mode_by_sr1(struct spi_nor *nor,
372 u8 *addr_mode)
373 {
374 struct spi_mem_op op =
375 CYPRESS_NOR_RD_ANY_REG_OP(3, SPINOR_REG_CYPRESS_STR1V, 0,
376 nor->bouncebuf);
377 bool is3byte, is4byte;
378 int ret;
379
380 ret = spi_nor_read_sr(nor, &nor->bouncebuf[1]);
381 if (ret)
382 return ret;
383
384 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
385 if (ret)
386 return ret;
387
388 is3byte = (nor->bouncebuf[0] == nor->bouncebuf[1]);
389
390 op = (struct spi_mem_op)
391 CYPRESS_NOR_RD_ANY_REG_OP(4, SPINOR_REG_CYPRESS_STR1V, 0,
392 nor->bouncebuf);
393 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
394 if (ret)
395 return ret;
396
397 is4byte = (nor->bouncebuf[0] == nor->bouncebuf[1]);
398
399 if (is3byte == is4byte)
400 return -EIO;
401 if (is3byte)
402 *addr_mode = 3;
403 else
404 *addr_mode = 4;
405
406 return 0;
407 }
408
409 /**
410 * cypress_nor_set_addr_mode_nbytes() - Set the number of address bytes mode of
411 * current address mode.
412 * @nor: pointer to a 'struct spi_nor'
413 *
414 * Determine current address mode by reading SR1 with different methods, then
415 * query CFR2V[7] to confirm. If determination is failed, force enter to 4-byte
416 * address mode.
417 *
418 * Return: 0 on success, -errno otherwise.
419 */
cypress_nor_set_addr_mode_nbytes(struct spi_nor * nor)420 static int cypress_nor_set_addr_mode_nbytes(struct spi_nor *nor)
421 {
422 struct spi_mem_op op;
423 u8 addr_mode;
424 int ret;
425
426 /*
427 * Read SR1 by RDSR1 and RDAR(3- AND 4-byte addr). Use write enable
428 * that sets bit-1 in SR1.
429 */
430 ret = spi_nor_write_enable(nor);
431 if (ret)
432 return ret;
433 ret = cypress_nor_determine_addr_mode_by_sr1(nor, &addr_mode);
434 if (ret) {
435 ret = spi_nor_set_4byte_addr_mode(nor, true);
436 if (ret)
437 return ret;
438 return spi_nor_write_disable(nor);
439 }
440 ret = spi_nor_write_disable(nor);
441 if (ret)
442 return ret;
443
444 /*
445 * Query CFR2V and make sure no contradiction between determined address
446 * mode and CFR2V[7].
447 */
448 op = (struct spi_mem_op)
449 CYPRESS_NOR_RD_ANY_REG_OP(addr_mode, SPINOR_REG_CYPRESS_CFR2V,
450 0, nor->bouncebuf);
451 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
452 if (ret)
453 return ret;
454
455 if (nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR2_ADRBYT) {
456 if (addr_mode != 4)
457 return spi_nor_set_4byte_addr_mode(nor, true);
458 } else {
459 if (addr_mode != 3)
460 return spi_nor_set_4byte_addr_mode(nor, true);
461 }
462
463 nor->params->addr_nbytes = addr_mode;
464 nor->params->addr_mode_nbytes = addr_mode;
465
466 return 0;
467 }
468
469 /**
470 * cypress_nor_get_page_size() - Get flash page size configuration.
471 * @nor: pointer to a 'struct spi_nor'
472 *
473 * The BFPT table advertises a 512B or 256B page size depending on part but the
474 * page size is actually configurable (with the default being 256B). Read from
475 * CFR3V[4] and set the correct size.
476 *
477 * Return: 0 on success, -errno otherwise.
478 */
cypress_nor_get_page_size(struct spi_nor * nor)479 static int cypress_nor_get_page_size(struct spi_nor *nor)
480 {
481 struct spi_mem_op op =
482 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes,
483 0, 0, nor->bouncebuf);
484 struct spi_nor_flash_parameter *params = nor->params;
485 int ret;
486 u8 i;
487
488 /*
489 * Use the minimum common page size configuration. Programming 256-byte
490 * under 512-byte page size configuration is safe.
491 */
492 params->page_size = 256;
493 for (i = 0; i < params->n_dice; i++) {
494 op.addr.val = params->vreg_offset[i] + SPINOR_REG_CYPRESS_CFR3;
495
496 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
497 if (ret)
498 return ret;
499
500 if (!(nor->bouncebuf[0] & SPINOR_REG_CYPRESS_CFR3_PGSZ))
501 return 0;
502 }
503
504 params->page_size = 512;
505
506 return 0;
507 }
508
cypress_nor_ecc_init(struct spi_nor * nor)509 static void cypress_nor_ecc_init(struct spi_nor *nor)
510 {
511 /*
512 * Programming is supported only in 16-byte ECC data unit granularity.
513 * Byte-programming, bit-walking, or multiple program operations to the
514 * same ECC data unit without an erase are not allowed.
515 */
516 nor->params->writesize = 16;
517 nor->flags |= SNOR_F_ECC;
518 }
519
520 static int
s25fs256t_post_bfpt_fixup(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt)521 s25fs256t_post_bfpt_fixup(struct spi_nor *nor,
522 const struct sfdp_parameter_header *bfpt_header,
523 const struct sfdp_bfpt *bfpt)
524 {
525 struct spi_mem_op op;
526 int ret;
527
528 ret = cypress_nor_set_addr_mode_nbytes(nor);
529 if (ret)
530 return ret;
531
532 /* Read Architecture Configuration Register (ARCFN) */
533 op = (struct spi_mem_op)
534 CYPRESS_NOR_RD_ANY_REG_OP(nor->params->addr_mode_nbytes,
535 SPINOR_REG_CYPRESS_ARCFN, 1,
536 nor->bouncebuf);
537 ret = spi_nor_read_any_reg(nor, &op, nor->reg_proto);
538 if (ret)
539 return ret;
540
541 /* ARCFN value must be 0 if uniform sector is selected */
542 if (nor->bouncebuf[0])
543 return -ENODEV;
544
545 return 0;
546 }
547
s25fs256t_post_sfdp_fixup(struct spi_nor * nor)548 static int s25fs256t_post_sfdp_fixup(struct spi_nor *nor)
549 {
550 struct spi_nor_flash_parameter *params = nor->params;
551
552 /*
553 * S25FS256T does not define the SCCR map, but we would like to use the
554 * same code base for both single and multi chip package devices, thus
555 * set the vreg_offset and n_dice to be able to do so.
556 */
557 params->vreg_offset = devm_kmalloc(nor->dev, sizeof(u32), GFP_KERNEL);
558 if (!params->vreg_offset)
559 return -ENOMEM;
560
561 params->vreg_offset[0] = SPINOR_REG_CYPRESS_VREG;
562 params->n_dice = 1;
563
564 /* PP_1_1_4_4B is supported but missing in 4BAIT. */
565 params->hwcaps.mask |= SNOR_HWCAPS_PP_1_1_4;
566 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_1_1_4],
567 SPINOR_OP_PP_1_1_4_4B,
568 SNOR_PROTO_1_1_4);
569
570 return cypress_nor_get_page_size(nor);
571 }
572
s25fs256t_late_init(struct spi_nor * nor)573 static int s25fs256t_late_init(struct spi_nor *nor)
574 {
575 cypress_nor_ecc_init(nor);
576
577 return 0;
578 }
579
580 static struct spi_nor_fixups s25fs256t_fixups = {
581 .post_bfpt = s25fs256t_post_bfpt_fixup,
582 .post_sfdp = s25fs256t_post_sfdp_fixup,
583 .late_init = s25fs256t_late_init,
584 };
585
586 static int
s25hx_t_post_bfpt_fixup(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt)587 s25hx_t_post_bfpt_fixup(struct spi_nor *nor,
588 const struct sfdp_parameter_header *bfpt_header,
589 const struct sfdp_bfpt *bfpt)
590 {
591 int ret;
592
593 ret = cypress_nor_set_addr_mode_nbytes(nor);
594 if (ret)
595 return ret;
596
597 /* Replace Quad Enable with volatile version */
598 nor->params->quad_enable = cypress_nor_quad_enable_volatile;
599
600 return 0;
601 }
602
s25hx_t_post_sfdp_fixup(struct spi_nor * nor)603 static int s25hx_t_post_sfdp_fixup(struct spi_nor *nor)
604 {
605 struct spi_nor_flash_parameter *params = nor->params;
606 struct spi_nor_erase_type *erase_type = params->erase_map.erase_type;
607 unsigned int i;
608
609 if (!params->n_dice || !params->vreg_offset) {
610 dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n",
611 __func__);
612 return -EOPNOTSUPP;
613 }
614
615 /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */
616 if (params->size == SZ_256M)
617 params->n_dice = 2;
618
619 /*
620 * In some parts, 3byte erase opcodes are advertised by 4BAIT.
621 * Convert them to 4byte erase opcodes.
622 */
623 for (i = 0; i < SNOR_ERASE_TYPE_MAX; i++) {
624 switch (erase_type[i].opcode) {
625 case SPINOR_OP_SE:
626 erase_type[i].opcode = SPINOR_OP_SE_4B;
627 break;
628 case SPINOR_OP_BE_4K:
629 erase_type[i].opcode = SPINOR_OP_BE_4K_4B;
630 break;
631 default:
632 break;
633 }
634 }
635
636 return cypress_nor_get_page_size(nor);
637 }
638
s25hx_t_late_init(struct spi_nor * nor)639 static int s25hx_t_late_init(struct spi_nor *nor)
640 {
641 struct spi_nor_flash_parameter *params = nor->params;
642
643 /* Fast Read 4B requires mode cycles */
644 params->reads[SNOR_CMD_READ_FAST].num_mode_clocks = 8;
645 params->ready = cypress_nor_sr_ready_and_clear;
646 cypress_nor_ecc_init(nor);
647
648 return 0;
649 }
650
651 static struct spi_nor_fixups s25hx_t_fixups = {
652 .post_bfpt = s25hx_t_post_bfpt_fixup,
653 .post_sfdp = s25hx_t_post_sfdp_fixup,
654 .late_init = s25hx_t_late_init,
655 };
656
657 /**
658 * cypress_nor_set_octal_dtr() - Enable or disable octal DTR on Cypress flashes.
659 * @nor: pointer to a 'struct spi_nor'
660 * @enable: whether to enable or disable Octal DTR
661 *
662 * This also sets the memory access latency cycles to 24 to allow the flash to
663 * run at up to 200MHz.
664 *
665 * Return: 0 on success, -errno otherwise.
666 */
cypress_nor_set_octal_dtr(struct spi_nor * nor,bool enable)667 static int cypress_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
668 {
669 return enable ? cypress_nor_octal_dtr_en(nor) :
670 cypress_nor_octal_dtr_dis(nor);
671 }
672
s28hx_t_post_sfdp_fixup(struct spi_nor * nor)673 static int s28hx_t_post_sfdp_fixup(struct spi_nor *nor)
674 {
675 struct spi_nor_flash_parameter *params = nor->params;
676
677 if (!params->n_dice || !params->vreg_offset) {
678 dev_err(nor->dev, "%s failed. The volatile register offset could not be retrieved from SFDP.\n",
679 __func__);
680 return -EOPNOTSUPP;
681 }
682
683 /* The 2 Gb parts duplicate info and advertise 4 dice instead of 2. */
684 if (params->size == SZ_256M)
685 params->n_dice = 2;
686
687 /*
688 * On older versions of the flash the xSPI Profile 1.0 table has the
689 * 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE.
690 */
691 if (params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode == 0)
692 params->reads[SNOR_CMD_READ_8_8_8_DTR].opcode =
693 SPINOR_OP_CYPRESS_RD_FAST;
694
695 /* This flash is also missing the 4-byte Page Program opcode bit. */
696 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP],
697 SPINOR_OP_PP_4B, SNOR_PROTO_1_1_1);
698 /*
699 * Since xSPI Page Program opcode is backward compatible with
700 * Legacy SPI, use Legacy SPI opcode there as well.
701 */
702 spi_nor_set_pp_settings(¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR],
703 SPINOR_OP_PP_4B, SNOR_PROTO_8_8_8_DTR);
704
705 /*
706 * The xSPI Profile 1.0 table advertises the number of additional
707 * address bytes needed for Read Status Register command as 0 but the
708 * actual value for that is 4.
709 */
710 params->rdsr_addr_nbytes = 4;
711
712 return cypress_nor_get_page_size(nor);
713 }
714
s28hx_t_post_bfpt_fixup(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt)715 static int s28hx_t_post_bfpt_fixup(struct spi_nor *nor,
716 const struct sfdp_parameter_header *bfpt_header,
717 const struct sfdp_bfpt *bfpt)
718 {
719 return cypress_nor_set_addr_mode_nbytes(nor);
720 }
721
s28hx_t_late_init(struct spi_nor * nor)722 static int s28hx_t_late_init(struct spi_nor *nor)
723 {
724 struct spi_nor_flash_parameter *params = nor->params;
725
726 params->set_octal_dtr = cypress_nor_set_octal_dtr;
727 params->ready = cypress_nor_sr_ready_and_clear;
728 cypress_nor_ecc_init(nor);
729
730 return 0;
731 }
732
733 static const struct spi_nor_fixups s28hx_t_fixups = {
734 .post_sfdp = s28hx_t_post_sfdp_fixup,
735 .post_bfpt = s28hx_t_post_bfpt_fixup,
736 .late_init = s28hx_t_late_init,
737 };
738
739 static int
s25fs_s_nor_post_bfpt_fixups(struct spi_nor * nor,const struct sfdp_parameter_header * bfpt_header,const struct sfdp_bfpt * bfpt)740 s25fs_s_nor_post_bfpt_fixups(struct spi_nor *nor,
741 const struct sfdp_parameter_header *bfpt_header,
742 const struct sfdp_bfpt *bfpt)
743 {
744 /*
745 * The S25FS-S chip family reports 512-byte pages in BFPT but
746 * in reality the write buffer still wraps at the safe default
747 * of 256 bytes. Overwrite the page size advertised by BFPT
748 * to get the writes working.
749 */
750 nor->params->page_size = 256;
751
752 return 0;
753 }
754
755 static const struct spi_nor_fixups s25fs_s_nor_fixups = {
756 .post_bfpt = s25fs_s_nor_post_bfpt_fixups,
757 };
758
759 static const struct flash_info spansion_nor_parts[] = {
760 /* Spansion/Cypress -- single (large) sector size only, at least
761 * for the chips listed here (without boot sectors).
762 */
763 { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64)
764 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
765 { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128)
766 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
767 { "s25fl128s0", INFO6(0x012018, 0x4d0080, 256 * 1024, 64)
768 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
769 MFR_FLAGS(USE_CLSR)
770 },
771 { "s25fl128s1", INFO6(0x012018, 0x4d0180, 64 * 1024, 256)
772 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
773 MFR_FLAGS(USE_CLSR)
774 },
775 { "s25fl256s0", INFO6(0x010219, 0x4d0080, 256 * 1024, 128)
776 NO_SFDP_FLAGS(SPI_NOR_SKIP_SFDP | SPI_NOR_DUAL_READ |
777 SPI_NOR_QUAD_READ)
778 MFR_FLAGS(USE_CLSR)
779 },
780 { "s25fl256s1", INFO6(0x010219, 0x4d0180, 64 * 1024, 512)
781 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
782 MFR_FLAGS(USE_CLSR)
783 },
784 { "s25fl512s", INFO6(0x010220, 0x4d0080, 256 * 1024, 256)
785 FLAGS(SPI_NOR_HAS_LOCK)
786 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
787 MFR_FLAGS(USE_CLSR)
788 },
789 { "s25fs128s1", INFO6(0x012018, 0x4d0181, 64 * 1024, 256)
790 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
791 MFR_FLAGS(USE_CLSR)
792 .fixups = &s25fs_s_nor_fixups, },
793 { "s25fs256s0", INFO6(0x010219, 0x4d0081, 256 * 1024, 128)
794 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
795 MFR_FLAGS(USE_CLSR)
796 },
797 { "s25fs256s1", INFO6(0x010219, 0x4d0181, 64 * 1024, 512)
798 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
799 MFR_FLAGS(USE_CLSR)
800 },
801 { "s25fs512s", INFO6(0x010220, 0x4d0081, 256 * 1024, 256)
802 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
803 MFR_FLAGS(USE_CLSR)
804 .fixups = &s25fs_s_nor_fixups, },
805 { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64) },
806 { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256) },
807 { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64)
808 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
809 MFR_FLAGS(USE_CLSR)
810 },
811 { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256)
812 NO_SFDP_FLAGS(SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
813 MFR_FLAGS(USE_CLSR)
814 },
815 { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8) },
816 { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16) },
817 { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32) },
818 { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64) },
819 { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128) },
820 { "s25fl004k", INFO(0xef4013, 0, 64 * 1024, 8)
821 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
822 SPI_NOR_QUAD_READ) },
823 { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16)
824 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
825 SPI_NOR_QUAD_READ) },
826 { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32)
827 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
828 SPI_NOR_QUAD_READ) },
829 { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128)
830 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
831 SPI_NOR_QUAD_READ) },
832 { "s25fl116k", INFO(0x014015, 0, 64 * 1024, 32)
833 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ |
834 SPI_NOR_QUAD_READ) },
835 { "s25fl132k", INFO(0x014016, 0, 64 * 1024, 64)
836 NO_SFDP_FLAGS(SECT_4K) },
837 { "s25fl164k", INFO(0x014017, 0, 64 * 1024, 128)
838 NO_SFDP_FLAGS(SECT_4K) },
839 { "s25fl204k", INFO(0x014013, 0, 64 * 1024, 8)
840 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
841 { "s25fl208k", INFO(0x014014, 0, 64 * 1024, 16)
842 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ) },
843 { "s25fl064l", INFO(0x016017, 0, 64 * 1024, 128)
844 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
845 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
846 { "s25fl128l", INFO(0x016018, 0, 64 * 1024, 256)
847 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
848 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
849 { "s25fl256l", INFO(0x016019, 0, 64 * 1024, 512)
850 NO_SFDP_FLAGS(SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ)
851 FIXUP_FLAGS(SPI_NOR_4B_OPCODES) },
852 { "s25fs256t", INFO6(0x342b19, 0x0f0890, 0, 0)
853 PARSE_SFDP
854 MFR_FLAGS(USE_CLPEF)
855 .fixups = &s25fs256t_fixups },
856 { "s25hl512t", INFO6(0x342a1a, 0x0f0390, 0, 0)
857 PARSE_SFDP
858 MFR_FLAGS(USE_CLPEF)
859 .fixups = &s25hx_t_fixups },
860 { "s25hl01gt", INFO6(0x342a1b, 0x0f0390, 0, 0)
861 PARSE_SFDP
862 MFR_FLAGS(USE_CLPEF)
863 .fixups = &s25hx_t_fixups },
864 { "s25hl02gt", INFO6(0x342a1c, 0x0f0090, 0, 0)
865 PARSE_SFDP
866 MFR_FLAGS(USE_CLPEF)
867 FLAGS(NO_CHIP_ERASE)
868 .fixups = &s25hx_t_fixups },
869 { "s25hs512t", INFO6(0x342b1a, 0x0f0390, 0, 0)
870 PARSE_SFDP
871 MFR_FLAGS(USE_CLPEF)
872 .fixups = &s25hx_t_fixups },
873 { "s25hs01gt", INFO6(0x342b1b, 0x0f0390, 0, 0)
874 PARSE_SFDP
875 MFR_FLAGS(USE_CLPEF)
876 .fixups = &s25hx_t_fixups },
877 { "s25hs02gt", INFO6(0x342b1c, 0x0f0090, 0, 0)
878 PARSE_SFDP
879 MFR_FLAGS(USE_CLPEF)
880 FLAGS(NO_CHIP_ERASE)
881 .fixups = &s25hx_t_fixups },
882 { "cy15x104q", INFO6(0x042cc2, 0x7f7f7f, 512 * 1024, 1)
883 FLAGS(SPI_NOR_NO_ERASE) },
884 { "s28hl512t", INFO(0x345a1a, 0, 0, 0)
885 PARSE_SFDP
886 MFR_FLAGS(USE_CLPEF)
887 .fixups = &s28hx_t_fixups,
888 },
889 { "s28hl01gt", INFO(0x345a1b, 0, 0, 0)
890 PARSE_SFDP
891 MFR_FLAGS(USE_CLPEF)
892 .fixups = &s28hx_t_fixups,
893 },
894 { "s28hs512t", INFO(0x345b1a, 0, 0, 0)
895 PARSE_SFDP
896 MFR_FLAGS(USE_CLPEF)
897 .fixups = &s28hx_t_fixups,
898 },
899 { "s28hs01gt", INFO(0x345b1b, 0, 0, 0)
900 PARSE_SFDP
901 MFR_FLAGS(USE_CLPEF)
902 .fixups = &s28hx_t_fixups,
903 },
904 { "s28hs02gt", INFO(0x345b1c, 0, 0, 0)
905 PARSE_SFDP
906 MFR_FLAGS(USE_CLPEF)
907 .fixups = &s28hx_t_fixups,
908 },
909 };
910
911 /**
912 * spansion_nor_sr_ready_and_clear() - Query the Status Register to see if the
913 * flash is ready for new commands and clear it if there are any errors.
914 * @nor: pointer to 'struct spi_nor'.
915 *
916 * Return: 1 if ready, 0 if not ready, -errno on errors.
917 */
spansion_nor_sr_ready_and_clear(struct spi_nor * nor)918 static int spansion_nor_sr_ready_and_clear(struct spi_nor *nor)
919 {
920 int ret;
921
922 ret = spi_nor_read_sr(nor, nor->bouncebuf);
923 if (ret)
924 return ret;
925
926 if (nor->bouncebuf[0] & (SR_E_ERR | SR_P_ERR)) {
927 if (nor->bouncebuf[0] & SR_E_ERR)
928 dev_err(nor->dev, "Erase Error occurred\n");
929 else
930 dev_err(nor->dev, "Programming Error occurred\n");
931
932 spansion_nor_clear_sr(nor);
933
934 /*
935 * WEL bit remains set to one when an erase or page program
936 * error occurs. Issue a Write Disable command to protect
937 * against inadvertent writes that can possibly corrupt the
938 * contents of the memory.
939 */
940 ret = spi_nor_write_disable(nor);
941 if (ret)
942 return ret;
943
944 return -EIO;
945 }
946
947 return !(nor->bouncebuf[0] & SR_WIP);
948 }
949
spansion_nor_late_init(struct spi_nor * nor)950 static int spansion_nor_late_init(struct spi_nor *nor)
951 {
952 struct spi_nor_flash_parameter *params = nor->params;
953 struct spansion_nor_params *priv_params;
954 u8 mfr_flags = nor->info->mfr_flags;
955
956 if (params->size > SZ_16M) {
957 nor->flags |= SNOR_F_4B_OPCODES;
958 /* No small sector erase for 4-byte command set */
959 nor->erase_opcode = SPINOR_OP_SE;
960 nor->mtd.erasesize = nor->info->sector_size;
961 }
962
963 if (mfr_flags & (USE_CLSR | USE_CLPEF)) {
964 priv_params = devm_kmalloc(nor->dev, sizeof(*priv_params),
965 GFP_KERNEL);
966 if (!priv_params)
967 return -ENOMEM;
968
969 if (mfr_flags & USE_CLSR)
970 priv_params->clsr = SPINOR_OP_CLSR;
971 else if (mfr_flags & USE_CLPEF)
972 priv_params->clsr = SPINOR_OP_CLPEF;
973
974 params->priv = priv_params;
975 params->ready = spansion_nor_sr_ready_and_clear;
976 }
977
978 return 0;
979 }
980
981 static const struct spi_nor_fixups spansion_nor_fixups = {
982 .late_init = spansion_nor_late_init,
983 };
984
985 const struct spi_nor_manufacturer spi_nor_spansion = {
986 .name = "spansion",
987 .parts = spansion_nor_parts,
988 .nparts = ARRAY_SIZE(spansion_nor_parts),
989 .fixups = &spansion_nor_fixups,
990 };
991