1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright(c) 2022 Mediatek Inc. All rights reserved.
4 //
5 // Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 // Tinghan Shen <tinghan.shen@mediatek.com>
7
8 /*
9 * Hardware interface for audio DSP on mt8186
10 */
11
12 #include <linux/delay.h>
13 #include <linux/firmware.h>
14 #include <linux/io.h>
15 #include <linux/of_address.h>
16 #include <linux/of_irq.h>
17 #include <linux/of_platform.h>
18 #include <linux/of_reserved_mem.h>
19 #include <linux/module.h>
20
21 #include <sound/sof.h>
22 #include <sound/sof/xtensa.h>
23 #include "../../ops.h"
24 #include "../../sof-of-dev.h"
25 #include "../../sof-audio.h"
26 #include "../adsp_helper.h"
27 #include "../mtk-adsp-common.h"
28 #include "mt8186.h"
29 #include "mt8186-clk.h"
30
mt8186_get_mailbox_offset(struct snd_sof_dev * sdev)31 static int mt8186_get_mailbox_offset(struct snd_sof_dev *sdev)
32 {
33 return MBOX_OFFSET;
34 }
35
mt8186_get_window_offset(struct snd_sof_dev * sdev,u32 id)36 static int mt8186_get_window_offset(struct snd_sof_dev *sdev, u32 id)
37 {
38 return MBOX_OFFSET;
39 }
40
mt8186_send_msg(struct snd_sof_dev * sdev,struct snd_sof_ipc_msg * msg)41 static int mt8186_send_msg(struct snd_sof_dev *sdev,
42 struct snd_sof_ipc_msg *msg)
43 {
44 struct adsp_priv *priv = sdev->pdata->hw_pdata;
45
46 sof_mailbox_write(sdev, sdev->host_box.offset, msg->msg_data,
47 msg->msg_size);
48
49 return mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_REQ, MTK_ADSP_IPC_OP_REQ);
50 }
51
mt8186_dsp_handle_reply(struct mtk_adsp_ipc * ipc)52 static void mt8186_dsp_handle_reply(struct mtk_adsp_ipc *ipc)
53 {
54 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
55 unsigned long flags;
56
57 spin_lock_irqsave(&priv->sdev->ipc_lock, flags);
58 snd_sof_ipc_process_reply(priv->sdev, 0);
59 spin_unlock_irqrestore(&priv->sdev->ipc_lock, flags);
60 }
61
mt8186_dsp_handle_request(struct mtk_adsp_ipc * ipc)62 static void mt8186_dsp_handle_request(struct mtk_adsp_ipc *ipc)
63 {
64 struct adsp_priv *priv = mtk_adsp_ipc_get_data(ipc);
65 u32 p; /* panic code */
66 int ret;
67
68 /* Read the message from the debug box. */
69 sof_mailbox_read(priv->sdev, priv->sdev->debug_box.offset + 4,
70 &p, sizeof(p));
71
72 /* Check to see if the message is a panic code 0x0dead*** */
73 if ((p & SOF_IPC_PANIC_MAGIC_MASK) == SOF_IPC_PANIC_MAGIC) {
74 snd_sof_dsp_panic(priv->sdev, p, true);
75 } else {
76 snd_sof_ipc_msgs_rx(priv->sdev);
77
78 /* tell DSP cmd is done */
79 ret = mtk_adsp_ipc_send(priv->dsp_ipc, MTK_ADSP_IPC_RSP, MTK_ADSP_IPC_OP_RSP);
80 if (ret)
81 dev_err(priv->dev, "request send ipc failed");
82 }
83 }
84
85 static struct mtk_adsp_ipc_ops dsp_ops = {
86 .handle_reply = mt8186_dsp_handle_reply,
87 .handle_request = mt8186_dsp_handle_request,
88 };
89
platform_parse_resource(struct platform_device * pdev,void * data)90 static int platform_parse_resource(struct platform_device *pdev, void *data)
91 {
92 struct resource *mmio;
93 struct resource res;
94 struct device_node *mem_region;
95 struct device *dev = &pdev->dev;
96 struct mtk_adsp_chip_info *adsp = data;
97 int ret;
98
99 mem_region = of_parse_phandle(dev->of_node, "memory-region", 0);
100 if (!mem_region) {
101 dev_err(dev, "no dma memory-region phandle\n");
102 return -ENODEV;
103 }
104
105 ret = of_address_to_resource(mem_region, 0, &res);
106 of_node_put(mem_region);
107 if (ret) {
108 dev_err(dev, "of_address_to_resource dma failed\n");
109 return ret;
110 }
111
112 dev_dbg(dev, "DMA %pR\n", &res);
113
114 adsp->pa_shared_dram = (phys_addr_t)res.start;
115 adsp->shared_size = resource_size(&res);
116 if (adsp->pa_shared_dram & DRAM_REMAP_MASK) {
117 dev_err(dev, "adsp shared dma memory(%#x) is not 4K-aligned\n",
118 (u32)adsp->pa_shared_dram);
119 return -EINVAL;
120 }
121
122 ret = of_reserved_mem_device_init(dev);
123 if (ret) {
124 dev_err(dev, "of_reserved_mem_device_init failed\n");
125 return ret;
126 }
127
128 mem_region = of_parse_phandle(dev->of_node, "memory-region", 1);
129 if (!mem_region) {
130 dev_err(dev, "no memory-region sysmem phandle\n");
131 return -ENODEV;
132 }
133
134 ret = of_address_to_resource(mem_region, 0, &res);
135 of_node_put(mem_region);
136 if (ret) {
137 dev_err(dev, "of_address_to_resource sysmem failed\n");
138 return ret;
139 }
140
141 adsp->pa_dram = (phys_addr_t)res.start;
142 if (adsp->pa_dram & DRAM_REMAP_MASK) {
143 dev_err(dev, "adsp memory(%#x) is not 4K-aligned\n",
144 (u32)adsp->pa_dram);
145 return -EINVAL;
146 }
147
148 adsp->dramsize = resource_size(&res);
149 if (adsp->dramsize < TOTAL_SIZE_SHARED_DRAM_FROM_TAIL) {
150 dev_err(dev, "adsp memory(%#x) is not enough for share\n",
151 adsp->dramsize);
152 return -EINVAL;
153 }
154
155 dev_dbg(dev, "dram pbase=%pa size=%#x\n", &adsp->pa_dram, adsp->dramsize);
156
157 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
158 if (!mmio) {
159 dev_err(dev, "no ADSP-CFG register resource\n");
160 return -ENXIO;
161 }
162
163 adsp->va_cfgreg = devm_ioremap_resource(dev, mmio);
164 if (IS_ERR(adsp->va_cfgreg))
165 return PTR_ERR(adsp->va_cfgreg);
166
167 adsp->pa_cfgreg = (phys_addr_t)mmio->start;
168 adsp->cfgregsize = resource_size(mmio);
169
170 dev_dbg(dev, "cfgreg pbase=%pa size=%#x\n", &adsp->pa_cfgreg, adsp->cfgregsize);
171
172 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sram");
173 if (!mmio) {
174 dev_err(dev, "no SRAM resource\n");
175 return -ENXIO;
176 }
177
178 adsp->pa_sram = (phys_addr_t)mmio->start;
179 adsp->sramsize = resource_size(mmio);
180
181 dev_dbg(dev, "sram pbase=%pa size=%#x\n", &adsp->pa_sram, adsp->sramsize);
182
183 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sec");
184 if (!mmio) {
185 dev_err(dev, "no SEC register resource\n");
186 return -ENXIO;
187 }
188
189 adsp->va_secreg = devm_ioremap_resource(dev, mmio);
190 if (IS_ERR(adsp->va_secreg))
191 return PTR_ERR(adsp->va_secreg);
192
193 adsp->pa_secreg = (phys_addr_t)mmio->start;
194 adsp->secregsize = resource_size(mmio);
195
196 dev_dbg(dev, "secreg pbase=%pa size=%#x\n", &adsp->pa_secreg, adsp->secregsize);
197
198 mmio = platform_get_resource_byname(pdev, IORESOURCE_MEM, "bus");
199 if (!mmio) {
200 dev_err(dev, "no BUS register resource\n");
201 return -ENXIO;
202 }
203
204 adsp->va_busreg = devm_ioremap_resource(dev, mmio);
205 if (IS_ERR(adsp->va_busreg))
206 return PTR_ERR(adsp->va_busreg);
207
208 adsp->pa_busreg = (phys_addr_t)mmio->start;
209 adsp->busregsize = resource_size(mmio);
210
211 dev_dbg(dev, "busreg pbase=%pa size=%#x\n", &adsp->pa_busreg, adsp->busregsize);
212
213 return 0;
214 }
215
adsp_sram_power_on(struct snd_sof_dev * sdev)216 static void adsp_sram_power_on(struct snd_sof_dev *sdev)
217 {
218 snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
219 DSP_SRAM_POOL_PD_MASK, 0);
220 }
221
adsp_sram_power_off(struct snd_sof_dev * sdev)222 static void adsp_sram_power_off(struct snd_sof_dev *sdev)
223 {
224 snd_sof_dsp_update_bits(sdev, DSP_BUSREG_BAR, ADSP_SRAM_POOL_CON,
225 DSP_SRAM_POOL_PD_MASK, DSP_SRAM_POOL_PD_MASK);
226 }
227
228 /* Init the basic DSP DRAM address */
adsp_memory_remap_init(struct snd_sof_dev * sdev,struct mtk_adsp_chip_info * adsp)229 static int adsp_memory_remap_init(struct snd_sof_dev *sdev, struct mtk_adsp_chip_info *adsp)
230 {
231 u32 offset;
232
233 offset = adsp->pa_dram - DRAM_PHYS_BASE_FROM_DSP_VIEW;
234 adsp->dram_offset = offset;
235 offset >>= DRAM_REMAP_SHIFT;
236
237 dev_dbg(sdev->dev, "adsp->pa_dram %pa, offset %#x\n", &adsp->pa_dram, offset);
238
239 snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR, offset);
240 snd_sof_dsp_write(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR, offset);
241
242 if (offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_EMI_MAP_ADDR) ||
243 offset != snd_sof_dsp_read(sdev, DSP_BUSREG_BAR, DSP_C0_DMAEMI_MAP_ADDR)) {
244 dev_err(sdev->dev, "emi remap fail\n");
245 return -EIO;
246 }
247
248 return 0;
249 }
250
adsp_shared_base_ioremap(struct platform_device * pdev,void * data)251 static int adsp_shared_base_ioremap(struct platform_device *pdev, void *data)
252 {
253 struct device *dev = &pdev->dev;
254 struct mtk_adsp_chip_info *adsp = data;
255
256 /* remap shared-dram base to be non-cachable */
257 adsp->shared_dram = devm_ioremap(dev, adsp->pa_shared_dram,
258 adsp->shared_size);
259 if (!adsp->shared_dram) {
260 dev_err(dev, "failed to ioremap base %pa size %#x\n",
261 adsp->shared_dram, adsp->shared_size);
262 return -ENOMEM;
263 }
264
265 dev_dbg(dev, "shared-dram vbase=%p, phy addr :%pa, size=%#x\n",
266 adsp->shared_dram, &adsp->pa_shared_dram, adsp->shared_size);
267
268 return 0;
269 }
270
mt8186_run(struct snd_sof_dev * sdev)271 static int mt8186_run(struct snd_sof_dev *sdev)
272 {
273 u32 adsp_bootup_addr;
274
275 adsp_bootup_addr = SRAM_PHYS_BASE_FROM_DSP_VIEW;
276 dev_dbg(sdev->dev, "HIFIxDSP boot from base : 0x%08X\n", adsp_bootup_addr);
277 mt8186_sof_hifixdsp_boot_sequence(sdev, adsp_bootup_addr);
278
279 return 0;
280 }
281
mt8186_dsp_probe(struct snd_sof_dev * sdev)282 static int mt8186_dsp_probe(struct snd_sof_dev *sdev)
283 {
284 struct platform_device *pdev = container_of(sdev->dev, struct platform_device, dev);
285 struct adsp_priv *priv;
286 int ret;
287
288 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
289 if (!priv)
290 return -ENOMEM;
291
292 sdev->pdata->hw_pdata = priv;
293 priv->dev = sdev->dev;
294 priv->sdev = sdev;
295
296 priv->adsp = devm_kzalloc(&pdev->dev, sizeof(struct mtk_adsp_chip_info), GFP_KERNEL);
297 if (!priv->adsp)
298 return -ENOMEM;
299
300 ret = platform_parse_resource(pdev, priv->adsp);
301 if (ret)
302 return ret;
303
304 sdev->bar[SOF_FW_BLK_TYPE_IRAM] = devm_ioremap(sdev->dev,
305 priv->adsp->pa_sram,
306 priv->adsp->sramsize);
307 if (!sdev->bar[SOF_FW_BLK_TYPE_IRAM]) {
308 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
309 &priv->adsp->pa_sram, priv->adsp->sramsize);
310 return -ENOMEM;
311 }
312
313 priv->adsp->va_sram = sdev->bar[SOF_FW_BLK_TYPE_IRAM];
314
315 sdev->bar[SOF_FW_BLK_TYPE_SRAM] = devm_ioremap(sdev->dev,
316 priv->adsp->pa_dram,
317 priv->adsp->dramsize);
318
319 if (!sdev->bar[SOF_FW_BLK_TYPE_SRAM]) {
320 dev_err(sdev->dev, "failed to ioremap base %pa size %#x\n",
321 &priv->adsp->pa_dram, priv->adsp->dramsize);
322 return -ENOMEM;
323 }
324
325 priv->adsp->va_dram = sdev->bar[SOF_FW_BLK_TYPE_SRAM];
326
327 ret = adsp_shared_base_ioremap(pdev, priv->adsp);
328 if (ret) {
329 dev_err(sdev->dev, "adsp_shared_base_ioremap fail!\n");
330 return ret;
331 }
332
333 sdev->bar[DSP_REG_BAR] = priv->adsp->va_cfgreg;
334 sdev->bar[DSP_SECREG_BAR] = priv->adsp->va_secreg;
335 sdev->bar[DSP_BUSREG_BAR] = priv->adsp->va_busreg;
336
337 sdev->mmio_bar = SOF_FW_BLK_TYPE_SRAM;
338 sdev->mailbox_bar = SOF_FW_BLK_TYPE_SRAM;
339
340 /* set default mailbox offset for FW ready message */
341 sdev->dsp_box.offset = mt8186_get_mailbox_offset(sdev);
342
343 ret = adsp_memory_remap_init(sdev, priv->adsp);
344 if (ret) {
345 dev_err(sdev->dev, "adsp_memory_remap_init fail!\n");
346 return ret;
347 }
348
349 /* enable adsp clock before touching registers */
350 ret = mt8186_adsp_init_clock(sdev);
351 if (ret) {
352 dev_err(sdev->dev, "mt8186_adsp_init_clock failed\n");
353 return ret;
354 }
355
356 ret = mt8186_adsp_clock_on(sdev);
357 if (ret) {
358 dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
359 return ret;
360 }
361
362 adsp_sram_power_on(sdev);
363
364 priv->ipc_dev = platform_device_register_data(&pdev->dev, "mtk-adsp-ipc",
365 PLATFORM_DEVID_NONE,
366 pdev, sizeof(*pdev));
367 if (IS_ERR(priv->ipc_dev)) {
368 ret = PTR_ERR(priv->ipc_dev);
369 dev_err(sdev->dev, "failed to create mtk-adsp-ipc device\n");
370 goto err_adsp_off;
371 }
372
373 priv->dsp_ipc = dev_get_drvdata(&priv->ipc_dev->dev);
374 if (!priv->dsp_ipc) {
375 ret = -EPROBE_DEFER;
376 dev_err(sdev->dev, "failed to get drvdata\n");
377 goto exit_pdev_unregister;
378 }
379
380 mtk_adsp_ipc_set_data(priv->dsp_ipc, priv);
381 priv->dsp_ipc->ops = &dsp_ops;
382
383 return 0;
384
385 exit_pdev_unregister:
386 platform_device_unregister(priv->ipc_dev);
387 err_adsp_off:
388 adsp_sram_power_off(sdev);
389 mt8186_adsp_clock_off(sdev);
390
391 return ret;
392 }
393
mt8186_dsp_remove(struct snd_sof_dev * sdev)394 static int mt8186_dsp_remove(struct snd_sof_dev *sdev)
395 {
396 struct adsp_priv *priv = sdev->pdata->hw_pdata;
397
398 platform_device_unregister(priv->ipc_dev);
399 mt8186_sof_hifixdsp_shutdown(sdev);
400 adsp_sram_power_off(sdev);
401 mt8186_adsp_clock_off(sdev);
402
403 return 0;
404 }
405
mt8186_dsp_shutdown(struct snd_sof_dev * sdev)406 static int mt8186_dsp_shutdown(struct snd_sof_dev *sdev)
407 {
408 return snd_sof_suspend(sdev->dev);
409 }
410
mt8186_dsp_suspend(struct snd_sof_dev * sdev,u32 target_state)411 static int mt8186_dsp_suspend(struct snd_sof_dev *sdev, u32 target_state)
412 {
413 mt8186_sof_hifixdsp_shutdown(sdev);
414 adsp_sram_power_off(sdev);
415 mt8186_adsp_clock_off(sdev);
416
417 return 0;
418 }
419
mt8186_dsp_resume(struct snd_sof_dev * sdev)420 static int mt8186_dsp_resume(struct snd_sof_dev *sdev)
421 {
422 int ret;
423
424 ret = mt8186_adsp_clock_on(sdev);
425 if (ret) {
426 dev_err(sdev->dev, "mt8186_adsp_clock_on fail!\n");
427 return ret;
428 }
429
430 adsp_sram_power_on(sdev);
431
432 return ret;
433 }
434
435 /* on mt8186 there is 1 to 1 match between type and BAR idx */
mt8186_get_bar_index(struct snd_sof_dev * sdev,u32 type)436 static int mt8186_get_bar_index(struct snd_sof_dev *sdev, u32 type)
437 {
438 return type;
439 }
440
mt8186_pcm_hw_params(struct snd_sof_dev * sdev,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_sof_platform_stream_params * platform_params)441 static int mt8186_pcm_hw_params(struct snd_sof_dev *sdev,
442 struct snd_pcm_substream *substream,
443 struct snd_pcm_hw_params *params,
444 struct snd_sof_platform_stream_params *platform_params)
445 {
446 platform_params->cont_update_posn = 1;
447
448 return 0;
449 }
450
mt8186_pcm_pointer(struct snd_sof_dev * sdev,struct snd_pcm_substream * substream)451 static snd_pcm_uframes_t mt8186_pcm_pointer(struct snd_sof_dev *sdev,
452 struct snd_pcm_substream *substream)
453 {
454 int ret;
455 snd_pcm_uframes_t pos;
456 struct snd_sof_pcm *spcm;
457 struct sof_ipc_stream_posn posn;
458 struct snd_sof_pcm_stream *stream;
459 struct snd_soc_component *scomp = sdev->component;
460 struct snd_soc_pcm_runtime *rtd = asoc_substream_to_rtd(substream);
461
462 spcm = snd_sof_find_spcm_dai(scomp, rtd);
463 if (!spcm) {
464 dev_warn_ratelimited(sdev->dev, "warn: can't find PCM with DAI ID %d\n",
465 rtd->dai_link->id);
466 return 0;
467 }
468
469 stream = &spcm->stream[substream->stream];
470 ret = snd_sof_ipc_msg_data(sdev, stream, &posn, sizeof(posn));
471 if (ret < 0) {
472 dev_warn(sdev->dev, "failed to read stream position: %d\n", ret);
473 return 0;
474 }
475
476 memcpy(&stream->posn, &posn, sizeof(posn));
477 pos = spcm->stream[substream->stream].posn.host_posn;
478 pos = bytes_to_frames(substream->runtime, pos);
479
480 return pos;
481 }
482
mt8186_adsp_dump(struct snd_sof_dev * sdev,u32 flags)483 static void mt8186_adsp_dump(struct snd_sof_dev *sdev, u32 flags)
484 {
485 u32 dbg_pc, dbg_data, dbg_inst, dbg_ls0stat, dbg_status, faultinfo;
486
487 /* dump debug registers */
488 dbg_pc = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGPC);
489 dbg_data = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGDATA);
490 dbg_inst = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGINST);
491 dbg_ls0stat = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGLS0STAT);
492 dbg_status = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PDEBUGSTATUS);
493 faultinfo = snd_sof_dsp_read(sdev, DSP_REG_BAR, DSP_PFAULTINFO);
494
495 dev_info(sdev->dev, "adsp dump : pc %#x, data %#x, dbg_inst %#x,",
496 dbg_pc, dbg_data, dbg_inst);
497 dev_info(sdev->dev, "ls0stat %#x, status %#x, faultinfo %#x",
498 dbg_ls0stat, dbg_status, faultinfo);
499
500 mtk_adsp_dump(sdev, flags);
501 }
502
503 static struct snd_soc_dai_driver mt8186_dai[] = {
504 {
505 .name = "SOF_DL1",
506 .playback = {
507 .channels_min = 1,
508 .channels_max = 2,
509 },
510 },
511 {
512 .name = "SOF_DL2",
513 .playback = {
514 .channels_min = 1,
515 .channels_max = 2,
516 },
517 },
518 {
519 .name = "SOF_UL1",
520 .capture = {
521 .channels_min = 1,
522 .channels_max = 2,
523 },
524 },
525 {
526 .name = "SOF_UL2",
527 .capture = {
528 .channels_min = 1,
529 .channels_max = 2,
530 },
531 },
532 };
533
534 /* mt8186 ops */
535 static struct snd_sof_dsp_ops sof_mt8186_ops = {
536 /* probe and remove */
537 .probe = mt8186_dsp_probe,
538 .remove = mt8186_dsp_remove,
539 .shutdown = mt8186_dsp_shutdown,
540
541 /* DSP core boot */
542 .run = mt8186_run,
543
544 /* Block IO */
545 .block_read = sof_block_read,
546 .block_write = sof_block_write,
547
548 /* Mailbox IO */
549 .mailbox_read = sof_mailbox_read,
550 .mailbox_write = sof_mailbox_write,
551
552 /* Register IO */
553 .write = sof_io_write,
554 .read = sof_io_read,
555 .write64 = sof_io_write64,
556 .read64 = sof_io_read64,
557
558 /* ipc */
559 .send_msg = mt8186_send_msg,
560 .get_mailbox_offset = mt8186_get_mailbox_offset,
561 .get_window_offset = mt8186_get_window_offset,
562 .ipc_msg_data = sof_ipc_msg_data,
563 .set_stream_data_offset = sof_set_stream_data_offset,
564
565 /* misc */
566 .get_bar_index = mt8186_get_bar_index,
567
568 /* stream callbacks */
569 .pcm_open = sof_stream_pcm_open,
570 .pcm_hw_params = mt8186_pcm_hw_params,
571 .pcm_pointer = mt8186_pcm_pointer,
572 .pcm_close = sof_stream_pcm_close,
573
574 /* firmware loading */
575 .load_firmware = snd_sof_load_firmware_memcpy,
576
577 /* Firmware ops */
578 .dsp_arch_ops = &sof_xtensa_arch_ops,
579
580 /* DAI drivers */
581 .drv = mt8186_dai,
582 .num_drv = ARRAY_SIZE(mt8186_dai),
583
584 /* Debug information */
585 .dbg_dump = mt8186_adsp_dump,
586 .debugfs_add_region_item = snd_sof_debugfs_add_region_item_iomem,
587
588 /* PM */
589 .suspend = mt8186_dsp_suspend,
590 .resume = mt8186_dsp_resume,
591
592 /* ALSA HW info flags */
593 .hw_info = SNDRV_PCM_INFO_MMAP |
594 SNDRV_PCM_INFO_MMAP_VALID |
595 SNDRV_PCM_INFO_INTERLEAVED |
596 SNDRV_PCM_INFO_PAUSE |
597 SNDRV_PCM_INFO_NO_PERIOD_WAKEUP,
598 };
599
600 static struct snd_sof_of_mach sof_mt8186_machs[] = {
601 {
602 .compatible = "mediatek,mt8186",
603 .sof_tplg_filename = "sof-mt8186.tplg",
604 },
605 {}
606 };
607
608 static const struct sof_dev_desc sof_of_mt8186_desc = {
609 .of_machines = sof_mt8186_machs,
610 .ipc_supported_mask = BIT(SOF_IPC),
611 .ipc_default = SOF_IPC,
612 .default_fw_path = {
613 [SOF_IPC] = "mediatek/sof",
614 },
615 .default_tplg_path = {
616 [SOF_IPC] = "mediatek/sof-tplg",
617 },
618 .default_fw_filename = {
619 [SOF_IPC] = "sof-mt8186.ri",
620 },
621 .nocodec_tplg_filename = "sof-mt8186-nocodec.tplg",
622 .ops = &sof_mt8186_ops,
623 };
624
625 /*
626 * DL2, DL3, UL4, UL5 are registered as SOF FE, so creating the corresponding
627 * SOF BE to complete the pipeline.
628 */
629 static struct snd_soc_dai_driver mt8188_dai[] = {
630 {
631 .name = "SOF_DL2",
632 .playback = {
633 .channels_min = 1,
634 .channels_max = 2,
635 },
636 },
637 {
638 .name = "SOF_DL3",
639 .playback = {
640 .channels_min = 1,
641 .channels_max = 2,
642 },
643 },
644 {
645 .name = "SOF_UL4",
646 .capture = {
647 .channels_min = 1,
648 .channels_max = 2,
649 },
650 },
651 {
652 .name = "SOF_UL5",
653 .capture = {
654 .channels_min = 1,
655 .channels_max = 2,
656 },
657 },
658 };
659
660 /* mt8188 ops */
661 static struct snd_sof_dsp_ops sof_mt8188_ops;
662
sof_mt8188_ops_init(struct snd_sof_dev * sdev)663 static int sof_mt8188_ops_init(struct snd_sof_dev *sdev)
664 {
665 /* common defaults */
666 memcpy(&sof_mt8188_ops, &sof_mt8186_ops, sizeof(sof_mt8188_ops));
667
668 sof_mt8188_ops.drv = mt8188_dai;
669 sof_mt8188_ops.num_drv = ARRAY_SIZE(mt8188_dai);
670
671 return 0;
672 }
673
674 static struct snd_sof_of_mach sof_mt8188_machs[] = {
675 {
676 .compatible = "mediatek,mt8188",
677 .sof_tplg_filename = "sof-mt8188.tplg",
678 },
679 {}
680 };
681
682 static const struct sof_dev_desc sof_of_mt8188_desc = {
683 .of_machines = sof_mt8188_machs,
684 .ipc_supported_mask = BIT(SOF_IPC),
685 .ipc_default = SOF_IPC,
686 .default_fw_path = {
687 [SOF_IPC] = "mediatek/sof",
688 },
689 .default_tplg_path = {
690 [SOF_IPC] = "mediatek/sof-tplg",
691 },
692 .default_fw_filename = {
693 [SOF_IPC] = "sof-mt8188.ri",
694 },
695 .nocodec_tplg_filename = "sof-mt8188-nocodec.tplg",
696 .ops = &sof_mt8188_ops,
697 .ops_init = sof_mt8188_ops_init,
698 };
699
700 static const struct of_device_id sof_of_mt8186_ids[] = {
701 { .compatible = "mediatek,mt8186-dsp", .data = &sof_of_mt8186_desc},
702 { .compatible = "mediatek,mt8188-dsp", .data = &sof_of_mt8188_desc},
703 { }
704 };
705 MODULE_DEVICE_TABLE(of, sof_of_mt8186_ids);
706
707 /* DT driver definition */
708 static struct platform_driver snd_sof_of_mt8186_driver = {
709 .probe = sof_of_probe,
710 .remove = sof_of_remove,
711 .shutdown = sof_of_shutdown,
712 .driver = {
713 .name = "sof-audio-of-mt8186",
714 .pm = &sof_of_pm,
715 .of_match_table = sof_of_mt8186_ids,
716 },
717 };
718 module_platform_driver(snd_sof_of_mt8186_driver);
719
720 MODULE_IMPORT_NS(SND_SOC_SOF_XTENSA);
721 MODULE_IMPORT_NS(SND_SOC_SOF_MTK_COMMON);
722 MODULE_LICENSE("Dual BSD/GPL");
723