1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // Copyright(c) 2023 Intel Corporation. All rights reserved.
4
5 /*
6 * Hardware interface for audio DSP on LunarLake.
7 */
8
9 #include <linux/firmware.h>
10 #include <sound/hda_register.h>
11 #include <sound/sof/ipc4/header.h>
12 #include <trace/events/sof_intel.h>
13 #include "../ipc4-priv.h"
14 #include "../ops.h"
15 #include "hda.h"
16 #include "hda-ipc.h"
17 #include "../sof-audio.h"
18 #include "mtl.h"
19 #include "lnl.h"
20 #include <sound/hda-mlink.h>
21
22 /* LunarLake ops */
23 struct snd_sof_dsp_ops sof_lnl_ops;
24 EXPORT_SYMBOL_NS(sof_lnl_ops, SND_SOC_SOF_INTEL_HDA_COMMON);
25
26 static const struct snd_sof_debugfs_map lnl_dsp_debugfs[] = {
27 {"hda", HDA_DSP_HDA_BAR, 0, 0x4000, SOF_DEBUGFS_ACCESS_ALWAYS},
28 {"pp", HDA_DSP_PP_BAR, 0, 0x1000, SOF_DEBUGFS_ACCESS_ALWAYS},
29 {"dsp", HDA_DSP_BAR, 0, 0x10000, SOF_DEBUGFS_ACCESS_ALWAYS},
30 };
31
32 /* this helps allows the DSP to setup DMIC/SSP */
hdac_bus_offload_dmic_ssp(struct hdac_bus * bus)33 static int hdac_bus_offload_dmic_ssp(struct hdac_bus *bus)
34 {
35 int ret;
36
37 ret = hdac_bus_eml_enable_offload(bus, true, AZX_REG_ML_LEPTR_ID_INTEL_SSP, true);
38 if (ret < 0)
39 return ret;
40
41 ret = hdac_bus_eml_enable_offload(bus, true, AZX_REG_ML_LEPTR_ID_INTEL_DMIC, true);
42 if (ret < 0)
43 return ret;
44
45 return 0;
46 }
47
lnl_hda_dsp_probe(struct snd_sof_dev * sdev)48 static int lnl_hda_dsp_probe(struct snd_sof_dev *sdev)
49 {
50 int ret;
51
52 ret = hda_dsp_probe(sdev);
53 if (ret < 0)
54 return ret;
55
56 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev));
57 }
58
lnl_hda_dsp_resume(struct snd_sof_dev * sdev)59 static int lnl_hda_dsp_resume(struct snd_sof_dev *sdev)
60 {
61 int ret;
62
63 ret = hda_dsp_resume(sdev);
64 if (ret < 0)
65 return ret;
66
67 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev));
68 }
69
lnl_hda_dsp_runtime_resume(struct snd_sof_dev * sdev)70 static int lnl_hda_dsp_runtime_resume(struct snd_sof_dev *sdev)
71 {
72 int ret;
73
74 ret = hda_dsp_runtime_resume(sdev);
75 if (ret < 0)
76 return ret;
77
78 return hdac_bus_offload_dmic_ssp(sof_to_bus(sdev));
79 }
80
sof_lnl_ops_init(struct snd_sof_dev * sdev)81 int sof_lnl_ops_init(struct snd_sof_dev *sdev)
82 {
83 struct sof_ipc4_fw_data *ipc4_data;
84
85 /* common defaults */
86 memcpy(&sof_lnl_ops, &sof_hda_common_ops, sizeof(struct snd_sof_dsp_ops));
87
88 /* probe */
89 sof_lnl_ops.probe = lnl_hda_dsp_probe;
90
91 /* shutdown */
92 sof_lnl_ops.shutdown = hda_dsp_shutdown;
93
94 /* doorbell */
95 sof_lnl_ops.irq_thread = mtl_ipc_irq_thread;
96
97 /* ipc */
98 sof_lnl_ops.send_msg = mtl_ipc_send_msg;
99 sof_lnl_ops.get_mailbox_offset = mtl_dsp_ipc_get_mailbox_offset;
100 sof_lnl_ops.get_window_offset = mtl_dsp_ipc_get_window_offset;
101
102 /* debug */
103 sof_lnl_ops.debug_map = lnl_dsp_debugfs;
104 sof_lnl_ops.debug_map_count = ARRAY_SIZE(lnl_dsp_debugfs);
105 sof_lnl_ops.dbg_dump = mtl_dsp_dump;
106 sof_lnl_ops.ipc_dump = mtl_ipc_dump;
107
108 /* pre/post fw run */
109 sof_lnl_ops.pre_fw_run = mtl_dsp_pre_fw_run;
110 sof_lnl_ops.post_fw_run = mtl_dsp_post_fw_run;
111
112 /* parse platform specific extended manifest */
113 sof_lnl_ops.parse_platform_ext_manifest = NULL;
114
115 /* dsp core get/put */
116 /* TODO: add core_get and core_put */
117
118 /* PM */
119 sof_lnl_ops.resume = lnl_hda_dsp_resume;
120 sof_lnl_ops.runtime_resume = lnl_hda_dsp_runtime_resume;
121
122 sof_lnl_ops.get_stream_position = mtl_dsp_get_stream_hda_link_position;
123
124 sdev->private = devm_kzalloc(sdev->dev, sizeof(struct sof_ipc4_fw_data), GFP_KERNEL);
125 if (!sdev->private)
126 return -ENOMEM;
127
128 ipc4_data = sdev->private;
129 ipc4_data->manifest_fw_hdr_offset = SOF_MAN4_FW_HDR_OFFSET;
130
131 ipc4_data->mtrace_type = SOF_IPC4_MTRACE_INTEL_CAVS_2;
132
133 /* External library loading support */
134 ipc4_data->load_library = hda_dsp_ipc4_load_library;
135
136 /* set DAI ops */
137 hda_set_dai_drv_ops(sdev, &sof_lnl_ops);
138
139 sof_lnl_ops.set_power_state = hda_dsp_set_power_state_ipc4;
140
141 return 0;
142 };
143 EXPORT_SYMBOL_NS(sof_lnl_ops_init, SND_SOC_SOF_INTEL_HDA_COMMON);
144
145 /* Check if an SDW IRQ occurred */
lnl_dsp_check_sdw_irq(struct snd_sof_dev * sdev)146 static bool lnl_dsp_check_sdw_irq(struct snd_sof_dev *sdev)
147 {
148 struct hdac_bus *bus = sof_to_bus(sdev);
149
150 return hdac_bus_eml_check_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW);
151 }
152
lnl_enable_sdw_irq(struct snd_sof_dev * sdev,bool enable)153 static void lnl_enable_sdw_irq(struct snd_sof_dev *sdev, bool enable)
154 {
155 struct hdac_bus *bus = sof_to_bus(sdev);
156
157 hdac_bus_eml_enable_interrupt(bus, true, AZX_REG_ML_LEPTR_ID_SDW, enable);
158 }
159
lnl_dsp_disable_interrupts(struct snd_sof_dev * sdev)160 static int lnl_dsp_disable_interrupts(struct snd_sof_dev *sdev)
161 {
162 lnl_enable_sdw_irq(sdev, false);
163 mtl_disable_ipc_interrupts(sdev);
164 return mtl_enable_interrupts(sdev, false);
165 }
166
167 const struct sof_intel_dsp_desc lnl_chip_info = {
168 .cores_num = 5,
169 .init_core_mask = BIT(0),
170 .host_managed_cores_mask = BIT(0),
171 .ipc_req = MTL_DSP_REG_HFIPCXIDR,
172 .ipc_req_mask = MTL_DSP_REG_HFIPCXIDR_BUSY,
173 .ipc_ack = MTL_DSP_REG_HFIPCXIDA,
174 .ipc_ack_mask = MTL_DSP_REG_HFIPCXIDA_DONE,
175 .ipc_ctl = MTL_DSP_REG_HFIPCXCTL,
176 .rom_status_reg = LNL_DSP_REG_HFDSC,
177 .rom_init_timeout = 300,
178 .ssp_count = MTL_SSP_COUNT,
179 .d0i3_offset = MTL_HDA_VS_D0I3C,
180 .read_sdw_lcount = hda_sdw_check_lcount_ext,
181 .enable_sdw_irq = lnl_enable_sdw_irq,
182 .check_sdw_irq = lnl_dsp_check_sdw_irq,
183 .check_ipc_irq = mtl_dsp_check_ipc_irq,
184 .cl_init = mtl_dsp_cl_init,
185 .power_down_dsp = mtl_power_down_dsp,
186 .disable_interrupts = lnl_dsp_disable_interrupts,
187 .hw_ip_version = SOF_INTEL_ACE_2_0,
188 };
189 EXPORT_SYMBOL_NS(lnl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
190