1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2016-2017 Intel Corporation
4 */
5
6 #include <asm/io.h>
7 #include <asm/arch/fpga_manager.h>
8 #include <asm/arch/misc.h>
9 #include <asm/arch/reset_manager.h>
10 #include <asm/arch/system_manager.h>
11 #include <common.h>
12 #include <errno.h>
13 #include <fdtdec.h>
14 #include <wait_bit.h>
15
16 DECLARE_GLOBAL_DATA_PTR;
17
18 static const struct socfpga_reset_manager *reset_manager_base =
19 (void *)SOCFPGA_RSTMGR_ADDRESS;
20 static const struct socfpga_system_manager *sysmgr_regs =
21 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
22
23 struct bridge_cfg {
24 int compat_id;
25 u32 mask_noc;
26 u32 mask_rstmgr;
27 };
28
29 static const struct bridge_cfg bridge_cfg_tbl[] = {
30 {
31 COMPAT_ALTERA_SOCFPGA_H2F_BRG,
32 ALT_SYSMGR_NOC_H2F_SET_MSK,
33 ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
34 },
35 {
36 COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
37 ALT_SYSMGR_NOC_LWH2F_SET_MSK,
38 ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
39 },
40 {
41 COMPAT_ALTERA_SOCFPGA_F2H_BRG,
42 ALT_SYSMGR_NOC_F2H_SET_MSK,
43 ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
44 },
45 {
46 COMPAT_ALTERA_SOCFPGA_F2SDR0,
47 ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
48 ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
49 },
50 {
51 COMPAT_ALTERA_SOCFPGA_F2SDR1,
52 ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
53 ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
54 },
55 {
56 COMPAT_ALTERA_SOCFPGA_F2SDR2,
57 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
58 ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
59 },
60 };
61
62 /* Disable the watchdog (toggle reset to watchdog) */
socfpga_watchdog_disable(void)63 void socfpga_watchdog_disable(void)
64 {
65 /* assert reset for watchdog */
66 setbits_le32(&reset_manager_base->per1modrst,
67 ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
68 }
69
70 /* Release NOC ddr scheduler from reset */
socfpga_reset_deassert_noc_ddr_scheduler(void)71 void socfpga_reset_deassert_noc_ddr_scheduler(void)
72 {
73 clrbits_le32(&reset_manager_base->brgmodrst,
74 ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
75 }
76
get_bridge_init_val(const void * blob,int compat_id)77 static int get_bridge_init_val(const void *blob, int compat_id)
78 {
79 int node;
80
81 node = fdtdec_next_compatible(blob, 0, compat_id);
82 if (node < 0)
83 return 0;
84
85 return fdtdec_get_uint(blob, node, "init-val", 0);
86 }
87
88 /* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
socfpga_reset_deassert_bridges_handoff(void)89 int socfpga_reset_deassert_bridges_handoff(void)
90 {
91 u32 mask_noc = 0, mask_rstmgr = 0;
92 int i;
93
94 for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
95 if (get_bridge_init_val(gd->fdt_blob,
96 bridge_cfg_tbl[i].compat_id)) {
97 mask_noc |= bridge_cfg_tbl[i].mask_noc;
98 mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
99 }
100 }
101
102 /* clear idle request to all bridges */
103 setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
104
105 /* Release bridges from reset state per handoff value */
106 clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
107
108 /* Poll until all idleack to 0, timeout at 1000ms */
109 return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
110 false, 1000, false);
111 }
112
113 /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
socfpga_reset_deassert_osc1wd0(void)114 void socfpga_reset_deassert_osc1wd0(void)
115 {
116 clrbits_le32(&reset_manager_base->per1modrst,
117 ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
118 }
119
120 /*
121 * Assert or de-assert SoCFPGA reset manager reset.
122 */
socfpga_per_reset(u32 reset,int set)123 void socfpga_per_reset(u32 reset, int set)
124 {
125 const u32 *reg;
126 u32 rstmgr_bank = RSTMGR_BANK(reset);
127
128 switch (rstmgr_bank) {
129 case 0:
130 reg = &reset_manager_base->mpumodrst;
131 break;
132 case 1:
133 reg = &reset_manager_base->per0modrst;
134 break;
135 case 2:
136 reg = &reset_manager_base->per1modrst;
137 break;
138 case 3:
139 reg = &reset_manager_base->brgmodrst;
140 break;
141 case 4:
142 reg = &reset_manager_base->sysmodrst;
143 break;
144
145 default:
146 return;
147 }
148
149 if (set)
150 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
151 else
152 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
153 }
154
155 /*
156 * Assert reset on every peripheral but L4WD0.
157 * Watchdog must be kept intact to prevent glitches
158 * and/or hangs.
159 * For the Arria10, we disable all the peripherals except L4 watchdog0,
160 * L4 Timer 0, and ECC.
161 */
socfpga_per_reset_all(void)162 void socfpga_per_reset_all(void)
163 {
164 const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
165 (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
166 unsigned mask_ecc_ocp =
167 ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
168 ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
169 ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
170 ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
171 ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
172 ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
173 ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
174 ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
175
176 /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
177 writel(~l4wd0, &reset_manager_base->per1modrst);
178 setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
179
180 /* Finally disable the ECC_OCP */
181 setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
182 }
183
socfpga_bridges_reset(void)184 int socfpga_bridges_reset(void)
185 {
186 int ret;
187
188 /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
189 fpga2sdram) */
190 /* set idle request to all bridges */
191 writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
192 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
193 ALT_SYSMGR_NOC_F2H_SET_MSK |
194 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
195 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
196 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
197 &sysmgr_regs->noc_idlereq_set);
198
199 /* Enable the NOC timeout */
200 writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
201
202 /* Poll until all idleack to 1 */
203 ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
204 ALT_SYSMGR_NOC_H2F_SET_MSK |
205 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
206 ALT_SYSMGR_NOC_F2H_SET_MSK |
207 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
208 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
209 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
210 true, 10000, false);
211 if (ret)
212 return ret;
213
214 /* Poll until all idlestatus to 1 */
215 ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
216 ALT_SYSMGR_NOC_H2F_SET_MSK |
217 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
218 ALT_SYSMGR_NOC_F2H_SET_MSK |
219 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
220 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
221 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
222 true, 10000, false);
223 if (ret)
224 return ret;
225
226 /* Put all bridges (except NOR DDR scheduler) into reset state */
227 setbits_le32(&reset_manager_base->brgmodrst,
228 (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
229 ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
230 ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
231 ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
232 ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
233 ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
234
235 /* Disable NOC timeout */
236 writel(0, &sysmgr_regs->noc_timeout);
237
238 return 0;
239 }
240