1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2017-2018, Intel Corporation. All rights reserved
4 * Copyright Altera Corporation (C) 2014-2016. All rights reserved.
5 * Copyright 2011-2012 Calxeda, Inc.
6 */
7
8 #include <asm/cacheflush.h>
9 #include <linux/ctype.h>
10 #include <linux/delay.h>
11 #include <linux/edac.h>
12 #include <linux/firmware/intel/stratix10-smc.h>
13 #include <linux/genalloc.h>
14 #include <linux/interrupt.h>
15 #include <linux/irqchip/chained_irq.h>
16 #include <linux/kernel.h>
17 #include <linux/mfd/altera-sysmgr.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/notifier.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/panic_notifier.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
26 #include <linux/types.h>
27 #include <linux/uaccess.h>
28
29 #include "altera_edac.h"
30 #include "edac_module.h"
31
32 #define EDAC_MOD_STR "altera_edac"
33 #define EDAC_DEVICE "Altera"
34
35 #ifdef CONFIG_EDAC_ALTERA_SDRAM
36 static const struct altr_sdram_prv_data c5_data = {
37 .ecc_ctrl_offset = CV_CTLCFG_OFST,
38 .ecc_ctl_en_mask = CV_CTLCFG_ECC_AUTO_EN,
39 .ecc_stat_offset = CV_DRAMSTS_OFST,
40 .ecc_stat_ce_mask = CV_DRAMSTS_SBEERR,
41 .ecc_stat_ue_mask = CV_DRAMSTS_DBEERR,
42 .ecc_saddr_offset = CV_ERRADDR_OFST,
43 .ecc_daddr_offset = CV_ERRADDR_OFST,
44 .ecc_cecnt_offset = CV_SBECOUNT_OFST,
45 .ecc_uecnt_offset = CV_DBECOUNT_OFST,
46 .ecc_irq_en_offset = CV_DRAMINTR_OFST,
47 .ecc_irq_en_mask = CV_DRAMINTR_INTREN,
48 .ecc_irq_clr_offset = CV_DRAMINTR_OFST,
49 .ecc_irq_clr_mask = (CV_DRAMINTR_INTRCLR | CV_DRAMINTR_INTREN),
50 .ecc_cnt_rst_offset = CV_DRAMINTR_OFST,
51 .ecc_cnt_rst_mask = CV_DRAMINTR_INTRCLR,
52 .ce_ue_trgr_offset = CV_CTLCFG_OFST,
53 .ce_set_mask = CV_CTLCFG_GEN_SB_ERR,
54 .ue_set_mask = CV_CTLCFG_GEN_DB_ERR,
55 };
56
57 static const struct altr_sdram_prv_data a10_data = {
58 .ecc_ctrl_offset = A10_ECCCTRL1_OFST,
59 .ecc_ctl_en_mask = A10_ECCCTRL1_ECC_EN,
60 .ecc_stat_offset = A10_INTSTAT_OFST,
61 .ecc_stat_ce_mask = A10_INTSTAT_SBEERR,
62 .ecc_stat_ue_mask = A10_INTSTAT_DBEERR,
63 .ecc_saddr_offset = A10_SERRADDR_OFST,
64 .ecc_daddr_offset = A10_DERRADDR_OFST,
65 .ecc_irq_en_offset = A10_ERRINTEN_OFST,
66 .ecc_irq_en_mask = A10_ECC_IRQ_EN_MASK,
67 .ecc_irq_clr_offset = A10_INTSTAT_OFST,
68 .ecc_irq_clr_mask = (A10_INTSTAT_SBEERR | A10_INTSTAT_DBEERR),
69 .ecc_cnt_rst_offset = A10_ECCCTRL1_OFST,
70 .ecc_cnt_rst_mask = A10_ECC_CNT_RESET_MASK,
71 .ce_ue_trgr_offset = A10_DIAGINTTEST_OFST,
72 .ce_set_mask = A10_DIAGINT_TSERRA_MASK,
73 .ue_set_mask = A10_DIAGINT_TDERRA_MASK,
74 };
75
76 /*********************** EDAC Memory Controller Functions ****************/
77
78 /* The SDRAM controller uses the EDAC Memory Controller framework. */
79
altr_sdram_mc_err_handler(int irq,void * dev_id)80 static irqreturn_t altr_sdram_mc_err_handler(int irq, void *dev_id)
81 {
82 struct mem_ctl_info *mci = dev_id;
83 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
84 const struct altr_sdram_prv_data *priv = drvdata->data;
85 u32 status, err_count = 1, err_addr;
86
87 regmap_read(drvdata->mc_vbase, priv->ecc_stat_offset, &status);
88
89 if (status & priv->ecc_stat_ue_mask) {
90 regmap_read(drvdata->mc_vbase, priv->ecc_daddr_offset,
91 &err_addr);
92 if (priv->ecc_uecnt_offset)
93 regmap_read(drvdata->mc_vbase, priv->ecc_uecnt_offset,
94 &err_count);
95 panic("\nEDAC: [%d Uncorrectable errors @ 0x%08X]\n",
96 err_count, err_addr);
97 }
98 if (status & priv->ecc_stat_ce_mask) {
99 regmap_read(drvdata->mc_vbase, priv->ecc_saddr_offset,
100 &err_addr);
101 if (priv->ecc_cecnt_offset)
102 regmap_read(drvdata->mc_vbase, priv->ecc_cecnt_offset,
103 &err_count);
104 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, err_count,
105 err_addr >> PAGE_SHIFT,
106 err_addr & ~PAGE_MASK, 0,
107 0, 0, -1, mci->ctl_name, "");
108 /* Clear IRQ to resume */
109 regmap_write(drvdata->mc_vbase, priv->ecc_irq_clr_offset,
110 priv->ecc_irq_clr_mask);
111
112 return IRQ_HANDLED;
113 }
114 return IRQ_NONE;
115 }
116
altr_sdr_mc_err_inject_write(struct file * file,const char __user * data,size_t count,loff_t * ppos)117 static ssize_t altr_sdr_mc_err_inject_write(struct file *file,
118 const char __user *data,
119 size_t count, loff_t *ppos)
120 {
121 struct mem_ctl_info *mci = file->private_data;
122 struct altr_sdram_mc_data *drvdata = mci->pvt_info;
123 const struct altr_sdram_prv_data *priv = drvdata->data;
124 u32 *ptemp;
125 dma_addr_t dma_handle;
126 u32 reg, read_reg;
127
128 ptemp = dma_alloc_coherent(mci->pdev, 16, &dma_handle, GFP_KERNEL);
129 if (!ptemp) {
130 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
131 edac_printk(KERN_ERR, EDAC_MC,
132 "Inject: Buffer Allocation error\n");
133 return -ENOMEM;
134 }
135
136 regmap_read(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
137 &read_reg);
138 read_reg &= ~(priv->ce_set_mask | priv->ue_set_mask);
139
140 /* Error are injected by writing a word while the SBE or DBE
141 * bit in the CTLCFG register is set. Reading the word will
142 * trigger the SBE or DBE error and the corresponding IRQ.
143 */
144 if (count == 3) {
145 edac_printk(KERN_ALERT, EDAC_MC,
146 "Inject Double bit error\n");
147 local_irq_disable();
148 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
149 (read_reg | priv->ue_set_mask));
150 local_irq_enable();
151 } else {
152 edac_printk(KERN_ALERT, EDAC_MC,
153 "Inject Single bit error\n");
154 local_irq_disable();
155 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset,
156 (read_reg | priv->ce_set_mask));
157 local_irq_enable();
158 }
159
160 ptemp[0] = 0x5A5A5A5A;
161 ptemp[1] = 0xA5A5A5A5;
162
163 /* Clear the error injection bits */
164 regmap_write(drvdata->mc_vbase, priv->ce_ue_trgr_offset, read_reg);
165 /* Ensure it has been written out */
166 wmb();
167
168 /*
169 * To trigger the error, we need to read the data back
170 * (the data was written with errors above).
171 * The READ_ONCE macros and printk are used to prevent the
172 * the compiler optimizing these reads out.
173 */
174 reg = READ_ONCE(ptemp[0]);
175 read_reg = READ_ONCE(ptemp[1]);
176 /* Force Read */
177 rmb();
178
179 edac_printk(KERN_ALERT, EDAC_MC, "Read Data [0x%X, 0x%X]\n",
180 reg, read_reg);
181
182 dma_free_coherent(mci->pdev, 16, ptemp, dma_handle);
183
184 return count;
185 }
186
187 static const struct file_operations altr_sdr_mc_debug_inject_fops = {
188 .open = simple_open,
189 .write = altr_sdr_mc_err_inject_write,
190 .llseek = generic_file_llseek,
191 };
192
altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info * mci)193 static void altr_sdr_mc_create_debugfs_nodes(struct mem_ctl_info *mci)
194 {
195 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
196 return;
197
198 if (!mci->debugfs)
199 return;
200
201 edac_debugfs_create_file("altr_trigger", S_IWUSR, mci->debugfs, mci,
202 &altr_sdr_mc_debug_inject_fops);
203 }
204
205 /* Get total memory size from Open Firmware DTB */
get_total_mem(void)206 static unsigned long get_total_mem(void)
207 {
208 struct device_node *np = NULL;
209 struct resource res;
210 int ret;
211 unsigned long total_mem = 0;
212
213 for_each_node_by_type(np, "memory") {
214 ret = of_address_to_resource(np, 0, &res);
215 if (ret)
216 continue;
217
218 total_mem += resource_size(&res);
219 }
220 edac_dbg(0, "total_mem 0x%lx\n", total_mem);
221 return total_mem;
222 }
223
224 static const struct of_device_id altr_sdram_ctrl_of_match[] = {
225 { .compatible = "altr,sdram-edac", .data = &c5_data},
226 { .compatible = "altr,sdram-edac-a10", .data = &a10_data},
227 {},
228 };
229 MODULE_DEVICE_TABLE(of, altr_sdram_ctrl_of_match);
230
a10_init(struct regmap * mc_vbase)231 static int a10_init(struct regmap *mc_vbase)
232 {
233 if (regmap_update_bits(mc_vbase, A10_INTMODE_OFST,
234 A10_INTMODE_SB_INT, A10_INTMODE_SB_INT)) {
235 edac_printk(KERN_ERR, EDAC_MC,
236 "Error setting SB IRQ mode\n");
237 return -ENODEV;
238 }
239
240 if (regmap_write(mc_vbase, A10_SERRCNTREG_OFST, 1)) {
241 edac_printk(KERN_ERR, EDAC_MC,
242 "Error setting trigger count\n");
243 return -ENODEV;
244 }
245
246 return 0;
247 }
248
a10_unmask_irq(struct platform_device * pdev,u32 mask)249 static int a10_unmask_irq(struct platform_device *pdev, u32 mask)
250 {
251 void __iomem *sm_base;
252 int ret = 0;
253
254 if (!request_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32),
255 dev_name(&pdev->dev))) {
256 edac_printk(KERN_ERR, EDAC_MC,
257 "Unable to request mem region\n");
258 return -EBUSY;
259 }
260
261 sm_base = ioremap(A10_SYMAN_INTMASK_CLR, sizeof(u32));
262 if (!sm_base) {
263 edac_printk(KERN_ERR, EDAC_MC,
264 "Unable to ioremap device\n");
265
266 ret = -ENOMEM;
267 goto release;
268 }
269
270 iowrite32(mask, sm_base);
271
272 iounmap(sm_base);
273
274 release:
275 release_mem_region(A10_SYMAN_INTMASK_CLR, sizeof(u32));
276
277 return ret;
278 }
279
altr_sdram_probe(struct platform_device * pdev)280 static int altr_sdram_probe(struct platform_device *pdev)
281 {
282 const struct of_device_id *id;
283 struct edac_mc_layer layers[2];
284 struct mem_ctl_info *mci;
285 struct altr_sdram_mc_data *drvdata;
286 const struct altr_sdram_prv_data *priv;
287 struct regmap *mc_vbase;
288 struct dimm_info *dimm;
289 u32 read_reg;
290 int irq, irq2, res = 0;
291 unsigned long mem_size, irqflags = 0;
292
293 id = of_match_device(altr_sdram_ctrl_of_match, &pdev->dev);
294 if (!id)
295 return -ENODEV;
296
297 /* Grab the register range from the sdr controller in device tree */
298 mc_vbase = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
299 "altr,sdr-syscon");
300 if (IS_ERR(mc_vbase)) {
301 edac_printk(KERN_ERR, EDAC_MC,
302 "regmap for altr,sdr-syscon lookup failed.\n");
303 return -ENODEV;
304 }
305
306 /* Check specific dependencies for the module */
307 priv = of_match_node(altr_sdram_ctrl_of_match,
308 pdev->dev.of_node)->data;
309
310 /* Validate the SDRAM controller has ECC enabled */
311 if (regmap_read(mc_vbase, priv->ecc_ctrl_offset, &read_reg) ||
312 ((read_reg & priv->ecc_ctl_en_mask) != priv->ecc_ctl_en_mask)) {
313 edac_printk(KERN_ERR, EDAC_MC,
314 "No ECC/ECC disabled [0x%08X]\n", read_reg);
315 return -ENODEV;
316 }
317
318 /* Grab memory size from device tree. */
319 mem_size = get_total_mem();
320 if (!mem_size) {
321 edac_printk(KERN_ERR, EDAC_MC, "Unable to calculate memory size\n");
322 return -ENODEV;
323 }
324
325 /* Ensure the SDRAM Interrupt is disabled */
326 if (regmap_update_bits(mc_vbase, priv->ecc_irq_en_offset,
327 priv->ecc_irq_en_mask, 0)) {
328 edac_printk(KERN_ERR, EDAC_MC,
329 "Error disabling SDRAM ECC IRQ\n");
330 return -ENODEV;
331 }
332
333 /* Toggle to clear the SDRAM Error count */
334 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
335 priv->ecc_cnt_rst_mask,
336 priv->ecc_cnt_rst_mask)) {
337 edac_printk(KERN_ERR, EDAC_MC,
338 "Error clearing SDRAM ECC count\n");
339 return -ENODEV;
340 }
341
342 if (regmap_update_bits(mc_vbase, priv->ecc_cnt_rst_offset,
343 priv->ecc_cnt_rst_mask, 0)) {
344 edac_printk(KERN_ERR, EDAC_MC,
345 "Error clearing SDRAM ECC count\n");
346 return -ENODEV;
347 }
348
349 irq = platform_get_irq(pdev, 0);
350 if (irq < 0) {
351 edac_printk(KERN_ERR, EDAC_MC,
352 "No irq %d in DT\n", irq);
353 return irq;
354 }
355
356 /* Arria10 has a 2nd IRQ */
357 irq2 = platform_get_irq(pdev, 1);
358
359 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
360 layers[0].size = 1;
361 layers[0].is_virt_csrow = true;
362 layers[1].type = EDAC_MC_LAYER_CHANNEL;
363 layers[1].size = 1;
364 layers[1].is_virt_csrow = false;
365 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
366 sizeof(struct altr_sdram_mc_data));
367 if (!mci)
368 return -ENOMEM;
369
370 mci->pdev = &pdev->dev;
371 drvdata = mci->pvt_info;
372 drvdata->mc_vbase = mc_vbase;
373 drvdata->data = priv;
374 platform_set_drvdata(pdev, mci);
375
376 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
377 edac_printk(KERN_ERR, EDAC_MC,
378 "Unable to get managed device resource\n");
379 res = -ENOMEM;
380 goto free;
381 }
382
383 mci->mtype_cap = MEM_FLAG_DDR3;
384 mci->edac_ctl_cap = EDAC_FLAG_NONE | EDAC_FLAG_SECDED;
385 mci->edac_cap = EDAC_FLAG_SECDED;
386 mci->mod_name = EDAC_MOD_STR;
387 mci->ctl_name = dev_name(&pdev->dev);
388 mci->scrub_mode = SCRUB_SW_SRC;
389 mci->dev_name = dev_name(&pdev->dev);
390
391 dimm = *mci->dimms;
392 dimm->nr_pages = ((mem_size - 1) >> PAGE_SHIFT) + 1;
393 dimm->grain = 8;
394 dimm->dtype = DEV_X8;
395 dimm->mtype = MEM_DDR3;
396 dimm->edac_mode = EDAC_SECDED;
397
398 res = edac_mc_add_mc(mci);
399 if (res < 0)
400 goto err;
401
402 /* Only the Arria10 has separate IRQs */
403 if (of_machine_is_compatible("altr,socfpga-arria10")) {
404 /* Arria10 specific initialization */
405 res = a10_init(mc_vbase);
406 if (res < 0)
407 goto err2;
408
409 res = devm_request_irq(&pdev->dev, irq2,
410 altr_sdram_mc_err_handler,
411 IRQF_SHARED, dev_name(&pdev->dev), mci);
412 if (res < 0) {
413 edac_mc_printk(mci, KERN_ERR,
414 "Unable to request irq %d\n", irq2);
415 res = -ENODEV;
416 goto err2;
417 }
418
419 res = a10_unmask_irq(pdev, A10_DDR0_IRQ_MASK);
420 if (res < 0)
421 goto err2;
422
423 irqflags = IRQF_SHARED;
424 }
425
426 res = devm_request_irq(&pdev->dev, irq, altr_sdram_mc_err_handler,
427 irqflags, dev_name(&pdev->dev), mci);
428 if (res < 0) {
429 edac_mc_printk(mci, KERN_ERR,
430 "Unable to request irq %d\n", irq);
431 res = -ENODEV;
432 goto err2;
433 }
434
435 /* Infrastructure ready - enable the IRQ */
436 if (regmap_update_bits(drvdata->mc_vbase, priv->ecc_irq_en_offset,
437 priv->ecc_irq_en_mask, priv->ecc_irq_en_mask)) {
438 edac_mc_printk(mci, KERN_ERR,
439 "Error enabling SDRAM ECC IRQ\n");
440 res = -ENODEV;
441 goto err2;
442 }
443
444 altr_sdr_mc_create_debugfs_nodes(mci);
445
446 devres_close_group(&pdev->dev, NULL);
447
448 return 0;
449
450 err2:
451 edac_mc_del_mc(&pdev->dev);
452 err:
453 devres_release_group(&pdev->dev, NULL);
454 free:
455 edac_mc_free(mci);
456 edac_printk(KERN_ERR, EDAC_MC,
457 "EDAC Probe Failed; Error %d\n", res);
458
459 return res;
460 }
461
altr_sdram_remove(struct platform_device * pdev)462 static int altr_sdram_remove(struct platform_device *pdev)
463 {
464 struct mem_ctl_info *mci = platform_get_drvdata(pdev);
465
466 edac_mc_del_mc(&pdev->dev);
467 edac_mc_free(mci);
468 platform_set_drvdata(pdev, NULL);
469
470 return 0;
471 }
472
473 /*
474 * If you want to suspend, need to disable EDAC by removing it
475 * from the device tree or defconfig.
476 */
477 #ifdef CONFIG_PM
altr_sdram_prepare(struct device * dev)478 static int altr_sdram_prepare(struct device *dev)
479 {
480 pr_err("Suspend not allowed when EDAC is enabled.\n");
481
482 return -EPERM;
483 }
484
485 static const struct dev_pm_ops altr_sdram_pm_ops = {
486 .prepare = altr_sdram_prepare,
487 };
488 #endif
489
490 static struct platform_driver altr_sdram_edac_driver = {
491 .probe = altr_sdram_probe,
492 .remove = altr_sdram_remove,
493 .driver = {
494 .name = "altr_sdram_edac",
495 #ifdef CONFIG_PM
496 .pm = &altr_sdram_pm_ops,
497 #endif
498 .of_match_table = altr_sdram_ctrl_of_match,
499 },
500 };
501
502 module_platform_driver(altr_sdram_edac_driver);
503
504 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
505
506 /************************* EDAC Parent Probe *************************/
507
508 static const struct of_device_id altr_edac_device_of_match[];
509
510 static const struct of_device_id altr_edac_of_match[] = {
511 { .compatible = "altr,socfpga-ecc-manager" },
512 {},
513 };
514 MODULE_DEVICE_TABLE(of, altr_edac_of_match);
515
altr_edac_probe(struct platform_device * pdev)516 static int altr_edac_probe(struct platform_device *pdev)
517 {
518 of_platform_populate(pdev->dev.of_node, altr_edac_device_of_match,
519 NULL, &pdev->dev);
520 return 0;
521 }
522
523 static struct platform_driver altr_edac_driver = {
524 .probe = altr_edac_probe,
525 .driver = {
526 .name = "socfpga_ecc_manager",
527 .of_match_table = altr_edac_of_match,
528 },
529 };
530 module_platform_driver(altr_edac_driver);
531
532 /************************* EDAC Device Functions *************************/
533
534 /*
535 * EDAC Device Functions (shared between various IPs).
536 * The discrete memories use the EDAC Device framework. The probe
537 * and error handling functions are very similar between memories
538 * so they are shared. The memory allocation and freeing for EDAC
539 * trigger testing are different for each memory.
540 */
541
542 #ifdef CONFIG_EDAC_ALTERA_OCRAM
543 static const struct edac_device_prv_data ocramecc_data;
544 #endif
545 #ifdef CONFIG_EDAC_ALTERA_L2C
546 static const struct edac_device_prv_data l2ecc_data;
547 #endif
548 #ifdef CONFIG_EDAC_ALTERA_OCRAM
549 static const struct edac_device_prv_data a10_ocramecc_data;
550 #endif
551 #ifdef CONFIG_EDAC_ALTERA_L2C
552 static const struct edac_device_prv_data a10_l2ecc_data;
553 #endif
554
altr_edac_device_handler(int irq,void * dev_id)555 static irqreturn_t altr_edac_device_handler(int irq, void *dev_id)
556 {
557 irqreturn_t ret_value = IRQ_NONE;
558 struct edac_device_ctl_info *dci = dev_id;
559 struct altr_edac_device_dev *drvdata = dci->pvt_info;
560 const struct edac_device_prv_data *priv = drvdata->data;
561
562 if (irq == drvdata->sb_irq) {
563 if (priv->ce_clear_mask)
564 writel(priv->ce_clear_mask, drvdata->base);
565 edac_device_handle_ce(dci, 0, 0, drvdata->edac_dev_name);
566 ret_value = IRQ_HANDLED;
567 } else if (irq == drvdata->db_irq) {
568 if (priv->ue_clear_mask)
569 writel(priv->ue_clear_mask, drvdata->base);
570 edac_device_handle_ue(dci, 0, 0, drvdata->edac_dev_name);
571 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
572 ret_value = IRQ_HANDLED;
573 } else {
574 WARN_ON(1);
575 }
576
577 return ret_value;
578 }
579
580 static ssize_t __maybe_unused
altr_edac_device_trig(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)581 altr_edac_device_trig(struct file *file, const char __user *user_buf,
582 size_t count, loff_t *ppos)
583
584 {
585 u32 *ptemp, i, error_mask;
586 int result = 0;
587 u8 trig_type;
588 unsigned long flags;
589 struct edac_device_ctl_info *edac_dci = file->private_data;
590 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
591 const struct edac_device_prv_data *priv = drvdata->data;
592 void *generic_ptr = edac_dci->dev;
593
594 if (!user_buf || get_user(trig_type, user_buf))
595 return -EFAULT;
596
597 if (!priv->alloc_mem)
598 return -ENOMEM;
599
600 /*
601 * Note that generic_ptr is initialized to the device * but in
602 * some alloc_functions, this is overridden and returns data.
603 */
604 ptemp = priv->alloc_mem(priv->trig_alloc_sz, &generic_ptr);
605 if (!ptemp) {
606 edac_printk(KERN_ERR, EDAC_DEVICE,
607 "Inject: Buffer Allocation error\n");
608 return -ENOMEM;
609 }
610
611 if (trig_type == ALTR_UE_TRIGGER_CHAR)
612 error_mask = priv->ue_set_mask;
613 else
614 error_mask = priv->ce_set_mask;
615
616 edac_printk(KERN_ALERT, EDAC_DEVICE,
617 "Trigger Error Mask (0x%X)\n", error_mask);
618
619 local_irq_save(flags);
620 /* write ECC corrupted data out. */
621 for (i = 0; i < (priv->trig_alloc_sz / sizeof(*ptemp)); i++) {
622 /* Read data so we're in the correct state */
623 rmb();
624 if (READ_ONCE(ptemp[i]))
625 result = -1;
626 /* Toggle Error bit (it is latched), leave ECC enabled */
627 writel(error_mask, (drvdata->base + priv->set_err_ofst));
628 writel(priv->ecc_enable_mask, (drvdata->base +
629 priv->set_err_ofst));
630 ptemp[i] = i;
631 }
632 /* Ensure it has been written out */
633 wmb();
634 local_irq_restore(flags);
635
636 if (result)
637 edac_printk(KERN_ERR, EDAC_DEVICE, "Mem Not Cleared\n");
638
639 /* Read out written data. ECC error caused here */
640 for (i = 0; i < ALTR_TRIGGER_READ_WRD_CNT; i++)
641 if (READ_ONCE(ptemp[i]) != i)
642 edac_printk(KERN_ERR, EDAC_DEVICE,
643 "Read doesn't match written data\n");
644
645 if (priv->free_mem)
646 priv->free_mem(ptemp, priv->trig_alloc_sz, generic_ptr);
647
648 return count;
649 }
650
651 static const struct file_operations altr_edac_device_inject_fops __maybe_unused = {
652 .open = simple_open,
653 .write = altr_edac_device_trig,
654 .llseek = generic_file_llseek,
655 };
656
657 static ssize_t __maybe_unused
658 altr_edac_a10_device_trig(struct file *file, const char __user *user_buf,
659 size_t count, loff_t *ppos);
660
661 static const struct file_operations altr_edac_a10_device_inject_fops __maybe_unused = {
662 .open = simple_open,
663 .write = altr_edac_a10_device_trig,
664 .llseek = generic_file_llseek,
665 };
666
667 static ssize_t __maybe_unused
668 altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf,
669 size_t count, loff_t *ppos);
670
671 static const struct file_operations altr_edac_a10_device_inject2_fops __maybe_unused = {
672 .open = simple_open,
673 .write = altr_edac_a10_device_trig2,
674 .llseek = generic_file_llseek,
675 };
676
altr_create_edacdev_dbgfs(struct edac_device_ctl_info * edac_dci,const struct edac_device_prv_data * priv)677 static void altr_create_edacdev_dbgfs(struct edac_device_ctl_info *edac_dci,
678 const struct edac_device_prv_data *priv)
679 {
680 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
681
682 if (!IS_ENABLED(CONFIG_EDAC_DEBUG))
683 return;
684
685 drvdata->debugfs_dir = edac_debugfs_create_dir(drvdata->edac_dev_name);
686 if (!drvdata->debugfs_dir)
687 return;
688
689 if (!edac_debugfs_create_file("altr_trigger", S_IWUSR,
690 drvdata->debugfs_dir, edac_dci,
691 priv->inject_fops))
692 debugfs_remove_recursive(drvdata->debugfs_dir);
693 }
694
695 static const struct of_device_id altr_edac_device_of_match[] = {
696 #ifdef CONFIG_EDAC_ALTERA_L2C
697 { .compatible = "altr,socfpga-l2-ecc", .data = &l2ecc_data },
698 #endif
699 #ifdef CONFIG_EDAC_ALTERA_OCRAM
700 { .compatible = "altr,socfpga-ocram-ecc", .data = &ocramecc_data },
701 #endif
702 {},
703 };
704 MODULE_DEVICE_TABLE(of, altr_edac_device_of_match);
705
706 /*
707 * altr_edac_device_probe()
708 * This is a generic EDAC device driver that will support
709 * various Altera memory devices such as the L2 cache ECC and
710 * OCRAM ECC as well as the memories for other peripherals.
711 * Module specific initialization is done by passing the
712 * function index in the device tree.
713 */
altr_edac_device_probe(struct platform_device * pdev)714 static int altr_edac_device_probe(struct platform_device *pdev)
715 {
716 struct edac_device_ctl_info *dci;
717 struct altr_edac_device_dev *drvdata;
718 struct resource *r;
719 int res = 0;
720 struct device_node *np = pdev->dev.of_node;
721 char *ecc_name = (char *)np->name;
722 static int dev_instance;
723
724 if (!devres_open_group(&pdev->dev, NULL, GFP_KERNEL)) {
725 edac_printk(KERN_ERR, EDAC_DEVICE,
726 "Unable to open devm\n");
727 return -ENOMEM;
728 }
729
730 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
731 if (!r) {
732 edac_printk(KERN_ERR, EDAC_DEVICE,
733 "Unable to get mem resource\n");
734 res = -ENODEV;
735 goto fail;
736 }
737
738 if (!devm_request_mem_region(&pdev->dev, r->start, resource_size(r),
739 dev_name(&pdev->dev))) {
740 edac_printk(KERN_ERR, EDAC_DEVICE,
741 "%s:Error requesting mem region\n", ecc_name);
742 res = -EBUSY;
743 goto fail;
744 }
745
746 dci = edac_device_alloc_ctl_info(sizeof(*drvdata), ecc_name,
747 1, ecc_name, 1, 0, NULL, 0,
748 dev_instance++);
749
750 if (!dci) {
751 edac_printk(KERN_ERR, EDAC_DEVICE,
752 "%s: Unable to allocate EDAC device\n", ecc_name);
753 res = -ENOMEM;
754 goto fail;
755 }
756
757 drvdata = dci->pvt_info;
758 dci->dev = &pdev->dev;
759 platform_set_drvdata(pdev, dci);
760 drvdata->edac_dev_name = ecc_name;
761
762 drvdata->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
763 if (!drvdata->base) {
764 res = -ENOMEM;
765 goto fail1;
766 }
767
768 /* Get driver specific data for this EDAC device */
769 drvdata->data = of_match_node(altr_edac_device_of_match, np)->data;
770
771 /* Check specific dependencies for the module */
772 if (drvdata->data->setup) {
773 res = drvdata->data->setup(drvdata);
774 if (res)
775 goto fail1;
776 }
777
778 drvdata->sb_irq = platform_get_irq(pdev, 0);
779 res = devm_request_irq(&pdev->dev, drvdata->sb_irq,
780 altr_edac_device_handler,
781 0, dev_name(&pdev->dev), dci);
782 if (res)
783 goto fail1;
784
785 drvdata->db_irq = platform_get_irq(pdev, 1);
786 res = devm_request_irq(&pdev->dev, drvdata->db_irq,
787 altr_edac_device_handler,
788 0, dev_name(&pdev->dev), dci);
789 if (res)
790 goto fail1;
791
792 dci->mod_name = "Altera ECC Manager";
793 dci->dev_name = drvdata->edac_dev_name;
794
795 res = edac_device_add_device(dci);
796 if (res)
797 goto fail1;
798
799 altr_create_edacdev_dbgfs(dci, drvdata->data);
800
801 devres_close_group(&pdev->dev, NULL);
802
803 return 0;
804
805 fail1:
806 edac_device_free_ctl_info(dci);
807 fail:
808 devres_release_group(&pdev->dev, NULL);
809 edac_printk(KERN_ERR, EDAC_DEVICE,
810 "%s:Error setting up EDAC device: %d\n", ecc_name, res);
811
812 return res;
813 }
814
altr_edac_device_remove(struct platform_device * pdev)815 static int altr_edac_device_remove(struct platform_device *pdev)
816 {
817 struct edac_device_ctl_info *dci = platform_get_drvdata(pdev);
818 struct altr_edac_device_dev *drvdata = dci->pvt_info;
819
820 debugfs_remove_recursive(drvdata->debugfs_dir);
821 edac_device_del_device(&pdev->dev);
822 edac_device_free_ctl_info(dci);
823
824 return 0;
825 }
826
827 static struct platform_driver altr_edac_device_driver = {
828 .probe = altr_edac_device_probe,
829 .remove = altr_edac_device_remove,
830 .driver = {
831 .name = "altr_edac_device",
832 .of_match_table = altr_edac_device_of_match,
833 },
834 };
835 module_platform_driver(altr_edac_device_driver);
836
837 /******************* Arria10 Device ECC Shared Functions *****************/
838
839 /*
840 * Test for memory's ECC dependencies upon entry because platform specific
841 * startup should have initialized the memory and enabled the ECC.
842 * Can't turn on ECC here because accessing un-initialized memory will
843 * cause CE/UE errors possibly causing an ABORT.
844 */
845 static int __maybe_unused
altr_check_ecc_deps(struct altr_edac_device_dev * device)846 altr_check_ecc_deps(struct altr_edac_device_dev *device)
847 {
848 void __iomem *base = device->base;
849 const struct edac_device_prv_data *prv = device->data;
850
851 if (readl(base + prv->ecc_en_ofst) & prv->ecc_enable_mask)
852 return 0;
853
854 edac_printk(KERN_ERR, EDAC_DEVICE,
855 "%s: No ECC present or ECC disabled.\n",
856 device->edac_dev_name);
857 return -ENODEV;
858 }
859
altr_edac_a10_ecc_irq(int irq,void * dev_id)860 static irqreturn_t __maybe_unused altr_edac_a10_ecc_irq(int irq, void *dev_id)
861 {
862 struct altr_edac_device_dev *dci = dev_id;
863 void __iomem *base = dci->base;
864
865 if (irq == dci->sb_irq) {
866 writel(ALTR_A10_ECC_SERRPENA,
867 base + ALTR_A10_ECC_INTSTAT_OFST);
868 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
869
870 return IRQ_HANDLED;
871 } else if (irq == dci->db_irq) {
872 writel(ALTR_A10_ECC_DERRPENA,
873 base + ALTR_A10_ECC_INTSTAT_OFST);
874 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
875 if (dci->data->panic)
876 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
877
878 return IRQ_HANDLED;
879 }
880
881 WARN_ON(1);
882
883 return IRQ_NONE;
884 }
885
886 /******************* Arria10 Memory Buffer Functions *********************/
887
a10_get_irq_mask(struct device_node * np)888 static inline int a10_get_irq_mask(struct device_node *np)
889 {
890 int irq;
891 const u32 *handle = of_get_property(np, "interrupts", NULL);
892
893 if (!handle)
894 return -ENODEV;
895 irq = be32_to_cpup(handle);
896 return irq;
897 }
898
ecc_set_bits(u32 bit_mask,void __iomem * ioaddr)899 static inline void ecc_set_bits(u32 bit_mask, void __iomem *ioaddr)
900 {
901 u32 value = readl(ioaddr);
902
903 value |= bit_mask;
904 writel(value, ioaddr);
905 }
906
ecc_clear_bits(u32 bit_mask,void __iomem * ioaddr)907 static inline void ecc_clear_bits(u32 bit_mask, void __iomem *ioaddr)
908 {
909 u32 value = readl(ioaddr);
910
911 value &= ~bit_mask;
912 writel(value, ioaddr);
913 }
914
ecc_test_bits(u32 bit_mask,void __iomem * ioaddr)915 static inline int ecc_test_bits(u32 bit_mask, void __iomem *ioaddr)
916 {
917 u32 value = readl(ioaddr);
918
919 return (value & bit_mask) ? 1 : 0;
920 }
921
922 /*
923 * This function uses the memory initialization block in the Arria10 ECC
924 * controller to initialize/clear the entire memory data and ECC data.
925 */
altr_init_memory_port(void __iomem * ioaddr,int port)926 static int __maybe_unused altr_init_memory_port(void __iomem *ioaddr, int port)
927 {
928 int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
929 u32 init_mask, stat_mask, clear_mask;
930 int ret = 0;
931
932 if (port) {
933 init_mask = ALTR_A10_ECC_INITB;
934 stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
935 clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
936 } else {
937 init_mask = ALTR_A10_ECC_INITA;
938 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
939 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
940 }
941
942 ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
943 while (limit--) {
944 if (ecc_test_bits(stat_mask,
945 (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
946 break;
947 udelay(1);
948 }
949 if (limit < 0)
950 ret = -EBUSY;
951
952 /* Clear any pending ECC interrupts */
953 writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
954
955 return ret;
956 }
957
958 static __init int __maybe_unused
altr_init_a10_ecc_block(struct device_node * np,u32 irq_mask,u32 ecc_ctrl_en_mask,bool dual_port)959 altr_init_a10_ecc_block(struct device_node *np, u32 irq_mask,
960 u32 ecc_ctrl_en_mask, bool dual_port)
961 {
962 int ret = 0;
963 void __iomem *ecc_block_base;
964 struct regmap *ecc_mgr_map;
965 char *ecc_name;
966 struct device_node *np_eccmgr;
967
968 ecc_name = (char *)np->name;
969
970 /* Get the ECC Manager - parent of the device EDACs */
971 np_eccmgr = of_get_parent(np);
972
973 ecc_mgr_map =
974 altr_sysmgr_regmap_lookup_by_phandle(np_eccmgr,
975 "altr,sysmgr-syscon");
976
977 of_node_put(np_eccmgr);
978 if (IS_ERR(ecc_mgr_map)) {
979 edac_printk(KERN_ERR, EDAC_DEVICE,
980 "Unable to get syscon altr,sysmgr-syscon\n");
981 return -ENODEV;
982 }
983
984 /* Map the ECC Block */
985 ecc_block_base = of_iomap(np, 0);
986 if (!ecc_block_base) {
987 edac_printk(KERN_ERR, EDAC_DEVICE,
988 "Unable to map %s ECC block\n", ecc_name);
989 return -ENODEV;
990 }
991
992 /* Disable ECC */
993 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST, irq_mask);
994 writel(ALTR_A10_ECC_SERRINTEN,
995 (ecc_block_base + ALTR_A10_ECC_ERRINTENR_OFST));
996 ecc_clear_bits(ecc_ctrl_en_mask,
997 (ecc_block_base + ALTR_A10_ECC_CTRL_OFST));
998 /* Ensure all writes complete */
999 wmb();
1000 /* Use HW initialization block to initialize memory for ECC */
1001 ret = altr_init_memory_port(ecc_block_base, 0);
1002 if (ret) {
1003 edac_printk(KERN_ERR, EDAC_DEVICE,
1004 "ECC: cannot init %s PORTA memory\n", ecc_name);
1005 goto out;
1006 }
1007
1008 if (dual_port) {
1009 ret = altr_init_memory_port(ecc_block_base, 1);
1010 if (ret) {
1011 edac_printk(KERN_ERR, EDAC_DEVICE,
1012 "ECC: cannot init %s PORTB memory\n",
1013 ecc_name);
1014 goto out;
1015 }
1016 }
1017
1018 /* Enable ECC */
1019 ecc_set_bits(ecc_ctrl_en_mask, (ecc_block_base +
1020 ALTR_A10_ECC_CTRL_OFST));
1021 writel(ALTR_A10_ECC_SERRINTEN,
1022 (ecc_block_base + ALTR_A10_ECC_ERRINTENS_OFST));
1023 regmap_write(ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST, irq_mask);
1024 /* Ensure all writes complete */
1025 wmb();
1026 out:
1027 iounmap(ecc_block_base);
1028 return ret;
1029 }
1030
1031 static int validate_parent_available(struct device_node *np);
1032 static const struct of_device_id altr_edac_a10_device_of_match[];
altr_init_a10_ecc_device_type(char * compat)1033 static int __init __maybe_unused altr_init_a10_ecc_device_type(char *compat)
1034 {
1035 int irq;
1036 struct device_node *child, *np;
1037
1038 np = of_find_compatible_node(NULL, NULL,
1039 "altr,socfpga-a10-ecc-manager");
1040 if (!np) {
1041 edac_printk(KERN_ERR, EDAC_DEVICE, "ECC Manager not found\n");
1042 return -ENODEV;
1043 }
1044
1045 for_each_child_of_node(np, child) {
1046 const struct of_device_id *pdev_id;
1047 const struct edac_device_prv_data *prv;
1048
1049 if (!of_device_is_available(child))
1050 continue;
1051 if (!of_device_is_compatible(child, compat))
1052 continue;
1053
1054 if (validate_parent_available(child))
1055 continue;
1056
1057 irq = a10_get_irq_mask(child);
1058 if (irq < 0)
1059 continue;
1060
1061 /* Get matching node and check for valid result */
1062 pdev_id = of_match_node(altr_edac_a10_device_of_match, child);
1063 if (IS_ERR_OR_NULL(pdev_id))
1064 continue;
1065
1066 /* Validate private data pointer before dereferencing */
1067 prv = pdev_id->data;
1068 if (!prv)
1069 continue;
1070
1071 altr_init_a10_ecc_block(child, BIT(irq),
1072 prv->ecc_enable_mask, 0);
1073 }
1074
1075 of_node_put(np);
1076 return 0;
1077 }
1078
1079 /*********************** SDRAM EDAC Device Functions *********************/
1080
1081 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1082
1083 /*
1084 * A legacy U-Boot bug only enabled memory mapped access to the ECC Enable
1085 * register if ECC is enabled. Linux checks the ECC Enable register to
1086 * determine ECC status.
1087 * Use an SMC call (which always works) to determine ECC enablement.
1088 */
altr_s10_sdram_check_ecc_deps(struct altr_edac_device_dev * device)1089 static int altr_s10_sdram_check_ecc_deps(struct altr_edac_device_dev *device)
1090 {
1091 const struct edac_device_prv_data *prv = device->data;
1092 unsigned long sdram_ecc_addr;
1093 struct arm_smccc_res result;
1094 struct device_node *np;
1095 phys_addr_t sdram_addr;
1096 u32 read_reg;
1097 int ret;
1098
1099 np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
1100 if (!np)
1101 goto sdram_err;
1102
1103 sdram_addr = of_translate_address(np, of_get_address(np, 0,
1104 NULL, NULL));
1105 of_node_put(np);
1106 sdram_ecc_addr = (unsigned long)sdram_addr + prv->ecc_en_ofst;
1107 arm_smccc_smc(INTEL_SIP_SMC_REG_READ, sdram_ecc_addr,
1108 0, 0, 0, 0, 0, 0, &result);
1109 read_reg = (unsigned int)result.a1;
1110 ret = (int)result.a0;
1111 if (!ret && (read_reg & prv->ecc_enable_mask))
1112 return 0;
1113
1114 sdram_err:
1115 edac_printk(KERN_ERR, EDAC_DEVICE,
1116 "%s: No ECC present or ECC disabled.\n",
1117 device->edac_dev_name);
1118 return -ENODEV;
1119 }
1120
1121 static const struct edac_device_prv_data s10_sdramecc_data = {
1122 .setup = altr_s10_sdram_check_ecc_deps,
1123 .ce_clear_mask = ALTR_S10_ECC_SERRPENA,
1124 .ue_clear_mask = ALTR_S10_ECC_DERRPENA,
1125 .ecc_enable_mask = ALTR_S10_ECC_EN,
1126 .ecc_en_ofst = ALTR_S10_ECC_CTRL_SDRAM_OFST,
1127 .ce_set_mask = ALTR_S10_ECC_TSERRA,
1128 .ue_set_mask = ALTR_S10_ECC_TDERRA,
1129 .set_err_ofst = ALTR_S10_ECC_INTTEST_OFST,
1130 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1131 .inject_fops = &altr_edac_a10_device_inject_fops,
1132 };
1133 #endif /* CONFIG_EDAC_ALTERA_SDRAM */
1134
1135 /*********************** OCRAM EDAC Device Functions *********************/
1136
1137 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1138
ocram_alloc_mem(size_t size,void ** other)1139 static void *ocram_alloc_mem(size_t size, void **other)
1140 {
1141 struct device_node *np;
1142 struct gen_pool *gp;
1143 void *sram_addr;
1144
1145 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-ocram-ecc");
1146 if (!np)
1147 return NULL;
1148
1149 gp = of_gen_pool_get(np, "iram", 0);
1150 of_node_put(np);
1151 if (!gp)
1152 return NULL;
1153
1154 sram_addr = (void *)gen_pool_alloc(gp, size);
1155 if (!sram_addr)
1156 return NULL;
1157
1158 memset(sram_addr, 0, size);
1159 /* Ensure data is written out */
1160 wmb();
1161
1162 /* Remember this handle for freeing later */
1163 *other = gp;
1164
1165 return sram_addr;
1166 }
1167
ocram_free_mem(void * p,size_t size,void * other)1168 static void ocram_free_mem(void *p, size_t size, void *other)
1169 {
1170 gen_pool_free((struct gen_pool *)other, (unsigned long)p, size);
1171 }
1172
1173 static const struct edac_device_prv_data ocramecc_data = {
1174 .setup = altr_check_ecc_deps,
1175 .ce_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_SERR),
1176 .ue_clear_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_DERR),
1177 .alloc_mem = ocram_alloc_mem,
1178 .free_mem = ocram_free_mem,
1179 .ecc_enable_mask = ALTR_OCR_ECC_EN,
1180 .ecc_en_ofst = ALTR_OCR_ECC_REG_OFFSET,
1181 .ce_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJS),
1182 .ue_set_mask = (ALTR_OCR_ECC_EN | ALTR_OCR_ECC_INJD),
1183 .set_err_ofst = ALTR_OCR_ECC_REG_OFFSET,
1184 .trig_alloc_sz = ALTR_TRIG_OCRAM_BYTE_SIZE,
1185 .inject_fops = &altr_edac_device_inject_fops,
1186 };
1187
1188 static int __maybe_unused
altr_check_ocram_deps_init(struct altr_edac_device_dev * device)1189 altr_check_ocram_deps_init(struct altr_edac_device_dev *device)
1190 {
1191 void __iomem *base = device->base;
1192 int ret;
1193
1194 ret = altr_check_ecc_deps(device);
1195 if (ret)
1196 return ret;
1197
1198 /* Verify OCRAM has been initialized */
1199 if (!ecc_test_bits(ALTR_A10_ECC_INITCOMPLETEA,
1200 (base + ALTR_A10_ECC_INITSTAT_OFST)))
1201 return -ENODEV;
1202
1203 /* Enable IRQ on Single Bit Error */
1204 writel(ALTR_A10_ECC_SERRINTEN, (base + ALTR_A10_ECC_ERRINTENS_OFST));
1205 /* Ensure all writes complete */
1206 wmb();
1207
1208 return 0;
1209 }
1210
1211 static const struct edac_device_prv_data a10_ocramecc_data = {
1212 .setup = altr_check_ocram_deps_init,
1213 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1214 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1215 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_OCRAM,
1216 .ecc_enable_mask = ALTR_A10_OCRAM_ECC_EN_CTL,
1217 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1218 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1219 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1220 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1221 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1222 .inject_fops = &altr_edac_a10_device_inject2_fops,
1223 /*
1224 * OCRAM panic on uncorrectable error because sleep/resume
1225 * functions and FPGA contents are stored in OCRAM. Prefer
1226 * a kernel panic over executing/loading corrupted data.
1227 */
1228 .panic = true,
1229 };
1230
1231 #endif /* CONFIG_EDAC_ALTERA_OCRAM */
1232
1233 /********************* L2 Cache EDAC Device Functions ********************/
1234
1235 #ifdef CONFIG_EDAC_ALTERA_L2C
1236
l2_alloc_mem(size_t size,void ** other)1237 static void *l2_alloc_mem(size_t size, void **other)
1238 {
1239 struct device *dev = *other;
1240 void *ptemp = devm_kzalloc(dev, size, GFP_KERNEL);
1241
1242 if (!ptemp)
1243 return NULL;
1244
1245 /* Make sure everything is written out */
1246 wmb();
1247
1248 /*
1249 * Clean all cache levels up to LoC (includes L2)
1250 * This ensures the corrupted data is written into
1251 * L2 cache for readback test (which causes ECC error).
1252 */
1253 flush_cache_all();
1254
1255 return ptemp;
1256 }
1257
l2_free_mem(void * p,size_t size,void * other)1258 static void l2_free_mem(void *p, size_t size, void *other)
1259 {
1260 struct device *dev = other;
1261
1262 if (dev && p)
1263 devm_kfree(dev, p);
1264 }
1265
1266 /*
1267 * altr_l2_check_deps()
1268 * Test for L2 cache ECC dependencies upon entry because
1269 * platform specific startup should have initialized the L2
1270 * memory and enabled the ECC.
1271 * Bail if ECC is not enabled.
1272 * Note that L2 Cache Enable is forced at build time.
1273 */
altr_l2_check_deps(struct altr_edac_device_dev * device)1274 static int altr_l2_check_deps(struct altr_edac_device_dev *device)
1275 {
1276 void __iomem *base = device->base;
1277 const struct edac_device_prv_data *prv = device->data;
1278
1279 if ((readl(base) & prv->ecc_enable_mask) ==
1280 prv->ecc_enable_mask)
1281 return 0;
1282
1283 edac_printk(KERN_ERR, EDAC_DEVICE,
1284 "L2: No ECC present, or ECC disabled\n");
1285 return -ENODEV;
1286 }
1287
altr_edac_a10_l2_irq(int irq,void * dev_id)1288 static irqreturn_t altr_edac_a10_l2_irq(int irq, void *dev_id)
1289 {
1290 struct altr_edac_device_dev *dci = dev_id;
1291
1292 if (irq == dci->sb_irq) {
1293 regmap_write(dci->edac->ecc_mgr_map,
1294 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1295 A10_SYSGMR_MPU_CLEAR_L2_ECC_SB);
1296 edac_device_handle_ce(dci->edac_dev, 0, 0, dci->edac_dev_name);
1297
1298 return IRQ_HANDLED;
1299 } else if (irq == dci->db_irq) {
1300 regmap_write(dci->edac->ecc_mgr_map,
1301 A10_SYSGMR_MPU_CLEAR_L2_ECC_OFST,
1302 A10_SYSGMR_MPU_CLEAR_L2_ECC_MB);
1303 edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
1304 panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
1305
1306 return IRQ_HANDLED;
1307 }
1308
1309 WARN_ON(1);
1310
1311 return IRQ_NONE;
1312 }
1313
1314 static const struct edac_device_prv_data l2ecc_data = {
1315 .setup = altr_l2_check_deps,
1316 .ce_clear_mask = 0,
1317 .ue_clear_mask = 0,
1318 .alloc_mem = l2_alloc_mem,
1319 .free_mem = l2_free_mem,
1320 .ecc_enable_mask = ALTR_L2_ECC_EN,
1321 .ce_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJS),
1322 .ue_set_mask = (ALTR_L2_ECC_EN | ALTR_L2_ECC_INJD),
1323 .set_err_ofst = ALTR_L2_ECC_REG_OFFSET,
1324 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1325 .inject_fops = &altr_edac_device_inject_fops,
1326 };
1327
1328 static const struct edac_device_prv_data a10_l2ecc_data = {
1329 .setup = altr_l2_check_deps,
1330 .ce_clear_mask = ALTR_A10_L2_ECC_SERR_CLR,
1331 .ue_clear_mask = ALTR_A10_L2_ECC_MERR_CLR,
1332 .irq_status_mask = A10_SYSMGR_ECC_INTSTAT_L2,
1333 .alloc_mem = l2_alloc_mem,
1334 .free_mem = l2_free_mem,
1335 .ecc_enable_mask = ALTR_A10_L2_ECC_EN_CTL,
1336 .ce_set_mask = ALTR_A10_L2_ECC_CE_INJ_MASK,
1337 .ue_set_mask = ALTR_A10_L2_ECC_UE_INJ_MASK,
1338 .set_err_ofst = ALTR_A10_L2_ECC_INJ_OFST,
1339 .ecc_irq_handler = altr_edac_a10_l2_irq,
1340 .trig_alloc_sz = ALTR_TRIG_L2C_BYTE_SIZE,
1341 .inject_fops = &altr_edac_device_inject_fops,
1342 };
1343
1344 #endif /* CONFIG_EDAC_ALTERA_L2C */
1345
1346 /********************* Ethernet Device Functions ********************/
1347
1348 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1349
socfpga_init_ethernet_ecc(struct altr_edac_device_dev * dev)1350 static int __init socfpga_init_ethernet_ecc(struct altr_edac_device_dev *dev)
1351 {
1352 int ret;
1353
1354 ret = altr_init_a10_ecc_device_type("altr,socfpga-eth-mac-ecc");
1355 if (ret)
1356 return ret;
1357
1358 return altr_check_ecc_deps(dev);
1359 }
1360
1361 static const struct edac_device_prv_data a10_enetecc_data = {
1362 .setup = socfpga_init_ethernet_ecc,
1363 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1364 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1365 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1366 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1367 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1368 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1369 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1370 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1371 .inject_fops = &altr_edac_a10_device_inject2_fops,
1372 };
1373
1374 #endif /* CONFIG_EDAC_ALTERA_ETHERNET */
1375
1376 /********************** NAND Device Functions **********************/
1377
1378 #ifdef CONFIG_EDAC_ALTERA_NAND
1379
socfpga_init_nand_ecc(struct altr_edac_device_dev * device)1380 static int __init socfpga_init_nand_ecc(struct altr_edac_device_dev *device)
1381 {
1382 int ret;
1383
1384 ret = altr_init_a10_ecc_device_type("altr,socfpga-nand-ecc");
1385 if (ret)
1386 return ret;
1387
1388 return altr_check_ecc_deps(device);
1389 }
1390
1391 static const struct edac_device_prv_data a10_nandecc_data = {
1392 .setup = socfpga_init_nand_ecc,
1393 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1394 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1395 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1396 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1397 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1398 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1399 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1400 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1401 .inject_fops = &altr_edac_a10_device_inject_fops,
1402 };
1403
1404 #endif /* CONFIG_EDAC_ALTERA_NAND */
1405
1406 /********************** DMA Device Functions **********************/
1407
1408 #ifdef CONFIG_EDAC_ALTERA_DMA
1409
socfpga_init_dma_ecc(struct altr_edac_device_dev * device)1410 static int __init socfpga_init_dma_ecc(struct altr_edac_device_dev *device)
1411 {
1412 int ret;
1413
1414 ret = altr_init_a10_ecc_device_type("altr,socfpga-dma-ecc");
1415 if (ret)
1416 return ret;
1417
1418 return altr_check_ecc_deps(device);
1419 }
1420
1421 static const struct edac_device_prv_data a10_dmaecc_data = {
1422 .setup = socfpga_init_dma_ecc,
1423 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1424 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1425 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1426 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1427 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1428 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1429 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1430 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1431 .inject_fops = &altr_edac_a10_device_inject_fops,
1432 };
1433
1434 #endif /* CONFIG_EDAC_ALTERA_DMA */
1435
1436 /********************** USB Device Functions **********************/
1437
1438 #ifdef CONFIG_EDAC_ALTERA_USB
1439
socfpga_init_usb_ecc(struct altr_edac_device_dev * device)1440 static int __init socfpga_init_usb_ecc(struct altr_edac_device_dev *device)
1441 {
1442 int ret;
1443
1444 ret = altr_init_a10_ecc_device_type("altr,socfpga-usb-ecc");
1445 if (ret)
1446 return ret;
1447
1448 return altr_check_ecc_deps(device);
1449 }
1450
1451 static const struct edac_device_prv_data a10_usbecc_data = {
1452 .setup = socfpga_init_usb_ecc,
1453 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1454 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1455 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1456 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1457 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1458 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1459 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1460 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1461 .inject_fops = &altr_edac_a10_device_inject2_fops,
1462 };
1463
1464 #endif /* CONFIG_EDAC_ALTERA_USB */
1465
1466 /********************** QSPI Device Functions **********************/
1467
1468 #ifdef CONFIG_EDAC_ALTERA_QSPI
1469
socfpga_init_qspi_ecc(struct altr_edac_device_dev * device)1470 static int __init socfpga_init_qspi_ecc(struct altr_edac_device_dev *device)
1471 {
1472 int ret;
1473
1474 ret = altr_init_a10_ecc_device_type("altr,socfpga-qspi-ecc");
1475 if (ret)
1476 return ret;
1477
1478 return altr_check_ecc_deps(device);
1479 }
1480
1481 static const struct edac_device_prv_data a10_qspiecc_data = {
1482 .setup = socfpga_init_qspi_ecc,
1483 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1484 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1485 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1486 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1487 .ce_set_mask = ALTR_A10_ECC_TSERRA,
1488 .ue_set_mask = ALTR_A10_ECC_TDERRA,
1489 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1490 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1491 .inject_fops = &altr_edac_a10_device_inject_fops,
1492 };
1493
1494 #endif /* CONFIG_EDAC_ALTERA_QSPI */
1495
1496 /********************* SDMMC Device Functions **********************/
1497
1498 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1499
1500 static const struct edac_device_prv_data a10_sdmmceccb_data;
altr_portb_setup(struct altr_edac_device_dev * device)1501 static int altr_portb_setup(struct altr_edac_device_dev *device)
1502 {
1503 struct edac_device_ctl_info *dci;
1504 struct altr_edac_device_dev *altdev;
1505 char *ecc_name = "sdmmcb-ecc";
1506 int edac_idx, rc;
1507 struct device_node *np;
1508 const struct edac_device_prv_data *prv = &a10_sdmmceccb_data;
1509
1510 rc = altr_check_ecc_deps(device);
1511 if (rc)
1512 return rc;
1513
1514 np = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1515 if (!np) {
1516 edac_printk(KERN_WARNING, EDAC_DEVICE, "SDMMC node not found\n");
1517 return -ENODEV;
1518 }
1519
1520 /* Create the PortB EDAC device */
1521 edac_idx = edac_device_alloc_index();
1522 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name, 1,
1523 ecc_name, 1, 0, NULL, 0, edac_idx);
1524 if (!dci) {
1525 edac_printk(KERN_ERR, EDAC_DEVICE,
1526 "%s: Unable to allocate PortB EDAC device\n",
1527 ecc_name);
1528 return -ENOMEM;
1529 }
1530
1531 /* Initialize the PortB EDAC device structure from PortA structure */
1532 altdev = dci->pvt_info;
1533 *altdev = *device;
1534
1535 if (!devres_open_group(&altdev->ddev, altr_portb_setup, GFP_KERNEL))
1536 return -ENOMEM;
1537
1538 /* Update PortB specific values */
1539 altdev->edac_dev_name = ecc_name;
1540 altdev->edac_idx = edac_idx;
1541 altdev->edac_dev = dci;
1542 altdev->data = prv;
1543 dci->dev = &altdev->ddev;
1544 dci->ctl_name = "Altera ECC Manager";
1545 dci->mod_name = ecc_name;
1546 dci->dev_name = ecc_name;
1547
1548 /*
1549 * Update the PortB IRQs - A10 has 4, S10 has 2, Index accordingly
1550 *
1551 * FIXME: Instead of ifdefs with different architectures the driver
1552 * should properly use compatibles.
1553 */
1554 #ifdef CONFIG_64BIT
1555 altdev->sb_irq = irq_of_parse_and_map(np, 1);
1556 #else
1557 altdev->sb_irq = irq_of_parse_and_map(np, 2);
1558 #endif
1559 if (!altdev->sb_irq) {
1560 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB SBIRQ alloc\n");
1561 rc = -ENODEV;
1562 goto err_release_group_1;
1563 }
1564 rc = devm_request_irq(&altdev->ddev, altdev->sb_irq,
1565 prv->ecc_irq_handler,
1566 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1567 ecc_name, altdev);
1568 if (rc) {
1569 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB SBERR IRQ error\n");
1570 goto err_release_group_1;
1571 }
1572
1573 #ifdef CONFIG_64BIT
1574 /* Use IRQ to determine SError origin instead of assigning IRQ */
1575 rc = of_property_read_u32_index(np, "interrupts", 1, &altdev->db_irq);
1576 if (rc) {
1577 edac_printk(KERN_ERR, EDAC_DEVICE,
1578 "Error PortB DBIRQ alloc\n");
1579 goto err_release_group_1;
1580 }
1581 #else
1582 altdev->db_irq = irq_of_parse_and_map(np, 3);
1583 if (!altdev->db_irq) {
1584 edac_printk(KERN_ERR, EDAC_DEVICE, "Error PortB DBIRQ alloc\n");
1585 rc = -ENODEV;
1586 goto err_release_group_1;
1587 }
1588 rc = devm_request_irq(&altdev->ddev, altdev->db_irq,
1589 prv->ecc_irq_handler,
1590 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1591 ecc_name, altdev);
1592 if (rc) {
1593 edac_printk(KERN_ERR, EDAC_DEVICE, "PortB DBERR IRQ error\n");
1594 goto err_release_group_1;
1595 }
1596 #endif
1597
1598 rc = edac_device_add_device(dci);
1599 if (rc) {
1600 edac_printk(KERN_ERR, EDAC_DEVICE,
1601 "edac_device_add_device portB failed\n");
1602 rc = -ENOMEM;
1603 goto err_release_group_1;
1604 }
1605 altr_create_edacdev_dbgfs(dci, prv);
1606
1607 list_add(&altdev->next, &altdev->edac->a10_ecc_devices);
1608
1609 devres_remove_group(&altdev->ddev, altr_portb_setup);
1610
1611 return 0;
1612
1613 err_release_group_1:
1614 edac_device_free_ctl_info(dci);
1615 devres_release_group(&altdev->ddev, altr_portb_setup);
1616 edac_printk(KERN_ERR, EDAC_DEVICE,
1617 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
1618 return rc;
1619 }
1620
socfpga_init_sdmmc_ecc(struct altr_edac_device_dev * device)1621 static int __init socfpga_init_sdmmc_ecc(struct altr_edac_device_dev *device)
1622 {
1623 int rc = -ENODEV;
1624 struct device_node *child;
1625
1626 child = of_find_compatible_node(NULL, NULL, "altr,socfpga-sdmmc-ecc");
1627 if (!child)
1628 return -ENODEV;
1629
1630 if (!of_device_is_available(child))
1631 goto exit;
1632
1633 if (validate_parent_available(child))
1634 goto exit;
1635
1636 /* Init portB */
1637 rc = altr_init_a10_ecc_block(child, ALTR_A10_SDMMC_IRQ_MASK,
1638 a10_sdmmceccb_data.ecc_enable_mask, 1);
1639 if (rc)
1640 goto exit;
1641
1642 /* Setup portB */
1643 return altr_portb_setup(device);
1644
1645 exit:
1646 of_node_put(child);
1647 return rc;
1648 }
1649
altr_edac_a10_ecc_irq_portb(int irq,void * dev_id)1650 static irqreturn_t altr_edac_a10_ecc_irq_portb(int irq, void *dev_id)
1651 {
1652 struct altr_edac_device_dev *ad = dev_id;
1653 void __iomem *base = ad->base;
1654 const struct edac_device_prv_data *priv = ad->data;
1655
1656 if (irq == ad->sb_irq) {
1657 writel(priv->ce_clear_mask,
1658 base + ALTR_A10_ECC_INTSTAT_OFST);
1659 edac_device_handle_ce(ad->edac_dev, 0, 0, ad->edac_dev_name);
1660 return IRQ_HANDLED;
1661 } else if (irq == ad->db_irq) {
1662 writel(priv->ue_clear_mask,
1663 base + ALTR_A10_ECC_INTSTAT_OFST);
1664 edac_device_handle_ue(ad->edac_dev, 0, 0, ad->edac_dev_name);
1665 return IRQ_HANDLED;
1666 }
1667
1668 WARN_ONCE(1, "Unhandled IRQ%d on Port B.", irq);
1669
1670 return IRQ_NONE;
1671 }
1672
1673 static const struct edac_device_prv_data a10_sdmmcecca_data = {
1674 .setup = socfpga_init_sdmmc_ecc,
1675 .ce_clear_mask = ALTR_A10_ECC_SERRPENA,
1676 .ue_clear_mask = ALTR_A10_ECC_DERRPENA,
1677 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1678 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1679 .ce_set_mask = ALTR_A10_ECC_SERRPENA,
1680 .ue_set_mask = ALTR_A10_ECC_DERRPENA,
1681 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1682 .ecc_irq_handler = altr_edac_a10_ecc_irq,
1683 .inject_fops = &altr_edac_a10_device_inject_fops,
1684 };
1685
1686 static const struct edac_device_prv_data a10_sdmmceccb_data = {
1687 .setup = socfpga_init_sdmmc_ecc,
1688 .ce_clear_mask = ALTR_A10_ECC_SERRPENB,
1689 .ue_clear_mask = ALTR_A10_ECC_DERRPENB,
1690 .ecc_enable_mask = ALTR_A10_COMMON_ECC_EN_CTL,
1691 .ecc_en_ofst = ALTR_A10_ECC_CTRL_OFST,
1692 .ce_set_mask = ALTR_A10_ECC_TSERRB,
1693 .ue_set_mask = ALTR_A10_ECC_TDERRB,
1694 .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
1695 .ecc_irq_handler = altr_edac_a10_ecc_irq_portb,
1696 .inject_fops = &altr_edac_a10_device_inject_fops,
1697 };
1698
1699 #endif /* CONFIG_EDAC_ALTERA_SDMMC */
1700
1701 /********************* Arria10 EDAC Device Functions *************************/
1702 static const struct of_device_id altr_edac_a10_device_of_match[] = {
1703 #ifdef CONFIG_EDAC_ALTERA_L2C
1704 { .compatible = "altr,socfpga-a10-l2-ecc", .data = &a10_l2ecc_data },
1705 #endif
1706 #ifdef CONFIG_EDAC_ALTERA_OCRAM
1707 { .compatible = "altr,socfpga-a10-ocram-ecc",
1708 .data = &a10_ocramecc_data },
1709 #endif
1710 #ifdef CONFIG_EDAC_ALTERA_ETHERNET
1711 { .compatible = "altr,socfpga-eth-mac-ecc",
1712 .data = &a10_enetecc_data },
1713 #endif
1714 #ifdef CONFIG_EDAC_ALTERA_NAND
1715 { .compatible = "altr,socfpga-nand-ecc", .data = &a10_nandecc_data },
1716 #endif
1717 #ifdef CONFIG_EDAC_ALTERA_DMA
1718 { .compatible = "altr,socfpga-dma-ecc", .data = &a10_dmaecc_data },
1719 #endif
1720 #ifdef CONFIG_EDAC_ALTERA_USB
1721 { .compatible = "altr,socfpga-usb-ecc", .data = &a10_usbecc_data },
1722 #endif
1723 #ifdef CONFIG_EDAC_ALTERA_QSPI
1724 { .compatible = "altr,socfpga-qspi-ecc", .data = &a10_qspiecc_data },
1725 #endif
1726 #ifdef CONFIG_EDAC_ALTERA_SDMMC
1727 { .compatible = "altr,socfpga-sdmmc-ecc", .data = &a10_sdmmcecca_data },
1728 #endif
1729 #ifdef CONFIG_EDAC_ALTERA_SDRAM
1730 { .compatible = "altr,sdram-edac-s10", .data = &s10_sdramecc_data },
1731 #endif
1732 {},
1733 };
1734 MODULE_DEVICE_TABLE(of, altr_edac_a10_device_of_match);
1735
1736 /*
1737 * The Arria10 EDAC Device Functions differ from the Cyclone5/Arria5
1738 * because 2 IRQs are shared among the all ECC peripherals. The ECC
1739 * manager manages the IRQs and the children.
1740 * Based on xgene_edac.c peripheral code.
1741 */
1742
1743 static ssize_t __maybe_unused
altr_edac_a10_device_trig(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)1744 altr_edac_a10_device_trig(struct file *file, const char __user *user_buf,
1745 size_t count, loff_t *ppos)
1746 {
1747 struct edac_device_ctl_info *edac_dci = file->private_data;
1748 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1749 const struct edac_device_prv_data *priv = drvdata->data;
1750 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1751 unsigned long flags;
1752 u8 trig_type;
1753
1754 if (!user_buf || get_user(trig_type, user_buf))
1755 return -EFAULT;
1756
1757 local_irq_save(flags);
1758 if (trig_type == ALTR_UE_TRIGGER_CHAR)
1759 writew(priv->ue_set_mask, set_addr);
1760 else
1761 writew(priv->ce_set_mask, set_addr);
1762
1763 /* Ensure the interrupt test bits are set */
1764 wmb();
1765 local_irq_restore(flags);
1766
1767 return count;
1768 }
1769
1770 /*
1771 * The Stratix10 EDAC Error Injection Functions differ from Arria10
1772 * slightly. A few Arria10 peripherals can use this injection function.
1773 * Inject the error into the memory and then readback to trigger the IRQ.
1774 */
1775 static ssize_t __maybe_unused
altr_edac_a10_device_trig2(struct file * file,const char __user * user_buf,size_t count,loff_t * ppos)1776 altr_edac_a10_device_trig2(struct file *file, const char __user *user_buf,
1777 size_t count, loff_t *ppos)
1778 {
1779 struct edac_device_ctl_info *edac_dci = file->private_data;
1780 struct altr_edac_device_dev *drvdata = edac_dci->pvt_info;
1781 const struct edac_device_prv_data *priv = drvdata->data;
1782 void __iomem *set_addr = (drvdata->base + priv->set_err_ofst);
1783 unsigned long flags;
1784 u8 trig_type;
1785
1786 if (!user_buf || get_user(trig_type, user_buf))
1787 return -EFAULT;
1788
1789 local_irq_save(flags);
1790 if (trig_type == ALTR_UE_TRIGGER_CHAR) {
1791 writew(priv->ue_set_mask, set_addr);
1792 } else {
1793 /* Setup read/write of 4 bytes */
1794 writel(ECC_WORD_WRITE, drvdata->base + ECC_BLK_DBYTECTRL_OFST);
1795 /* Setup Address to 0 */
1796 writel(0, drvdata->base + ECC_BLK_ADDRESS_OFST);
1797 /* Setup accctrl to read & ecc & data override */
1798 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1799 /* Kick it. */
1800 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1801 /* Setup write for single bit change */
1802 writel(readl(drvdata->base + ECC_BLK_RDATA0_OFST) ^ 0x1,
1803 drvdata->base + ECC_BLK_WDATA0_OFST);
1804 writel(readl(drvdata->base + ECC_BLK_RDATA1_OFST),
1805 drvdata->base + ECC_BLK_WDATA1_OFST);
1806 writel(readl(drvdata->base + ECC_BLK_RDATA2_OFST),
1807 drvdata->base + ECC_BLK_WDATA2_OFST);
1808 writel(readl(drvdata->base + ECC_BLK_RDATA3_OFST),
1809 drvdata->base + ECC_BLK_WDATA3_OFST);
1810
1811 /* Copy Read ECC to Write ECC */
1812 writel(readl(drvdata->base + ECC_BLK_RECC0_OFST),
1813 drvdata->base + ECC_BLK_WECC0_OFST);
1814 writel(readl(drvdata->base + ECC_BLK_RECC1_OFST),
1815 drvdata->base + ECC_BLK_WECC1_OFST);
1816 /* Setup accctrl to write & ecc override & data override */
1817 writel(ECC_WRITE_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1818 /* Kick it. */
1819 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1820 /* Setup accctrl to read & ecc overwrite & data overwrite */
1821 writel(ECC_READ_EDOVR, drvdata->base + ECC_BLK_ACCCTRL_OFST);
1822 /* Kick it. */
1823 writel(ECC_XACT_KICK, drvdata->base + ECC_BLK_STARTACC_OFST);
1824 }
1825
1826 /* Ensure the interrupt test bits are set */
1827 wmb();
1828 local_irq_restore(flags);
1829
1830 return count;
1831 }
1832
altr_edac_a10_irq_handler(struct irq_desc * desc)1833 static void altr_edac_a10_irq_handler(struct irq_desc *desc)
1834 {
1835 int dberr, bit, sm_offset, irq_status;
1836 struct altr_arria10_edac *edac = irq_desc_get_handler_data(desc);
1837 struct irq_chip *chip = irq_desc_get_chip(desc);
1838 int irq = irq_desc_get_irq(desc);
1839 unsigned long bits;
1840
1841 dberr = (irq == edac->db_irq) ? 1 : 0;
1842 sm_offset = dberr ? A10_SYSMGR_ECC_INTSTAT_DERR_OFST :
1843 A10_SYSMGR_ECC_INTSTAT_SERR_OFST;
1844
1845 chained_irq_enter(chip, desc);
1846
1847 regmap_read(edac->ecc_mgr_map, sm_offset, &irq_status);
1848
1849 bits = irq_status;
1850 for_each_set_bit(bit, &bits, 32)
1851 generic_handle_domain_irq(edac->domain, dberr * 32 + bit);
1852
1853 chained_irq_exit(chip, desc);
1854 }
1855
validate_parent_available(struct device_node * np)1856 static int validate_parent_available(struct device_node *np)
1857 {
1858 struct device_node *parent;
1859 int ret = 0;
1860
1861 /* SDRAM must be present for Linux (implied parent) */
1862 if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1863 return 0;
1864
1865 /* Ensure parent device is enabled if parent node exists */
1866 parent = of_parse_phandle(np, "altr,ecc-parent", 0);
1867 if (parent && !of_device_is_available(parent))
1868 ret = -ENODEV;
1869
1870 of_node_put(parent);
1871 return ret;
1872 }
1873
get_s10_sdram_edac_resource(struct device_node * np,struct resource * res)1874 static int get_s10_sdram_edac_resource(struct device_node *np,
1875 struct resource *res)
1876 {
1877 struct device_node *parent;
1878 int ret;
1879
1880 parent = of_parse_phandle(np, "altr,sdr-syscon", 0);
1881 if (!parent)
1882 return -ENODEV;
1883
1884 ret = of_address_to_resource(parent, 0, res);
1885 of_node_put(parent);
1886
1887 return ret;
1888 }
1889
altr_edac_a10_device_add(struct altr_arria10_edac * edac,struct device_node * np)1890 static int altr_edac_a10_device_add(struct altr_arria10_edac *edac,
1891 struct device_node *np)
1892 {
1893 struct edac_device_ctl_info *dci;
1894 struct altr_edac_device_dev *altdev;
1895 char *ecc_name = (char *)np->name;
1896 struct resource res;
1897 int edac_idx;
1898 int rc = 0;
1899 const struct edac_device_prv_data *prv;
1900 /* Get matching node and check for valid result */
1901 const struct of_device_id *pdev_id =
1902 of_match_node(altr_edac_a10_device_of_match, np);
1903 if (IS_ERR_OR_NULL(pdev_id))
1904 return -ENODEV;
1905
1906 /* Get driver specific data for this EDAC device */
1907 prv = pdev_id->data;
1908 if (IS_ERR_OR_NULL(prv))
1909 return -ENODEV;
1910
1911 if (validate_parent_available(np))
1912 return -ENODEV;
1913
1914 if (!devres_open_group(edac->dev, altr_edac_a10_device_add, GFP_KERNEL))
1915 return -ENOMEM;
1916
1917 if (of_device_is_compatible(np, "altr,sdram-edac-s10"))
1918 rc = get_s10_sdram_edac_resource(np, &res);
1919 else
1920 rc = of_address_to_resource(np, 0, &res);
1921
1922 if (rc < 0) {
1923 edac_printk(KERN_ERR, EDAC_DEVICE,
1924 "%s: no resource address\n", ecc_name);
1925 goto err_release_group;
1926 }
1927
1928 edac_idx = edac_device_alloc_index();
1929 dci = edac_device_alloc_ctl_info(sizeof(*altdev), ecc_name,
1930 1, ecc_name, 1, 0, NULL, 0,
1931 edac_idx);
1932
1933 if (!dci) {
1934 edac_printk(KERN_ERR, EDAC_DEVICE,
1935 "%s: Unable to allocate EDAC device\n", ecc_name);
1936 rc = -ENOMEM;
1937 goto err_release_group;
1938 }
1939
1940 altdev = dci->pvt_info;
1941 dci->dev = edac->dev;
1942 altdev->edac_dev_name = ecc_name;
1943 altdev->edac_idx = edac_idx;
1944 altdev->edac = edac;
1945 altdev->edac_dev = dci;
1946 altdev->data = prv;
1947 altdev->ddev = *edac->dev;
1948 dci->dev = &altdev->ddev;
1949 dci->ctl_name = "Altera ECC Manager";
1950 dci->mod_name = ecc_name;
1951 dci->dev_name = ecc_name;
1952
1953 altdev->base = devm_ioremap_resource(edac->dev, &res);
1954 if (IS_ERR(altdev->base)) {
1955 rc = PTR_ERR(altdev->base);
1956 goto err_release_group1;
1957 }
1958
1959 /* Check specific dependencies for the module */
1960 if (altdev->data->setup) {
1961 rc = altdev->data->setup(altdev);
1962 if (rc)
1963 goto err_release_group1;
1964 }
1965
1966 altdev->sb_irq = irq_of_parse_and_map(np, 0);
1967 if (!altdev->sb_irq) {
1968 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating SBIRQ\n");
1969 rc = -ENODEV;
1970 goto err_release_group1;
1971 }
1972 rc = devm_request_irq(edac->dev, altdev->sb_irq, prv->ecc_irq_handler,
1973 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1974 ecc_name, altdev);
1975 if (rc) {
1976 edac_printk(KERN_ERR, EDAC_DEVICE, "No SBERR IRQ resource\n");
1977 goto err_release_group1;
1978 }
1979
1980 #ifdef CONFIG_64BIT
1981 /* Use IRQ to determine SError origin instead of assigning IRQ */
1982 rc = of_property_read_u32_index(np, "interrupts", 0, &altdev->db_irq);
1983 if (rc) {
1984 edac_printk(KERN_ERR, EDAC_DEVICE,
1985 "Unable to parse DB IRQ index\n");
1986 goto err_release_group1;
1987 }
1988 #else
1989 altdev->db_irq = irq_of_parse_and_map(np, 1);
1990 if (!altdev->db_irq) {
1991 edac_printk(KERN_ERR, EDAC_DEVICE, "Error allocating DBIRQ\n");
1992 rc = -ENODEV;
1993 goto err_release_group1;
1994 }
1995 rc = devm_request_irq(edac->dev, altdev->db_irq, prv->ecc_irq_handler,
1996 IRQF_ONESHOT | IRQF_TRIGGER_HIGH,
1997 ecc_name, altdev);
1998 if (rc) {
1999 edac_printk(KERN_ERR, EDAC_DEVICE, "No DBERR IRQ resource\n");
2000 goto err_release_group1;
2001 }
2002 #endif
2003
2004 rc = edac_device_add_device(dci);
2005 if (rc) {
2006 dev_err(edac->dev, "edac_device_add_device failed\n");
2007 rc = -ENOMEM;
2008 goto err_release_group1;
2009 }
2010
2011 altr_create_edacdev_dbgfs(dci, prv);
2012
2013 list_add(&altdev->next, &edac->a10_ecc_devices);
2014
2015 devres_remove_group(edac->dev, altr_edac_a10_device_add);
2016
2017 return 0;
2018
2019 err_release_group1:
2020 edac_device_free_ctl_info(dci);
2021 err_release_group:
2022 devres_release_group(edac->dev, NULL);
2023 edac_printk(KERN_ERR, EDAC_DEVICE,
2024 "%s:Error setting up EDAC device: %d\n", ecc_name, rc);
2025
2026 return rc;
2027 }
2028
a10_eccmgr_irq_mask(struct irq_data * d)2029 static void a10_eccmgr_irq_mask(struct irq_data *d)
2030 {
2031 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2032
2033 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
2034 BIT(d->hwirq));
2035 }
2036
a10_eccmgr_irq_unmask(struct irq_data * d)2037 static void a10_eccmgr_irq_unmask(struct irq_data *d)
2038 {
2039 struct altr_arria10_edac *edac = irq_data_get_irq_chip_data(d);
2040
2041 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_CLR_OFST,
2042 BIT(d->hwirq));
2043 }
2044
a10_eccmgr_irqdomain_map(struct irq_domain * d,unsigned int irq,irq_hw_number_t hwirq)2045 static int a10_eccmgr_irqdomain_map(struct irq_domain *d, unsigned int irq,
2046 irq_hw_number_t hwirq)
2047 {
2048 struct altr_arria10_edac *edac = d->host_data;
2049
2050 irq_set_chip_and_handler(irq, &edac->irq_chip, handle_simple_irq);
2051 irq_set_chip_data(irq, edac);
2052 irq_set_noprobe(irq);
2053
2054 return 0;
2055 }
2056
2057 static const struct irq_domain_ops a10_eccmgr_ic_ops = {
2058 .map = a10_eccmgr_irqdomain_map,
2059 .xlate = irq_domain_xlate_twocell,
2060 };
2061
2062 /************** Stratix 10 EDAC Double Bit Error Handler ************/
2063 #define to_a10edac(p, m) container_of(p, struct altr_arria10_edac, m)
2064
2065 #ifdef CONFIG_64BIT
2066 /* panic routine issues reboot on non-zero panic_timeout */
2067 extern int panic_timeout;
2068
2069 /*
2070 * The double bit error is handled through SError which is fatal. This is
2071 * called as a panic notifier to printout ECC error info as part of the panic.
2072 */
s10_edac_dberr_handler(struct notifier_block * this,unsigned long event,void * ptr)2073 static int s10_edac_dberr_handler(struct notifier_block *this,
2074 unsigned long event, void *ptr)
2075 {
2076 struct altr_arria10_edac *edac = to_a10edac(this, panic_notifier);
2077 int err_addr, dberror;
2078
2079 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_ECC_INTSTAT_DERR_OFST,
2080 &dberror);
2081 regmap_write(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST, dberror);
2082 if (dberror & S10_DBE_IRQ_MASK) {
2083 struct list_head *position;
2084 struct altr_edac_device_dev *ed;
2085 struct arm_smccc_res result;
2086
2087 /* Find the matching DBE in the list of devices */
2088 list_for_each(position, &edac->a10_ecc_devices) {
2089 ed = list_entry(position, struct altr_edac_device_dev,
2090 next);
2091 if (!(BIT(ed->db_irq) & dberror))
2092 continue;
2093
2094 writel(ALTR_A10_ECC_DERRPENA,
2095 ed->base + ALTR_A10_ECC_INTSTAT_OFST);
2096 err_addr = readl(ed->base + ALTR_S10_DERR_ADDRA_OFST);
2097 regmap_write(edac->ecc_mgr_map,
2098 S10_SYSMGR_UE_ADDR_OFST, err_addr);
2099 edac_printk(KERN_ERR, EDAC_DEVICE,
2100 "EDAC: [Fatal DBE on %s @ 0x%08X]\n",
2101 ed->edac_dev_name, err_addr);
2102 break;
2103 }
2104 /* Notify the System through SMC. Reboot delay = 1 second */
2105 panic_timeout = 1;
2106 arm_smccc_smc(INTEL_SIP_SMC_ECC_DBE, dberror, 0, 0, 0, 0,
2107 0, 0, &result);
2108 }
2109
2110 return NOTIFY_DONE;
2111 }
2112 #endif
2113
2114 /****************** Arria 10 EDAC Probe Function *********************/
altr_edac_a10_probe(struct platform_device * pdev)2115 static int altr_edac_a10_probe(struct platform_device *pdev)
2116 {
2117 struct altr_arria10_edac *edac;
2118 struct device_node *child;
2119
2120 edac = devm_kzalloc(&pdev->dev, sizeof(*edac), GFP_KERNEL);
2121 if (!edac)
2122 return -ENOMEM;
2123
2124 edac->dev = &pdev->dev;
2125 platform_set_drvdata(pdev, edac);
2126 INIT_LIST_HEAD(&edac->a10_ecc_devices);
2127
2128 edac->ecc_mgr_map =
2129 altr_sysmgr_regmap_lookup_by_phandle(pdev->dev.of_node,
2130 "altr,sysmgr-syscon");
2131
2132 if (IS_ERR(edac->ecc_mgr_map)) {
2133 edac_printk(KERN_ERR, EDAC_DEVICE,
2134 "Unable to get syscon altr,sysmgr-syscon\n");
2135 return PTR_ERR(edac->ecc_mgr_map);
2136 }
2137
2138 /* Set irq mask for DDR SBE to avoid any pending irq before registration */
2139 regmap_write(edac->ecc_mgr_map, A10_SYSMGR_ECC_INTMASK_SET_OFST,
2140 (A10_SYSMGR_ECC_INTMASK_SDMMCB | A10_SYSMGR_ECC_INTMASK_DDR0));
2141
2142 edac->irq_chip.name = pdev->dev.of_node->name;
2143 edac->irq_chip.irq_mask = a10_eccmgr_irq_mask;
2144 edac->irq_chip.irq_unmask = a10_eccmgr_irq_unmask;
2145 edac->domain = irq_domain_add_linear(pdev->dev.of_node, 64,
2146 &a10_eccmgr_ic_ops, edac);
2147 if (!edac->domain) {
2148 dev_err(&pdev->dev, "Error adding IRQ domain\n");
2149 return -ENOMEM;
2150 }
2151
2152 edac->sb_irq = platform_get_irq(pdev, 0);
2153 if (edac->sb_irq < 0)
2154 return edac->sb_irq;
2155
2156 irq_set_chained_handler_and_data(edac->sb_irq,
2157 altr_edac_a10_irq_handler,
2158 edac);
2159
2160 #ifdef CONFIG_64BIT
2161 {
2162 int dberror, err_addr;
2163
2164 edac->panic_notifier.notifier_call = s10_edac_dberr_handler;
2165 atomic_notifier_chain_register(&panic_notifier_list,
2166 &edac->panic_notifier);
2167
2168 /* Printout a message if uncorrectable error previously. */
2169 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_VAL_OFST,
2170 &dberror);
2171 if (dberror) {
2172 regmap_read(edac->ecc_mgr_map, S10_SYSMGR_UE_ADDR_OFST,
2173 &err_addr);
2174 edac_printk(KERN_ERR, EDAC_DEVICE,
2175 "Previous Boot UE detected[0x%X] @ 0x%X\n",
2176 dberror, err_addr);
2177 /* Reset the sticky registers */
2178 regmap_write(edac->ecc_mgr_map,
2179 S10_SYSMGR_UE_VAL_OFST, 0);
2180 regmap_write(edac->ecc_mgr_map,
2181 S10_SYSMGR_UE_ADDR_OFST, 0);
2182 }
2183 }
2184 #else
2185 edac->db_irq = platform_get_irq(pdev, 1);
2186 if (edac->db_irq < 0)
2187 return edac->db_irq;
2188
2189 irq_set_chained_handler_and_data(edac->db_irq,
2190 altr_edac_a10_irq_handler, edac);
2191 #endif
2192
2193 for_each_child_of_node(pdev->dev.of_node, child) {
2194 if (!of_device_is_available(child))
2195 continue;
2196
2197 if (of_match_node(altr_edac_a10_device_of_match, child))
2198 altr_edac_a10_device_add(edac, child);
2199
2200 #ifdef CONFIG_EDAC_ALTERA_SDRAM
2201 else if (of_device_is_compatible(child, "altr,sdram-edac-a10"))
2202 of_platform_populate(pdev->dev.of_node,
2203 altr_sdram_ctrl_of_match,
2204 NULL, &pdev->dev);
2205 #endif
2206 }
2207
2208 return 0;
2209 }
2210
2211 static const struct of_device_id altr_edac_a10_of_match[] = {
2212 { .compatible = "altr,socfpga-a10-ecc-manager" },
2213 { .compatible = "altr,socfpga-s10-ecc-manager" },
2214 {},
2215 };
2216 MODULE_DEVICE_TABLE(of, altr_edac_a10_of_match);
2217
2218 static struct platform_driver altr_edac_a10_driver = {
2219 .probe = altr_edac_a10_probe,
2220 .driver = {
2221 .name = "socfpga_a10_ecc_manager",
2222 .of_match_table = altr_edac_a10_of_match,
2223 },
2224 };
2225 module_platform_driver(altr_edac_a10_driver);
2226
2227 MODULE_AUTHOR("Thor Thayer");
2228 MODULE_DESCRIPTION("EDAC Driver for Altera Memories");
2229