1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <linux/firmware.h>
24 #include <linux/slab.h>
25 #include <linux/module.h>
26 #include <linux/pci.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_atombios.h"
30 #include "amdgpu_ih.h"
31 #include "amdgpu_uvd.h"
32 #include "amdgpu_vce.h"
33 #include "amdgpu_ucode.h"
34 #include "amdgpu_psp.h"
35 #include "amdgpu_smu.h"
36 #include "atom.h"
37 #include "amd_pcie.h"
38
39 #include "gc/gc_11_0_0_offset.h"
40 #include "gc/gc_11_0_0_sh_mask.h"
41 #include "mp/mp_13_0_0_offset.h"
42
43 #include "soc15.h"
44 #include "soc15_common.h"
45 #include "soc21.h"
46 #include "mxgpu_nv.h"
47
48 static const struct amd_ip_funcs soc21_common_ip_funcs;
49
50 /* SOC21 */
51 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
52 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
53 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
54 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
55 };
56
57 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
58 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
59 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 0)},
60 };
61
62 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn0 = {
63 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn0),
64 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn0,
65 };
66
67 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_encode_vcn1 = {
68 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_encode_array_vcn1),
69 .codec_array = vcn_4_0_0_video_codecs_encode_array_vcn1,
70 };
71
72 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
73 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
74 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
75 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
76 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
77 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
78 };
79
80 static const struct amdgpu_video_codec_info vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
81 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
82 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
83 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 4096, 4096, 0)},
84 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
85 };
86
87 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn0 = {
88 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn0),
89 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn0,
90 };
91
92 static const struct amdgpu_video_codecs vcn_4_0_0_video_codecs_decode_vcn1 = {
93 .codec_count = ARRAY_SIZE(vcn_4_0_0_video_codecs_decode_array_vcn1),
94 .codec_array = vcn_4_0_0_video_codecs_decode_array_vcn1,
95 };
96
97 /* SRIOV SOC21, not const since data is controlled by host */
98 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn0[] = {
99 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
100 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
101 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
102 };
103
104 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_encode_array_vcn1[] = {
105 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 2304, 0)},
106 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 4096, 2304, 0)},
107 };
108
109 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn0 = {
110 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
111 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
112 };
113
114 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_encode_vcn1 = {
115 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
116 .codec_array = sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
117 };
118
119 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn0[] = {
120 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
121 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
122 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
123 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
124 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1, 8192, 4352, 0)},
125 };
126
127 static struct amdgpu_video_codec_info sriov_vcn_4_0_0_video_codecs_decode_array_vcn1[] = {
128 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC, 4096, 4096, 52)},
129 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC, 8192, 4352, 186)},
130 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG, 16384, 16384, 0)},
131 {codec_info_build(AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9, 8192, 4352, 0)},
132 };
133
134 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn0 = {
135 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0),
136 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
137 };
138
139 static struct amdgpu_video_codecs sriov_vcn_4_0_0_video_codecs_decode_vcn1 = {
140 .codec_count = ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1),
141 .codec_array = sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
142 };
143
soc21_query_video_codecs(struct amdgpu_device * adev,bool encode,const struct amdgpu_video_codecs ** codecs)144 static int soc21_query_video_codecs(struct amdgpu_device *adev, bool encode,
145 const struct amdgpu_video_codecs **codecs)
146 {
147 if (adev->vcn.num_vcn_inst == hweight8(adev->vcn.harvest_config))
148 return -EINVAL;
149
150 switch (adev->ip_versions[UVD_HWIP][0]) {
151 case IP_VERSION(4, 0, 0):
152 case IP_VERSION(4, 0, 2):
153 case IP_VERSION(4, 0, 4):
154 if (amdgpu_sriov_vf(adev)) {
155 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
156 !amdgpu_sriov_is_av1_support(adev)) {
157 if (encode)
158 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn1;
159 else
160 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn1;
161 } else {
162 if (encode)
163 *codecs = &sriov_vcn_4_0_0_video_codecs_encode_vcn0;
164 else
165 *codecs = &sriov_vcn_4_0_0_video_codecs_decode_vcn0;
166 }
167 } else {
168 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0)) {
169 if (encode)
170 *codecs = &vcn_4_0_0_video_codecs_encode_vcn1;
171 else
172 *codecs = &vcn_4_0_0_video_codecs_decode_vcn1;
173 } else {
174 if (encode)
175 *codecs = &vcn_4_0_0_video_codecs_encode_vcn0;
176 else
177 *codecs = &vcn_4_0_0_video_codecs_decode_vcn0;
178 }
179 }
180 return 0;
181 default:
182 return -EINVAL;
183 }
184 }
185
soc21_didt_rreg(struct amdgpu_device * adev,u32 reg)186 static u32 soc21_didt_rreg(struct amdgpu_device *adev, u32 reg)
187 {
188 unsigned long flags, address, data;
189 u32 r;
190
191 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
192 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
193
194 spin_lock_irqsave(&adev->didt_idx_lock, flags);
195 WREG32(address, (reg));
196 r = RREG32(data);
197 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
198 return r;
199 }
200
soc21_didt_wreg(struct amdgpu_device * adev,u32 reg,u32 v)201 static void soc21_didt_wreg(struct amdgpu_device *adev, u32 reg, u32 v)
202 {
203 unsigned long flags, address, data;
204
205 address = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_INDEX);
206 data = SOC15_REG_OFFSET(GC, 0, regDIDT_IND_DATA);
207
208 spin_lock_irqsave(&adev->didt_idx_lock, flags);
209 WREG32(address, (reg));
210 WREG32(data, (v));
211 spin_unlock_irqrestore(&adev->didt_idx_lock, flags);
212 }
213
soc21_get_config_memsize(struct amdgpu_device * adev)214 static u32 soc21_get_config_memsize(struct amdgpu_device *adev)
215 {
216 return adev->nbio.funcs->get_memsize(adev);
217 }
218
soc21_get_xclk(struct amdgpu_device * adev)219 static u32 soc21_get_xclk(struct amdgpu_device *adev)
220 {
221 return adev->clock.spll.reference_freq;
222 }
223
224
soc21_grbm_select(struct amdgpu_device * adev,u32 me,u32 pipe,u32 queue,u32 vmid)225 void soc21_grbm_select(struct amdgpu_device *adev,
226 u32 me, u32 pipe, u32 queue, u32 vmid)
227 {
228 u32 grbm_gfx_cntl = 0;
229 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, PIPEID, pipe);
230 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, MEID, me);
231 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, VMID, vmid);
232 grbm_gfx_cntl = REG_SET_FIELD(grbm_gfx_cntl, GRBM_GFX_CNTL, QUEUEID, queue);
233
234 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, grbm_gfx_cntl);
235 }
236
soc21_read_disabled_bios(struct amdgpu_device * adev)237 static bool soc21_read_disabled_bios(struct amdgpu_device *adev)
238 {
239 /* todo */
240 return false;
241 }
242
243 static struct soc15_allowed_register_entry soc21_allowed_read_registers[] = {
244 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS)},
245 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS2)},
246 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE0)},
247 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE1)},
248 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE2)},
249 { SOC15_REG_ENTRY(GC, 0, regGRBM_STATUS_SE3)},
250 { SOC15_REG_ENTRY(SDMA0, 0, regSDMA0_STATUS_REG)},
251 { SOC15_REG_ENTRY(SDMA1, 0, regSDMA1_STATUS_REG)},
252 { SOC15_REG_ENTRY(GC, 0, regCP_STAT)},
253 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT1)},
254 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT2)},
255 { SOC15_REG_ENTRY(GC, 0, regCP_STALLED_STAT3)},
256 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_BUSY_STAT)},
257 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STALLED_STAT1)},
258 { SOC15_REG_ENTRY(GC, 0, regCP_CPF_STATUS)},
259 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_BUSY_STAT)},
260 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STALLED_STAT1)},
261 { SOC15_REG_ENTRY(GC, 0, regCP_CPC_STATUS)},
262 { SOC15_REG_ENTRY(GC, 0, regGB_ADDR_CONFIG)},
263 };
264
soc21_read_indexed_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset)265 static uint32_t soc21_read_indexed_register(struct amdgpu_device *adev, u32 se_num,
266 u32 sh_num, u32 reg_offset)
267 {
268 uint32_t val;
269
270 mutex_lock(&adev->grbm_idx_mutex);
271 if (se_num != 0xffffffff || sh_num != 0xffffffff)
272 amdgpu_gfx_select_se_sh(adev, se_num, sh_num, 0xffffffff, 0);
273
274 val = RREG32(reg_offset);
275
276 if (se_num != 0xffffffff || sh_num != 0xffffffff)
277 amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
278 mutex_unlock(&adev->grbm_idx_mutex);
279 return val;
280 }
281
soc21_get_register_value(struct amdgpu_device * adev,bool indexed,u32 se_num,u32 sh_num,u32 reg_offset)282 static uint32_t soc21_get_register_value(struct amdgpu_device *adev,
283 bool indexed, u32 se_num,
284 u32 sh_num, u32 reg_offset)
285 {
286 if (indexed) {
287 return soc21_read_indexed_register(adev, se_num, sh_num, reg_offset);
288 } else {
289 if (reg_offset == SOC15_REG_OFFSET(GC, 0, regGB_ADDR_CONFIG) && adev->gfx.config.gb_addr_config)
290 return adev->gfx.config.gb_addr_config;
291 return RREG32(reg_offset);
292 }
293 }
294
soc21_read_register(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 reg_offset,u32 * value)295 static int soc21_read_register(struct amdgpu_device *adev, u32 se_num,
296 u32 sh_num, u32 reg_offset, u32 *value)
297 {
298 uint32_t i;
299 struct soc15_allowed_register_entry *en;
300
301 *value = 0;
302 for (i = 0; i < ARRAY_SIZE(soc21_allowed_read_registers); i++) {
303 en = &soc21_allowed_read_registers[i];
304 if (!adev->reg_offset[en->hwip][en->inst])
305 continue;
306 else if (reg_offset != (adev->reg_offset[en->hwip][en->inst][en->seg]
307 + en->reg_offset))
308 continue;
309
310 *value = soc21_get_register_value(adev,
311 soc21_allowed_read_registers[i].grbm_indexed,
312 se_num, sh_num, reg_offset);
313 return 0;
314 }
315 return -EINVAL;
316 }
317
318 #if 0
319 static int soc21_asic_mode1_reset(struct amdgpu_device *adev)
320 {
321 u32 i;
322 int ret = 0;
323
324 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
325
326 /* disable BM */
327 pci_clear_master(adev->pdev);
328
329 amdgpu_device_cache_pci_state(adev->pdev);
330
331 if (amdgpu_dpm_is_mode1_reset_supported(adev)) {
332 dev_info(adev->dev, "GPU smu mode1 reset\n");
333 ret = amdgpu_dpm_mode1_reset(adev);
334 } else {
335 dev_info(adev->dev, "GPU psp mode1 reset\n");
336 ret = psp_gpu_reset(adev);
337 }
338
339 if (ret)
340 dev_err(adev->dev, "GPU mode1 reset failed\n");
341 amdgpu_device_load_pci_state(adev->pdev);
342
343 /* wait for asic to come out of reset */
344 for (i = 0; i < adev->usec_timeout; i++) {
345 u32 memsize = adev->nbio.funcs->get_memsize(adev);
346
347 if (memsize != 0xffffffff)
348 break;
349 udelay(1);
350 }
351
352 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
353
354 return ret;
355 }
356 #endif
357
358 static enum amd_reset_method
soc21_asic_reset_method(struct amdgpu_device * adev)359 soc21_asic_reset_method(struct amdgpu_device *adev)
360 {
361 if (amdgpu_reset_method == AMD_RESET_METHOD_MODE1 ||
362 amdgpu_reset_method == AMD_RESET_METHOD_MODE2 ||
363 amdgpu_reset_method == AMD_RESET_METHOD_BACO)
364 return amdgpu_reset_method;
365
366 if (amdgpu_reset_method != -1)
367 dev_warn(adev->dev, "Specified reset method:%d isn't supported, using AUTO instead.\n",
368 amdgpu_reset_method);
369
370 switch (adev->ip_versions[MP1_HWIP][0]) {
371 case IP_VERSION(13, 0, 0):
372 case IP_VERSION(13, 0, 7):
373 case IP_VERSION(13, 0, 10):
374 return AMD_RESET_METHOD_MODE1;
375 case IP_VERSION(13, 0, 4):
376 case IP_VERSION(13, 0, 11):
377 return AMD_RESET_METHOD_MODE2;
378 default:
379 if (amdgpu_dpm_is_baco_supported(adev))
380 return AMD_RESET_METHOD_BACO;
381 else
382 return AMD_RESET_METHOD_MODE1;
383 }
384 }
385
soc21_asic_reset(struct amdgpu_device * adev)386 static int soc21_asic_reset(struct amdgpu_device *adev)
387 {
388 int ret = 0;
389
390 switch (soc21_asic_reset_method(adev)) {
391 case AMD_RESET_METHOD_PCI:
392 dev_info(adev->dev, "PCI reset\n");
393 ret = amdgpu_device_pci_reset(adev);
394 break;
395 case AMD_RESET_METHOD_BACO:
396 dev_info(adev->dev, "BACO reset\n");
397 ret = amdgpu_dpm_baco_reset(adev);
398 break;
399 case AMD_RESET_METHOD_MODE2:
400 dev_info(adev->dev, "MODE2 reset\n");
401 ret = amdgpu_dpm_mode2_reset(adev);
402 break;
403 default:
404 dev_info(adev->dev, "MODE1 reset\n");
405 ret = amdgpu_device_mode1_reset(adev);
406 break;
407 }
408
409 return ret;
410 }
411
soc21_set_uvd_clocks(struct amdgpu_device * adev,u32 vclk,u32 dclk)412 static int soc21_set_uvd_clocks(struct amdgpu_device *adev, u32 vclk, u32 dclk)
413 {
414 /* todo */
415 return 0;
416 }
417
soc21_set_vce_clocks(struct amdgpu_device * adev,u32 evclk,u32 ecclk)418 static int soc21_set_vce_clocks(struct amdgpu_device *adev, u32 evclk, u32 ecclk)
419 {
420 /* todo */
421 return 0;
422 }
423
soc21_program_aspm(struct amdgpu_device * adev)424 static void soc21_program_aspm(struct amdgpu_device *adev)
425 {
426 if (!amdgpu_device_should_use_aspm(adev))
427 return;
428
429 if (!(adev->flags & AMD_IS_APU) &&
430 (adev->nbio.funcs->program_aspm))
431 adev->nbio.funcs->program_aspm(adev);
432 }
433
434 const struct amdgpu_ip_block_version soc21_common_ip_block = {
435 .type = AMD_IP_BLOCK_TYPE_COMMON,
436 .major = 1,
437 .minor = 0,
438 .rev = 0,
439 .funcs = &soc21_common_ip_funcs,
440 };
441
soc21_need_full_reset(struct amdgpu_device * adev)442 static bool soc21_need_full_reset(struct amdgpu_device *adev)
443 {
444 switch (adev->ip_versions[GC_HWIP][0]) {
445 case IP_VERSION(11, 0, 0):
446 case IP_VERSION(11, 0, 2):
447 case IP_VERSION(11, 0, 3):
448 default:
449 return true;
450 }
451 }
452
soc21_need_reset_on_init(struct amdgpu_device * adev)453 static bool soc21_need_reset_on_init(struct amdgpu_device *adev)
454 {
455 u32 sol_reg;
456
457 if (adev->flags & AMD_IS_APU)
458 return false;
459
460 /* Check sOS sign of life register to confirm sys driver and sOS
461 * are already been loaded.
462 */
463 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
464 if (sol_reg)
465 return true;
466
467 return false;
468 }
469
soc21_init_doorbell_index(struct amdgpu_device * adev)470 static void soc21_init_doorbell_index(struct amdgpu_device *adev)
471 {
472 adev->doorbell_index.kiq = AMDGPU_NAVI10_DOORBELL_KIQ;
473 adev->doorbell_index.mec_ring0 = AMDGPU_NAVI10_DOORBELL_MEC_RING0;
474 adev->doorbell_index.mec_ring1 = AMDGPU_NAVI10_DOORBELL_MEC_RING1;
475 adev->doorbell_index.mec_ring2 = AMDGPU_NAVI10_DOORBELL_MEC_RING2;
476 adev->doorbell_index.mec_ring3 = AMDGPU_NAVI10_DOORBELL_MEC_RING3;
477 adev->doorbell_index.mec_ring4 = AMDGPU_NAVI10_DOORBELL_MEC_RING4;
478 adev->doorbell_index.mec_ring5 = AMDGPU_NAVI10_DOORBELL_MEC_RING5;
479 adev->doorbell_index.mec_ring6 = AMDGPU_NAVI10_DOORBELL_MEC_RING6;
480 adev->doorbell_index.mec_ring7 = AMDGPU_NAVI10_DOORBELL_MEC_RING7;
481 adev->doorbell_index.userqueue_start = AMDGPU_NAVI10_DOORBELL_USERQUEUE_START;
482 adev->doorbell_index.userqueue_end = AMDGPU_NAVI10_DOORBELL_USERQUEUE_END;
483 adev->doorbell_index.gfx_ring0 = AMDGPU_NAVI10_DOORBELL_GFX_RING0;
484 adev->doorbell_index.gfx_ring1 = AMDGPU_NAVI10_DOORBELL_GFX_RING1;
485 adev->doorbell_index.gfx_userqueue_start =
486 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_START;
487 adev->doorbell_index.gfx_userqueue_end =
488 AMDGPU_NAVI10_DOORBELL_GFX_USERQUEUE_END;
489 adev->doorbell_index.mes_ring0 = AMDGPU_NAVI10_DOORBELL_MES_RING0;
490 adev->doorbell_index.mes_ring1 = AMDGPU_NAVI10_DOORBELL_MES_RING1;
491 adev->doorbell_index.sdma_engine[0] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE0;
492 adev->doorbell_index.sdma_engine[1] = AMDGPU_NAVI10_DOORBELL_sDMA_ENGINE1;
493 adev->doorbell_index.ih = AMDGPU_NAVI10_DOORBELL_IH;
494 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_NAVI10_DOORBELL64_VCN0_1;
495 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_NAVI10_DOORBELL64_VCN2_3;
496 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_NAVI10_DOORBELL64_VCN4_5;
497 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_NAVI10_DOORBELL64_VCN6_7;
498 adev->doorbell_index.first_non_cp = AMDGPU_NAVI10_DOORBELL64_FIRST_NON_CP;
499 adev->doorbell_index.last_non_cp = AMDGPU_NAVI10_DOORBELL64_LAST_NON_CP;
500
501 adev->doorbell_index.max_assignment = AMDGPU_NAVI10_DOORBELL_MAX_ASSIGNMENT << 1;
502 adev->doorbell_index.sdma_doorbell_range = 20;
503 }
504
soc21_pre_asic_init(struct amdgpu_device * adev)505 static void soc21_pre_asic_init(struct amdgpu_device *adev)
506 {
507 }
508
soc21_update_umd_stable_pstate(struct amdgpu_device * adev,bool enter)509 static int soc21_update_umd_stable_pstate(struct amdgpu_device *adev,
510 bool enter)
511 {
512 if (enter)
513 amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
514 else
515 amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
516
517 if (adev->gfx.funcs->update_perfmon_mgcg)
518 adev->gfx.funcs->update_perfmon_mgcg(adev, !enter);
519
520 return 0;
521 }
522
523 static const struct amdgpu_asic_funcs soc21_asic_funcs = {
524 .read_disabled_bios = &soc21_read_disabled_bios,
525 .read_bios_from_rom = &amdgpu_soc15_read_bios_from_rom,
526 .read_register = &soc21_read_register,
527 .reset = &soc21_asic_reset,
528 .reset_method = &soc21_asic_reset_method,
529 .get_xclk = &soc21_get_xclk,
530 .set_uvd_clocks = &soc21_set_uvd_clocks,
531 .set_vce_clocks = &soc21_set_vce_clocks,
532 .get_config_memsize = &soc21_get_config_memsize,
533 .init_doorbell_index = &soc21_init_doorbell_index,
534 .need_full_reset = &soc21_need_full_reset,
535 .need_reset_on_init = &soc21_need_reset_on_init,
536 .get_pcie_replay_count = &amdgpu_nbio_get_pcie_replay_count,
537 .supports_baco = &amdgpu_dpm_is_baco_supported,
538 .pre_asic_init = &soc21_pre_asic_init,
539 .query_video_codecs = &soc21_query_video_codecs,
540 .update_umd_stable_pstate = &soc21_update_umd_stable_pstate,
541 };
542
soc21_common_early_init(void * handle)543 static int soc21_common_early_init(void *handle)
544 {
545 #define MMIO_REG_HOLE_OFFSET (0x80000 - PAGE_SIZE)
546 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
547
548 adev->rmmio_remap.reg_offset = MMIO_REG_HOLE_OFFSET;
549 adev->rmmio_remap.bus_addr = adev->rmmio_base + MMIO_REG_HOLE_OFFSET;
550 adev->smc_rreg = NULL;
551 adev->smc_wreg = NULL;
552 adev->pcie_rreg = &amdgpu_device_indirect_rreg;
553 adev->pcie_wreg = &amdgpu_device_indirect_wreg;
554 adev->pcie_rreg64 = &amdgpu_device_indirect_rreg64;
555 adev->pcie_wreg64 = &amdgpu_device_indirect_wreg64;
556 adev->pciep_rreg = amdgpu_device_pcie_port_rreg;
557 adev->pciep_wreg = amdgpu_device_pcie_port_wreg;
558
559 /* TODO: will add them during VCN v2 implementation */
560 adev->uvd_ctx_rreg = NULL;
561 adev->uvd_ctx_wreg = NULL;
562
563 adev->didt_rreg = &soc21_didt_rreg;
564 adev->didt_wreg = &soc21_didt_wreg;
565
566 adev->asic_funcs = &soc21_asic_funcs;
567
568 adev->rev_id = amdgpu_device_get_rev_id(adev);
569 adev->external_rev_id = 0xff;
570 switch (adev->ip_versions[GC_HWIP][0]) {
571 case IP_VERSION(11, 0, 0):
572 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
573 AMD_CG_SUPPORT_GFX_CGLS |
574 #if 0
575 AMD_CG_SUPPORT_GFX_3D_CGCG |
576 AMD_CG_SUPPORT_GFX_3D_CGLS |
577 #endif
578 AMD_CG_SUPPORT_GFX_MGCG |
579 AMD_CG_SUPPORT_REPEATER_FGCG |
580 AMD_CG_SUPPORT_GFX_FGCG |
581 AMD_CG_SUPPORT_GFX_PERF_CLK |
582 AMD_CG_SUPPORT_VCN_MGCG |
583 AMD_CG_SUPPORT_JPEG_MGCG |
584 AMD_CG_SUPPORT_ATHUB_MGCG |
585 AMD_CG_SUPPORT_ATHUB_LS |
586 AMD_CG_SUPPORT_MC_MGCG |
587 AMD_CG_SUPPORT_MC_LS |
588 AMD_CG_SUPPORT_IH_CG |
589 AMD_CG_SUPPORT_HDP_SD;
590 adev->pg_flags = AMD_PG_SUPPORT_VCN |
591 AMD_PG_SUPPORT_VCN_DPG |
592 AMD_PG_SUPPORT_JPEG |
593 AMD_PG_SUPPORT_ATHUB |
594 AMD_PG_SUPPORT_MMHUB;
595 adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
596 break;
597 case IP_VERSION(11, 0, 2):
598 adev->cg_flags =
599 AMD_CG_SUPPORT_GFX_CGCG |
600 AMD_CG_SUPPORT_GFX_CGLS |
601 AMD_CG_SUPPORT_REPEATER_FGCG |
602 AMD_CG_SUPPORT_VCN_MGCG |
603 AMD_CG_SUPPORT_JPEG_MGCG |
604 AMD_CG_SUPPORT_ATHUB_MGCG |
605 AMD_CG_SUPPORT_ATHUB_LS |
606 AMD_CG_SUPPORT_IH_CG |
607 AMD_CG_SUPPORT_HDP_SD;
608 adev->pg_flags =
609 AMD_PG_SUPPORT_VCN |
610 AMD_PG_SUPPORT_VCN_DPG |
611 AMD_PG_SUPPORT_JPEG |
612 AMD_PG_SUPPORT_ATHUB |
613 AMD_PG_SUPPORT_MMHUB;
614 adev->external_rev_id = adev->rev_id + 0x10;
615 break;
616 case IP_VERSION(11, 0, 1):
617 adev->cg_flags =
618 AMD_CG_SUPPORT_GFX_CGCG |
619 AMD_CG_SUPPORT_GFX_CGLS |
620 AMD_CG_SUPPORT_GFX_MGCG |
621 AMD_CG_SUPPORT_GFX_FGCG |
622 AMD_CG_SUPPORT_REPEATER_FGCG |
623 AMD_CG_SUPPORT_GFX_PERF_CLK |
624 AMD_CG_SUPPORT_MC_MGCG |
625 AMD_CG_SUPPORT_MC_LS |
626 AMD_CG_SUPPORT_HDP_MGCG |
627 AMD_CG_SUPPORT_HDP_LS |
628 AMD_CG_SUPPORT_ATHUB_MGCG |
629 AMD_CG_SUPPORT_ATHUB_LS |
630 AMD_CG_SUPPORT_IH_CG |
631 AMD_CG_SUPPORT_BIF_MGCG |
632 AMD_CG_SUPPORT_BIF_LS |
633 AMD_CG_SUPPORT_VCN_MGCG |
634 AMD_CG_SUPPORT_JPEG_MGCG;
635 adev->pg_flags =
636 AMD_PG_SUPPORT_GFX_PG |
637 AMD_PG_SUPPORT_VCN |
638 AMD_PG_SUPPORT_VCN_DPG |
639 AMD_PG_SUPPORT_JPEG;
640 adev->external_rev_id = adev->rev_id + 0x1;
641 break;
642 case IP_VERSION(11, 0, 3):
643 adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
644 AMD_CG_SUPPORT_JPEG_MGCG |
645 AMD_CG_SUPPORT_GFX_CGCG |
646 AMD_CG_SUPPORT_GFX_CGLS |
647 AMD_CG_SUPPORT_REPEATER_FGCG |
648 AMD_CG_SUPPORT_GFX_MGCG |
649 AMD_CG_SUPPORT_HDP_SD |
650 AMD_CG_SUPPORT_ATHUB_MGCG |
651 AMD_CG_SUPPORT_ATHUB_LS;
652 adev->pg_flags = AMD_PG_SUPPORT_VCN |
653 AMD_PG_SUPPORT_VCN_DPG |
654 AMD_PG_SUPPORT_JPEG;
655 adev->external_rev_id = adev->rev_id + 0x20;
656 break;
657 case IP_VERSION(11, 0, 4):
658 adev->cg_flags =
659 AMD_CG_SUPPORT_GFX_CGCG |
660 AMD_CG_SUPPORT_GFX_CGLS |
661 AMD_CG_SUPPORT_GFX_MGCG |
662 AMD_CG_SUPPORT_GFX_FGCG |
663 AMD_CG_SUPPORT_REPEATER_FGCG |
664 AMD_CG_SUPPORT_GFX_PERF_CLK |
665 AMD_CG_SUPPORT_MC_MGCG |
666 AMD_CG_SUPPORT_MC_LS |
667 AMD_CG_SUPPORT_HDP_MGCG |
668 AMD_CG_SUPPORT_HDP_LS |
669 AMD_CG_SUPPORT_ATHUB_MGCG |
670 AMD_CG_SUPPORT_ATHUB_LS |
671 AMD_CG_SUPPORT_IH_CG |
672 AMD_CG_SUPPORT_BIF_MGCG |
673 AMD_CG_SUPPORT_BIF_LS |
674 AMD_CG_SUPPORT_VCN_MGCG |
675 AMD_CG_SUPPORT_JPEG_MGCG;
676 adev->pg_flags = AMD_PG_SUPPORT_VCN |
677 AMD_PG_SUPPORT_VCN_DPG |
678 AMD_PG_SUPPORT_GFX_PG |
679 AMD_PG_SUPPORT_JPEG;
680 adev->external_rev_id = adev->rev_id + 0x80;
681 break;
682
683 default:
684 /* FIXME: not supported yet */
685 return -EINVAL;
686 }
687
688 if (amdgpu_sriov_vf(adev)) {
689 amdgpu_virt_init_setting(adev);
690 xgpu_nv_mailbox_set_irq_funcs(adev);
691 }
692
693 return 0;
694 }
695
soc21_common_late_init(void * handle)696 static int soc21_common_late_init(void *handle)
697 {
698 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
699
700 if (amdgpu_sriov_vf(adev)) {
701 xgpu_nv_mailbox_get_irq(adev);
702 if ((adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) ||
703 !amdgpu_sriov_is_av1_support(adev)) {
704 amdgpu_virt_update_sriov_video_codec(adev,
705 sriov_vcn_4_0_0_video_codecs_encode_array_vcn1,
706 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn1),
707 sriov_vcn_4_0_0_video_codecs_decode_array_vcn1,
708 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn1));
709 } else {
710 amdgpu_virt_update_sriov_video_codec(adev,
711 sriov_vcn_4_0_0_video_codecs_encode_array_vcn0,
712 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_encode_array_vcn0),
713 sriov_vcn_4_0_0_video_codecs_decode_array_vcn0,
714 ARRAY_SIZE(sriov_vcn_4_0_0_video_codecs_decode_array_vcn0));
715 }
716 } else {
717 if (adev->nbio.ras &&
718 adev->nbio.ras_err_event_athub_irq.funcs)
719 /* don't need to fail gpu late init
720 * if enabling athub_err_event interrupt failed
721 * nbio v4_3 only support fatal error hanlding
722 * just enable the interrupt directly */
723 amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);
724 }
725
726 /* Enable selfring doorbell aperture late because doorbell BAR
727 * aperture will change if resize BAR successfully in gmc sw_init.
728 */
729 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true);
730
731 return 0;
732 }
733
soc21_common_sw_init(void * handle)734 static int soc21_common_sw_init(void *handle)
735 {
736 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
737
738 if (amdgpu_sriov_vf(adev))
739 xgpu_nv_mailbox_add_irq_id(adev);
740
741 return 0;
742 }
743
soc21_common_sw_fini(void * handle)744 static int soc21_common_sw_fini(void *handle)
745 {
746 return 0;
747 }
748
soc21_common_hw_init(void * handle)749 static int soc21_common_hw_init(void *handle)
750 {
751 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
752
753 /* enable aspm */
754 soc21_program_aspm(adev);
755 /* setup nbio registers */
756 adev->nbio.funcs->init_registers(adev);
757 /* remap HDP registers to a hole in mmio space,
758 * for the purpose of expose those registers
759 * to process space
760 */
761 if (adev->nbio.funcs->remap_hdp_registers && !amdgpu_sriov_vf(adev))
762 adev->nbio.funcs->remap_hdp_registers(adev);
763 /* enable the doorbell aperture */
764 adev->nbio.funcs->enable_doorbell_aperture(adev, true);
765
766 return 0;
767 }
768
soc21_common_hw_fini(void * handle)769 static int soc21_common_hw_fini(void *handle)
770 {
771 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
772
773 /* Disable the doorbell aperture and selfring doorbell aperture
774 * separately in hw_fini because soc21_enable_doorbell_aperture
775 * has been removed and there is no need to delay disabling
776 * selfring doorbell.
777 */
778 adev->nbio.funcs->enable_doorbell_aperture(adev, false);
779 adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false);
780
781 if (amdgpu_sriov_vf(adev)) {
782 xgpu_nv_mailbox_put_irq(adev);
783 } else {
784 if (adev->nbio.ras &&
785 adev->nbio.ras_err_event_athub_irq.funcs)
786 amdgpu_irq_put(adev, &adev->nbio.ras_err_event_athub_irq, 0);
787 }
788
789 return 0;
790 }
791
soc21_common_suspend(void * handle)792 static int soc21_common_suspend(void *handle)
793 {
794 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
795
796 return soc21_common_hw_fini(adev);
797 }
798
soc21_need_reset_on_resume(struct amdgpu_device * adev)799 static bool soc21_need_reset_on_resume(struct amdgpu_device *adev)
800 {
801 u32 sol_reg1, sol_reg2;
802
803 /* Will reset for the following suspend abort cases.
804 * 1) Only reset dGPU side.
805 * 2) S3 suspend got aborted and TOS is active.
806 */
807 if (!(adev->flags & AMD_IS_APU) && adev->in_s3 &&
808 !adev->suspend_complete) {
809 sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
810 msleep(100);
811 sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
812
813 return (sol_reg1 != sol_reg2);
814 }
815
816 return false;
817 }
818
soc21_common_resume(void * handle)819 static int soc21_common_resume(void *handle)
820 {
821 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
822
823 if (soc21_need_reset_on_resume(adev)) {
824 dev_info(adev->dev, "S3 suspend aborted, resetting...");
825 soc21_asic_reset(adev);
826 }
827
828 return soc21_common_hw_init(adev);
829 }
830
soc21_common_is_idle(void * handle)831 static bool soc21_common_is_idle(void *handle)
832 {
833 return true;
834 }
835
soc21_common_wait_for_idle(void * handle)836 static int soc21_common_wait_for_idle(void *handle)
837 {
838 return 0;
839 }
840
soc21_common_soft_reset(void * handle)841 static int soc21_common_soft_reset(void *handle)
842 {
843 return 0;
844 }
845
soc21_common_set_clockgating_state(void * handle,enum amd_clockgating_state state)846 static int soc21_common_set_clockgating_state(void *handle,
847 enum amd_clockgating_state state)
848 {
849 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
850
851 switch (adev->ip_versions[NBIO_HWIP][0]) {
852 case IP_VERSION(4, 3, 0):
853 case IP_VERSION(4, 3, 1):
854 case IP_VERSION(7, 7, 0):
855 adev->nbio.funcs->update_medium_grain_clock_gating(adev,
856 state == AMD_CG_STATE_GATE);
857 adev->nbio.funcs->update_medium_grain_light_sleep(adev,
858 state == AMD_CG_STATE_GATE);
859 adev->hdp.funcs->update_clock_gating(adev,
860 state == AMD_CG_STATE_GATE);
861 break;
862 default:
863 break;
864 }
865 return 0;
866 }
867
soc21_common_set_powergating_state(void * handle,enum amd_powergating_state state)868 static int soc21_common_set_powergating_state(void *handle,
869 enum amd_powergating_state state)
870 {
871 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
872
873 switch (adev->ip_versions[LSDMA_HWIP][0]) {
874 case IP_VERSION(6, 0, 0):
875 case IP_VERSION(6, 0, 2):
876 adev->lsdma.funcs->update_memory_power_gating(adev,
877 state == AMD_PG_STATE_GATE);
878 break;
879 default:
880 break;
881 }
882
883 return 0;
884 }
885
soc21_common_get_clockgating_state(void * handle,u64 * flags)886 static void soc21_common_get_clockgating_state(void *handle, u64 *flags)
887 {
888 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
889
890 adev->nbio.funcs->get_clockgating_state(adev, flags);
891
892 adev->hdp.funcs->get_clock_gating_state(adev, flags);
893
894 return;
895 }
896
897 static const struct amd_ip_funcs soc21_common_ip_funcs = {
898 .name = "soc21_common",
899 .early_init = soc21_common_early_init,
900 .late_init = soc21_common_late_init,
901 .sw_init = soc21_common_sw_init,
902 .sw_fini = soc21_common_sw_fini,
903 .hw_init = soc21_common_hw_init,
904 .hw_fini = soc21_common_hw_fini,
905 .suspend = soc21_common_suspend,
906 .resume = soc21_common_resume,
907 .is_idle = soc21_common_is_idle,
908 .wait_for_idle = soc21_common_wait_for_idle,
909 .soft_reset = soc21_common_soft_reset,
910 .set_clockgating_state = soc21_common_set_clockgating_state,
911 .set_powergating_state = soc21_common_set_powergating_state,
912 .get_clockgating_state = soc21_common_get_clockgating_state,
913 };
914