1 /*
2 * SMBIOS Support
3 *
4 * Copyright (C) 2009 Hewlett-Packard Development Company, L.P.
5 * Copyright (C) 2013 Red Hat, Inc.
6 *
7 * Authors:
8 * Alex Williamson <alex.williamson@hp.com>
9 * Markus Armbruster <armbru@redhat.com>
10 *
11 * This work is licensed under the terms of the GNU GPL, version 2. See
12 * the COPYING file in the top-level directory.
13 *
14 * Contributions after 2012-01-13 are licensed under the terms of the
15 * GNU GPL, version 2 or (at your option) any later version.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/units.h"
20 #include "qemu/bswap.h"
21 #include "qapi/error.h"
22 #include "qemu/config-file.h"
23 #include "qemu/module.h"
24 #include "qemu/option.h"
25 #include "system/system.h"
26 #include "qemu/uuid.h"
27 #include "hw/firmware/smbios.h"
28 #include "hw/loader.h"
29 #include "hw/boards.h"
30 #include "hw/pci/pci_bus.h"
31 #include "hw/pci/pci_device.h"
32 #include "smbios_build.h"
33
34 /*
35 * SMBIOS tables provided by user with '-smbios file=<foo>' option
36 */
37 uint8_t *usr_blobs;
38 size_t usr_blobs_len;
39 static unsigned usr_table_max;
40 static unsigned usr_table_cnt;
41
42 uint8_t *smbios_tables;
43 size_t smbios_tables_len;
44 unsigned smbios_table_max;
45 unsigned smbios_table_cnt;
46
47 static SmbiosEntryPoint ep;
48
49 static int smbios_type4_count = 0;
50 static bool smbios_have_defaults;
51 static uint32_t smbios_cpuid_version, smbios_cpuid_features;
52
53 DECLARE_BITMAP(smbios_have_binfile_bitmap, SMBIOS_MAX_TYPE + 1);
54 DECLARE_BITMAP(smbios_have_fields_bitmap, SMBIOS_MAX_TYPE + 1);
55
56 smbios_type0_t smbios_type0;
57 smbios_type1_t smbios_type1;
58
59 static struct {
60 const char *manufacturer, *product, *version, *serial, *asset, *location;
61 } type2;
62
63 static struct {
64 const char *manufacturer, *version, *serial, *asset, *sku;
65 } type3;
66
67 /*
68 * SVVP requires max_speed and current_speed to be set and not being
69 * 0 which counts as unknown (SMBIOS 3.1.0/Table 21). Set the
70 * default value to 2000MHz as we did before.
71 */
72 #define DEFAULT_CPU_SPEED 2000
73
74 static struct {
75 uint16_t processor_family;
76 const char *sock_pfx, *manufacturer, *version, *serial, *asset, *part;
77 uint64_t max_speed;
78 uint64_t current_speed;
79 uint64_t processor_id;
80 } type4 = {
81 .max_speed = DEFAULT_CPU_SPEED,
82 .current_speed = DEFAULT_CPU_SPEED,
83 .processor_id = 0,
84 .processor_family = 0x01, /* Other */
85 };
86
87 struct type8_instance {
88 const char *internal_reference, *external_reference;
89 uint8_t connector_type, port_type;
90 QTAILQ_ENTRY(type8_instance) next;
91 };
92 static QTAILQ_HEAD(, type8_instance) type8 = QTAILQ_HEAD_INITIALIZER(type8);
93
94 /* type 9 instance for parsing */
95 struct type9_instance {
96 const char *slot_designation, *pcidev;
97 uint8_t slot_type, slot_data_bus_width, current_usage, slot_length,
98 slot_characteristics1, slot_characteristics2;
99 uint16_t slot_id;
100 QTAILQ_ENTRY(type9_instance) next;
101 };
102 static QTAILQ_HEAD(, type9_instance) type9 = QTAILQ_HEAD_INITIALIZER(type9);
103
104 static struct {
105 size_t nvalues;
106 char **values;
107 } type11;
108
109 static struct {
110 const char *loc_pfx, *bank, *manufacturer, *serial, *asset, *part;
111 uint16_t speed;
112 } type17;
113
114 static QEnumLookup type41_kind_lookup = {
115 .array = (const char *const[]) {
116 "other",
117 "unknown",
118 "video",
119 "scsi",
120 "ethernet",
121 "tokenring",
122 "sound",
123 "pata",
124 "sata",
125 "sas",
126 },
127 .size = 10
128 };
129 struct type41_instance {
130 const char *designation, *pcidev;
131 uint8_t instance, kind;
132 QTAILQ_ENTRY(type41_instance) next;
133 };
134 static QTAILQ_HEAD(, type41_instance) type41 = QTAILQ_HEAD_INITIALIZER(type41);
135
136 static QemuOptsList qemu_smbios_opts = {
137 .name = "smbios",
138 .head = QTAILQ_HEAD_INITIALIZER(qemu_smbios_opts.head),
139 .desc = {
140 /*
141 * no elements => accept any params
142 * validation will happen later
143 */
144 { /* end of list */ }
145 }
146 };
147
148 static const QemuOptDesc qemu_smbios_file_opts[] = {
149 {
150 .name = "file",
151 .type = QEMU_OPT_STRING,
152 .help = "binary file containing an SMBIOS element",
153 },
154 { /* end of list */ }
155 };
156
157 static const QemuOptDesc qemu_smbios_type0_opts[] = {
158 {
159 .name = "type",
160 .type = QEMU_OPT_NUMBER,
161 .help = "SMBIOS element type",
162 },{
163 .name = "vendor",
164 .type = QEMU_OPT_STRING,
165 .help = "vendor name",
166 },{
167 .name = "version",
168 .type = QEMU_OPT_STRING,
169 .help = "version number",
170 },{
171 .name = "date",
172 .type = QEMU_OPT_STRING,
173 .help = "release date",
174 },{
175 .name = "release",
176 .type = QEMU_OPT_STRING,
177 .help = "revision number",
178 },{
179 .name = "uefi",
180 .type = QEMU_OPT_BOOL,
181 .help = "uefi support",
182 },
183 { /* end of list */ }
184 };
185
186 static const QemuOptDesc qemu_smbios_type1_opts[] = {
187 {
188 .name = "type",
189 .type = QEMU_OPT_NUMBER,
190 .help = "SMBIOS element type",
191 },{
192 .name = "manufacturer",
193 .type = QEMU_OPT_STRING,
194 .help = "manufacturer name",
195 },{
196 .name = "product",
197 .type = QEMU_OPT_STRING,
198 .help = "product name",
199 },{
200 .name = "version",
201 .type = QEMU_OPT_STRING,
202 .help = "version number",
203 },{
204 .name = "serial",
205 .type = QEMU_OPT_STRING,
206 .help = "serial number",
207 },{
208 .name = "uuid",
209 .type = QEMU_OPT_STRING,
210 .help = "UUID",
211 },{
212 .name = "sku",
213 .type = QEMU_OPT_STRING,
214 .help = "SKU number",
215 },{
216 .name = "family",
217 .type = QEMU_OPT_STRING,
218 .help = "family name",
219 },
220 { /* end of list */ }
221 };
222
223 static const QemuOptDesc qemu_smbios_type2_opts[] = {
224 {
225 .name = "type",
226 .type = QEMU_OPT_NUMBER,
227 .help = "SMBIOS element type",
228 },{
229 .name = "manufacturer",
230 .type = QEMU_OPT_STRING,
231 .help = "manufacturer name",
232 },{
233 .name = "product",
234 .type = QEMU_OPT_STRING,
235 .help = "product name",
236 },{
237 .name = "version",
238 .type = QEMU_OPT_STRING,
239 .help = "version number",
240 },{
241 .name = "serial",
242 .type = QEMU_OPT_STRING,
243 .help = "serial number",
244 },{
245 .name = "asset",
246 .type = QEMU_OPT_STRING,
247 .help = "asset tag number",
248 },{
249 .name = "location",
250 .type = QEMU_OPT_STRING,
251 .help = "location in chassis",
252 },
253 { /* end of list */ }
254 };
255
256 static const QemuOptDesc qemu_smbios_type3_opts[] = {
257 {
258 .name = "type",
259 .type = QEMU_OPT_NUMBER,
260 .help = "SMBIOS element type",
261 },{
262 .name = "manufacturer",
263 .type = QEMU_OPT_STRING,
264 .help = "manufacturer name",
265 },{
266 .name = "version",
267 .type = QEMU_OPT_STRING,
268 .help = "version number",
269 },{
270 .name = "serial",
271 .type = QEMU_OPT_STRING,
272 .help = "serial number",
273 },{
274 .name = "asset",
275 .type = QEMU_OPT_STRING,
276 .help = "asset tag number",
277 },{
278 .name = "sku",
279 .type = QEMU_OPT_STRING,
280 .help = "SKU number",
281 },
282 { /* end of list */ }
283 };
284
285 static const QemuOptDesc qemu_smbios_type4_opts[] = {
286 {
287 .name = "type",
288 .type = QEMU_OPT_NUMBER,
289 .help = "SMBIOS element type",
290 },{
291 .name = "sock_pfx",
292 .type = QEMU_OPT_STRING,
293 .help = "socket designation string prefix",
294 },{
295 .name = "manufacturer",
296 .type = QEMU_OPT_STRING,
297 .help = "manufacturer name",
298 },{
299 .name = "version",
300 .type = QEMU_OPT_STRING,
301 .help = "version number",
302 },{
303 .name = "max-speed",
304 .type = QEMU_OPT_NUMBER,
305 .help = "max speed in MHz",
306 },{
307 .name = "current-speed",
308 .type = QEMU_OPT_NUMBER,
309 .help = "speed at system boot in MHz",
310 },{
311 .name = "serial",
312 .type = QEMU_OPT_STRING,
313 .help = "serial number",
314 },{
315 .name = "asset",
316 .type = QEMU_OPT_STRING,
317 .help = "asset tag number",
318 },{
319 .name = "part",
320 .type = QEMU_OPT_STRING,
321 .help = "part number",
322 }, {
323 .name = "processor-family",
324 .type = QEMU_OPT_NUMBER,
325 .help = "processor family",
326 }, {
327 .name = "processor-id",
328 .type = QEMU_OPT_NUMBER,
329 .help = "processor id",
330 },
331 { /* end of list */ }
332 };
333
334 static const QemuOptDesc qemu_smbios_type8_opts[] = {
335 {
336 .name = "type",
337 .type = QEMU_OPT_NUMBER,
338 .help = "SMBIOS element type",
339 },
340 {
341 .name = "internal_reference",
342 .type = QEMU_OPT_STRING,
343 .help = "internal reference designator",
344 },
345 {
346 .name = "external_reference",
347 .type = QEMU_OPT_STRING,
348 .help = "external reference designator",
349 },
350 {
351 .name = "connector_type",
352 .type = QEMU_OPT_NUMBER,
353 .help = "connector type",
354 },
355 {
356 .name = "port_type",
357 .type = QEMU_OPT_NUMBER,
358 .help = "port type",
359 },
360 { /* end of list */ }
361 };
362
363 static const QemuOptDesc qemu_smbios_type9_opts[] = {
364 {
365 .name = "type",
366 .type = QEMU_OPT_NUMBER,
367 .help = "SMBIOS element type",
368 },
369 {
370 .name = "slot_designation",
371 .type = QEMU_OPT_STRING,
372 .help = "string number for reference designation",
373 },
374 {
375 .name = "slot_type",
376 .type = QEMU_OPT_NUMBER,
377 .help = "connector type",
378 },
379 {
380 .name = "slot_data_bus_width",
381 .type = QEMU_OPT_NUMBER,
382 .help = "port type",
383 },
384 {
385 .name = "current_usage",
386 .type = QEMU_OPT_NUMBER,
387 .help = "current usage",
388 },
389 {
390 .name = "slot_length",
391 .type = QEMU_OPT_NUMBER,
392 .help = "system slot length",
393 },
394 {
395 .name = "slot_id",
396 .type = QEMU_OPT_NUMBER,
397 .help = "system slot id",
398 },
399 {
400 .name = "slot_characteristics1",
401 .type = QEMU_OPT_NUMBER,
402 .help = "slot characteristics1, see the spec",
403 },
404 {
405 .name = "slot_characteristics2",
406 .type = QEMU_OPT_NUMBER,
407 .help = "slot characteristics2, see the spec",
408 },
409 {
410 .name = "pci_device",
411 .type = QEMU_OPT_STRING,
412 .help = "PCI device, if provided."
413 }
414 };
415
416 static const QemuOptDesc qemu_smbios_type11_opts[] = {
417 {
418 .name = "type",
419 .type = QEMU_OPT_NUMBER,
420 .help = "SMBIOS element type",
421 },
422 {
423 .name = "value",
424 .type = QEMU_OPT_STRING,
425 .help = "OEM string data",
426 },
427 {
428 .name = "path",
429 .type = QEMU_OPT_STRING,
430 .help = "OEM string data from file",
431 },
432 { /* end of list */ }
433 };
434
435 static const QemuOptDesc qemu_smbios_type17_opts[] = {
436 {
437 .name = "type",
438 .type = QEMU_OPT_NUMBER,
439 .help = "SMBIOS element type",
440 },{
441 .name = "loc_pfx",
442 .type = QEMU_OPT_STRING,
443 .help = "device locator string prefix",
444 },{
445 .name = "bank",
446 .type = QEMU_OPT_STRING,
447 .help = "bank locator string",
448 },{
449 .name = "manufacturer",
450 .type = QEMU_OPT_STRING,
451 .help = "manufacturer name",
452 },{
453 .name = "serial",
454 .type = QEMU_OPT_STRING,
455 .help = "serial number",
456 },{
457 .name = "asset",
458 .type = QEMU_OPT_STRING,
459 .help = "asset tag number",
460 },{
461 .name = "part",
462 .type = QEMU_OPT_STRING,
463 .help = "part number",
464 },{
465 .name = "speed",
466 .type = QEMU_OPT_NUMBER,
467 .help = "maximum capable speed",
468 },
469 { /* end of list */ }
470 };
471
472 static const QemuOptDesc qemu_smbios_type41_opts[] = {
473 {
474 .name = "type",
475 .type = QEMU_OPT_NUMBER,
476 .help = "SMBIOS element type",
477 },{
478 .name = "designation",
479 .type = QEMU_OPT_STRING,
480 .help = "reference designation string",
481 },{
482 .name = "kind",
483 .type = QEMU_OPT_STRING,
484 .help = "device type",
485 .def_value_str = "other",
486 },{
487 .name = "instance",
488 .type = QEMU_OPT_NUMBER,
489 .help = "device type instance",
490 },{
491 .name = "pcidev",
492 .type = QEMU_OPT_STRING,
493 .help = "PCI device",
494 },
495 { /* end of list */ }
496 };
497
smbios_register_config(void)498 static void smbios_register_config(void)
499 {
500 qemu_add_opts(&qemu_smbios_opts);
501 }
502
503 opts_init(smbios_register_config);
504
505 /*
506 * The SMBIOS 2.1 "structure table length" field in the
507 * entry point uses a 16-bit integer, so we're limited
508 * in total table size
509 */
510 #define SMBIOS_21_MAX_TABLES_LEN 0xffff
511
smbios_check_type4_count(uint32_t expected_t4_count,Error ** errp)512 static bool smbios_check_type4_count(uint32_t expected_t4_count, Error **errp)
513 {
514 if (smbios_type4_count && smbios_type4_count != expected_t4_count) {
515 error_setg(errp, "Expected %d SMBIOS Type 4 tables, got %d instead",
516 expected_t4_count, smbios_type4_count);
517 return false;
518 }
519 return true;
520 }
521
smbios_validate_table(SmbiosEntryPointType ep_type,Error ** errp)522 bool smbios_validate_table(SmbiosEntryPointType ep_type, Error **errp)
523 {
524 if (ep_type == SMBIOS_ENTRY_POINT_TYPE_32 &&
525 smbios_tables_len > SMBIOS_21_MAX_TABLES_LEN) {
526 error_setg(errp, "SMBIOS 2.1 table length %zu exceeds %d",
527 smbios_tables_len, SMBIOS_21_MAX_TABLES_LEN);
528 return false;
529 }
530 return true;
531 }
532
smbios_skip_table(uint8_t type,bool required_table)533 bool smbios_skip_table(uint8_t type, bool required_table)
534 {
535 if (test_bit(type, smbios_have_binfile_bitmap)) {
536 return true; /* user provided their own binary blob(s) */
537 }
538 if (test_bit(type, smbios_have_fields_bitmap)) {
539 return false; /* user provided fields via command line */
540 }
541 if (smbios_have_defaults && required_table) {
542 return false; /* we're building tables, and this one's required */
543 }
544 return true;
545 }
546
547 #define T0_BASE 0x000
548 #define T1_BASE 0x100
549 #define T2_BASE 0x200
550 #define T3_BASE 0x300
551 #define T4_BASE 0x400
552 #define T9_BASE 0x900
553 #define T11_BASE 0xe00
554
555 #define T16_BASE 0x1000
556 #define T17_BASE 0x1100
557 #define T19_BASE 0x1300
558 #define T32_BASE 0x2000
559 #define T41_BASE 0x2900
560 #define T127_BASE 0x7F00
561
smbios_build_type_0_table(void)562 static void smbios_build_type_0_table(void)
563 {
564 SMBIOS_BUILD_TABLE_PRE(0, T0_BASE, false); /* optional, leave up to BIOS */
565
566 SMBIOS_TABLE_SET_STR(0, vendor_str, smbios_type0.vendor);
567 SMBIOS_TABLE_SET_STR(0, bios_version_str, smbios_type0.version);
568
569 t->bios_starting_address_segment = cpu_to_le16(0xE800); /* from SeaBIOS */
570
571 SMBIOS_TABLE_SET_STR(0, bios_release_date_str, smbios_type0.date);
572
573 t->bios_rom_size = 0; /* hardcoded in SeaBIOS with FIXME comment */
574
575 t->bios_characteristics = cpu_to_le64(0x08); /* Not supported */
576 t->bios_characteristics_extension_bytes[0] = 0;
577 t->bios_characteristics_extension_bytes[1] = 0x14; /* TCD/SVVP | VM */
578 if (smbios_type0.uefi) {
579 t->bios_characteristics_extension_bytes[1] |= 0x08; /* |= UEFI */
580 }
581
582 if (smbios_type0.have_major_minor) {
583 t->system_bios_major_release = smbios_type0.major;
584 t->system_bios_minor_release = smbios_type0.minor;
585 } else {
586 t->system_bios_major_release = 0;
587 t->system_bios_minor_release = 0;
588 }
589
590 /* hardcoded in SeaBIOS */
591 t->embedded_controller_major_release = 0xFF;
592 t->embedded_controller_minor_release = 0xFF;
593
594 SMBIOS_BUILD_TABLE_POST;
595 }
596
597 /* Encode UUID from the big endian encoding described on RFC4122 to the wire
598 * format specified by SMBIOS version 2.6.
599 */
smbios_encode_uuid(struct smbios_uuid * uuid,QemuUUID * in)600 static void smbios_encode_uuid(struct smbios_uuid *uuid, QemuUUID *in)
601 {
602 memcpy(uuid, in, 16);
603 uuid->time_low = bswap32(uuid->time_low);
604 uuid->time_mid = bswap16(uuid->time_mid);
605 uuid->time_hi_and_version = bswap16(uuid->time_hi_and_version);
606 }
607
smbios_build_type_1_table(void)608 static void smbios_build_type_1_table(void)
609 {
610 SMBIOS_BUILD_TABLE_PRE(1, T1_BASE, true); /* required */
611
612 SMBIOS_TABLE_SET_STR(1, manufacturer_str, smbios_type1.manufacturer);
613 SMBIOS_TABLE_SET_STR(1, product_name_str, smbios_type1.product);
614 SMBIOS_TABLE_SET_STR(1, version_str, smbios_type1.version);
615 SMBIOS_TABLE_SET_STR(1, serial_number_str, smbios_type1.serial);
616 if (qemu_uuid_set) {
617 smbios_encode_uuid(&t->uuid, &qemu_uuid);
618 } else {
619 memset(&t->uuid, 0, 16);
620 }
621 t->wake_up_type = 0x06; /* power switch */
622 SMBIOS_TABLE_SET_STR(1, sku_number_str, smbios_type1.sku);
623 SMBIOS_TABLE_SET_STR(1, family_str, smbios_type1.family);
624
625 SMBIOS_BUILD_TABLE_POST;
626 }
627
smbios_build_type_2_table(void)628 static void smbios_build_type_2_table(void)
629 {
630 SMBIOS_BUILD_TABLE_PRE(2, T2_BASE, false); /* optional */
631
632 SMBIOS_TABLE_SET_STR(2, manufacturer_str, type2.manufacturer);
633 SMBIOS_TABLE_SET_STR(2, product_str, type2.product);
634 SMBIOS_TABLE_SET_STR(2, version_str, type2.version);
635 SMBIOS_TABLE_SET_STR(2, serial_number_str, type2.serial);
636 SMBIOS_TABLE_SET_STR(2, asset_tag_number_str, type2.asset);
637 t->feature_flags = 0x01; /* Motherboard */
638 SMBIOS_TABLE_SET_STR(2, location_str, type2.location);
639 t->chassis_handle = cpu_to_le16(0x300); /* Type 3 (System enclosure) */
640 t->board_type = 0x0A; /* Motherboard */
641 t->contained_element_count = 0;
642
643 SMBIOS_BUILD_TABLE_POST;
644 }
645
smbios_build_type_3_table(void)646 static void smbios_build_type_3_table(void)
647 {
648 SMBIOS_BUILD_TABLE_PRE(3, T3_BASE, true); /* required */
649
650 SMBIOS_TABLE_SET_STR(3, manufacturer_str, type3.manufacturer);
651 t->type = 0x01; /* Other */
652 SMBIOS_TABLE_SET_STR(3, version_str, type3.version);
653 SMBIOS_TABLE_SET_STR(3, serial_number_str, type3.serial);
654 SMBIOS_TABLE_SET_STR(3, asset_tag_number_str, type3.asset);
655 t->boot_up_state = 0x03; /* Safe */
656 t->power_supply_state = 0x03; /* Safe */
657 t->thermal_state = 0x03; /* Safe */
658 t->security_status = 0x02; /* Unknown */
659 t->oem_defined = cpu_to_le32(0);
660 t->height = 0;
661 t->number_of_power_cords = 0;
662 t->contained_element_count = 0;
663 t->contained_element_record_length = 0;
664 SMBIOS_TABLE_SET_STR(3, sku_number_str, type3.sku);
665
666 SMBIOS_BUILD_TABLE_POST;
667 }
668
smbios_build_type_4_table(MachineState * ms,unsigned instance,SmbiosEntryPointType ep_type,Error ** errp)669 static void smbios_build_type_4_table(MachineState *ms, unsigned instance,
670 SmbiosEntryPointType ep_type,
671 Error **errp)
672 {
673 char sock_str[128];
674 size_t tbl_len = SMBIOS_TYPE_4_LEN_V28;
675 unsigned threads_per_socket;
676 unsigned cores_per_socket;
677
678 if (ep_type == SMBIOS_ENTRY_POINT_TYPE_64) {
679 tbl_len = SMBIOS_TYPE_4_LEN_V30;
680 }
681
682 SMBIOS_BUILD_TABLE_PRE_SIZE(4, T4_BASE + instance,
683 true, tbl_len); /* required */
684
685 snprintf(sock_str, sizeof(sock_str), "%s%2x", type4.sock_pfx, instance);
686 SMBIOS_TABLE_SET_STR(4, socket_designation_str, sock_str);
687 t->processor_type = 0x03; /* CPU */
688 t->processor_family = 0xfe; /* use Processor Family 2 field */
689 SMBIOS_TABLE_SET_STR(4, processor_manufacturer_str, type4.manufacturer);
690 if (type4.processor_id == 0) {
691 t->processor_id[0] = cpu_to_le32(smbios_cpuid_version);
692 t->processor_id[1] = cpu_to_le32(smbios_cpuid_features);
693 } else {
694 t->processor_id[0] = cpu_to_le32((uint32_t)type4.processor_id);
695 t->processor_id[1] = cpu_to_le32(type4.processor_id >> 32);
696 }
697 SMBIOS_TABLE_SET_STR(4, processor_version_str, type4.version);
698 t->voltage = 0;
699 t->external_clock = cpu_to_le16(0); /* Unknown */
700 t->max_speed = cpu_to_le16(type4.max_speed);
701 t->current_speed = cpu_to_le16(type4.current_speed);
702 t->status = 0x41; /* Socket populated, CPU enabled */
703 t->processor_upgrade = 0x01; /* Other */
704 t->l1_cache_handle = cpu_to_le16(0xFFFF); /* N/A */
705 t->l2_cache_handle = cpu_to_le16(0xFFFF); /* N/A */
706 t->l3_cache_handle = cpu_to_le16(0xFFFF); /* N/A */
707 SMBIOS_TABLE_SET_STR(4, serial_number_str, type4.serial);
708 SMBIOS_TABLE_SET_STR(4, asset_tag_number_str, type4.asset);
709 SMBIOS_TABLE_SET_STR(4, part_number_str, type4.part);
710
711 threads_per_socket = machine_topo_get_threads_per_socket(ms);
712 cores_per_socket = machine_topo_get_cores_per_socket(ms);
713
714 t->core_count = (cores_per_socket > 255) ? 0xFF : cores_per_socket;
715 t->core_enabled = t->core_count;
716
717 t->thread_count = (threads_per_socket > 255) ? 0xFF : threads_per_socket;
718
719 t->processor_characteristics = cpu_to_le16(0x02); /* Unknown */
720 t->processor_family2 = cpu_to_le16(type4.processor_family);
721
722 if (tbl_len == SMBIOS_TYPE_4_LEN_V30) {
723 t->core_count2 = t->core_enabled2 = cpu_to_le16(cores_per_socket);
724 t->thread_count2 = cpu_to_le16(threads_per_socket);
725 } else if (t->core_count == 0xFF || t->thread_count == 0xFF) {
726 error_setg(errp, "SMBIOS 2.0 doesn't support number of processor "
727 "cores/threads more than 255, use "
728 "-machine smbios-entry-point-type=64 option to enable "
729 "SMBIOS 3.0 support");
730 return;
731 }
732
733 SMBIOS_BUILD_TABLE_POST;
734 smbios_type4_count++;
735 }
736
smbios_build_type_8_table(void)737 static void smbios_build_type_8_table(void)
738 {
739 unsigned instance = 0;
740 struct type8_instance *t8;
741
742 QTAILQ_FOREACH(t8, &type8, next) {
743 SMBIOS_BUILD_TABLE_PRE(8, T0_BASE + instance, true);
744
745 SMBIOS_TABLE_SET_STR(8, internal_reference_str, t8->internal_reference);
746 SMBIOS_TABLE_SET_STR(8, external_reference_str, t8->external_reference);
747 /* most vendors seem to set this to None */
748 t->internal_connector_type = 0x0;
749 t->external_connector_type = t8->connector_type;
750 t->port_type = t8->port_type;
751
752 SMBIOS_BUILD_TABLE_POST;
753 instance++;
754 }
755 }
756
smbios_build_type_9_table(Error ** errp)757 static void smbios_build_type_9_table(Error **errp)
758 {
759 unsigned instance = 0;
760 struct type9_instance *t9;
761
762 QTAILQ_FOREACH(t9, &type9, next) {
763 SMBIOS_BUILD_TABLE_PRE(9, T9_BASE + instance, true);
764
765 SMBIOS_TABLE_SET_STR(9, slot_designation, t9->slot_designation);
766 t->slot_type = t9->slot_type;
767 t->slot_data_bus_width = t9->slot_data_bus_width;
768 t->current_usage = t9->current_usage;
769 t->slot_length = t9->slot_length;
770 t->slot_id = t9->slot_id;
771 t->slot_characteristics1 = t9->slot_characteristics1;
772 t->slot_characteristics2 = t9->slot_characteristics2;
773
774 if (t9->pcidev) {
775 PCIDevice *pdev = NULL;
776 int rc = pci_qdev_find_device(t9->pcidev, &pdev);
777 if (rc != 0) {
778 error_setg(errp,
779 "No PCI device %s for SMBIOS type 9 entry %s",
780 t9->pcidev, t9->slot_designation);
781 return;
782 }
783 /*
784 * We only handle the case were the device is attached to
785 * the PCI root bus. The general case is more complex as
786 * bridges are enumerated later and the table would need
787 * to be updated at this moment.
788 */
789 if (!pci_bus_is_root(pci_get_bus(pdev))) {
790 error_setg(errp,
791 "Cannot create type 9 entry for PCI device %s: "
792 "not attached to the root bus",
793 t9->pcidev);
794 return;
795 }
796 t->segment_group_number = cpu_to_le16(0);
797 t->bus_number = pci_dev_bus_num(pdev);
798 t->device_number = pdev->devfn;
799 } else {
800 /*
801 * Per SMBIOS spec, For slots that are not of the PCI, AGP, PCI-X,
802 * or PCI-Express type that do not have bus/device/function
803 * information, 0FFh should be populated in the fields of Segment
804 * Group Number, Bus Number, Device/Function Number.
805 */
806 t->segment_group_number = 0xff;
807 t->bus_number = 0xff;
808 t->device_number = 0xff;
809 }
810
811 SMBIOS_BUILD_TABLE_POST;
812 instance++;
813 }
814 }
815
smbios_build_type_11_table(void)816 static void smbios_build_type_11_table(void)
817 {
818 char count_str[128];
819 size_t i;
820
821 if (type11.nvalues == 0) {
822 return;
823 }
824
825 SMBIOS_BUILD_TABLE_PRE(11, T11_BASE, true); /* required */
826
827 snprintf(count_str, sizeof(count_str), "%zu", type11.nvalues);
828 t->count = type11.nvalues;
829
830 for (i = 0; i < type11.nvalues; i++) {
831 SMBIOS_TABLE_SET_STR_LIST(11, type11.values[i]);
832 g_free(type11.values[i]);
833 type11.values[i] = NULL;
834 }
835
836 SMBIOS_BUILD_TABLE_POST;
837 }
838
839 #define MAX_T16_STD_SZ 0x80000000 /* 2T in Kilobytes */
840
smbios_build_type_16_table(unsigned dimm_cnt)841 static void smbios_build_type_16_table(unsigned dimm_cnt)
842 {
843 uint64_t size_kb;
844
845 SMBIOS_BUILD_TABLE_PRE(16, T16_BASE, true); /* required */
846
847 t->location = 0x01; /* Other */
848 t->use = 0x03; /* System memory */
849 t->error_correction = 0x06; /* Multi-bit ECC (for Microsoft, per SeaBIOS) */
850 size_kb = QEMU_ALIGN_UP(current_machine->ram_size, KiB) / KiB;
851 if (size_kb < MAX_T16_STD_SZ) {
852 t->maximum_capacity = cpu_to_le32(size_kb);
853 t->extended_maximum_capacity = cpu_to_le64(0);
854 } else {
855 t->maximum_capacity = cpu_to_le32(MAX_T16_STD_SZ);
856 t->extended_maximum_capacity = cpu_to_le64(current_machine->ram_size);
857 }
858 t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */
859 t->number_of_memory_devices = cpu_to_le16(dimm_cnt);
860
861 SMBIOS_BUILD_TABLE_POST;
862 }
863
864 #define MAX_T17_STD_SZ 0x7FFF /* (32G - 1M), in Megabytes */
865 #define MAX_T17_EXT_SZ 0x80000000 /* 2P, in Megabytes */
866
smbios_build_type_17_table(unsigned instance,uint64_t size)867 static void smbios_build_type_17_table(unsigned instance, uint64_t size)
868 {
869 char loc_str[128];
870 uint64_t size_mb;
871
872 SMBIOS_BUILD_TABLE_PRE(17, T17_BASE + instance, true); /* required */
873
874 t->physical_memory_array_handle = cpu_to_le16(0x1000); /* Type 16 above */
875 t->memory_error_information_handle = cpu_to_le16(0xFFFE); /* Not provided */
876 t->total_width = cpu_to_le16(0xFFFF); /* Unknown */
877 t->data_width = cpu_to_le16(0xFFFF); /* Unknown */
878 size_mb = QEMU_ALIGN_UP(size, MiB) / MiB;
879 if (size_mb < MAX_T17_STD_SZ) {
880 t->size = cpu_to_le16(size_mb);
881 t->extended_size = cpu_to_le32(0);
882 } else {
883 assert(size_mb < MAX_T17_EXT_SZ);
884 t->size = cpu_to_le16(MAX_T17_STD_SZ);
885 t->extended_size = cpu_to_le32(size_mb);
886 }
887 t->form_factor = 0x09; /* DIMM */
888 t->device_set = 0; /* Not in a set */
889 snprintf(loc_str, sizeof(loc_str), "%s %d", type17.loc_pfx, instance);
890 SMBIOS_TABLE_SET_STR(17, device_locator_str, loc_str);
891 SMBIOS_TABLE_SET_STR(17, bank_locator_str, type17.bank);
892 t->memory_type = 0x07; /* RAM */
893 t->type_detail = cpu_to_le16(0x02); /* Other */
894 t->speed = cpu_to_le16(type17.speed);
895 SMBIOS_TABLE_SET_STR(17, manufacturer_str, type17.manufacturer);
896 SMBIOS_TABLE_SET_STR(17, serial_number_str, type17.serial);
897 SMBIOS_TABLE_SET_STR(17, asset_tag_number_str, type17.asset);
898 SMBIOS_TABLE_SET_STR(17, part_number_str, type17.part);
899 t->attributes = 0; /* Unknown */
900 t->configured_clock_speed = t->speed; /* reuse value for max speed */
901 t->minimum_voltage = cpu_to_le16(0); /* Unknown */
902 t->maximum_voltage = cpu_to_le16(0); /* Unknown */
903 t->configured_voltage = cpu_to_le16(0); /* Unknown */
904
905 SMBIOS_BUILD_TABLE_POST;
906 }
907
smbios_build_type_19_table(unsigned instance,unsigned offset,uint64_t start,uint64_t size)908 static void smbios_build_type_19_table(unsigned instance, unsigned offset,
909 uint64_t start, uint64_t size)
910 {
911 uint64_t end, start_kb, end_kb;
912
913 SMBIOS_BUILD_TABLE_PRE(19, T19_BASE + offset + instance,
914 true); /* required */
915
916 end = start + size - 1;
917 assert(end > start);
918 start_kb = start / KiB;
919 end_kb = end / KiB;
920 if (start_kb < UINT32_MAX && end_kb < UINT32_MAX) {
921 t->starting_address = cpu_to_le32(start_kb);
922 t->ending_address = cpu_to_le32(end_kb);
923 t->extended_starting_address =
924 t->extended_ending_address = cpu_to_le64(0);
925 } else {
926 t->starting_address = t->ending_address = cpu_to_le32(UINT32_MAX);
927 t->extended_starting_address = cpu_to_le64(start);
928 t->extended_ending_address = cpu_to_le64(end);
929 }
930 t->memory_array_handle = cpu_to_le16(0x1000); /* Type 16 above */
931 t->partition_width = 1; /* One device per row */
932
933 SMBIOS_BUILD_TABLE_POST;
934 }
935
smbios_build_type_32_table(void)936 static void smbios_build_type_32_table(void)
937 {
938 SMBIOS_BUILD_TABLE_PRE(32, T32_BASE, true); /* required */
939
940 memset(t->reserved, 0, 6);
941 t->boot_status = 0; /* No errors detected */
942
943 SMBIOS_BUILD_TABLE_POST;
944 }
945
smbios_build_type_41_table(Error ** errp)946 static void smbios_build_type_41_table(Error **errp)
947 {
948 unsigned instance = 0;
949 struct type41_instance *t41;
950
951 QTAILQ_FOREACH(t41, &type41, next) {
952 SMBIOS_BUILD_TABLE_PRE(41, T41_BASE + instance, true);
953
954 SMBIOS_TABLE_SET_STR(41, reference_designation_str, t41->designation);
955 t->device_type = t41->kind;
956 t->device_type_instance = t41->instance;
957 t->segment_group_number = cpu_to_le16(0);
958 t->bus_number = 0;
959 t->device_number = 0;
960
961 if (t41->pcidev) {
962 PCIDevice *pdev = NULL;
963 int rc = pci_qdev_find_device(t41->pcidev, &pdev);
964 if (rc != 0) {
965 error_setg(errp,
966 "No PCI device %s for SMBIOS type 41 entry %s",
967 t41->pcidev, t41->designation);
968 return;
969 }
970 /*
971 * We only handle the case were the device is attached to
972 * the PCI root bus. The general case is more complex as
973 * bridges are enumerated later and the table would need
974 * to be updated at this moment.
975 */
976 if (!pci_bus_is_root(pci_get_bus(pdev))) {
977 error_setg(errp,
978 "Cannot create type 41 entry for PCI device %s: "
979 "not attached to the root bus",
980 t41->pcidev);
981 return;
982 }
983 t->segment_group_number = cpu_to_le16(0);
984 t->bus_number = pci_dev_bus_num(pdev);
985 t->device_number = pdev->devfn;
986 }
987
988 SMBIOS_BUILD_TABLE_POST;
989 instance++;
990 }
991 }
992
smbios_build_type_127_table(void)993 static void smbios_build_type_127_table(void)
994 {
995 SMBIOS_BUILD_TABLE_PRE(127, T127_BASE, true); /* required */
996 SMBIOS_BUILD_TABLE_POST;
997 }
998
smbios_set_cpuid(uint32_t version,uint32_t features)999 void smbios_set_cpuid(uint32_t version, uint32_t features)
1000 {
1001 smbios_cpuid_version = version;
1002 smbios_cpuid_features = features;
1003 }
1004
1005 #define SMBIOS_SET_DEFAULT(field, value) \
1006 if (!field) { \
1007 field = value; \
1008 }
1009
smbios_set_default_processor_family(uint16_t processor_family)1010 void smbios_set_default_processor_family(uint16_t processor_family)
1011 {
1012 if (type4.processor_family <= 0x01) {
1013 type4.processor_family = processor_family;
1014 }
1015 }
1016
smbios_set_defaults(const char * manufacturer,const char * product,const char * version)1017 void smbios_set_defaults(const char *manufacturer, const char *product,
1018 const char *version)
1019 {
1020 smbios_have_defaults = true;
1021
1022 SMBIOS_SET_DEFAULT(smbios_type1.manufacturer, manufacturer);
1023 SMBIOS_SET_DEFAULT(smbios_type1.product, product);
1024 SMBIOS_SET_DEFAULT(smbios_type1.version, version);
1025 SMBIOS_SET_DEFAULT(type2.manufacturer, manufacturer);
1026 SMBIOS_SET_DEFAULT(type2.product, product);
1027 SMBIOS_SET_DEFAULT(type2.version, version);
1028 SMBIOS_SET_DEFAULT(type3.manufacturer, manufacturer);
1029 SMBIOS_SET_DEFAULT(type3.version, version);
1030 SMBIOS_SET_DEFAULT(type4.sock_pfx, "CPU");
1031 SMBIOS_SET_DEFAULT(type4.manufacturer, manufacturer);
1032 SMBIOS_SET_DEFAULT(type4.version, version);
1033 SMBIOS_SET_DEFAULT(type17.loc_pfx, "DIMM");
1034 SMBIOS_SET_DEFAULT(type17.manufacturer, manufacturer);
1035 }
1036
smbios_entry_point_setup(SmbiosEntryPointType ep_type)1037 static void smbios_entry_point_setup(SmbiosEntryPointType ep_type)
1038 {
1039 switch (ep_type) {
1040 case SMBIOS_ENTRY_POINT_TYPE_32:
1041 memcpy(ep.ep21.anchor_string, "_SM_", 4);
1042 memcpy(ep.ep21.intermediate_anchor_string, "_DMI_", 5);
1043 ep.ep21.length = sizeof(struct smbios_21_entry_point);
1044 ep.ep21.entry_point_revision = 0; /* formatted_area reserved */
1045 memset(ep.ep21.formatted_area, 0, 5);
1046
1047 /* compliant with smbios spec v2.8 */
1048 ep.ep21.smbios_major_version = 2;
1049 ep.ep21.smbios_minor_version = 8;
1050 ep.ep21.smbios_bcd_revision = 0x28;
1051
1052 /* set during table construction, but BIOS may override: */
1053 ep.ep21.structure_table_length = cpu_to_le16(smbios_tables_len);
1054 ep.ep21.max_structure_size = cpu_to_le16(smbios_table_max);
1055 ep.ep21.number_of_structures = cpu_to_le16(smbios_table_cnt);
1056
1057 /* BIOS must recalculate */
1058 ep.ep21.checksum = 0;
1059 ep.ep21.intermediate_checksum = 0;
1060 ep.ep21.structure_table_address = cpu_to_le32(0);
1061
1062 break;
1063 case SMBIOS_ENTRY_POINT_TYPE_64:
1064 memcpy(ep.ep30.anchor_string, "_SM3_", 5);
1065 ep.ep30.length = sizeof(struct smbios_30_entry_point);
1066 ep.ep30.entry_point_revision = 1;
1067 ep.ep30.reserved = 0;
1068
1069 /* compliant with smbios spec 3.0 */
1070 ep.ep30.smbios_major_version = 3;
1071 ep.ep30.smbios_minor_version = 0;
1072 ep.ep30.smbios_doc_rev = 0;
1073
1074 /* set during table construct, but BIOS might override */
1075 ep.ep30.structure_table_max_size = cpu_to_le32(smbios_tables_len);
1076
1077 /* BIOS must recalculate */
1078 ep.ep30.checksum = 0;
1079 ep.ep30.structure_table_address = cpu_to_le64(0);
1080
1081 break;
1082 default:
1083 abort();
1084 break;
1085 }
1086 }
1087
smbios_get_tables_ep(MachineState * ms,SmbiosEntryPointType ep_type,const struct smbios_phys_mem_area * mem_array,const unsigned int mem_array_size,uint8_t ** tables,size_t * tables_len,uint8_t ** anchor,size_t * anchor_len,Error ** errp)1088 static bool smbios_get_tables_ep(MachineState *ms,
1089 SmbiosEntryPointType ep_type,
1090 const struct smbios_phys_mem_area *mem_array,
1091 const unsigned int mem_array_size,
1092 uint8_t **tables, size_t *tables_len,
1093 uint8_t **anchor, size_t *anchor_len,
1094 Error **errp)
1095 {
1096 unsigned i, dimm_cnt, offset;
1097 MachineClass *mc = MACHINE_GET_CLASS(ms);
1098 ERRP_GUARD();
1099
1100 assert(ep_type == SMBIOS_ENTRY_POINT_TYPE_32 ||
1101 ep_type == SMBIOS_ENTRY_POINT_TYPE_64);
1102
1103 g_free(smbios_tables);
1104 smbios_type4_count = 0;
1105 smbios_tables = g_memdup2(usr_blobs, usr_blobs_len);
1106 smbios_tables_len = usr_blobs_len;
1107 smbios_table_max = usr_table_max;
1108 smbios_table_cnt = usr_table_cnt;
1109
1110 smbios_build_type_0_table();
1111 smbios_build_type_1_table();
1112 smbios_build_type_2_table();
1113 smbios_build_type_3_table();
1114
1115 assert(ms->smp.sockets >= 1);
1116
1117 for (i = 0; i < ms->smp.sockets; i++) {
1118 smbios_build_type_4_table(ms, i, ep_type, errp);
1119 if (*errp) {
1120 goto err_exit;
1121 }
1122 }
1123
1124 smbios_build_type_8_table();
1125 smbios_build_type_9_table(errp);
1126 smbios_build_type_11_table();
1127
1128 #define GET_DIMM_SZ ((i < dimm_cnt - 1) ? mc->smbios_memory_device_size \
1129 : ((current_machine->ram_size - 1) % mc->smbios_memory_device_size) + 1)
1130
1131 dimm_cnt = QEMU_ALIGN_UP(current_machine->ram_size,
1132 mc->smbios_memory_device_size) /
1133 mc->smbios_memory_device_size;
1134
1135 /*
1136 * The offset determines if we need to keep additional space between
1137 * table 17 and table 19 header handle numbers so that they do
1138 * not overlap. For example, for a VM with larger than 8 TB guest
1139 * memory and DIMM like chunks of 16 GiB, the default space between
1140 * the two tables (T19_BASE - T17_BASE = 512) is not enough.
1141 */
1142 offset = (dimm_cnt > (T19_BASE - T17_BASE)) ? \
1143 dimm_cnt - (T19_BASE - T17_BASE) : 0;
1144
1145 smbios_build_type_16_table(dimm_cnt);
1146
1147 for (i = 0; i < dimm_cnt; i++) {
1148 smbios_build_type_17_table(i, GET_DIMM_SZ);
1149 }
1150
1151 for (i = 0; i < mem_array_size; i++) {
1152 smbios_build_type_19_table(i, offset, mem_array[i].address,
1153 mem_array[i].length);
1154 }
1155
1156 /*
1157 * make sure 16 bit handle numbers in the headers of tables 19
1158 * and 32 do not overlap.
1159 */
1160 assert((mem_array_size + offset) < (T32_BASE - T19_BASE));
1161
1162 smbios_build_type_32_table();
1163 smbios_build_type_38_table();
1164 smbios_build_type_41_table(errp);
1165 smbios_build_type_127_table();
1166
1167 if (!smbios_check_type4_count(ms->smp.sockets, errp)) {
1168 goto err_exit;
1169 }
1170 if (!smbios_validate_table(ep_type, errp)) {
1171 goto err_exit;
1172 }
1173 smbios_entry_point_setup(ep_type);
1174
1175 /* return tables blob and entry point (anchor), and their sizes */
1176 *tables = smbios_tables;
1177 *tables_len = smbios_tables_len;
1178 *anchor = (uint8_t *)&ep;
1179 /* calculate length based on anchor string */
1180 if (!strncmp((char *)&ep, "_SM_", 4)) {
1181 *anchor_len = sizeof(struct smbios_21_entry_point);
1182 } else if (!strncmp((char *)&ep, "_SM3_", 5)) {
1183 *anchor_len = sizeof(struct smbios_30_entry_point);
1184 } else {
1185 abort();
1186 }
1187
1188 return true;
1189 err_exit:
1190 g_free(smbios_tables);
1191 smbios_tables = NULL;
1192 return false;
1193 }
1194
smbios_get_tables(MachineState * ms,SmbiosEntryPointType ep_type,const struct smbios_phys_mem_area * mem_array,const unsigned int mem_array_size,uint8_t ** tables,size_t * tables_len,uint8_t ** anchor,size_t * anchor_len,Error ** errp)1195 void smbios_get_tables(MachineState *ms,
1196 SmbiosEntryPointType ep_type,
1197 const struct smbios_phys_mem_area *mem_array,
1198 const unsigned int mem_array_size,
1199 uint8_t **tables, size_t *tables_len,
1200 uint8_t **anchor, size_t *anchor_len,
1201 Error **errp)
1202 {
1203 Error *local_err = NULL;
1204 bool is_valid;
1205 ERRP_GUARD();
1206
1207 switch (ep_type) {
1208 case SMBIOS_ENTRY_POINT_TYPE_AUTO:
1209 case SMBIOS_ENTRY_POINT_TYPE_32:
1210 is_valid = smbios_get_tables_ep(ms, SMBIOS_ENTRY_POINT_TYPE_32,
1211 mem_array, mem_array_size,
1212 tables, tables_len,
1213 anchor, anchor_len,
1214 &local_err);
1215 if (is_valid || ep_type != SMBIOS_ENTRY_POINT_TYPE_AUTO) {
1216 break;
1217 }
1218 /*
1219 * fall through in case AUTO endpoint is selected and
1220 * SMBIOS 2.x tables can't be generated, to try if SMBIOS 3.x
1221 * tables would work
1222 */
1223 case SMBIOS_ENTRY_POINT_TYPE_64:
1224 error_free(local_err);
1225 local_err = NULL;
1226 is_valid = smbios_get_tables_ep(ms, SMBIOS_ENTRY_POINT_TYPE_64,
1227 mem_array, mem_array_size,
1228 tables, tables_len,
1229 anchor, anchor_len,
1230 &local_err);
1231 break;
1232 default:
1233 abort();
1234 }
1235 if (!is_valid) {
1236 error_propagate(errp, local_err);
1237 }
1238 }
1239
save_opt(const char ** dest,QemuOpts * opts,const char * name)1240 static void save_opt(const char **dest, QemuOpts *opts, const char *name)
1241 {
1242 const char *val = qemu_opt_get(opts, name);
1243
1244 if (val) {
1245 *dest = val;
1246 }
1247 }
1248
1249
1250 struct opt_list {
1251 size_t *ndest;
1252 char ***dest;
1253 };
1254
save_opt_one(void * opaque,const char * name,const char * value,Error ** errp)1255 static int save_opt_one(void *opaque,
1256 const char *name, const char *value,
1257 Error **errp)
1258 {
1259 struct opt_list *opt = opaque;
1260
1261 if (g_str_equal(name, "path")) {
1262 g_autoptr(GByteArray) data = g_byte_array_new();
1263 g_autofree char *buf = g_new(char, 4096);
1264 ssize_t ret;
1265 int fd = qemu_open(value, O_RDONLY, errp);
1266 if (fd < 0) {
1267 return -1;
1268 }
1269
1270 while (1) {
1271 ret = read(fd, buf, 4096);
1272 if (ret == 0) {
1273 break;
1274 }
1275 if (ret < 0) {
1276 error_setg(errp, "Unable to read from %s: %s",
1277 value, strerror(errno));
1278 qemu_close(fd);
1279 return -1;
1280 }
1281 if (memchr(buf, '\0', ret)) {
1282 error_setg(errp, "NUL in OEM strings value in %s", value);
1283 qemu_close(fd);
1284 return -1;
1285 }
1286 g_byte_array_append(data, (guint8 *)buf, ret);
1287 }
1288
1289 buf[0] = '\0';
1290 g_byte_array_append(data, (guint8 *)buf, 1);
1291
1292 qemu_close(fd);
1293
1294 *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1);
1295 (*opt->dest)[*opt->ndest] = (char *)g_byte_array_free(data, FALSE);
1296 (*opt->ndest)++;
1297 data = NULL;
1298 } else if (g_str_equal(name, "value")) {
1299 *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1);
1300 (*opt->dest)[*opt->ndest] = g_strdup(value);
1301 (*opt->ndest)++;
1302 } else if (!g_str_equal(name, "type")) {
1303 error_setg(errp, "Unexpected option %s", name);
1304 return -1;
1305 }
1306
1307 return 0;
1308 }
1309
save_opt_list(size_t * ndest,char *** dest,QemuOpts * opts,Error ** errp)1310 static bool save_opt_list(size_t *ndest, char ***dest, QemuOpts *opts,
1311 Error **errp)
1312 {
1313 struct opt_list opt = {
1314 ndest, dest,
1315 };
1316 if (!qemu_opt_foreach(opts, save_opt_one, &opt, errp)) {
1317 return false;
1318 }
1319 return true;
1320 }
1321
smbios_entry_add(QemuOpts * opts,Error ** errp)1322 void smbios_entry_add(QemuOpts *opts, Error **errp)
1323 {
1324 const char *val;
1325
1326 val = qemu_opt_get(opts, "file");
1327 if (val) {
1328 struct smbios_structure_header *header;
1329 size_t size;
1330
1331 if (!qemu_opts_validate(opts, qemu_smbios_file_opts, errp)) {
1332 return;
1333 }
1334
1335 size = get_image_size(val);
1336 if (size == -1 || size < sizeof(struct smbios_structure_header)) {
1337 error_setg(errp, "Cannot read SMBIOS file %s", val);
1338 return;
1339 }
1340
1341 /*
1342 * NOTE: standard double '\0' terminator expected, per smbios spec.
1343 * (except in legacy mode, where the second '\0' is implicit and
1344 * will be inserted by the BIOS).
1345 */
1346 usr_blobs = g_realloc(usr_blobs, usr_blobs_len + size);
1347 header = (struct smbios_structure_header *)(usr_blobs +
1348 usr_blobs_len);
1349
1350 if (load_image_size(val, (uint8_t *)header, size) != size) {
1351 error_setg(errp, "Failed to load SMBIOS file %s", val);
1352 return;
1353 }
1354
1355 if (header->type <= SMBIOS_MAX_TYPE) {
1356 if (test_bit(header->type, smbios_have_fields_bitmap)) {
1357 error_setg(errp,
1358 "can't load type %d struct, fields already specified!",
1359 header->type);
1360 return;
1361 }
1362 set_bit(header->type, smbios_have_binfile_bitmap);
1363 }
1364
1365 if (header->type == 4) {
1366 smbios_type4_count++;
1367 }
1368
1369 /*
1370 * preserve blob size for legacy mode so it could build its
1371 * blobs flavor from 'usr_blobs'
1372 */
1373 smbios_add_usr_blob_size(size);
1374
1375 usr_blobs_len += size;
1376 if (size > usr_table_max) {
1377 usr_table_max = size;
1378 }
1379 usr_table_cnt++;
1380
1381 return;
1382 }
1383
1384 val = qemu_opt_get(opts, "type");
1385 if (val) {
1386 unsigned long type = strtoul(val, NULL, 0);
1387
1388 if (type > SMBIOS_MAX_TYPE) {
1389 error_setg(errp, "out of range!");
1390 return;
1391 }
1392
1393 if (test_bit(type, smbios_have_binfile_bitmap)) {
1394 error_setg(errp, "can't add fields, binary file already loaded!");
1395 return;
1396 }
1397 set_bit(type, smbios_have_fields_bitmap);
1398
1399 switch (type) {
1400 case 0:
1401 if (!qemu_opts_validate(opts, qemu_smbios_type0_opts, errp)) {
1402 return;
1403 }
1404 save_opt(&smbios_type0.vendor, opts, "vendor");
1405 save_opt(&smbios_type0.version, opts, "version");
1406 save_opt(&smbios_type0.date, opts, "date");
1407 smbios_type0.uefi = qemu_opt_get_bool(opts, "uefi", false);
1408
1409 val = qemu_opt_get(opts, "release");
1410 if (val) {
1411 if (sscanf(val, "%hhu.%hhu", &smbios_type0.major,
1412 &smbios_type0.minor) != 2) {
1413 error_setg(errp, "Invalid release");
1414 return;
1415 }
1416 smbios_type0.have_major_minor = true;
1417 }
1418 return;
1419 case 1:
1420 if (!qemu_opts_validate(opts, qemu_smbios_type1_opts, errp)) {
1421 return;
1422 }
1423 save_opt(&smbios_type1.manufacturer, opts, "manufacturer");
1424 save_opt(&smbios_type1.product, opts, "product");
1425 save_opt(&smbios_type1.version, opts, "version");
1426 save_opt(&smbios_type1.serial, opts, "serial");
1427 save_opt(&smbios_type1.sku, opts, "sku");
1428 save_opt(&smbios_type1.family, opts, "family");
1429
1430 val = qemu_opt_get(opts, "uuid");
1431 if (val) {
1432 if (qemu_uuid_parse(val, &qemu_uuid) != 0) {
1433 error_setg(errp, "Invalid UUID");
1434 return;
1435 }
1436 qemu_uuid_set = true;
1437 }
1438 return;
1439 case 2:
1440 if (!qemu_opts_validate(opts, qemu_smbios_type2_opts, errp)) {
1441 return;
1442 }
1443 save_opt(&type2.manufacturer, opts, "manufacturer");
1444 save_opt(&type2.product, opts, "product");
1445 save_opt(&type2.version, opts, "version");
1446 save_opt(&type2.serial, opts, "serial");
1447 save_opt(&type2.asset, opts, "asset");
1448 save_opt(&type2.location, opts, "location");
1449 return;
1450 case 3:
1451 if (!qemu_opts_validate(opts, qemu_smbios_type3_opts, errp)) {
1452 return;
1453 }
1454 save_opt(&type3.manufacturer, opts, "manufacturer");
1455 save_opt(&type3.version, opts, "version");
1456 save_opt(&type3.serial, opts, "serial");
1457 save_opt(&type3.asset, opts, "asset");
1458 save_opt(&type3.sku, opts, "sku");
1459 return;
1460 case 4:
1461 if (!qemu_opts_validate(opts, qemu_smbios_type4_opts, errp)) {
1462 return;
1463 }
1464 save_opt(&type4.sock_pfx, opts, "sock_pfx");
1465 type4.processor_family = qemu_opt_get_number(opts,
1466 "processor-family",
1467 0x01 /* Other */);
1468 save_opt(&type4.manufacturer, opts, "manufacturer");
1469 save_opt(&type4.version, opts, "version");
1470 save_opt(&type4.serial, opts, "serial");
1471 save_opt(&type4.asset, opts, "asset");
1472 save_opt(&type4.part, opts, "part");
1473 /* If the value is 0, it will take the value from the CPU model. */
1474 type4.processor_id = qemu_opt_get_number(opts, "processor-id", 0);
1475 type4.max_speed = qemu_opt_get_number(opts, "max-speed",
1476 DEFAULT_CPU_SPEED);
1477 type4.current_speed = qemu_opt_get_number(opts, "current-speed",
1478 DEFAULT_CPU_SPEED);
1479 if (type4.max_speed > UINT16_MAX ||
1480 type4.current_speed > UINT16_MAX) {
1481 error_setg(errp, "SMBIOS CPU speed is too large (> %d)",
1482 UINT16_MAX);
1483 }
1484 return;
1485 case 8:
1486 if (!qemu_opts_validate(opts, qemu_smbios_type8_opts, errp)) {
1487 return;
1488 }
1489 struct type8_instance *t8_i;
1490 t8_i = g_new0(struct type8_instance, 1);
1491 save_opt(&t8_i->internal_reference, opts, "internal_reference");
1492 save_opt(&t8_i->external_reference, opts, "external_reference");
1493 t8_i->connector_type = qemu_opt_get_number(opts,
1494 "connector_type", 0);
1495 t8_i->port_type = qemu_opt_get_number(opts, "port_type", 0);
1496 QTAILQ_INSERT_TAIL(&type8, t8_i, next);
1497 return;
1498 case 9: {
1499 if (!qemu_opts_validate(opts, qemu_smbios_type9_opts, errp)) {
1500 return;
1501 }
1502 struct type9_instance *t;
1503 t = g_new0(struct type9_instance, 1);
1504 save_opt(&t->slot_designation, opts, "slot_designation");
1505 t->slot_type = qemu_opt_get_number(opts, "slot_type", 0);
1506 t->slot_data_bus_width =
1507 qemu_opt_get_number(opts, "slot_data_bus_width", 0);
1508 t->current_usage = qemu_opt_get_number(opts, "current_usage", 0);
1509 t->slot_length = qemu_opt_get_number(opts, "slot_length", 0);
1510 t->slot_id = qemu_opt_get_number(opts, "slot_id", 0);
1511 t->slot_characteristics1 =
1512 qemu_opt_get_number(opts, "slot_characteristics1", 0);
1513 t->slot_characteristics2 =
1514 qemu_opt_get_number(opts, "slot_characteristics2", 0);
1515 save_opt(&t->pcidev, opts, "pcidev");
1516 QTAILQ_INSERT_TAIL(&type9, t, next);
1517 return;
1518 }
1519 case 11:
1520 if (!qemu_opts_validate(opts, qemu_smbios_type11_opts, errp)) {
1521 return;
1522 }
1523 if (!save_opt_list(&type11.nvalues, &type11.values, opts, errp)) {
1524 return;
1525 }
1526 return;
1527 case 17:
1528 if (!qemu_opts_validate(opts, qemu_smbios_type17_opts, errp)) {
1529 return;
1530 }
1531 save_opt(&type17.loc_pfx, opts, "loc_pfx");
1532 save_opt(&type17.bank, opts, "bank");
1533 save_opt(&type17.manufacturer, opts, "manufacturer");
1534 save_opt(&type17.serial, opts, "serial");
1535 save_opt(&type17.asset, opts, "asset");
1536 save_opt(&type17.part, opts, "part");
1537 type17.speed = qemu_opt_get_number(opts, "speed", 0);
1538 return;
1539 case 41: {
1540 struct type41_instance *t41_i;
1541 Error *local_err = NULL;
1542
1543 if (!qemu_opts_validate(opts, qemu_smbios_type41_opts, errp)) {
1544 return;
1545 }
1546 t41_i = g_new0(struct type41_instance, 1);
1547 save_opt(&t41_i->designation, opts, "designation");
1548 t41_i->kind = qapi_enum_parse(&type41_kind_lookup,
1549 qemu_opt_get(opts, "kind"),
1550 0, &local_err) + 1;
1551 t41_i->kind |= 0x80; /* enabled */
1552 if (local_err != NULL) {
1553 error_propagate(errp, local_err);
1554 g_free(t41_i);
1555 return;
1556 }
1557 t41_i->instance = qemu_opt_get_number(opts, "instance", 1);
1558 save_opt(&t41_i->pcidev, opts, "pcidev");
1559
1560 QTAILQ_INSERT_TAIL(&type41, t41_i, next);
1561 return;
1562 }
1563 default:
1564 error_setg(errp,
1565 "Don't know how to build fields for SMBIOS type %ld",
1566 type);
1567 return;
1568 }
1569 }
1570
1571 error_setg(errp, "Must specify type= or file=");
1572 }
1573