1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/phy/pcie.h>
18 #include <linux/phy/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/reset.h>
23 #include <linux/slab.h>
24
25 #include "phy-qcom-qmp.h"
26 #include "phy-qcom-qmp-pcs-misc-v3.h"
27 #include "phy-qcom-qmp-pcs-pcie-v4.h"
28 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
29 #include "phy-qcom-qmp-pcs-pcie-v5.h"
30 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
31 #include "phy-qcom-qmp-pcs-pcie-v6.h"
32 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
33 #include "phy-qcom-qmp-pcie-qhp.h"
34
35 /* QPHY_SW_RESET bit */
36 #define SW_RESET BIT(0)
37 /* QPHY_POWER_DOWN_CONTROL */
38 #define SW_PWRDN BIT(0)
39 #define REFCLK_DRV_DSBL BIT(1)
40 /* QPHY_START_CONTROL bits */
41 #define SERDES_START BIT(0)
42 #define PCS_START BIT(1)
43 /* QPHY_PCS_STATUS bit */
44 #define PHYSTATUS BIT(6)
45 #define PHYSTATUS_4_20 BIT(7)
46
47 #define PHY_INIT_COMPLETE_TIMEOUT 10000
48
49 struct qmp_phy_init_tbl {
50 unsigned int offset;
51 unsigned int val;
52 /*
53 * mask of lanes for which this register is written
54 * for cases when second lane needs different values
55 */
56 u8 lane_mask;
57 };
58
59 #define QMP_PHY_INIT_CFG(o, v) \
60 { \
61 .offset = o, \
62 .val = v, \
63 .lane_mask = 0xff, \
64 }
65
66 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \
67 { \
68 .offset = o, \
69 .val = v, \
70 .lane_mask = l, \
71 }
72
73 /* set of registers with offsets different per-PHY */
74 enum qphy_reg_layout {
75 /* PCS registers */
76 QPHY_SW_RESET,
77 QPHY_START_CTRL,
78 QPHY_PCS_STATUS,
79 QPHY_PCS_POWER_DOWN_CONTROL,
80 /* Keep last to ensure regs_layout arrays are properly initialized */
81 QPHY_LAYOUT_SIZE
82 };
83
84 static const unsigned int pciephy_v2_regs_layout[QPHY_LAYOUT_SIZE] = {
85 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
86 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
87 [QPHY_PCS_STATUS] = QPHY_V2_PCS_PCI_PCS_STATUS,
88 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
89 };
90
91 static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = {
92 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
93 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
94 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
95 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
96 };
97
98 static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = {
99 [QPHY_SW_RESET] = 0x00,
100 [QPHY_START_CTRL] = 0x08,
101 [QPHY_PCS_STATUS] = 0x2ac,
102 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04,
103 };
104
105 static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = {
106 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
107 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
108 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
109 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
110 };
111
112 static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
113 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
114 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
115 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
116 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
117 };
118
119 static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
120 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
121 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
122 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x0f),
123 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
124 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
125 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
126 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
127 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
128 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
129 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
130 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
131 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
132 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
133 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
134 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
135 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
136 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
137 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x03),
138 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x55),
139 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x55),
140 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
141 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
142 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
143 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
144 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x08),
145 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
146 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x34),
147 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
148 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
149 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
150 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x07),
151 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
152 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
153 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
154 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
155 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
156 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
157 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
158 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
159 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
160 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
161 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
162 };
163
164 static const struct qmp_phy_init_tbl msm8998_pcie_tx_tbl[] = {
165 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
166 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
167 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
168 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
169 };
170
171 static const struct qmp_phy_init_tbl msm8998_pcie_rx_tbl[] = {
172 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
173 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x1c),
174 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
175 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0a),
176 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
177 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
178 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
179 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
180 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
181 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x00),
182 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
183 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
184 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
185 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
186 };
187
188 static const struct qmp_phy_init_tbl msm8998_pcie_pcs_tbl[] = {
189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
192 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
194 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x99),
198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
199 };
200
201 static const struct qmp_phy_init_tbl ipq6018_pcie_serdes_tbl[] = {
202 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER1, 0x7d),
203 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_PER2, 0x01),
204 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE0, 0x0a),
205 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE0, 0x05),
206 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE1_MODE1, 0x08),
207 QMP_PHY_INIT_CFG(QSERDES_PLL_SSC_STEP_SIZE2_MODE1, 0x04),
208 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
209 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
210 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
211 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
212 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
213 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0xd4),
214 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x14),
215 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0xaa),
216 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x29),
217 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
218 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0x09),
219 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x09),
220 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
221 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
222 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
223 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
224 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
225 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
226 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
227 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
228 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x68),
229 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x53),
230 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0xab),
231 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0xaa),
232 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x02),
233 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x55),
234 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x55),
235 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x05),
236 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0xa0),
237 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0xa0),
238 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
239 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
240 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
241 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
242 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
243 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x01),
244 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x00),
245 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
246 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
247 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
248 };
249
250 static const struct qmp_phy_init_tbl ipq6018_pcie_tx_tbl[] = {
251 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
252 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
253 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
254 };
255
256 static const struct qmp_phy_init_tbl ipq6018_pcie_rx_tbl[] = {
257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
258 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
259 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
260 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
261 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x61),
262 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
263 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1e),
264 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
265 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
266 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
267 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
268 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
269 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
270 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
271 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
272 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x01),
273 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
274 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
275 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
276 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
277 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
278 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
279 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
280 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
281 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
282 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
283 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
284 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
285 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
286 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
287 };
288
289 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_tbl[] = {
290 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
291 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
292 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
293 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
294 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
295 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
296 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
297 };
298
299 static const struct qmp_phy_init_tbl ipq6018_pcie_pcs_misc_tbl[] = {
300 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
301 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
302 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
303 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
304 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
305 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
306 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
307 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
308 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
309 };
310
311 static const struct qmp_phy_init_tbl ipq8074_pcie_serdes_tbl[] = {
312 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
313 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
314 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0xf),
315 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x1),
316 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x0),
317 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
318 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
319 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x6),
320 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0xf),
321 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x0),
322 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x1),
323 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x20),
324 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0xa),
325 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20),
326 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0xa),
327 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xa),
328 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
329 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x3),
330 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
331 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
332 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x0),
333 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0xD),
334 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xD04),
335 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
336 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x2),
337 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
338 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0xb),
339 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
340 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
341 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x0),
342 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
343 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x1),
344 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x1),
345 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
346 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x1),
347 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x2),
348 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x0),
349 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
350 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
351 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
352 };
353
354 static const struct qmp_phy_init_tbl ipq8074_pcie_tx_tbl[] = {
355 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
356 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x6),
357 QMP_PHY_INIT_CFG(QSERDES_TX_RES_CODE_LANE_OFFSET, 0x2),
358 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
359 QMP_PHY_INIT_CFG(QSERDES_TX_TX_EMP_POST1_LVL, 0x36),
360 QMP_PHY_INIT_CFG(QSERDES_TX_SLEW_CNTL, 0x0a),
361 };
362
363 static const struct qmp_phy_init_tbl ipq8074_pcie_rx_tbl[] = {
364 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
365 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
366 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x1),
367 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x0),
368 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
369 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
370 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x4),
371 };
372
373 static const struct qmp_phy_init_tbl ipq8074_pcie_pcs_tbl[] = {
374 QMP_PHY_INIT_CFG(QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE, 0x4),
375 QMP_PHY_INIT_CFG(QPHY_V2_PCS_OSC_DTCT_ACTIONS, 0x0),
376 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x40),
377 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x0),
378 QMP_PHY_INIT_CFG(QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x40),
379 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB, 0x0),
380 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x40),
381 QMP_PHY_INIT_CFG(QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
382 QMP_PHY_INIT_CFG(QPHY_V2_PCS_RX_SIGDET_LVL, 0x99),
383 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M6DB_V0, 0x15),
384 QMP_PHY_INIT_CFG(QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0, 0xe),
385 };
386
387 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_serdes_tbl[] = {
388 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CLKBUFLR_EN, 0x18),
389 QMP_PHY_INIT_CFG(QSERDES_PLL_BIAS_EN_CTRL_BY_PSM, 0x01),
390 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x31),
391 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_IVCO, 0x0f),
392 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TRIM, 0x0f),
393 QMP_PHY_INIT_CFG(QSERDES_PLL_CMN_CONFIG, 0x06),
394 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP_EN, 0x42),
395 QMP_PHY_INIT_CFG(QSERDES_PLL_RESETSM_CNTRL, 0x20),
396 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x01),
397 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_MAP, 0x04),
398 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
399 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER1, 0xff),
400 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE_TIMER2, 0x3f),
401 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x30),
402 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x21),
403 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE0, 0x82),
404 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE0, 0x03),
405 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE0, 0x355),
406 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE0, 0x35555),
407 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE0, 0x1a),
408 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE0, 0x1a0a),
409 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE0, 0xb),
410 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE0, 0x16),
411 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE0, 0x28),
412 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE0, 0x0),
413 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE0, 0x40),
414 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE0, 0x02),
415 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE0, 0x24),
416 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
417 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x20),
418 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV, 0xa),
419 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_SELECT, 0x32),
420 QMP_PHY_INIT_CFG(QSERDES_PLL_SYS_CLK_CTRL, 0x02),
421 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_BUF_ENABLE, 0x07),
422 QMP_PHY_INIT_CFG(QSERDES_PLL_SYSCLK_EN_SEL, 0x08),
423 QMP_PHY_INIT_CFG(QSERDES_PLL_BG_TIMER, 0xa),
424 QMP_PHY_INIT_CFG(QSERDES_PLL_HSCLK_SEL, 0x1),
425 QMP_PHY_INIT_CFG(QSERDES_PLL_DEC_START_MODE1, 0x68),
426 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START3_MODE1, 0x2),
427 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START2_MODE1, 0x2aa),
428 QMP_PHY_INIT_CFG(QSERDES_PLL_DIV_FRAC_START1_MODE1, 0x2aaab),
429 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
430 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP2_MODE1, 0x34),
431 QMP_PHY_INIT_CFG(QSERDES_PLL_LOCK_CMP1_MODE1, 0x3414),
432 QMP_PHY_INIT_CFG(QSERDES_PLL_CP_CTRL_MODE1, 0x0b),
433 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_RCTRL_MODE1, 0x16),
434 QMP_PHY_INIT_CFG(QSERDES_PLL_PLL_CCTRL_MODE1, 0x28),
435 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN1_MODE1, 0x0),
436 QMP_PHY_INIT_CFG(QSERDES_PLL_INTEGLOOP_GAIN0_MODE1, 0x40),
437 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE2_MODE1, 0x03),
438 QMP_PHY_INIT_CFG(QSERDES_PLL_VCO_TUNE1_MODE1, 0xb4),
439 QMP_PHY_INIT_CFG(QSERDES_PLL_SVS_MODE_CLK_SEL, 0x05),
440 QMP_PHY_INIT_CFG(QSERDES_PLL_CORE_CLK_EN, 0x0),
441 QMP_PHY_INIT_CFG(QSERDES_PLL_CORECLK_DIV_MODE1, 0x08),
442 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE0, 0x19),
443 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_EP_DIV_MODE1, 0x28),
444 QMP_PHY_INIT_CFG(QSERDES_PLL_CLK_ENABLE1, 0x90),
445 };
446
447 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_tx_tbl[] = {
448 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
449 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
450 QMP_PHY_INIT_CFG(QSERDES_V4_TX_HIGHZ_DRVR_EN, 0x10),
451 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x06),
452 };
453
454 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_rx_tbl[] = {
455 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
456 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
457 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
458 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0xe),
459 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4),
460 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b),
461 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
462 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
463 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
464 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x73),
465 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
466 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0x00),
467 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x02),
468 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8),
469 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x09),
470 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1),
471 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x01),
472 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x02),
473 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8),
474 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x09),
475 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1),
476 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xf0),
477 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2),
478 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x2f),
479 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xd3),
480 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x40),
481 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
482 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
483 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
484 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x02),
485 };
486
487 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_tbl[] = {
488 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL2, 0x83),
489 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_L, 0x9),
490 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNT_VAL_H_TOL, 0x42),
491 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_MAN_CODE, 0x40),
492 QMP_PHY_INIT_CFG(QPHY_V4_PCS_FLL_CNTRL1, 0x01),
493 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H, 0x0),
494 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x1),
495 QMP_PHY_INIT_CFG(QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB, 0x10),
496 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_DCC_CAL_CONFIG, 0x01),
497 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
498 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
499 };
500
501 static const struct qmp_phy_init_tbl ipq8074_pcie_gen3_pcs_misc_tbl[] = {
502 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x0),
503 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
504 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
505 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H, 0x00),
506 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
507 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG1, 0x11),
508 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0xb),
509 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
510 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_CONFIG2, 0x52),
511 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG2, 0x50),
512 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG4, 0x1a),
513 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x6),
514 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
515 };
516
517 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_serdes_tbl[] = {
518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x007),
521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01),
523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20),
524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER1, 0xff),
528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_TIMER2, 0x3f),
529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_EP_DIV, 0x19),
533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x90),
534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0d),
540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x04),
541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
544 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
545 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
546 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x33),
547 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
548 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
549 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x04),
550 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
551 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
552 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x09),
553 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
554 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x40),
555 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
556 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x02),
557 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
558 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x7e),
559 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x15),
560 };
561
562 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_tx_tbl[] = {
563 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x02),
564 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
565 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
566 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
567 };
568
569 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_rx_tbl[] = {
570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
571 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x10),
572 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
573 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
574 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04),
575 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a),
576 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
577 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x04),
578 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN_HALF, 0x04),
579 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x71),
580 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
581 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_01, 0x59),
582 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
583 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40),
584 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x71),
585 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x40),
586 };
587
588 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_tbl[] = {
589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE, 0x04),
590
591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
596
597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_OSC_DTCT_ACTIONS, 0x00),
598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x01),
599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB, 0x20),
601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB, 0x00),
602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME, 0x73),
604
605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xbb),
606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_SIGDET_CNTRL, 0x03),
607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x0d),
608
609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG4, 0x00),
610 };
611
612 static const struct qmp_phy_init_tbl sdm845_qmp_pcie_pcs_misc_tbl[] = {
613 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2, 0x52),
614 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2, 0x10),
615 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4, 0x1a),
616 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5, 0x06),
617 QMP_PHY_INIT_CFG(QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
618 };
619
620 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_serdes_tbl[] = {
621 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL, 0x27),
622 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_EN_CENTER, 0x01),
623 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER1, 0x31),
624 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_PER2, 0x01),
625 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1, 0xde),
626 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2, 0x07),
627 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
628 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1, 0x06),
629 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN, 0x18),
630 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_ENABLE1, 0xb0),
631 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0, 0x8c),
632 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0, 0x20),
633 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1, 0x14),
634 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1, 0x34),
635 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE0, 0x06),
636 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CP_CTRL_MODE1, 0x06),
637 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0, 0x16),
638 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1, 0x16),
639 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0, 0x36),
640 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1, 0x36),
641 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_RESTRIM_CTRL2, 0x05),
642 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_LOCK_CMP_EN, 0x42),
643 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE0, 0x82),
644 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DEC_START_MODE1, 0x68),
645 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0, 0x55),
646 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0, 0x55),
647 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0, 0x03),
648 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1, 0xab),
649 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1, 0xaa),
650 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1, 0x02),
651 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
652 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1, 0x3f),
653 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VCO_TUNE_MAP, 0x10),
654 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CLK_SELECT, 0x04),
655 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_HSCLK_SEL1, 0x30),
656 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV, 0x04),
657 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORE_CLK_EN, 0x73),
658 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_CONFIG, 0x0c),
659 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL, 0x15),
660 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1, 0x04),
661 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_CMN_MODE, 0x01),
662 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV1, 0x22),
663 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_VREGCLK_DIV2, 0x00),
664 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BGV_TRIM, 0x20),
665 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_COM_BG_CTRL, 0x07),
666 };
667
668 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_tx_tbl[] = {
669 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL0, 0x00),
670 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_TAP_EN, 0x0d),
671 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TX_BAND_MODE, 0x01),
672 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_LANE_MODE, 0x1a),
673 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PARALLEL_RATE, 0x2f),
674 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE0, 0x09),
675 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE1, 0x09),
676 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CML_CTRL_MODE2, 0x1b),
677 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1, 0x01),
678 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2, 0x07),
679 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0, 0x31),
680 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1, 0x31),
681 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2, 0x03),
682 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE, 0x02),
683 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CGA_THRESH_DFE, 0x00),
684 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXENGINE_EN0, 0x12),
685 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME, 0x25),
686 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME, 0x00),
687 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME, 0x05),
688 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME, 0x01),
689 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_GAIN, 0x26),
690 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DFE_GAIN, 0x12),
691 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_GAIN, 0x04),
692 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_OFFSET_GAIN, 0x04),
693 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PRE_GAIN, 0x09),
694 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EQ_INTVAL, 0x15),
695 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_EDAC_INITVAL, 0x28),
696 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB0, 0x7f),
697 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_INITB1, 0x07),
698 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1, 0x04),
699 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RXEQ_CTRL, 0x70),
700 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0, 0x8b),
701 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1, 0x08),
702 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2, 0x0a),
703 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0, 0x03),
704 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1, 0x04),
705 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2, 0x04),
706 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG, 0x0c),
707 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_BAND, 0x02),
708 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0, 0x5c),
709 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1, 0x3e),
710 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2, 0x3f),
711 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_ENABLES, 0x01),
712 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_CNTRL, 0xa0),
713 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL, 0x08),
714 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DCC_GAIN, 0x01),
715 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_EN_SIGNAL, 0xc3),
716 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL, 0x00),
717 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0, 0xbc),
718 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_TS0_TIMER, 0x7f),
719 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE, 0x15),
720 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL1, 0x0c),
721 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_DRVR_CTRL2, 0x0f),
722 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET, 0x04),
723 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_VGA_INITVAL, 0x20),
724 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_L0_RSM_START, 0x01),
725 };
726
727 static const struct qmp_phy_init_tbl sdm845_qhp_pcie_pcs_tbl[] = {
728 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG, 0x3f),
729 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG, 0x50),
730 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB, 0x19),
731 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB, 0x07),
732 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB, 0x17),
733 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB, 0x09),
734 QMP_PHY_INIT_CFG(PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5, 0x9f),
735 };
736
737 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_serdes_tbl[] = {
738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
766 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
767 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
768 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
769 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
770 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
771 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
772 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
773 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
774 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
775 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
776 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
777 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
778 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
779 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
780 };
781
782 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_tx_tbl[] = {
783 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
784 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x5),
785 };
786
787 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_rx_tbl[] = {
788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x07),
792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x6e),
793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6e),
794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x4a),
795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x37),
801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x39),
805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x39),
810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff),
813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xdb),
815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x75),
816 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
817 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
818 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
819 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0xc0),
820 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
821 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x05),
822 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
823 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
824 };
825
826 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_tbl[] = {
827 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
828 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
829 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
830 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
831 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x01),
832 };
833
834 static const struct qmp_phy_init_tbl sc8180x_qmp_pcie_pcs_misc_tbl[] = {
835 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
836 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
837 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
838 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
839 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
840 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
841 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
842 };
843
844 static const struct qmp_phy_init_tbl sc8280xp_qmp_pcie_serdes_tbl[] = {
845 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
846 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
847 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
848 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
849 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
850 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
851 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
852 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
853 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
854 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
855 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
856 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
857 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
858 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
859 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
860 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
861 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
862 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
863 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
864 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
865 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
866 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
867 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
868 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
869 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
870 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
871 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
872 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
873 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
874 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
875 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
876 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
877 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
878 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
879 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
880 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
881 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb9),
882 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
883 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x94),
884 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
885 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
886 };
887
888 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
889 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
890 };
891
892 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl[] = {
893 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
894 };
895
896 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl[] = {
897 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
898 };
899
900 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_tx_tbl[] = {
901 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
902 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
903 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
904 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
905 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
906 };
907
908 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_rx_tbl[] = {
909 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
910 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
911 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
912 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
913 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
914 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
915 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
916 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
917 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
918 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
919 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
920 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
921 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
922 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
923 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
924 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
925 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
926 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
927 };
928
929 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_tbl[] = {
930 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
931 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
932 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
933 };
934
935 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
936 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
937 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
938 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
939 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
940 };
941
942 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_tx_tbl[] = {
943 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
944 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
945 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
946 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
947 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
948 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
949 };
950
951 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_rx_tbl[] = {
952 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
953 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
954 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
955 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
956 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
957 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
958 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
959 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
960 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
961 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
962 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
963 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
964 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
965 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
966 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
967 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
968 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
969 };
970
971 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_tbl[] = {
972 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
973 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x88),
974 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
975 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x0f),
976 };
977
978 static const struct qmp_phy_init_tbl sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
979 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
980 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
981 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
982 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
983 };
984
985 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_serdes_tbl[] = {
986 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
987 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
989 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x42),
991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
992 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x03),
993 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0xb4),
994 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
995 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x03),
998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x55),
999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x55),
1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1a),
1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0a),
1002 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x68),
1003 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
1004 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xaa),
1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x34),
1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x14),
1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1012 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1013 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1014 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1015 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1016 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1017 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1018 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1019 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1020 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1021 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1022 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1023 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1024 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1025 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1026 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1027 };
1028
1029 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_serdes_tbl[] = {
1030 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x07),
1031 };
1032
1033 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_tx_tbl[] = {
1034 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1035 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35),
1036 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1037 };
1038
1039 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_rx_tbl[] = {
1040 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c),
1041 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x03),
1042 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1b),
1043 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1044 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1045 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0x30),
1046 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x04),
1047 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x07),
1048 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1049 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x70),
1050 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1051 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1052 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f),
1053 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x03),
1054 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_ENABLES, 0x1c),
1055 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
1056 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17),
1057 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xd4),
1058 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0x54),
1059 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xdb),
1060 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b),
1061 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0x31),
1062 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x24),
1063 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff),
1064 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1065 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1066 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xe4),
1067 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xec),
1068 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b),
1069 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x36),
1070 };
1071
1072 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_rx_tbl[] = {
1073 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RCLK_AUXDATA_SEL, 0x00),
1074 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x00),
1075 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1076 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f),
1077 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x14),
1078 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
1079 };
1080
1081 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_tbl[] = {
1082 QMP_PHY_INIT_CFG(QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1083 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0x77),
1084 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RATE_SLEW_CNTRL1, 0x0b),
1085 };
1086
1087 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_tbl[] = {
1088 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x0d),
1089 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x12),
1090 };
1091
1092 static const struct qmp_phy_init_tbl sm8250_qmp_pcie_pcs_misc_tbl[] = {
1093 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1094 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1095 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L, 0x01),
1096 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE, 0x33),
1097 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_PRE, 0x00),
1098 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_PRESET_P10_POST, 0x58),
1099 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1100 };
1101
1102 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1103 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1104 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_EQ_CONFIG2, 0x0f),
1105 };
1106
1107 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_tx_tbl[] = {
1108 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1109 };
1110
1111 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_rx_tbl[] = {
1112 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04),
1113 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
1114 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x15),
1115 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1116 };
1117
1118 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_tbl[] = {
1119 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x05),
1120 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG2, 0x0f),
1121 };
1122
1123 static const struct qmp_phy_init_tbl sm8250_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1124 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2, 0x0d),
1125 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1126 };
1127
1128 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_serdes_tbl[] = {
1129 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x18),
1130 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1131 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x46),
1132 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_CFG, 0x04),
1133 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1134 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x12),
1135 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1136 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x05),
1137 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x04),
1138 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC1, 0x88),
1139 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MISC2, 0x03),
1140 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_MODE, 0x17),
1141 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_DC_LEVEL_CTRL, 0x0b),
1142 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x22),
1143 };
1144
1145 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_serdes_tbl[] = {
1146 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
1147 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
1148 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
1149 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xce),
1150 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x0b),
1151 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0x97),
1152 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
1153 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x90),
1154 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE0, 0x0a),
1155 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_EP_DIV_MODE1, 0x10),
1156 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1157 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1158 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1159 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1160 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1161 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1162 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x08),
1163 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x04),
1164 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0d),
1165 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x0a),
1166 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x1a),
1167 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0xc3),
1168 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0xd0),
1169 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x05),
1170 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0x55),
1171 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0x55),
1172 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x05),
1173 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x34),
1174 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1175 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1176 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xd8),
1177 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x20),
1178 };
1179
1180 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_serdes_tbl[] = {
1181 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x02),
1182 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x07),
1183 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x0a),
1184 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x0a),
1185 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x19),
1186 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x19),
1187 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x03),
1188 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x03),
1189 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x00),
1190 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x7f),
1191 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x02),
1192 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0xff),
1193 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x04),
1194 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x4b),
1195 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x50),
1196 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x00),
1197 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1198 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1199 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1200 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1201 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x04),
1202 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x56),
1203 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1d),
1204 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x4b),
1205 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1f),
1206 };
1207
1208 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_tx_tbl[] = {
1209 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_1, 0x05),
1210 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_2, 0xf6),
1211 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_LANE_MODE_3, 0x13),
1212 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_VMODE_CTRL1, 0x00),
1213 QMP_PHY_INIT_CFG(QSERDES_V4_20_TX_PI_QEC_CTRL, 0x00),
1214 };
1215
1216 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rx_tbl[] = {
1217 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_FO_GAIN_RATE2, 0x0c),
1218 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_UCDR_PI_CONTROLS, 0x16),
1219 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE, 0x7f),
1220 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_3, 0x55),
1221 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE1, 0x0c),
1222 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_DAC_ENABLE2, 0x00),
1223 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_VGA_CAL_CNTRL2, 0x08),
1224 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
1225 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1, 0x1a),
1226 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2, 0x5a),
1227 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3, 0x09),
1228 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4, 0x37),
1229 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B0, 0xbd),
1230 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B1, 0xf9),
1231 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B2, 0xbf),
1232 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B3, 0xce),
1233 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE2_B4, 0x62),
1234 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B0, 0xbf),
1235 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B1, 0x7d),
1236 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B2, 0xbf),
1237 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B3, 0xcf),
1238 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_RX_MODE_RATE3_B4, 0xd6),
1239 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_PHPRE_CTRL, 0xa0),
1240 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1241 QMP_PHY_INIT_CFG(QSERDES_V4_20_RX_MARG_COARSE_CTRL2, 0x12),
1242 };
1243
1244 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_tbl[] = {
1245 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_RX_SIGDET_LVL, 0x77),
1246 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG2, 0x01),
1247 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG4, 0x16),
1248 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_EQ_CONFIG5, 0x02),
1249 };
1250
1251 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_pcs_misc_tbl[] = {
1252 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_EQ_CONFIG1, 0x17),
1253 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME, 0x13),
1254 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME, 0x13),
1255 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2, 0x01),
1256 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1257 };
1258
1259 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_rc_pcs_misc_tbl[] = {
1260 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1261 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1262 };
1263
1264 static const struct qmp_phy_init_tbl sdx55_qmp_pcie_ep_pcs_misc_tbl[] = {
1265 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
1266 QMP_PHY_INIT_CFG(QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
1267 };
1268
1269 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_serdes_tbl[] = {
1270 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
1271 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1272 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
1273 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1274 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
1275 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
1276 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
1277 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
1278 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
1279 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
1280 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
1281 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
1282 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
1283 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
1284 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
1285 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
1286 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
1287 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
1288 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
1289 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1290 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1291 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1292 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1293 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1294 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
1295 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1296 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1297 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1298 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1299 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
1300 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
1301 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
1302 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE_CONTD, 0x00),
1303 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
1304 };
1305
1306 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_tx_tbl[] = {
1307 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
1308 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
1309 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x00),
1310 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_VMODE_CTRL1, 0x00),
1311 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_PI_QEC_CTRL, 0x00),
1312 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
1313 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1314 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RCV_DETECT_LVL_2, 0x12),
1315 };
1316
1317 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_rx_tbl[] = {
1318 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
1319 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_1, 0x06),
1320 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_2, 0x06),
1321 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH1, 0x3e),
1322 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_PRE_THRESH2, 0x1e),
1323 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
1324 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
1325 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH1, 0x02),
1326 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_MAIN_THRESH2, 0x1d),
1327 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x44),
1328 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL2, 0x00),
1329 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00),
1330 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1331 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x74),
1332 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00),
1333 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_ENABLES, 0x1c),
1334 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_CNTRL, 0x03),
1335 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
1336 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x04),
1337 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
1338 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
1339 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
1340 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x64),
1341 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
1342 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
1343 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
1344 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DCC_CTRL1, 0x0c),
1345 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1346 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1347 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1348 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1349 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1350 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1351 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1352 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1353 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1354 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
1355 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
1356 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
1357 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
1358 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
1359 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
1360 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
1361 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE2, 0x00),
1362 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
1363 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
1364 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1365 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
1366 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xac),
1367 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
1368 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
1369 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x07),
1370 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
1371 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
1372 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc5),
1373 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xee),
1374 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
1375 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
1376 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
1377 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
1378 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
1379 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_EN_TIMER, 0x28),
1380 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1381 };
1382
1383 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_tbl[] = {
1384 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
1385 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0xaa),
1386 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG2, 0x0d),
1387 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
1388 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
1389 };
1390
1391 static const struct qmp_phy_init_tbl sdx65_qmp_pcie_pcs_misc_tbl[] = {
1392 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
1393 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
1394 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
1395 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG2, 0x0d),
1396 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1397 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
1398 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
1399 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
1400 };
1401
1402 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_serdes_tbl[] = {
1403 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1404 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1405 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1406 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1407 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42),
1408 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1409 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x03),
1410 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xb4),
1411 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1412 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1413 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1414 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
1415 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
1416 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1417 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
1418 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
1419 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x68),
1420 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1421 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xaa),
1422 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1423 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
1424 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
1425 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1426 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1427 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1428 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1429 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1430 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1431 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1432 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1433 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1434 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x18),
1435 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xa2),
1436 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1437 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1438 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1439 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1440 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1441 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x4c),
1442 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x06),
1443 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1444 };
1445
1446 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_serdes_tbl[] = {
1447 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x07),
1448 };
1449
1450 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_tx_tbl[] = {
1451 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1452 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1453 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1454 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
1455 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x04),
1456 };
1457
1458 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_rx_tbl[] = {
1459 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x7f),
1460 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xff),
1461 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xd8),
1462 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xdc),
1463 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xdc),
1464 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0x5c),
1465 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x34),
1466 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa6),
1467 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x34),
1468 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1469 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1470 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1471 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1472 QMP_PHY_INIT_CFG(QSERDES_V5_RX_TX_ADAPT_POST_THRESH, 0xf0),
1473 };
1474
1475 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_rc_rx_tbl[] = {
1476 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1477 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1478 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0x38),
1479 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1480 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1481 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07),
1482 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
1483 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1484 };
1485
1486 static const struct qmp_phy_init_tbl sm8450_qmp_gen3_pcie_pcs_tbl[] = {
1487 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x77),
1488 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RATE_SLEW_CNTRL1, 0x0b),
1489 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x05),
1490 };
1491
1492 static const struct qmp_phy_init_tbl sm8450_qmp_gen3x1_pcie_pcs_misc_tbl[] = {
1493 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1494 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1, 0x00),
1495 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_EQ_CONFIG2, 0x0f),
1496 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1497 };
1498
1499 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_tx_tbl[] = {
1500 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x20),
1501 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x75),
1502 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1503 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1504 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1505 };
1506
1507 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x1_pcie_rc_rx_tbl[] = {
1508 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbf),
1509 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3f),
1510 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x07),
1511 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf0),
1512 };
1513
1514 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_rx_tbl[] = {
1515 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
1516 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x34),
1517 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1518 };
1519
1520 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_tx_tbl[] = {
1521 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x02, 1),
1522 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_TX_PI_QEC_CTRL, 0x04, 2),
1523 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xd5),
1524 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1525 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1526 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1527 };
1528
1529 static const struct qmp_phy_init_tbl sm8350_qmp_gen3x2_pcie_rc_pcs_tbl[] = {
1530 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x0f),
1531 };
1532
1533 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_serdes_tbl[] = {
1534 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1535 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1536 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
1537 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
1538 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1539 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
1540 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1541 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1542 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1543 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
1544 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
1545 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
1546 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
1547 };
1548
1549 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_serdes_tbl[] = {
1550 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1551 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1552 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1553 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1554 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
1555 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
1556 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1557 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1558 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1559 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1560 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1561 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1562 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1563 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1564 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
1565 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
1566 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
1567 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
1568 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1569 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
1570 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1571 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
1572 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
1573 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
1574 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
1575 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
1576 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1577 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x20),
1578 };
1579
1580 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_tx_tbl[] = {
1581 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
1582 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
1583 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1a),
1584 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1585 };
1586
1587 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = {
1588 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
1589 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1590 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xcc),
1591 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x12),
1592 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xcc),
1593 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x4a),
1594 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
1595 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0xc5),
1596 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xad),
1597 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0xb6),
1598 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xc0),
1599 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x1f),
1600 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xfb),
1601 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0f),
1602 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xc7),
1603 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xef),
1604 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xbf),
1605 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xa0),
1606 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x81),
1607 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xde),
1608 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x7f),
1609 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
1610 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
1611 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
1612
1613 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x05),
1614
1615 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1616
1617 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1618 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1619 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1620 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1621 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1622 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1623 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1624 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1625
1626 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
1627 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x0a),
1628 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x0a),
1629 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1630 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
1631 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
1632 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x0f),
1633 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
1634 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
1635 };
1636
1637 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = {
1638 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
1639 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
1640 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
1641 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x99),
1642 };
1643
1644 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
1645 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
1646 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
1647 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
1648 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
1649 };
1650
1651 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl[] = {
1652 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1653 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1654 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_PRESET_P10_POST, 0x00),
1655 };
1656
1657 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_serdes_tbl[] = {
1658 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BG_TIMER, 0x02),
1659 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYS_CLK_CTRL, 0x07),
1660 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x27),
1661 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x0a),
1662 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x17),
1663 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x19),
1664 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x00),
1665 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x03),
1666 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x00),
1667 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff),
1668 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x04),
1669 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0xff),
1670 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x09),
1671 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x19),
1672 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x28),
1673 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0xfb),
1674 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE0, 0x01),
1675 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0xfb),
1676 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN1_MODE1, 0x01),
1677 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1678 };
1679
1680 static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl[] = {
1681 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5, 0x08),
1682 };
1683
1684 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_serdes_tbl[] = {
1685 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1686 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1687 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1688 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1689 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1690 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x93),
1691 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
1692 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1693 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1694 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
1695 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
1696 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
1697 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1698 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1699 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1700 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1701 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1702 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1703 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x42),
1704 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1705 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1706 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
1707 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
1708 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1709 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x34),
1710 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1711 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1712 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1713 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
1714 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
1715 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
1716 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1717 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1718 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
1719 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1720 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
1721 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC_3, 0x0f),
1722 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1723 };
1724
1725 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_tx_tbl[] = {
1726 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x15),
1727 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
1728 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x02),
1729 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
1730 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x18),
1731 };
1732
1733 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_rx_tbl[] = {
1734 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1735 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x11),
1736 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
1737 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf),
1738 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xb7),
1739 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xea),
1740 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
1741 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
1742 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
1743 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1a),
1744 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x89),
1745 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
1746 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH, 0x94),
1747 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH2, 0x5b),
1748 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH3, 0x1a),
1749 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_10_HIGH4, 0x89),
1750 QMP_PHY_INIT_CFG(QSERDES_V6_RX_TX_ADAPT_POST_THRESH, 0xf0),
1751 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x09),
1752 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x05),
1753 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
1754 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
1755 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
1756 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIDGET_ENABLES, 0x1c),
1757 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
1758 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
1759 };
1760
1761 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_tbl[] = {
1762 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x05),
1763 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x77),
1764 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RATE_SLEW_CNTRL1, 0x0b),
1765 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG2, 0x0f),
1766 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x8c),
1767 };
1768
1769 static const struct qmp_phy_init_tbl sm8550_qmp_gen3x2_pcie_pcs_misc_tbl[] = {
1770 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
1771 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_POWER_STATE_CONFIG4, 0x07),
1772 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
1773 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
1774 };
1775
1776 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_serdes_tbl[] = {
1777 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x26),
1778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06),
1780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1782 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1783 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x0a),
1784 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x1a),
1785 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x68),
1786 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
1787 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xaa),
1788 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
1789 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x12),
1790 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xf8),
1791 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1792 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1793 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1794 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1795 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1796 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x04),
1797 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0d),
1798 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
1799 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
1800 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xaa),
1801 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
1802 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1803 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1804 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1805 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1806 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1807 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_POST_DIV_MUX, 0x40),
1808 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x14),
1809 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x90),
1810 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x82),
1811 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1812 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x08),
1813 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x46),
1814 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1815 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1816 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x34),
1817 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1818 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x06),
1819 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MISC_1, 0x88),
1820 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_MODE, 0x14),
1821 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_VCO_DC_LEVEL_CTRL, 0x0f),
1822 };
1823
1824 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_ln_shrd_tbl[] = {
1825 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RXCLK_DIV2_CTRL, 0x01),
1826 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_Q_EN_RATES, 0xe),
1827 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_DFE_DAC_ENABLE1, 0x00),
1828 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH1, 0x00),
1829 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_TX_ADAPT_POST_THRESH2, 0x1f),
1830 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B0, 0x12),
1831 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B1, 0x12),
1832 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B2, 0xdb),
1833 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B3, 0x9a),
1834 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B4, 0x38),
1835 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B5, 0xb6),
1836 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MODE_RATE_0_1_B6, 0x64),
1837 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1838 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1839 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1840 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1841 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1842 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1843 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1844 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1845 QMP_PHY_INIT_CFG(QSERDES_V6_LN_SHRD_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1846 };
1847
1848 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_tx_tbl[] = {
1849 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1d),
1850 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_RES_CODE_LANE_OFFSET_RX, 0x03),
1851 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_1, 0x01),
1852 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_2, 0x00),
1853 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_LANE_MODE_3, 0x51),
1854 QMP_PHY_INIT_CFG(QSERDES_V6_20_TX_TRAN_DRVR_EMP_EN, 0x34),
1855 };
1856
1857 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_rx_tbl[] = {
1858 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_2, 0x0a),
1859 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_FO_GAIN_RATE_3, 0x0a),
1860 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_PI_CONTROLS, 0x16),
1861 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_UCDR_SO_ACC_DEFAULT_VAL_RATE3, 0x00),
1862 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_CAL_CTRL2, 0x80),
1863 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1864 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_3, 0x05),
1865 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_VGA_CAL_MAN_VAL, 0x0a),
1866 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_GM_CAL, 0x0d),
1867 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
1868 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_SIGDET_ENABLES, 0x1c),
1869 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_PHPRE_CTRL, 0x20),
1870 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x30),
1871 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
1872 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B0, 0x14),
1873 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B1, 0xb3),
1874 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B2, 0x58),
1875 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B3, 0x9a),
1876 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B4, 0x26),
1877 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B5, 0xb6),
1878 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE2_B6, 0xee),
1879 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B0, 0xdb),
1880 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B1, 0xdb),
1881 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B2, 0xa0),
1882 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B3, 0xdf),
1883 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B4, 0x78),
1884 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B5, 0x76),
1885 QMP_PHY_INIT_CFG(QSERDES_V6_20_RX_MODE_RATE3_B6, 0xff),
1886 };
1887
1888 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_tbl[] = {
1889 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_G3S2_PRE_GAIN, 0x2e),
1890 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_COM_ELECIDLE_DLY_SEL, 0x25),
1891 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG4, 0x00),
1892 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_EQ_CONFIG5, 0x22),
1893 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG1, 0x04),
1894 QMP_PHY_INIT_CFG(QPHY_V6_20_PCS_TX_RX_CONFIG2, 0x02),
1895 };
1896
1897 static const struct qmp_phy_init_tbl sm8550_qmp_gen4x2_pcie_pcs_misc_tbl[] = {
1898 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE, 0xc1),
1899 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS, 0x00),
1900 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG1, 0x16),
1901 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_EQ_CONFIG5, 0x02),
1902 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_PRE_GAIN, 0x2e),
1903 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG1, 0x03),
1904 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG3, 0x28),
1905 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG, 0xc0),
1906 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2, 0x1d),
1907 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_RX_MARGINING_CONFIG5, 0x0f),
1908 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G3_FOM_EQ_CONFIG5, 0xf2),
1909 QMP_PHY_INIT_CFG(QPHY_PCIE_V6_20_PCS_G4_FOM_EQ_CONFIG5, 0xf2),
1910 };
1911
1912 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl[] = {
1913 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
1914 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
1915 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
1916 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
1917 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1918 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
1919 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1920 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1921 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1922 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
1923 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1924 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
1925 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
1926 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
1927 };
1928
1929 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl[] = {
1930 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
1931 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1932 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1933 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1934 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1935 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
1936 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
1937 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
1938 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1939 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1940 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1941 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1942 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1943 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1944 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
1945 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
1946 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
1947 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
1948 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
1949 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1950 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
1951 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1952 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
1953 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
1954 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
1955 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
1956 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
1957 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
1958 };
1959
1960 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_rx_alt_tbl[] = {
1961 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
1962 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1963 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x9a),
1964 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
1965 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92),
1966 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
1967 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
1968 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x99),
1969 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x29),
1970 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a),
1971 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xfb),
1972 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92),
1973 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xec),
1974 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
1975 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
1976 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
1977 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
1978 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf8),
1979 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xec),
1980 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd6),
1981 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
1982 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf5),
1983 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x5e),
1984 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
1985 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
1986 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
1987 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
1988 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
1989 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
1990 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
1991 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
1992 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
1993 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
1994 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
1995 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
1996 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
1997 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
1998 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
1999 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
2000 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
2001 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
2002 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
2003 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2004 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
2005 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2006 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2007 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
2008 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
2009 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
2010 };
2011
2012 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_tx_tbl[] = {
2013 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
2014 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
2015 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_1, 0x05),
2016 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_2, 0xf6),
2017 QMP_PHY_INIT_CFG(QSERDES_V5_20_TX_LANE_MODE_3, 0x0f),
2018 };
2019
2020 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_pcs_misc_tbl[] = {
2021 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_EQ_CONFIG1, 0x16),
2022 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5, 0x02),
2023 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN, 0x2e),
2024 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3, 0x28),
2025 };
2026
2027 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl[] = {
2028 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2, 0x1d),
2029 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE, 0xc1),
2030 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS, 0x00),
2031 };
2032
2033 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl[] = {
2034 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2035 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2036 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_SW_CTRL2, 0x00),
2037 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_LANE1_INSIG_MX_CTRL2, 0x00),
2038 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2039 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
2040 };
2041
2042 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rx_alt_tbl[] = {
2043 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1, 0x3f),
2044 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3, 0x37),
2045 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_3, 0x00),
2046 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
2047 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_DFE_DAC_ENABLE1, 0x00),
2048 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_GM_CAL, 0x05),
2049 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_PHPRE_CTRL, 0x20),
2050 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0b),
2051 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x7c),
2052 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_IDAC_SAOFFSET, 0x10),
2053 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210, 0x1f),
2054 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3, 0x1f),
2055 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210, 0x1f),
2056 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3, 0x1f),
2057 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210, 0x1f),
2058 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3, 0x1f),
2059 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3, 0x1f),
2060 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3, 0x1f),
2061 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3, 0x1f),
2062 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x09),
2063 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B0, 0x99),
2064 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1, 0xb0),
2065 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2, 0x92),
2066 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3, 0xf0),
2067 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B4, 0x42),
2068 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5, 0x00),
2069 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6, 0x20),
2070 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B0, 0x9a),
2071 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B1, 0xb6),
2072 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B2, 0x92),
2073 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B3, 0xf0),
2074 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B4, 0x43),
2075 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B5, 0xdd),
2076 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE2_B6, 0x0d),
2077 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B0, 0xf3),
2078 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B1, 0xf6),
2079 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B2, 0xee),
2080 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B3, 0xd2),
2081 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B4, 0x83),
2082 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B5, 0xf9),
2083 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_RX_MODE_RATE3_B6, 0x3d),
2084 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1, 0x00),
2085 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2, 0x1f),
2086 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2, 0x0c),
2087 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3, 0x08),
2088 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_SO_GAIN_RATE3, 0x04),
2089 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_UCDR_PI_CONTROLS, 0x16),
2090 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_CNTRL1, 0x04),
2091 QMP_PHY_INIT_CFG(QSERDES_V5_20_RX_VGA_CAL_MAN_VAL, 0x08),
2092 };
2093
2094 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl[] = {
2095 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG4, 0x16),
2096 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_EQ_CONFIG5, 0x22),
2097 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_G3S2_PRE_GAIN, 0x2e),
2098 QMP_PHY_INIT_CFG(QPHY_V5_20_PCS_RX_SIGDET_LVL, 0x66),
2099 };
2100
2101 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl[] = {
2102 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f),
2103 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
2104 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
2105 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x46),
2106 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_CFG, 0x04),
2107 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
2108 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x12),
2109 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
2110 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
2111 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
2112 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MISC1, 0x88),
2113 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
2114 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x06),
2115 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_MODE, 0x14),
2116 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_DC_LEVEL_CTRL, 0x0f),
2117 };
2118
2119
2120 static const struct qmp_phy_init_tbl sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl[] = {
2121 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x00),
2122 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
2123 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
2124 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
2125 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
2126 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0x97),
2127 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0c),
2128 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
2129 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_ENABLE1, 0x90),
2130 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
2131 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
2132 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
2133 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
2134 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x08),
2135 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x0a),
2136 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x1a),
2137 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x14),
2138 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x34),
2139 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
2140 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0xd0),
2141 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
2142 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0x55),
2143 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x03),
2144 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
2145 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0x55),
2146 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
2147 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CLK_SELECT, 0x34),
2148 };
2149
2150 struct qmp_pcie_offsets {
2151 u16 serdes;
2152 u16 pcs;
2153 u16 pcs_misc;
2154 u16 tx;
2155 u16 rx;
2156 u16 tx2;
2157 u16 rx2;
2158 u16 ln_shrd;
2159 };
2160
2161 struct qmp_phy_cfg_tbls {
2162 const struct qmp_phy_init_tbl *serdes;
2163 int serdes_num;
2164 const struct qmp_phy_init_tbl *tx;
2165 int tx_num;
2166 const struct qmp_phy_init_tbl *rx;
2167 int rx_num;
2168 const struct qmp_phy_init_tbl *pcs;
2169 int pcs_num;
2170 const struct qmp_phy_init_tbl *pcs_misc;
2171 int pcs_misc_num;
2172 const struct qmp_phy_init_tbl *ln_shrd;
2173 int ln_shrd_num;
2174 };
2175
2176 /* struct qmp_phy_cfg - per-PHY initialization config */
2177 struct qmp_phy_cfg {
2178 int lanes;
2179
2180 const struct qmp_pcie_offsets *offsets;
2181
2182 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
2183 const struct qmp_phy_cfg_tbls tbls;
2184 /*
2185 * Additional init sequences for PHY blocks, providing additional
2186 * register programming. They are used for providing separate sequences
2187 * for the Root Complex and End Point use cases.
2188 *
2189 * If EP mode is not supported, both tables can be left unset.
2190 */
2191 const struct qmp_phy_cfg_tbls *tbls_rc;
2192 const struct qmp_phy_cfg_tbls *tbls_ep;
2193
2194 const struct qmp_phy_init_tbl *serdes_4ln_tbl;
2195 int serdes_4ln_num;
2196
2197 /* resets to be requested */
2198 const char * const *reset_list;
2199 int num_resets;
2200 /* regulators to be requested */
2201 const char * const *vreg_list;
2202 int num_vregs;
2203
2204 /* array of registers with different offsets */
2205 const unsigned int *regs;
2206
2207 unsigned int pwrdn_ctrl;
2208 /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
2209 unsigned int phy_status;
2210
2211 bool skip_start_delay;
2212
2213 bool has_nocsr_reset;
2214
2215 /* QMP PHY pipe clock interface rate */
2216 unsigned long pipe_clock_rate;
2217 };
2218
2219 struct qmp_pcie {
2220 struct device *dev;
2221
2222 const struct qmp_phy_cfg *cfg;
2223 bool tcsr_4ln_config;
2224
2225 void __iomem *serdes;
2226 void __iomem *pcs;
2227 void __iomem *pcs_misc;
2228 void __iomem *tx;
2229 void __iomem *rx;
2230 void __iomem *tx2;
2231 void __iomem *rx2;
2232 void __iomem *ln_shrd;
2233
2234 void __iomem *port_b;
2235
2236 struct clk_bulk_data *clks;
2237 struct clk_bulk_data pipe_clks[2];
2238 int num_pipe_clks;
2239
2240 struct reset_control_bulk_data *resets;
2241 struct reset_control *nocsr_reset;
2242 struct regulator_bulk_data *vregs;
2243
2244 struct phy *phy;
2245 int mode;
2246
2247 struct clk_fixed_rate pipe_clk_fixed;
2248 };
2249
qphy_setbits(void __iomem * base,u32 offset,u32 val)2250 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
2251 {
2252 u32 reg;
2253
2254 reg = readl(base + offset);
2255 reg |= val;
2256 writel(reg, base + offset);
2257
2258 /* ensure that above write is through */
2259 readl(base + offset);
2260 }
2261
qphy_clrbits(void __iomem * base,u32 offset,u32 val)2262 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
2263 {
2264 u32 reg;
2265
2266 reg = readl(base + offset);
2267 reg &= ~val;
2268 writel(reg, base + offset);
2269
2270 /* ensure that above write is through */
2271 readl(base + offset);
2272 }
2273
2274 /* list of clocks required by phy */
2275 static const char * const qmp_pciephy_clk_l[] = {
2276 "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux",
2277 };
2278
2279 /* list of regulators */
2280 static const char * const qmp_phy_vreg_l[] = {
2281 "vdda-phy", "vdda-pll",
2282 };
2283
2284 static const char * const sm8550_qmp_phy_vreg_l[] = {
2285 "vdda-phy", "vdda-pll", "vdda-qref",
2286 };
2287
2288 /* list of resets */
2289 static const char * const ipq8074_pciephy_reset_l[] = {
2290 "phy", "common",
2291 };
2292
2293 static const char * const sdm845_pciephy_reset_l[] = {
2294 "phy",
2295 };
2296
2297 static const struct qmp_pcie_offsets qmp_pcie_offsets_qhp = {
2298 .serdes = 0,
2299 .pcs = 0x1800,
2300 .tx = 0x0800,
2301 /* no .rx for QHP */
2302 };
2303
2304 static const struct qmp_pcie_offsets qmp_pcie_offsets_v2 = {
2305 .serdes = 0,
2306 .pcs = 0x0800,
2307 .tx = 0x0200,
2308 .rx = 0x0400,
2309 };
2310
2311 static const struct qmp_pcie_offsets qmp_pcie_offsets_v3 = {
2312 .serdes = 0,
2313 .pcs = 0x0800,
2314 .pcs_misc = 0x0600,
2315 .tx = 0x0200,
2316 .rx = 0x0400,
2317 };
2318
2319 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x1 = {
2320 .serdes = 0,
2321 .pcs = 0x0800,
2322 .pcs_misc = 0x0c00,
2323 .tx = 0x0200,
2324 .rx = 0x0400,
2325 };
2326
2327 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4x2 = {
2328 .serdes = 0,
2329 .pcs = 0x0a00,
2330 .pcs_misc = 0x0e00,
2331 .tx = 0x0200,
2332 .rx = 0x0400,
2333 .tx2 = 0x0600,
2334 .rx2 = 0x0800,
2335 };
2336
2337 static const struct qmp_pcie_offsets qmp_pcie_offsets_v4_20 = {
2338 .serdes = 0x1000,
2339 .pcs = 0x1200,
2340 .pcs_misc = 0x1600,
2341 .tx = 0x0000,
2342 .rx = 0x0200,
2343 .tx2 = 0x0800,
2344 .rx2 = 0x0a00,
2345 };
2346
2347 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5 = {
2348 .serdes = 0,
2349 .pcs = 0x0200,
2350 .pcs_misc = 0x0600,
2351 .tx = 0x0e00,
2352 .rx = 0x1000,
2353 .tx2 = 0x1600,
2354 .rx2 = 0x1800,
2355 };
2356
2357 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_20 = {
2358 .serdes = 0x1000,
2359 .pcs = 0x1200,
2360 .pcs_misc = 0x1400,
2361 .tx = 0x0000,
2362 .rx = 0x0200,
2363 .tx2 = 0x0800,
2364 .rx2 = 0x0a00,
2365 };
2366
2367 static const struct qmp_pcie_offsets qmp_pcie_offsets_v5_30 = {
2368 .serdes = 0x2000,
2369 .pcs = 0x2200,
2370 .pcs_misc = 0x2400,
2371 .tx = 0x0,
2372 .rx = 0x0200,
2373 .tx2 = 0x3800,
2374 .rx2 = 0x3a00,
2375 };
2376
2377 static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_20 = {
2378 .serdes = 0x1000,
2379 .pcs = 0x1200,
2380 .pcs_misc = 0x1400,
2381 .tx = 0x0000,
2382 .rx = 0x0200,
2383 .tx2 = 0x0800,
2384 .rx2 = 0x0a00,
2385 .ln_shrd = 0x0e00,
2386 };
2387
2388 static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
2389 .lanes = 1,
2390
2391 .offsets = &qmp_pcie_offsets_v2,
2392
2393 .tbls = {
2394 .serdes = ipq8074_pcie_serdes_tbl,
2395 .serdes_num = ARRAY_SIZE(ipq8074_pcie_serdes_tbl),
2396 .tx = ipq8074_pcie_tx_tbl,
2397 .tx_num = ARRAY_SIZE(ipq8074_pcie_tx_tbl),
2398 .rx = ipq8074_pcie_rx_tbl,
2399 .rx_num = ARRAY_SIZE(ipq8074_pcie_rx_tbl),
2400 .pcs = ipq8074_pcie_pcs_tbl,
2401 .pcs_num = ARRAY_SIZE(ipq8074_pcie_pcs_tbl),
2402 },
2403 .reset_list = ipq8074_pciephy_reset_l,
2404 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2405 .vreg_list = NULL,
2406 .num_vregs = 0,
2407 .regs = pciephy_v2_regs_layout,
2408
2409 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2410 .phy_status = PHYSTATUS,
2411 };
2412
2413 static const struct qmp_phy_cfg ipq8074_pciephy_gen3_cfg = {
2414 .lanes = 1,
2415
2416 .offsets = &qmp_pcie_offsets_v4x1,
2417
2418 .tbls = {
2419 .serdes = ipq8074_pcie_gen3_serdes_tbl,
2420 .serdes_num = ARRAY_SIZE(ipq8074_pcie_gen3_serdes_tbl),
2421 .tx = ipq8074_pcie_gen3_tx_tbl,
2422 .tx_num = ARRAY_SIZE(ipq8074_pcie_gen3_tx_tbl),
2423 .rx = ipq8074_pcie_gen3_rx_tbl,
2424 .rx_num = ARRAY_SIZE(ipq8074_pcie_gen3_rx_tbl),
2425 .pcs = ipq8074_pcie_gen3_pcs_tbl,
2426 .pcs_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_tbl),
2427 .pcs_misc = ipq8074_pcie_gen3_pcs_misc_tbl,
2428 .pcs_misc_num = ARRAY_SIZE(ipq8074_pcie_gen3_pcs_misc_tbl),
2429 },
2430 .reset_list = ipq8074_pciephy_reset_l,
2431 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2432 .vreg_list = NULL,
2433 .num_vregs = 0,
2434 .regs = pciephy_v4_regs_layout,
2435
2436 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2437 .phy_status = PHYSTATUS,
2438
2439 .pipe_clock_rate = 250000000,
2440 };
2441
2442 static const struct qmp_phy_cfg ipq6018_pciephy_cfg = {
2443 .lanes = 1,
2444
2445 .offsets = &qmp_pcie_offsets_v4x1,
2446
2447 .tbls = {
2448 .serdes = ipq6018_pcie_serdes_tbl,
2449 .serdes_num = ARRAY_SIZE(ipq6018_pcie_serdes_tbl),
2450 .tx = ipq6018_pcie_tx_tbl,
2451 .tx_num = ARRAY_SIZE(ipq6018_pcie_tx_tbl),
2452 .rx = ipq6018_pcie_rx_tbl,
2453 .rx_num = ARRAY_SIZE(ipq6018_pcie_rx_tbl),
2454 .pcs = ipq6018_pcie_pcs_tbl,
2455 .pcs_num = ARRAY_SIZE(ipq6018_pcie_pcs_tbl),
2456 .pcs_misc = ipq6018_pcie_pcs_misc_tbl,
2457 .pcs_misc_num = ARRAY_SIZE(ipq6018_pcie_pcs_misc_tbl),
2458 },
2459 .reset_list = ipq8074_pciephy_reset_l,
2460 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2461 .vreg_list = NULL,
2462 .num_vregs = 0,
2463 .regs = pciephy_v4_regs_layout,
2464
2465 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2466 .phy_status = PHYSTATUS,
2467 };
2468
2469 static const struct qmp_phy_cfg sdm845_qmp_pciephy_cfg = {
2470 .lanes = 1,
2471
2472 .offsets = &qmp_pcie_offsets_v3,
2473
2474 .tbls = {
2475 .serdes = sdm845_qmp_pcie_serdes_tbl,
2476 .serdes_num = ARRAY_SIZE(sdm845_qmp_pcie_serdes_tbl),
2477 .tx = sdm845_qmp_pcie_tx_tbl,
2478 .tx_num = ARRAY_SIZE(sdm845_qmp_pcie_tx_tbl),
2479 .rx = sdm845_qmp_pcie_rx_tbl,
2480 .rx_num = ARRAY_SIZE(sdm845_qmp_pcie_rx_tbl),
2481 .pcs = sdm845_qmp_pcie_pcs_tbl,
2482 .pcs_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_tbl),
2483 .pcs_misc = sdm845_qmp_pcie_pcs_misc_tbl,
2484 .pcs_misc_num = ARRAY_SIZE(sdm845_qmp_pcie_pcs_misc_tbl),
2485 },
2486 .reset_list = sdm845_pciephy_reset_l,
2487 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2488 .vreg_list = qmp_phy_vreg_l,
2489 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2490 .regs = pciephy_v3_regs_layout,
2491
2492 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2493 .phy_status = PHYSTATUS,
2494 };
2495
2496 static const struct qmp_phy_cfg sdm845_qhp_pciephy_cfg = {
2497 .lanes = 1,
2498
2499 .offsets = &qmp_pcie_offsets_qhp,
2500
2501 .tbls = {
2502 .serdes = sdm845_qhp_pcie_serdes_tbl,
2503 .serdes_num = ARRAY_SIZE(sdm845_qhp_pcie_serdes_tbl),
2504 .tx = sdm845_qhp_pcie_tx_tbl,
2505 .tx_num = ARRAY_SIZE(sdm845_qhp_pcie_tx_tbl),
2506 .pcs = sdm845_qhp_pcie_pcs_tbl,
2507 .pcs_num = ARRAY_SIZE(sdm845_qhp_pcie_pcs_tbl),
2508 },
2509 .reset_list = sdm845_pciephy_reset_l,
2510 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2511 .vreg_list = qmp_phy_vreg_l,
2512 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2513 .regs = sdm845_qhp_pciephy_regs_layout,
2514
2515 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2516 .phy_status = PHYSTATUS,
2517 };
2518
2519 static const struct qmp_phy_cfg sm8250_qmp_gen3x1_pciephy_cfg = {
2520 .lanes = 1,
2521
2522 .offsets = &qmp_pcie_offsets_v4x1,
2523
2524 .tbls = {
2525 .serdes = sm8250_qmp_pcie_serdes_tbl,
2526 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
2527 .tx = sm8250_qmp_pcie_tx_tbl,
2528 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
2529 .rx = sm8250_qmp_pcie_rx_tbl,
2530 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
2531 .pcs = sm8250_qmp_pcie_pcs_tbl,
2532 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
2533 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl,
2534 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
2535 },
2536 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2537 .serdes = sm8250_qmp_gen3x1_pcie_serdes_tbl,
2538 .serdes_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_serdes_tbl),
2539 .rx = sm8250_qmp_gen3x1_pcie_rx_tbl,
2540 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_rx_tbl),
2541 .pcs = sm8250_qmp_gen3x1_pcie_pcs_tbl,
2542 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_tbl),
2543 .pcs_misc = sm8250_qmp_gen3x1_pcie_pcs_misc_tbl,
2544 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x1_pcie_pcs_misc_tbl),
2545 },
2546 .reset_list = sdm845_pciephy_reset_l,
2547 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2548 .vreg_list = qmp_phy_vreg_l,
2549 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2550 .regs = pciephy_v4_regs_layout,
2551
2552 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2553 .phy_status = PHYSTATUS,
2554 };
2555
2556 static const struct qmp_phy_cfg sm8250_qmp_gen3x2_pciephy_cfg = {
2557 .lanes = 2,
2558
2559 .offsets = &qmp_pcie_offsets_v4x2,
2560
2561 .tbls = {
2562 .serdes = sm8250_qmp_pcie_serdes_tbl,
2563 .serdes_num = ARRAY_SIZE(sm8250_qmp_pcie_serdes_tbl),
2564 .tx = sm8250_qmp_pcie_tx_tbl,
2565 .tx_num = ARRAY_SIZE(sm8250_qmp_pcie_tx_tbl),
2566 .rx = sm8250_qmp_pcie_rx_tbl,
2567 .rx_num = ARRAY_SIZE(sm8250_qmp_pcie_rx_tbl),
2568 .pcs = sm8250_qmp_pcie_pcs_tbl,
2569 .pcs_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_tbl),
2570 .pcs_misc = sm8250_qmp_pcie_pcs_misc_tbl,
2571 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_pcie_pcs_misc_tbl),
2572 },
2573 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2574 .tx = sm8250_qmp_gen3x2_pcie_tx_tbl,
2575 .tx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_tx_tbl),
2576 .rx = sm8250_qmp_gen3x2_pcie_rx_tbl,
2577 .rx_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_rx_tbl),
2578 .pcs = sm8250_qmp_gen3x2_pcie_pcs_tbl,
2579 .pcs_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_tbl),
2580 .pcs_misc = sm8250_qmp_gen3x2_pcie_pcs_misc_tbl,
2581 .pcs_misc_num = ARRAY_SIZE(sm8250_qmp_gen3x2_pcie_pcs_misc_tbl),
2582 },
2583 .reset_list = sdm845_pciephy_reset_l,
2584 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2585 .vreg_list = qmp_phy_vreg_l,
2586 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2587 .regs = pciephy_v4_regs_layout,
2588
2589 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2590 .phy_status = PHYSTATUS,
2591 };
2592
2593 static const struct qmp_phy_cfg msm8998_pciephy_cfg = {
2594 .lanes = 1,
2595
2596 .offsets = &qmp_pcie_offsets_v3,
2597
2598 .tbls = {
2599 .serdes = msm8998_pcie_serdes_tbl,
2600 .serdes_num = ARRAY_SIZE(msm8998_pcie_serdes_tbl),
2601 .tx = msm8998_pcie_tx_tbl,
2602 .tx_num = ARRAY_SIZE(msm8998_pcie_tx_tbl),
2603 .rx = msm8998_pcie_rx_tbl,
2604 .rx_num = ARRAY_SIZE(msm8998_pcie_rx_tbl),
2605 .pcs = msm8998_pcie_pcs_tbl,
2606 .pcs_num = ARRAY_SIZE(msm8998_pcie_pcs_tbl),
2607 },
2608 .reset_list = ipq8074_pciephy_reset_l,
2609 .num_resets = ARRAY_SIZE(ipq8074_pciephy_reset_l),
2610 .vreg_list = qmp_phy_vreg_l,
2611 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2612 .regs = pciephy_v3_regs_layout,
2613
2614 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2615 .phy_status = PHYSTATUS,
2616
2617 .skip_start_delay = true,
2618 };
2619
2620 static const struct qmp_phy_cfg sc8180x_pciephy_cfg = {
2621 .lanes = 2,
2622
2623 .offsets = &qmp_pcie_offsets_v4x2,
2624
2625 .tbls = {
2626 .serdes = sc8180x_qmp_pcie_serdes_tbl,
2627 .serdes_num = ARRAY_SIZE(sc8180x_qmp_pcie_serdes_tbl),
2628 .tx = sc8180x_qmp_pcie_tx_tbl,
2629 .tx_num = ARRAY_SIZE(sc8180x_qmp_pcie_tx_tbl),
2630 .rx = sc8180x_qmp_pcie_rx_tbl,
2631 .rx_num = ARRAY_SIZE(sc8180x_qmp_pcie_rx_tbl),
2632 .pcs = sc8180x_qmp_pcie_pcs_tbl,
2633 .pcs_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_tbl),
2634 .pcs_misc = sc8180x_qmp_pcie_pcs_misc_tbl,
2635 .pcs_misc_num = ARRAY_SIZE(sc8180x_qmp_pcie_pcs_misc_tbl),
2636 },
2637 .reset_list = sdm845_pciephy_reset_l,
2638 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2639 .vreg_list = qmp_phy_vreg_l,
2640 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2641 .regs = pciephy_v4_regs_layout,
2642
2643 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2644 .phy_status = PHYSTATUS,
2645 };
2646
2647 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x1_pciephy_cfg = {
2648 .lanes = 1,
2649
2650 .offsets = &qmp_pcie_offsets_v5,
2651
2652 .tbls = {
2653 .serdes = sc8280xp_qmp_pcie_serdes_tbl,
2654 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
2655 .tx = sc8280xp_qmp_gen3x1_pcie_tx_tbl,
2656 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_tx_tbl),
2657 .rx = sc8280xp_qmp_gen3x1_pcie_rx_tbl,
2658 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rx_tbl),
2659 .pcs = sc8280xp_qmp_gen3x1_pcie_pcs_tbl,
2660 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_tbl),
2661 .pcs_misc = sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl,
2662 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_pcs_misc_tbl),
2663 },
2664
2665 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2666 .serdes = sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl,
2667 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x1_pcie_rc_serdes_tbl),
2668 },
2669
2670 .reset_list = sdm845_pciephy_reset_l,
2671 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2672 .vreg_list = qmp_phy_vreg_l,
2673 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2674 .regs = pciephy_v5_regs_layout,
2675
2676 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2677 .phy_status = PHYSTATUS,
2678 };
2679
2680 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x2_pciephy_cfg = {
2681 .lanes = 2,
2682
2683 .offsets = &qmp_pcie_offsets_v5,
2684
2685 .tbls = {
2686 .serdes = sc8280xp_qmp_pcie_serdes_tbl,
2687 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
2688 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
2689 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
2690 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
2691 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
2692 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
2693 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
2694 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
2695 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
2696 },
2697
2698 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2699 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
2700 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
2701 },
2702
2703 .reset_list = sdm845_pciephy_reset_l,
2704 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2705 .vreg_list = qmp_phy_vreg_l,
2706 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2707 .regs = pciephy_v5_regs_layout,
2708
2709 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2710 .phy_status = PHYSTATUS,
2711 };
2712
2713 static const struct qmp_phy_cfg sc8280xp_qmp_gen3x4_pciephy_cfg = {
2714 .lanes = 4,
2715
2716 .offsets = &qmp_pcie_offsets_v5,
2717
2718 .tbls = {
2719 .serdes = sc8280xp_qmp_pcie_serdes_tbl,
2720 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_pcie_serdes_tbl),
2721 .tx = sc8280xp_qmp_gen3x2_pcie_tx_tbl,
2722 .tx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_tx_tbl),
2723 .rx = sc8280xp_qmp_gen3x2_pcie_rx_tbl,
2724 .rx_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rx_tbl),
2725 .pcs = sc8280xp_qmp_gen3x2_pcie_pcs_tbl,
2726 .pcs_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_tbl),
2727 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
2728 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
2729 },
2730
2731 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2732 .serdes = sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl,
2733 .serdes_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_rc_serdes_tbl),
2734 },
2735
2736 .serdes_4ln_tbl = sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl,
2737 .serdes_4ln_num = ARRAY_SIZE(sc8280xp_qmp_gen3x4_pcie_serdes_4ln_tbl),
2738
2739 .reset_list = sdm845_pciephy_reset_l,
2740 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2741 .vreg_list = qmp_phy_vreg_l,
2742 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2743 .regs = pciephy_v5_regs_layout,
2744
2745 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2746 .phy_status = PHYSTATUS,
2747 };
2748
2749 static const struct qmp_phy_cfg sdx55_qmp_pciephy_cfg = {
2750 .lanes = 2,
2751
2752 .offsets = &qmp_pcie_offsets_v4_20,
2753
2754 .tbls = {
2755 .serdes = sdx55_qmp_pcie_serdes_tbl,
2756 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_serdes_tbl),
2757 .tx = sdx55_qmp_pcie_tx_tbl,
2758 .tx_num = ARRAY_SIZE(sdx55_qmp_pcie_tx_tbl),
2759 .rx = sdx55_qmp_pcie_rx_tbl,
2760 .rx_num = ARRAY_SIZE(sdx55_qmp_pcie_rx_tbl),
2761 .pcs = sdx55_qmp_pcie_pcs_tbl,
2762 .pcs_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_tbl),
2763 .pcs_misc = sdx55_qmp_pcie_pcs_misc_tbl,
2764 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_pcs_misc_tbl),
2765 },
2766
2767 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2768 .serdes = sdx55_qmp_pcie_rc_serdes_tbl,
2769 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_serdes_tbl),
2770 .pcs_misc = sdx55_qmp_pcie_rc_pcs_misc_tbl,
2771 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_rc_pcs_misc_tbl),
2772 },
2773
2774 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
2775 .serdes = sdx55_qmp_pcie_ep_serdes_tbl,
2776 .serdes_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_serdes_tbl),
2777 .pcs_misc = sdx55_qmp_pcie_ep_pcs_misc_tbl,
2778 .pcs_misc_num = ARRAY_SIZE(sdx55_qmp_pcie_ep_pcs_misc_tbl),
2779 },
2780
2781 .reset_list = sdm845_pciephy_reset_l,
2782 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2783 .vreg_list = qmp_phy_vreg_l,
2784 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2785 .regs = pciephy_v4_regs_layout,
2786
2787 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2788 .phy_status = PHYSTATUS_4_20,
2789 };
2790
2791 static const struct qmp_phy_cfg sm8350_qmp_gen3x1_pciephy_cfg = {
2792 .lanes = 1,
2793
2794 .offsets = &qmp_pcie_offsets_v5,
2795
2796 .tbls = {
2797 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
2798 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2799 .tx = sm8350_qmp_gen3x1_pcie_tx_tbl,
2800 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_tx_tbl),
2801 .rx = sm8450_qmp_gen3_pcie_rx_tbl,
2802 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2803 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2804 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2805 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
2806 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
2807 },
2808
2809 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2810 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
2811 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
2812 .rx = sm8350_qmp_gen3x1_pcie_rc_rx_tbl,
2813 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x1_pcie_rc_rx_tbl),
2814 },
2815
2816 .reset_list = sdm845_pciephy_reset_l,
2817 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2818 .vreg_list = qmp_phy_vreg_l,
2819 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2820 .regs = pciephy_v5_regs_layout,
2821
2822 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2823 .phy_status = PHYSTATUS,
2824 };
2825
2826 static const struct qmp_phy_cfg sm8350_qmp_gen3x2_pciephy_cfg = {
2827 .lanes = 2,
2828
2829 .offsets = &qmp_pcie_offsets_v5,
2830
2831 .tbls = {
2832 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
2833 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2834 .tx = sm8350_qmp_gen3x2_pcie_tx_tbl,
2835 .tx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_tx_tbl),
2836 .rx = sm8450_qmp_gen3_pcie_rx_tbl,
2837 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2838 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2839 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2840 .pcs_misc = sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl,
2841 .pcs_misc_num = ARRAY_SIZE(sc8280xp_qmp_gen3x2_pcie_pcs_misc_tbl),
2842 },
2843
2844 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2845 .rx = sm8350_qmp_gen3x2_pcie_rc_rx_tbl,
2846 .rx_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_rx_tbl),
2847 .pcs = sm8350_qmp_gen3x2_pcie_rc_pcs_tbl,
2848 .pcs_num = ARRAY_SIZE(sm8350_qmp_gen3x2_pcie_rc_pcs_tbl),
2849 },
2850
2851 .reset_list = sdm845_pciephy_reset_l,
2852 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2853 .vreg_list = qmp_phy_vreg_l,
2854 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2855 .regs = pciephy_v5_regs_layout,
2856
2857 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2858 .phy_status = PHYSTATUS,
2859 };
2860
2861 static const struct qmp_phy_cfg sdx65_qmp_pciephy_cfg = {
2862 .lanes = 2,
2863
2864 .offsets = &qmp_pcie_offsets_v6_20,
2865
2866 .tbls = {
2867 .serdes = sdx65_qmp_pcie_serdes_tbl,
2868 .serdes_num = ARRAY_SIZE(sdx65_qmp_pcie_serdes_tbl),
2869 .tx = sdx65_qmp_pcie_tx_tbl,
2870 .tx_num = ARRAY_SIZE(sdx65_qmp_pcie_tx_tbl),
2871 .rx = sdx65_qmp_pcie_rx_tbl,
2872 .rx_num = ARRAY_SIZE(sdx65_qmp_pcie_rx_tbl),
2873 .pcs = sdx65_qmp_pcie_pcs_tbl,
2874 .pcs_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_tbl),
2875 .pcs_misc = sdx65_qmp_pcie_pcs_misc_tbl,
2876 .pcs_misc_num = ARRAY_SIZE(sdx65_qmp_pcie_pcs_misc_tbl),
2877 },
2878 .reset_list = sdm845_pciephy_reset_l,
2879 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2880 .vreg_list = qmp_phy_vreg_l,
2881 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2882 .regs = pciephy_v5_regs_layout,
2883
2884 .pwrdn_ctrl = SW_PWRDN,
2885 .phy_status = PHYSTATUS_4_20,
2886 };
2887
2888 static const struct qmp_phy_cfg sm8450_qmp_gen3x1_pciephy_cfg = {
2889 .lanes = 1,
2890
2891 .offsets = &qmp_pcie_offsets_v5,
2892
2893 .tbls = {
2894 .serdes = sm8450_qmp_gen3_pcie_serdes_tbl,
2895 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_serdes_tbl),
2896 .tx = sm8450_qmp_gen3x1_pcie_tx_tbl,
2897 .tx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_tx_tbl),
2898 .rx = sm8450_qmp_gen3_pcie_rx_tbl,
2899 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_rx_tbl),
2900 .pcs = sm8450_qmp_gen3_pcie_pcs_tbl,
2901 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen3_pcie_pcs_tbl),
2902 .pcs_misc = sm8450_qmp_gen3x1_pcie_pcs_misc_tbl,
2903 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_pcs_misc_tbl),
2904 },
2905
2906 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2907 .serdes = sm8450_qmp_gen3x1_pcie_rc_serdes_tbl,
2908 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_serdes_tbl),
2909 .rx = sm8450_qmp_gen3x1_pcie_rc_rx_tbl,
2910 .rx_num = ARRAY_SIZE(sm8450_qmp_gen3x1_pcie_rc_rx_tbl),
2911 },
2912
2913 .reset_list = sdm845_pciephy_reset_l,
2914 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2915 .vreg_list = qmp_phy_vreg_l,
2916 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2917 .regs = pciephy_v5_regs_layout,
2918
2919 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2920 .phy_status = PHYSTATUS,
2921 };
2922
2923 static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = {
2924 .lanes = 2,
2925
2926 .offsets = &qmp_pcie_offsets_v5_20,
2927
2928 .tbls = {
2929 .serdes = sm8450_qmp_gen4x2_pcie_serdes_tbl,
2930 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_serdes_tbl),
2931 .tx = sm8450_qmp_gen4x2_pcie_tx_tbl,
2932 .tx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_tx_tbl),
2933 .rx = sm8450_qmp_gen4x2_pcie_rx_tbl,
2934 .rx_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rx_tbl),
2935 .pcs = sm8450_qmp_gen4x2_pcie_pcs_tbl,
2936 .pcs_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_tbl),
2937 .pcs_misc = sm8450_qmp_gen4x2_pcie_pcs_misc_tbl,
2938 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_pcs_misc_tbl),
2939 },
2940
2941 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
2942 .serdes = sm8450_qmp_gen4x2_pcie_rc_serdes_tbl,
2943 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_serdes_tbl),
2944 .pcs_misc = sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl,
2945 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_rc_pcs_misc_tbl),
2946 },
2947
2948 .tbls_ep = &(const struct qmp_phy_cfg_tbls) {
2949 .serdes = sm8450_qmp_gen4x2_pcie_ep_serdes_tbl,
2950 .serdes_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_serdes_tbl),
2951 .pcs_misc = sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl,
2952 .pcs_misc_num = ARRAY_SIZE(sm8450_qmp_gen4x2_pcie_ep_pcs_misc_tbl),
2953 },
2954
2955 .reset_list = sdm845_pciephy_reset_l,
2956 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2957 .vreg_list = qmp_phy_vreg_l,
2958 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2959 .regs = pciephy_v5_regs_layout,
2960
2961 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2962 .phy_status = PHYSTATUS_4_20,
2963 };
2964
2965 static const struct qmp_phy_cfg sm8550_qmp_gen3x2_pciephy_cfg = {
2966 .lanes = 2,
2967
2968 .offsets = &qmp_pcie_offsets_v5,
2969
2970 .tbls = {
2971 .serdes = sm8550_qmp_gen3x2_pcie_serdes_tbl,
2972 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_serdes_tbl),
2973 .tx = sm8550_qmp_gen3x2_pcie_tx_tbl,
2974 .tx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_tx_tbl),
2975 .rx = sm8550_qmp_gen3x2_pcie_rx_tbl,
2976 .rx_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_rx_tbl),
2977 .pcs = sm8550_qmp_gen3x2_pcie_pcs_tbl,
2978 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_tbl),
2979 .pcs_misc = sm8550_qmp_gen3x2_pcie_pcs_misc_tbl,
2980 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen3x2_pcie_pcs_misc_tbl),
2981 },
2982 .reset_list = sdm845_pciephy_reset_l,
2983 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
2984 .vreg_list = qmp_phy_vreg_l,
2985 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2986 .regs = pciephy_v5_regs_layout,
2987
2988 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
2989 .phy_status = PHYSTATUS,
2990 };
2991
2992 static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = {
2993 .lanes = 2,
2994
2995 .offsets = &qmp_pcie_offsets_v6_20,
2996
2997 .tbls = {
2998 .serdes = sm8550_qmp_gen4x2_pcie_serdes_tbl,
2999 .serdes_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_serdes_tbl),
3000 .tx = sm8550_qmp_gen4x2_pcie_tx_tbl,
3001 .tx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_tx_tbl),
3002 .rx = sm8550_qmp_gen4x2_pcie_rx_tbl,
3003 .rx_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_rx_tbl),
3004 .pcs = sm8550_qmp_gen4x2_pcie_pcs_tbl,
3005 .pcs_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_tbl),
3006 .pcs_misc = sm8550_qmp_gen4x2_pcie_pcs_misc_tbl,
3007 .pcs_misc_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_pcs_misc_tbl),
3008 .ln_shrd = sm8550_qmp_gen4x2_pcie_ln_shrd_tbl,
3009 .ln_shrd_num = ARRAY_SIZE(sm8550_qmp_gen4x2_pcie_ln_shrd_tbl),
3010 },
3011 .reset_list = sdm845_pciephy_reset_l,
3012 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3013 .vreg_list = sm8550_qmp_phy_vreg_l,
3014 .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
3015 .regs = pciephy_v5_regs_layout,
3016
3017 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3018 .phy_status = PHYSTATUS_4_20,
3019 .has_nocsr_reset = true,
3020 };
3021
3022 static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = {
3023 .lanes = 2,
3024 .offsets = &qmp_pcie_offsets_v5_20,
3025
3026 .tbls = {
3027 .serdes = sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl,
3028 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_serdes_alt_tbl),
3029 .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
3030 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
3031 .rx = sa8775p_qmp_gen4x2_pcie_rx_alt_tbl,
3032 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rx_alt_tbl),
3033 .pcs = sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl,
3034 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_pcs_alt_tbl),
3035 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
3036 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
3037 },
3038
3039 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3040 .serdes = sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl,
3041 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x2_pcie_rc_serdes_alt_tbl),
3042 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
3043 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
3044 },
3045
3046 .reset_list = sdm845_pciephy_reset_l,
3047 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3048 .vreg_list = qmp_phy_vreg_l,
3049 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3050 .regs = pciephy_v5_regs_layout,
3051
3052 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3053 .phy_status = PHYSTATUS_4_20,
3054 };
3055
3056 static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = {
3057 .lanes = 4,
3058 .offsets = &qmp_pcie_offsets_v5_30,
3059
3060 .tbls = {
3061 .serdes = sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl,
3062 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_serdes_alt_tbl),
3063 .tx = sa8775p_qmp_gen4_pcie_tx_tbl,
3064 .tx_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_tx_tbl),
3065 .rx = sa8775p_qmp_gen4x4_pcie_rx_alt_tbl,
3066 .rx_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rx_alt_tbl),
3067 .pcs = sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl,
3068 .pcs_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_pcs_alt_tbl),
3069 .pcs_misc = sa8775p_qmp_gen4_pcie_pcs_misc_tbl,
3070 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_pcs_misc_tbl),
3071 },
3072
3073 .tbls_rc = &(const struct qmp_phy_cfg_tbls) {
3074 .serdes = sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl,
3075 .serdes_num = ARRAY_SIZE(sa8775p_qmp_gen4x4_pcie_rc_serdes_alt_tbl),
3076 .pcs_misc = sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl,
3077 .pcs_misc_num = ARRAY_SIZE(sa8775p_qmp_gen4_pcie_rc_pcs_misc_tbl),
3078 },
3079
3080 .reset_list = sdm845_pciephy_reset_l,
3081 .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
3082 .vreg_list = qmp_phy_vreg_l,
3083 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
3084 .regs = pciephy_v5_regs_layout,
3085
3086 .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
3087 .phy_status = PHYSTATUS_4_20,
3088 };
3089
qmp_pcie_configure_lane(void __iomem * base,const struct qmp_phy_init_tbl tbl[],int num,u8 lane_mask)3090 static void qmp_pcie_configure_lane(void __iomem *base,
3091 const struct qmp_phy_init_tbl tbl[],
3092 int num,
3093 u8 lane_mask)
3094 {
3095 int i;
3096 const struct qmp_phy_init_tbl *t = tbl;
3097
3098 if (!t)
3099 return;
3100
3101 for (i = 0; i < num; i++, t++) {
3102 if (!(t->lane_mask & lane_mask))
3103 continue;
3104
3105 writel(t->val, base + t->offset);
3106 }
3107 }
3108
qmp_pcie_configure(void __iomem * base,const struct qmp_phy_init_tbl tbl[],int num)3109 static void qmp_pcie_configure(void __iomem *base,
3110 const struct qmp_phy_init_tbl tbl[],
3111 int num)
3112 {
3113 qmp_pcie_configure_lane(base, tbl, num, 0xff);
3114 }
3115
qmp_pcie_init_port_b(struct qmp_pcie * qmp,const struct qmp_phy_cfg_tbls * tbls)3116 static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
3117 {
3118 const struct qmp_phy_cfg *cfg = qmp->cfg;
3119 const struct qmp_pcie_offsets *offs = cfg->offsets;
3120 void __iomem *tx3, *rx3, *tx4, *rx4;
3121
3122 tx3 = qmp->port_b + offs->tx;
3123 rx3 = qmp->port_b + offs->rx;
3124 tx4 = qmp->port_b + offs->tx2;
3125 rx4 = qmp->port_b + offs->rx2;
3126
3127 qmp_pcie_configure_lane(tx3, tbls->tx, tbls->tx_num, 1);
3128 qmp_pcie_configure_lane(rx3, tbls->rx, tbls->rx_num, 1);
3129
3130 qmp_pcie_configure_lane(tx4, tbls->tx, tbls->tx_num, 2);
3131 qmp_pcie_configure_lane(rx4, tbls->rx, tbls->rx_num, 2);
3132 }
3133
qmp_pcie_init_registers(struct qmp_pcie * qmp,const struct qmp_phy_cfg_tbls * tbls)3134 static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
3135 {
3136 const struct qmp_phy_cfg *cfg = qmp->cfg;
3137 void __iomem *serdes = qmp->serdes;
3138 void __iomem *tx = qmp->tx;
3139 void __iomem *rx = qmp->rx;
3140 void __iomem *tx2 = qmp->tx2;
3141 void __iomem *rx2 = qmp->rx2;
3142 void __iomem *pcs = qmp->pcs;
3143 void __iomem *pcs_misc = qmp->pcs_misc;
3144 void __iomem *ln_shrd = qmp->ln_shrd;
3145
3146 if (!tbls)
3147 return;
3148
3149 qmp_pcie_configure(serdes, tbls->serdes, tbls->serdes_num);
3150
3151 qmp_pcie_configure_lane(tx, tbls->tx, tbls->tx_num, 1);
3152 qmp_pcie_configure_lane(rx, tbls->rx, tbls->rx_num, 1);
3153
3154 if (cfg->lanes >= 2) {
3155 qmp_pcie_configure_lane(tx2, tbls->tx, tbls->tx_num, 2);
3156 qmp_pcie_configure_lane(rx2, tbls->rx, tbls->rx_num, 2);
3157 }
3158
3159 qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num);
3160 qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num);
3161
3162 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
3163 qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num);
3164 qmp_pcie_init_port_b(qmp, tbls);
3165 }
3166
3167 qmp_pcie_configure(ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num);
3168 }
3169
qmp_pcie_init(struct phy * phy)3170 static int qmp_pcie_init(struct phy *phy)
3171 {
3172 struct qmp_pcie *qmp = phy_get_drvdata(phy);
3173 const struct qmp_phy_cfg *cfg = qmp->cfg;
3174 int ret;
3175
3176 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
3177 if (ret) {
3178 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
3179 return ret;
3180 }
3181
3182 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
3183 if (ret) {
3184 dev_err(qmp->dev, "reset assert failed\n");
3185 goto err_disable_regulators;
3186 }
3187
3188 ret = reset_control_assert(qmp->nocsr_reset);
3189 if (ret) {
3190 dev_err(qmp->dev, "no-csr reset assert failed\n");
3191 goto err_assert_reset;
3192 }
3193
3194 usleep_range(200, 300);
3195
3196 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
3197 if (ret) {
3198 dev_err(qmp->dev, "reset deassert failed\n");
3199 goto err_assert_reset;
3200 }
3201
3202 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
3203 if (ret)
3204 goto err_assert_reset;
3205
3206 return 0;
3207
3208 err_assert_reset:
3209 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
3210 err_disable_regulators:
3211 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
3212
3213 return ret;
3214 }
3215
qmp_pcie_exit(struct phy * phy)3216 static int qmp_pcie_exit(struct phy *phy)
3217 {
3218 struct qmp_pcie *qmp = phy_get_drvdata(phy);
3219 const struct qmp_phy_cfg *cfg = qmp->cfg;
3220
3221 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
3222
3223 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks);
3224
3225 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
3226
3227 return 0;
3228 }
3229
qmp_pcie_power_on(struct phy * phy)3230 static int qmp_pcie_power_on(struct phy *phy)
3231 {
3232 struct qmp_pcie *qmp = phy_get_drvdata(phy);
3233 const struct qmp_phy_cfg *cfg = qmp->cfg;
3234 const struct qmp_phy_cfg_tbls *mode_tbls;
3235 void __iomem *pcs = qmp->pcs;
3236 void __iomem *status;
3237 unsigned int mask, val;
3238 int ret;
3239
3240 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3241 cfg->pwrdn_ctrl);
3242
3243 if (qmp->mode == PHY_MODE_PCIE_RC)
3244 mode_tbls = cfg->tbls_rc;
3245 else
3246 mode_tbls = cfg->tbls_ep;
3247
3248 qmp_pcie_init_registers(qmp, &cfg->tbls);
3249 qmp_pcie_init_registers(qmp, mode_tbls);
3250
3251 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks);
3252 if (ret)
3253 return ret;
3254
3255 ret = reset_control_deassert(qmp->nocsr_reset);
3256 if (ret) {
3257 dev_err(qmp->dev, "no-csr reset deassert failed\n");
3258 goto err_disable_pipe_clk;
3259 }
3260
3261 /* Pull PHY out of reset state */
3262 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3263
3264 /* start SerDes and Phy-Coding-Sublayer */
3265 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
3266
3267 if (!cfg->skip_start_delay)
3268 usleep_range(1000, 1200);
3269
3270 status = pcs + cfg->regs[QPHY_PCS_STATUS];
3271 mask = cfg->phy_status;
3272 ret = readl_poll_timeout(status, val, !(val & mask), 200,
3273 PHY_INIT_COMPLETE_TIMEOUT);
3274 if (ret) {
3275 dev_err(qmp->dev, "phy initialization timed-out\n");
3276 goto err_disable_pipe_clk;
3277 }
3278
3279 return 0;
3280
3281 err_disable_pipe_clk:
3282 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
3283
3284 return ret;
3285 }
3286
qmp_pcie_power_off(struct phy * phy)3287 static int qmp_pcie_power_off(struct phy *phy)
3288 {
3289 struct qmp_pcie *qmp = phy_get_drvdata(phy);
3290 const struct qmp_phy_cfg *cfg = qmp->cfg;
3291
3292 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks);
3293
3294 /* PHY reset */
3295 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3296
3297 /* stop SerDes and Phy-Coding-Sublayer */
3298 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
3299 SERDES_START | PCS_START);
3300
3301 /* Put PHY into POWER DOWN state: active low */
3302 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3303 cfg->pwrdn_ctrl);
3304
3305 return 0;
3306 }
3307
qmp_pcie_enable(struct phy * phy)3308 static int qmp_pcie_enable(struct phy *phy)
3309 {
3310 int ret;
3311
3312 ret = qmp_pcie_init(phy);
3313 if (ret)
3314 return ret;
3315
3316 ret = qmp_pcie_power_on(phy);
3317 if (ret)
3318 qmp_pcie_exit(phy);
3319
3320 return ret;
3321 }
3322
qmp_pcie_disable(struct phy * phy)3323 static int qmp_pcie_disable(struct phy *phy)
3324 {
3325 int ret;
3326
3327 ret = qmp_pcie_power_off(phy);
3328 if (ret)
3329 return ret;
3330
3331 return qmp_pcie_exit(phy);
3332 }
3333
qmp_pcie_set_mode(struct phy * phy,enum phy_mode mode,int submode)3334 static int qmp_pcie_set_mode(struct phy *phy, enum phy_mode mode, int submode)
3335 {
3336 struct qmp_pcie *qmp = phy_get_drvdata(phy);
3337
3338 switch (submode) {
3339 case PHY_MODE_PCIE_RC:
3340 case PHY_MODE_PCIE_EP:
3341 qmp->mode = submode;
3342 break;
3343 default:
3344 dev_err(&phy->dev, "Unsupported submode %d\n", submode);
3345 return -EINVAL;
3346 }
3347
3348 return 0;
3349 }
3350
3351 static const struct phy_ops qmp_pcie_phy_ops = {
3352 .power_on = qmp_pcie_enable,
3353 .power_off = qmp_pcie_disable,
3354 .set_mode = qmp_pcie_set_mode,
3355 .owner = THIS_MODULE,
3356 };
3357
qmp_pcie_vreg_init(struct qmp_pcie * qmp)3358 static int qmp_pcie_vreg_init(struct qmp_pcie *qmp)
3359 {
3360 const struct qmp_phy_cfg *cfg = qmp->cfg;
3361 struct device *dev = qmp->dev;
3362 int num = cfg->num_vregs;
3363 int i;
3364
3365 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
3366 if (!qmp->vregs)
3367 return -ENOMEM;
3368
3369 for (i = 0; i < num; i++)
3370 qmp->vregs[i].supply = cfg->vreg_list[i];
3371
3372 return devm_regulator_bulk_get(dev, num, qmp->vregs);
3373 }
3374
qmp_pcie_reset_init(struct qmp_pcie * qmp)3375 static int qmp_pcie_reset_init(struct qmp_pcie *qmp)
3376 {
3377 const struct qmp_phy_cfg *cfg = qmp->cfg;
3378 struct device *dev = qmp->dev;
3379 int i;
3380 int ret;
3381
3382 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
3383 sizeof(*qmp->resets), GFP_KERNEL);
3384 if (!qmp->resets)
3385 return -ENOMEM;
3386
3387 for (i = 0; i < cfg->num_resets; i++)
3388 qmp->resets[i].id = cfg->reset_list[i];
3389
3390 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
3391 if (ret)
3392 return dev_err_probe(dev, ret, "failed to get resets\n");
3393
3394 if (cfg->has_nocsr_reset) {
3395 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr");
3396 if (IS_ERR(qmp->nocsr_reset))
3397 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset),
3398 "failed to get no-csr reset\n");
3399 }
3400
3401 return 0;
3402 }
3403
qmp_pcie_clk_init(struct qmp_pcie * qmp)3404 static int qmp_pcie_clk_init(struct qmp_pcie *qmp)
3405 {
3406 struct device *dev = qmp->dev;
3407 int num = ARRAY_SIZE(qmp_pciephy_clk_l);
3408 int i;
3409
3410 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
3411 if (!qmp->clks)
3412 return -ENOMEM;
3413
3414 for (i = 0; i < num; i++)
3415 qmp->clks[i].id = qmp_pciephy_clk_l[i];
3416
3417 return devm_clk_bulk_get_optional(dev, num, qmp->clks);
3418 }
3419
phy_clk_release_provider(void * res)3420 static void phy_clk_release_provider(void *res)
3421 {
3422 of_clk_del_provider(res);
3423 }
3424
3425 /*
3426 * Register a fixed rate pipe clock.
3427 *
3428 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
3429 * controls it. The <s>_pipe_clk coming out of the GCC is requested
3430 * by the PHY driver for its operations.
3431 * We register the <s>_pipe_clksrc here. The gcc driver takes care
3432 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
3433 * Below picture shows this relationship.
3434 *
3435 * +---------------+
3436 * | PHY block |<<---------------------------------------+
3437 * | | |
3438 * | +-------+ | +-----+ |
3439 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
3440 * clk | +-------+ | +-----+
3441 * +---------------+
3442 */
phy_pipe_clk_register(struct qmp_pcie * qmp,struct device_node * np)3443 static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np)
3444 {
3445 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
3446 struct clk_init_data init = { };
3447 int ret;
3448
3449 ret = of_property_read_string(np, "clock-output-names", &init.name);
3450 if (ret) {
3451 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
3452 return ret;
3453 }
3454
3455 init.ops = &clk_fixed_rate_ops;
3456
3457 /*
3458 * Controllers using QMP PHY-s use 125MHz pipe clock interface
3459 * unless other frequency is specified in the PHY config.
3460 */
3461 if (qmp->cfg->pipe_clock_rate)
3462 fixed->fixed_rate = qmp->cfg->pipe_clock_rate;
3463 else
3464 fixed->fixed_rate = 125000000;
3465
3466 fixed->hw.init = &init;
3467
3468 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
3469 if (ret)
3470 return ret;
3471
3472 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
3473 if (ret)
3474 return ret;
3475
3476 /*
3477 * Roll a devm action because the clock provider is the child node, but
3478 * the child node is not actually a device.
3479 */
3480 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
3481 }
3482
qmp_pcie_parse_dt_legacy(struct qmp_pcie * qmp,struct device_node * np)3483 static int qmp_pcie_parse_dt_legacy(struct qmp_pcie *qmp, struct device_node *np)
3484 {
3485 struct platform_device *pdev = to_platform_device(qmp->dev);
3486 const struct qmp_phy_cfg *cfg = qmp->cfg;
3487 struct device *dev = qmp->dev;
3488 struct clk *clk;
3489
3490 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
3491 if (IS_ERR(qmp->serdes))
3492 return PTR_ERR(qmp->serdes);
3493
3494 /*
3495 * Get memory resources for the PHY:
3496 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
3497 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
3498 * For single lane PHYs: pcs_misc (optional) -> 3.
3499 */
3500 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
3501 if (IS_ERR(qmp->tx))
3502 return PTR_ERR(qmp->tx);
3503
3504 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy"))
3505 qmp->rx = qmp->tx;
3506 else
3507 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
3508 if (IS_ERR(qmp->rx))
3509 return PTR_ERR(qmp->rx);
3510
3511 qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
3512 if (IS_ERR(qmp->pcs))
3513 return PTR_ERR(qmp->pcs);
3514
3515 if (cfg->lanes >= 2) {
3516 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
3517 if (IS_ERR(qmp->tx2))
3518 return PTR_ERR(qmp->tx2);
3519
3520 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
3521 if (IS_ERR(qmp->rx2))
3522 return PTR_ERR(qmp->rx2);
3523
3524 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
3525 } else {
3526 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
3527 }
3528
3529 if (IS_ERR(qmp->pcs_misc) &&
3530 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy"))
3531 qmp->pcs_misc = qmp->pcs + 0x400;
3532
3533 if (IS_ERR(qmp->pcs_misc)) {
3534 if (cfg->tbls.pcs_misc ||
3535 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) ||
3536 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) {
3537 return PTR_ERR(qmp->pcs_misc);
3538 }
3539 }
3540
3541 clk = devm_get_clk_from_child(dev, np, NULL);
3542 if (IS_ERR(clk)) {
3543 return dev_err_probe(dev, PTR_ERR(clk),
3544 "failed to get pipe clock\n");
3545 }
3546
3547 qmp->num_pipe_clks = 1;
3548 qmp->pipe_clks[0].id = "pipe";
3549 qmp->pipe_clks[0].clk = clk;
3550
3551 return 0;
3552 }
3553
qmp_pcie_get_4ln_config(struct qmp_pcie * qmp)3554 static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp)
3555 {
3556 struct regmap *tcsr;
3557 unsigned int args[2];
3558 int ret;
3559
3560 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node,
3561 "qcom,4ln-config-sel",
3562 ARRAY_SIZE(args), args);
3563 if (IS_ERR(tcsr)) {
3564 ret = PTR_ERR(tcsr);
3565 if (ret == -ENOENT)
3566 return 0;
3567
3568 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret);
3569 return ret;
3570 }
3571
3572 ret = regmap_test_bits(tcsr, args[0], BIT(args[1]));
3573 if (ret < 0) {
3574 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret);
3575 return ret;
3576 }
3577
3578 qmp->tcsr_4ln_config = ret;
3579
3580 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config);
3581
3582 return 0;
3583 }
3584
qmp_pcie_parse_dt(struct qmp_pcie * qmp)3585 static int qmp_pcie_parse_dt(struct qmp_pcie *qmp)
3586 {
3587 struct platform_device *pdev = to_platform_device(qmp->dev);
3588 const struct qmp_phy_cfg *cfg = qmp->cfg;
3589 const struct qmp_pcie_offsets *offs = cfg->offsets;
3590 struct device *dev = qmp->dev;
3591 void __iomem *base;
3592 int ret;
3593
3594 if (!offs)
3595 return -EINVAL;
3596
3597 ret = qmp_pcie_get_4ln_config(qmp);
3598 if (ret)
3599 return ret;
3600
3601 base = devm_platform_ioremap_resource(pdev, 0);
3602 if (IS_ERR(base))
3603 return PTR_ERR(base);
3604
3605 qmp->serdes = base + offs->serdes;
3606 qmp->pcs = base + offs->pcs;
3607 qmp->pcs_misc = base + offs->pcs_misc;
3608 qmp->tx = base + offs->tx;
3609 qmp->rx = base + offs->rx;
3610
3611 if (cfg->lanes >= 2) {
3612 qmp->tx2 = base + offs->tx2;
3613 qmp->rx2 = base + offs->rx2;
3614 }
3615
3616 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) {
3617 qmp->port_b = devm_platform_ioremap_resource(pdev, 1);
3618 if (IS_ERR(qmp->port_b))
3619 return PTR_ERR(qmp->port_b);
3620 }
3621
3622 if (cfg->tbls.ln_shrd)
3623 qmp->ln_shrd = base + offs->ln_shrd;
3624
3625 qmp->num_pipe_clks = 2;
3626 qmp->pipe_clks[0].id = "pipe";
3627 qmp->pipe_clks[1].id = "pipediv2";
3628
3629 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks);
3630 if (ret)
3631 return ret;
3632
3633 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1);
3634 if (ret)
3635 return ret;
3636
3637 return 0;
3638 }
3639
qmp_pcie_probe(struct platform_device * pdev)3640 static int qmp_pcie_probe(struct platform_device *pdev)
3641 {
3642 struct device *dev = &pdev->dev;
3643 struct phy_provider *phy_provider;
3644 struct device_node *np;
3645 struct qmp_pcie *qmp;
3646 int ret;
3647
3648 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
3649 if (!qmp)
3650 return -ENOMEM;
3651
3652 qmp->dev = dev;
3653
3654 qmp->cfg = of_device_get_match_data(dev);
3655 if (!qmp->cfg)
3656 return -EINVAL;
3657
3658 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl);
3659 WARN_ON_ONCE(!qmp->cfg->phy_status);
3660
3661 ret = qmp_pcie_clk_init(qmp);
3662 if (ret)
3663 return ret;
3664
3665 ret = qmp_pcie_reset_init(qmp);
3666 if (ret)
3667 return ret;
3668
3669 ret = qmp_pcie_vreg_init(qmp);
3670 if (ret)
3671 return ret;
3672
3673 /* Check for legacy binding with child node. */
3674 np = of_get_next_available_child(dev->of_node, NULL);
3675 if (np) {
3676 ret = qmp_pcie_parse_dt_legacy(qmp, np);
3677 } else {
3678 np = of_node_get(dev->of_node);
3679 ret = qmp_pcie_parse_dt(qmp);
3680 }
3681 if (ret)
3682 goto err_node_put;
3683
3684 ret = phy_pipe_clk_register(qmp, np);
3685 if (ret)
3686 goto err_node_put;
3687
3688 qmp->mode = PHY_MODE_PCIE_RC;
3689
3690 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops);
3691 if (IS_ERR(qmp->phy)) {
3692 ret = PTR_ERR(qmp->phy);
3693 dev_err(dev, "failed to create PHY: %d\n", ret);
3694 goto err_node_put;
3695 }
3696
3697 phy_set_drvdata(qmp->phy, qmp);
3698
3699 of_node_put(np);
3700
3701 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
3702
3703 return PTR_ERR_OR_ZERO(phy_provider);
3704
3705 err_node_put:
3706 of_node_put(np);
3707 return ret;
3708 }
3709
3710 static const struct of_device_id qmp_pcie_of_match_table[] = {
3711 {
3712 .compatible = "qcom,ipq6018-qmp-pcie-phy",
3713 .data = &ipq6018_pciephy_cfg,
3714 }, {
3715 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
3716 .data = &ipq8074_pciephy_gen3_cfg,
3717 }, {
3718 .compatible = "qcom,ipq8074-qmp-pcie-phy",
3719 .data = &ipq8074_pciephy_cfg,
3720 }, {
3721 .compatible = "qcom,msm8998-qmp-pcie-phy",
3722 .data = &msm8998_pciephy_cfg,
3723 }, {
3724 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
3725 .data = &sa8775p_qmp_gen4x2_pciephy_cfg,
3726 }, {
3727 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
3728 .data = &sa8775p_qmp_gen4x4_pciephy_cfg,
3729 }, {
3730 .compatible = "qcom,sc8180x-qmp-pcie-phy",
3731 .data = &sc8180x_pciephy_cfg,
3732 }, {
3733 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
3734 .data = &sc8280xp_qmp_gen3x1_pciephy_cfg,
3735 }, {
3736 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
3737 .data = &sc8280xp_qmp_gen3x2_pciephy_cfg,
3738 }, {
3739 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
3740 .data = &sc8280xp_qmp_gen3x4_pciephy_cfg,
3741 }, {
3742 .compatible = "qcom,sdm845-qhp-pcie-phy",
3743 .data = &sdm845_qhp_pciephy_cfg,
3744 }, {
3745 .compatible = "qcom,sdm845-qmp-pcie-phy",
3746 .data = &sdm845_qmp_pciephy_cfg,
3747 }, {
3748 .compatible = "qcom,sdx55-qmp-pcie-phy",
3749 .data = &sdx55_qmp_pciephy_cfg,
3750 }, {
3751 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
3752 .data = &sdx65_qmp_pciephy_cfg,
3753 }, {
3754 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
3755 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
3756 }, {
3757 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
3758 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
3759 }, {
3760 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
3761 .data = &sm8250_qmp_gen3x1_pciephy_cfg,
3762 }, {
3763 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
3764 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
3765 }, {
3766 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
3767 .data = &sm8250_qmp_gen3x2_pciephy_cfg,
3768 }, {
3769 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
3770 .data = &sm8350_qmp_gen3x1_pciephy_cfg,
3771 }, {
3772 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
3773 .data = &sm8350_qmp_gen3x2_pciephy_cfg,
3774 }, {
3775 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
3776 .data = &sm8450_qmp_gen3x1_pciephy_cfg,
3777 }, {
3778 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
3779 .data = &sm8450_qmp_gen4x2_pciephy_cfg,
3780 }, {
3781 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
3782 .data = &sm8550_qmp_gen3x2_pciephy_cfg,
3783 }, {
3784 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
3785 .data = &sm8550_qmp_gen4x2_pciephy_cfg,
3786 },
3787 { },
3788 };
3789 MODULE_DEVICE_TABLE(of, qmp_pcie_of_match_table);
3790
3791 static struct platform_driver qmp_pcie_driver = {
3792 .probe = qmp_pcie_probe,
3793 .driver = {
3794 .name = "qcom-qmp-pcie-phy",
3795 .of_match_table = qmp_pcie_of_match_table,
3796 },
3797 };
3798
3799 module_platform_driver(qmp_pcie_driver);
3800
3801 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
3802 MODULE_DESCRIPTION("Qualcomm QMP PCIe PHY driver");
3803 MODULE_LICENSE("GPL v2");
3804