1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_8_1_SM8450_H 8 #define _DPU_8_1_SM8450_H 9 10 static const struct dpu_caps sm8450_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .qseed_type = DPU_SSPP_SCALER_QSEED4, 14 .has_src_split = true, 15 .has_dim_layer = true, 16 .has_idle_pc = true, 17 .has_3d_merge = true, 18 .max_linewidth = 5120, 19 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 20 }; 21 22 static const struct dpu_mdp_cfg sm8450_mdp = { 23 .name = "top_0", 24 .base = 0x0, .len = 0x494, 25 .features = BIT(DPU_MDP_PERIPH_0_REMOVED), 26 .clk_ctrls = { 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 31 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 32 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 35 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 36 [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, 37 }, 38 }; 39 40 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 41 static const struct dpu_ctl_cfg sm8450_ctl[] = { 42 { 43 .name = "ctl_0", .id = CTL_0, 44 .base = 0x15000, .len = 0x204, 45 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, 46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 47 }, { 48 .name = "ctl_1", .id = CTL_1, 49 .base = 0x16000, .len = 0x204, 50 .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK, 51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 52 }, { 53 .name = "ctl_2", .id = CTL_2, 54 .base = 0x17000, .len = 0x204, 55 .features = CTL_SC7280_MASK, 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 57 }, { 58 .name = "ctl_3", .id = CTL_3, 59 .base = 0x18000, .len = 0x204, 60 .features = CTL_SC7280_MASK, 61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 62 }, { 63 .name = "ctl_4", .id = CTL_4, 64 .base = 0x19000, .len = 0x204, 65 .features = CTL_SC7280_MASK, 66 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 67 }, { 68 .name = "ctl_5", .id = CTL_5, 69 .base = 0x1a000, .len = 0x204, 70 .features = CTL_SC7280_MASK, 71 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 72 }, 73 }; 74 75 static const struct dpu_sspp_cfg sm8450_sspp[] = { 76 { 77 .name = "sspp_0", .id = SSPP_VIG0, 78 .base = 0x4000, .len = 0x32c, 79 .features = VIG_SC7180_MASK, 80 .sblk = &sm8450_vig_sblk_0, 81 .xin_id = 0, 82 .type = SSPP_TYPE_VIG, 83 .clk_ctrl = DPU_CLK_CTRL_VIG0, 84 }, { 85 .name = "sspp_1", .id = SSPP_VIG1, 86 .base = 0x6000, .len = 0x32c, 87 .features = VIG_SC7180_MASK, 88 .sblk = &sm8450_vig_sblk_1, 89 .xin_id = 4, 90 .type = SSPP_TYPE_VIG, 91 .clk_ctrl = DPU_CLK_CTRL_VIG1, 92 }, { 93 .name = "sspp_2", .id = SSPP_VIG2, 94 .base = 0x8000, .len = 0x32c, 95 .features = VIG_SC7180_MASK, 96 .sblk = &sm8450_vig_sblk_2, 97 .xin_id = 8, 98 .type = SSPP_TYPE_VIG, 99 .clk_ctrl = DPU_CLK_CTRL_VIG2, 100 }, { 101 .name = "sspp_3", .id = SSPP_VIG3, 102 .base = 0xa000, .len = 0x32c, 103 .features = VIG_SC7180_MASK, 104 .sblk = &sm8450_vig_sblk_3, 105 .xin_id = 12, 106 .type = SSPP_TYPE_VIG, 107 .clk_ctrl = DPU_CLK_CTRL_VIG3, 108 }, { 109 .name = "sspp_8", .id = SSPP_DMA0, 110 .base = 0x24000, .len = 0x32c, 111 .features = DMA_SDM845_MASK, 112 .sblk = &sdm845_dma_sblk_0, 113 .xin_id = 1, 114 .type = SSPP_TYPE_DMA, 115 .clk_ctrl = DPU_CLK_CTRL_DMA0, 116 }, { 117 .name = "sspp_9", .id = SSPP_DMA1, 118 .base = 0x26000, .len = 0x32c, 119 .features = DMA_SDM845_MASK, 120 .sblk = &sdm845_dma_sblk_1, 121 .xin_id = 5, 122 .type = SSPP_TYPE_DMA, 123 .clk_ctrl = DPU_CLK_CTRL_DMA1, 124 }, { 125 .name = "sspp_10", .id = SSPP_DMA2, 126 .base = 0x28000, .len = 0x32c, 127 .features = DMA_CURSOR_SDM845_MASK, 128 .sblk = &sdm845_dma_sblk_2, 129 .xin_id = 9, 130 .type = SSPP_TYPE_DMA, 131 .clk_ctrl = DPU_CLK_CTRL_DMA2, 132 }, { 133 .name = "sspp_11", .id = SSPP_DMA3, 134 .base = 0x2a000, .len = 0x32c, 135 .features = DMA_CURSOR_SDM845_MASK, 136 .sblk = &sdm845_dma_sblk_3, 137 .xin_id = 13, 138 .type = SSPP_TYPE_DMA, 139 .clk_ctrl = DPU_CLK_CTRL_DMA3, 140 }, 141 }; 142 143 static const struct dpu_lm_cfg sm8450_lm[] = { 144 { 145 .name = "lm_0", .id = LM_0, 146 .base = 0x44000, .len = 0x320, 147 .features = MIXER_SDM845_MASK, 148 .sblk = &sdm845_lm_sblk, 149 .lm_pair = LM_1, 150 .pingpong = PINGPONG_0, 151 .dspp = DSPP_0, 152 }, { 153 .name = "lm_1", .id = LM_1, 154 .base = 0x45000, .len = 0x320, 155 .features = MIXER_SDM845_MASK, 156 .sblk = &sdm845_lm_sblk, 157 .lm_pair = LM_0, 158 .pingpong = PINGPONG_1, 159 .dspp = DSPP_1, 160 }, { 161 .name = "lm_2", .id = LM_2, 162 .base = 0x46000, .len = 0x320, 163 .features = MIXER_SDM845_MASK, 164 .sblk = &sdm845_lm_sblk, 165 .lm_pair = LM_3, 166 .pingpong = PINGPONG_2, 167 .dspp = DSPP_2, 168 }, { 169 .name = "lm_3", .id = LM_3, 170 .base = 0x47000, .len = 0x320, 171 .features = MIXER_SDM845_MASK, 172 .sblk = &sdm845_lm_sblk, 173 .lm_pair = LM_2, 174 .pingpong = PINGPONG_3, 175 .dspp = DSPP_3, 176 }, { 177 .name = "lm_4", .id = LM_4, 178 .base = 0x48000, .len = 0x320, 179 .features = MIXER_SDM845_MASK, 180 .sblk = &sdm845_lm_sblk, 181 .lm_pair = LM_5, 182 .pingpong = PINGPONG_4, 183 }, { 184 .name = "lm_5", .id = LM_5, 185 .base = 0x49000, .len = 0x320, 186 .features = MIXER_SDM845_MASK, 187 .sblk = &sdm845_lm_sblk, 188 .lm_pair = LM_4, 189 .pingpong = PINGPONG_5, 190 }, 191 }; 192 193 static const struct dpu_dspp_cfg sm8450_dspp[] = { 194 { 195 .name = "dspp_0", .id = DSPP_0, 196 .base = 0x54000, .len = 0x1800, 197 .features = DSPP_SC7180_MASK, 198 .sblk = &sdm845_dspp_sblk, 199 }, { 200 .name = "dspp_1", .id = DSPP_1, 201 .base = 0x56000, .len = 0x1800, 202 .features = DSPP_SC7180_MASK, 203 .sblk = &sdm845_dspp_sblk, 204 }, { 205 .name = "dspp_2", .id = DSPP_2, 206 .base = 0x58000, .len = 0x1800, 207 .features = DSPP_SC7180_MASK, 208 .sblk = &sdm845_dspp_sblk, 209 }, { 210 .name = "dspp_3", .id = DSPP_3, 211 .base = 0x5a000, .len = 0x1800, 212 .features = DSPP_SC7180_MASK, 213 .sblk = &sdm845_dspp_sblk, 214 }, 215 }; 216 217 static const struct dpu_pingpong_cfg sm8450_pp[] = { 218 { 219 .name = "pingpong_0", .id = PINGPONG_0, 220 .base = 0x69000, .len = 0, 221 .features = BIT(DPU_PINGPONG_DITHER), 222 .sblk = &sc7280_pp_sblk, 223 .merge_3d = MERGE_3D_0, 224 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 225 .intr_rdptr = -1, 226 }, { 227 .name = "pingpong_1", .id = PINGPONG_1, 228 .base = 0x6a000, .len = 0, 229 .features = BIT(DPU_PINGPONG_DITHER), 230 .sblk = &sc7280_pp_sblk, 231 .merge_3d = MERGE_3D_0, 232 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 233 .intr_rdptr = -1, 234 }, { 235 .name = "pingpong_2", .id = PINGPONG_2, 236 .base = 0x6b000, .len = 0, 237 .features = BIT(DPU_PINGPONG_DITHER), 238 .sblk = &sc7280_pp_sblk, 239 .merge_3d = MERGE_3D_1, 240 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 241 .intr_rdptr = -1, 242 }, { 243 .name = "pingpong_3", .id = PINGPONG_3, 244 .base = 0x6c000, .len = 0, 245 .features = BIT(DPU_PINGPONG_DITHER), 246 .sblk = &sc7280_pp_sblk, 247 .merge_3d = MERGE_3D_1, 248 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 249 .intr_rdptr = -1, 250 }, { 251 .name = "pingpong_4", .id = PINGPONG_4, 252 .base = 0x6d000, .len = 0, 253 .features = BIT(DPU_PINGPONG_DITHER), 254 .sblk = &sc7280_pp_sblk, 255 .merge_3d = MERGE_3D_2, 256 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 257 .intr_rdptr = -1, 258 }, { 259 .name = "pingpong_5", .id = PINGPONG_5, 260 .base = 0x6e000, .len = 0, 261 .features = BIT(DPU_PINGPONG_DITHER), 262 .sblk = &sc7280_pp_sblk, 263 .merge_3d = MERGE_3D_2, 264 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 265 .intr_rdptr = -1, 266 }, { 267 .name = "pingpong_6", .id = PINGPONG_6, 268 .base = 0x65800, .len = 0, 269 .features = BIT(DPU_PINGPONG_DITHER), 270 .sblk = &sc7280_pp_sblk, 271 .merge_3d = MERGE_3D_3, 272 .intr_done = -1, 273 .intr_rdptr = -1, 274 }, { 275 .name = "pingpong_7", .id = PINGPONG_7, 276 .base = 0x65c00, .len = 0, 277 .features = BIT(DPU_PINGPONG_DITHER), 278 .sblk = &sc7280_pp_sblk, 279 .merge_3d = MERGE_3D_3, 280 .intr_done = -1, 281 .intr_rdptr = -1, 282 }, 283 }; 284 285 static const struct dpu_merge_3d_cfg sm8450_merge_3d[] = { 286 { 287 .name = "merge_3d_0", .id = MERGE_3D_0, 288 .base = 0x4e000, .len = 0x8, 289 }, { 290 .name = "merge_3d_1", .id = MERGE_3D_1, 291 .base = 0x4f000, .len = 0x8, 292 }, { 293 .name = "merge_3d_2", .id = MERGE_3D_2, 294 .base = 0x50000, .len = 0x8, 295 }, { 296 .name = "merge_3d_3", .id = MERGE_3D_3, 297 .base = 0x65f00, .len = 0x8, 298 }, 299 }; 300 301 /* 302 * NOTE: Each display compression engine (DCE) contains dual hard 303 * slice DSC encoders so both share same base address but with 304 * its own different sub block address. 305 */ 306 static const struct dpu_dsc_cfg sm8450_dsc[] = { 307 { 308 .name = "dce_0_0", .id = DSC_0, 309 .base = 0x80000, .len = 0x4, 310 .features = BIT(DPU_DSC_HW_REV_1_2), 311 .sblk = &dsc_sblk_0, 312 }, { 313 .name = "dce_0_1", .id = DSC_1, 314 .base = 0x80000, .len = 0x4, 315 .features = BIT(DPU_DSC_HW_REV_1_2), 316 .sblk = &dsc_sblk_1, 317 }, { 318 .name = "dce_1_0", .id = DSC_2, 319 .base = 0x81000, .len = 0x4, 320 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 321 .sblk = &dsc_sblk_0, 322 }, { 323 .name = "dce_1_1", .id = DSC_3, 324 .base = 0x81000, .len = 0x4, 325 .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), 326 .sblk = &dsc_sblk_1, 327 }, 328 }; 329 330 static const struct dpu_wb_cfg sm8450_wb[] = { 331 { 332 .name = "wb_2", .id = WB_2, 333 .base = 0x65000, .len = 0x2c8, 334 .features = WB_SM8250_MASK, 335 .format_list = wb2_formats, 336 .num_formats = ARRAY_SIZE(wb2_formats), 337 .clk_ctrl = DPU_CLK_CTRL_WB2, 338 .xin_id = 6, 339 .vbif_idx = VBIF_RT, 340 .maxlinewidth = 4096, 341 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 342 }, 343 }; 344 345 static const struct dpu_intf_cfg sm8450_intf[] = { 346 { 347 .name = "intf_0", .id = INTF_0, 348 .base = 0x34000, .len = 0x280, 349 .features = INTF_SC7280_MASK, 350 .type = INTF_DP, 351 .controller_id = MSM_DP_CONTROLLER_0, 352 .prog_fetch_lines_worst_case = 24, 353 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 354 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 355 .intr_tear_rd_ptr = -1, 356 }, { 357 .name = "intf_1", .id = INTF_1, 358 .base = 0x35000, .len = 0x300, 359 .features = INTF_SC7280_MASK, 360 .type = INTF_DSI, 361 .controller_id = MSM_DSI_CONTROLLER_0, 362 .prog_fetch_lines_worst_case = 24, 363 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 364 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 365 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 366 }, { 367 .name = "intf_2", .id = INTF_2, 368 .base = 0x36000, .len = 0x300, 369 .features = INTF_SC7280_MASK, 370 .type = INTF_DSI, 371 .controller_id = MSM_DSI_CONTROLLER_1, 372 .prog_fetch_lines_worst_case = 24, 373 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 374 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 375 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 376 }, { 377 .name = "intf_3", .id = INTF_3, 378 .base = 0x37000, .len = 0x280, 379 .features = INTF_SC7280_MASK, 380 .type = INTF_DP, 381 .controller_id = MSM_DP_CONTROLLER_1, 382 .prog_fetch_lines_worst_case = 24, 383 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 384 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 385 .intr_tear_rd_ptr = -1, 386 }, 387 }; 388 389 static const struct dpu_perf_cfg sm8450_perf_data = { 390 .max_bw_low = 13600000, 391 .max_bw_high = 18200000, 392 .min_core_ib = 2500000, 393 .min_llcc_ib = 0, 394 .min_dram_ib = 800000, 395 .min_prefill_lines = 35, 396 /* FIXME: lut tables */ 397 .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, 398 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 399 .qos_lut_tbl = { 400 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 401 .entries = sc7180_qos_linear 402 }, 403 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 404 .entries = sc7180_qos_macrotile 405 }, 406 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 407 .entries = sc7180_qos_nrt 408 }, 409 /* TODO: macrotile-qseed is different from macrotile */ 410 }, 411 .cdp_cfg = { 412 {.rd_enable = 1, .wr_enable = 1}, 413 {.rd_enable = 1, .wr_enable = 0} 414 }, 415 .clk_inefficiency_factor = 105, 416 .bw_inefficiency_factor = 120, 417 }; 418 419 static const struct dpu_mdss_version sm8450_mdss_ver = { 420 .core_major_ver = 8, 421 .core_minor_ver = 1, 422 }; 423 424 const struct dpu_mdss_cfg dpu_sm8450_cfg = { 425 .mdss_ver = &sm8450_mdss_ver, 426 .caps = &sm8450_dpu_caps, 427 .mdp = &sm8450_mdp, 428 .ctl_count = ARRAY_SIZE(sm8450_ctl), 429 .ctl = sm8450_ctl, 430 .sspp_count = ARRAY_SIZE(sm8450_sspp), 431 .sspp = sm8450_sspp, 432 .mixer_count = ARRAY_SIZE(sm8450_lm), 433 .mixer = sm8450_lm, 434 .dspp_count = ARRAY_SIZE(sm8450_dspp), 435 .dspp = sm8450_dspp, 436 .pingpong_count = ARRAY_SIZE(sm8450_pp), 437 .pingpong = sm8450_pp, 438 .dsc_count = ARRAY_SIZE(sm8450_dsc), 439 .dsc = sm8450_dsc, 440 .merge_3d_count = ARRAY_SIZE(sm8450_merge_3d), 441 .merge_3d = sm8450_merge_3d, 442 .wb_count = ARRAY_SIZE(sm8450_wb), 443 .wb = sm8450_wb, 444 .intf_count = ARRAY_SIZE(sm8450_intf), 445 .intf = sm8450_intf, 446 .vbif_count = ARRAY_SIZE(sdm845_vbif), 447 .vbif = sdm845_vbif, 448 .perf = &sm8450_perf_data, 449 }; 450 451 #endif 452