1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5  */
6 
7 #ifndef _DPU_5_0_SM8150_H
8 #define _DPU_5_0_SM8150_H
9 
10 static const struct dpu_caps sm8150_dpu_caps = {
11 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
12 	.max_mixer_blendstages = 0xb,
13 	.qseed_type = DPU_SSPP_SCALER_QSEED3,
14 	.has_src_split = true,
15 	.has_dim_layer = true,
16 	.has_idle_pc = true,
17 	.has_3d_merge = true,
18 	.max_linewidth = 4096,
19 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
20 	.max_hdeci_exp = MAX_HORZ_DECIMATION,
21 	.max_vdeci_exp = MAX_VERT_DECIMATION,
22 };
23 
24 static const struct dpu_mdp_cfg sm8150_mdp = {
25 	.name = "top_0",
26 	.base = 0x0, .len = 0x45c,
27 	.features = BIT(DPU_MDP_AUDIO_SELECT),
28 	.clk_ctrls = {
29 		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
30 		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
31 		[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
32 		[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
33 		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
34 		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
35 		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
36 		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
37 	},
38 };
39 
40 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
41 static const struct dpu_ctl_cfg sm8150_ctl[] = {
42 	{
43 		.name = "ctl_0", .id = CTL_0,
44 		.base = 0x1000, .len = 0x1e0,
45 		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
46 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
47 	}, {
48 		.name = "ctl_1", .id = CTL_1,
49 		.base = 0x1200, .len = 0x1e0,
50 		.features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
51 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
52 	}, {
53 		.name = "ctl_2", .id = CTL_2,
54 		.base = 0x1400, .len = 0x1e0,
55 		.features = BIT(DPU_CTL_ACTIVE_CFG),
56 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
57 	}, {
58 		.name = "ctl_3", .id = CTL_3,
59 		.base = 0x1600, .len = 0x1e0,
60 		.features = BIT(DPU_CTL_ACTIVE_CFG),
61 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
62 	}, {
63 		.name = "ctl_4", .id = CTL_4,
64 		.base = 0x1800, .len = 0x1e0,
65 		.features = BIT(DPU_CTL_ACTIVE_CFG),
66 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
67 	}, {
68 		.name = "ctl_5", .id = CTL_5,
69 		.base = 0x1a00, .len = 0x1e0,
70 		.features = BIT(DPU_CTL_ACTIVE_CFG),
71 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
72 	},
73 };
74 
75 static const struct dpu_sspp_cfg sm8150_sspp[] = {
76 	{
77 		.name = "sspp_0", .id = SSPP_VIG0,
78 		.base = 0x4000, .len = 0x1f0,
79 		.features = VIG_SDM845_MASK,
80 		.sblk = &sm8150_vig_sblk_0,
81 		.xin_id = 0,
82 		.type = SSPP_TYPE_VIG,
83 		.clk_ctrl = DPU_CLK_CTRL_VIG0,
84 	}, {
85 		.name = "sspp_1", .id = SSPP_VIG1,
86 		.base = 0x6000, .len = 0x1f0,
87 		.features = VIG_SDM845_MASK,
88 		.sblk = &sm8150_vig_sblk_1,
89 		.xin_id = 4,
90 		.type = SSPP_TYPE_VIG,
91 		.clk_ctrl = DPU_CLK_CTRL_VIG1,
92 	}, {
93 		.name = "sspp_2", .id = SSPP_VIG2,
94 		.base = 0x8000, .len = 0x1f0,
95 		.features = VIG_SDM845_MASK,
96 		.sblk = &sm8150_vig_sblk_2,
97 		.xin_id = 8,
98 		.type = SSPP_TYPE_VIG,
99 		.clk_ctrl = DPU_CLK_CTRL_VIG2,
100 	}, {
101 		.name = "sspp_3", .id = SSPP_VIG3,
102 		.base = 0xa000, .len = 0x1f0,
103 		.features = VIG_SDM845_MASK,
104 		.sblk = &sm8150_vig_sblk_3,
105 		.xin_id = 12,
106 		.type = SSPP_TYPE_VIG,
107 		.clk_ctrl = DPU_CLK_CTRL_VIG3,
108 	}, {
109 		.name = "sspp_8", .id = SSPP_DMA0,
110 		.base = 0x24000, .len = 0x1f0,
111 		.features = DMA_SDM845_MASK,
112 		.sblk = &sdm845_dma_sblk_0,
113 		.xin_id = 1,
114 		.type = SSPP_TYPE_DMA,
115 		.clk_ctrl = DPU_CLK_CTRL_DMA0,
116 	}, {
117 		.name = "sspp_9", .id = SSPP_DMA1,
118 		.base = 0x26000, .len = 0x1f0,
119 		.features = DMA_SDM845_MASK,
120 		.sblk = &sdm845_dma_sblk_1,
121 		.xin_id = 5,
122 		.type = SSPP_TYPE_DMA,
123 		.clk_ctrl = DPU_CLK_CTRL_DMA1,
124 	}, {
125 		.name = "sspp_10", .id = SSPP_DMA2,
126 		.base = 0x28000, .len = 0x1f0,
127 		.features = DMA_CURSOR_SDM845_MASK,
128 		.sblk = &sdm845_dma_sblk_2,
129 		.xin_id = 9,
130 		.type = SSPP_TYPE_DMA,
131 		.clk_ctrl = DPU_CLK_CTRL_DMA2,
132 	}, {
133 		.name = "sspp_11", .id = SSPP_DMA3,
134 		.base = 0x2a000, .len = 0x1f0,
135 		.features = DMA_CURSOR_SDM845_MASK,
136 		.sblk = &sdm845_dma_sblk_3,
137 		.xin_id = 13,
138 		.type = SSPP_TYPE_DMA,
139 		.clk_ctrl = DPU_CLK_CTRL_DMA3,
140 	},
141 };
142 
143 static const struct dpu_lm_cfg sm8150_lm[] = {
144 	{
145 		.name = "lm_0", .id = LM_0,
146 		.base = 0x44000, .len = 0x320,
147 		.features = MIXER_SDM845_MASK,
148 		.sblk = &sdm845_lm_sblk,
149 		.lm_pair = LM_1,
150 		.pingpong = PINGPONG_0,
151 		.dspp = DSPP_0,
152 	}, {
153 		.name = "lm_1", .id = LM_1,
154 		.base = 0x45000, .len = 0x320,
155 		.features = MIXER_SDM845_MASK,
156 		.sblk = &sdm845_lm_sblk,
157 		.lm_pair = LM_0,
158 		.pingpong = PINGPONG_1,
159 		.dspp = DSPP_1,
160 	}, {
161 		.name = "lm_2", .id = LM_2,
162 		.base = 0x46000, .len = 0x320,
163 		.features = MIXER_SDM845_MASK,
164 		.sblk = &sdm845_lm_sblk,
165 		.lm_pair = LM_3,
166 		.pingpong = PINGPONG_2,
167 	}, {
168 		.name = "lm_3", .id = LM_3,
169 		.base = 0x47000, .len = 0x320,
170 		.features = MIXER_SDM845_MASK,
171 		.sblk = &sdm845_lm_sblk,
172 		.lm_pair = LM_2,
173 		.pingpong = PINGPONG_3,
174 	}, {
175 		.name = "lm_4", .id = LM_4,
176 		.base = 0x48000, .len = 0x320,
177 		.features = MIXER_SDM845_MASK,
178 		.sblk = &sdm845_lm_sblk,
179 		.lm_pair = LM_5,
180 		.pingpong = PINGPONG_4,
181 	}, {
182 		.name = "lm_5", .id = LM_5,
183 		.base = 0x49000, .len = 0x320,
184 		.features = MIXER_SDM845_MASK,
185 		.sblk = &sdm845_lm_sblk,
186 		.lm_pair = LM_4,
187 		.pingpong = PINGPONG_5,
188 	},
189 };
190 
191 static const struct dpu_dspp_cfg sm8150_dspp[] = {
192 	{
193 		.name = "dspp_0", .id = DSPP_0,
194 		.base = 0x54000, .len = 0x1800,
195 		.features = DSPP_SC7180_MASK,
196 		.sblk = &sdm845_dspp_sblk,
197 	}, {
198 		.name = "dspp_1", .id = DSPP_1,
199 		.base = 0x56000, .len = 0x1800,
200 		.features = DSPP_SC7180_MASK,
201 		.sblk = &sdm845_dspp_sblk,
202 	}, {
203 		.name = "dspp_2", .id = DSPP_2,
204 		.base = 0x58000, .len = 0x1800,
205 		.features = DSPP_SC7180_MASK,
206 		.sblk = &sdm845_dspp_sblk,
207 	}, {
208 		.name = "dspp_3", .id = DSPP_3,
209 		.base = 0x5a000, .len = 0x1800,
210 		.features = DSPP_SC7180_MASK,
211 		.sblk = &sdm845_dspp_sblk,
212 	},
213 };
214 
215 static const struct dpu_pingpong_cfg sm8150_pp[] = {
216 	{
217 		.name = "pingpong_0", .id = PINGPONG_0,
218 		.base = 0x70000, .len = 0xd4,
219 		.features = PINGPONG_SM8150_MASK,
220 		.sblk = &sdm845_pp_sblk,
221 		.merge_3d = MERGE_3D_0,
222 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
223 		.intr_rdptr = -1,
224 	}, {
225 		.name = "pingpong_1", .id = PINGPONG_1,
226 		.base = 0x70800, .len = 0xd4,
227 		.features = PINGPONG_SM8150_MASK,
228 		.sblk = &sdm845_pp_sblk,
229 		.merge_3d = MERGE_3D_0,
230 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
231 		.intr_rdptr = -1,
232 	}, {
233 		.name = "pingpong_2", .id = PINGPONG_2,
234 		.base = 0x71000, .len = 0xd4,
235 		.features = PINGPONG_SM8150_MASK,
236 		.sblk = &sdm845_pp_sblk,
237 		.merge_3d = MERGE_3D_1,
238 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
239 		.intr_rdptr = -1,
240 	}, {
241 		.name = "pingpong_3", .id = PINGPONG_3,
242 		.base = 0x71800, .len = 0xd4,
243 		.features = PINGPONG_SM8150_MASK,
244 		.sblk = &sdm845_pp_sblk,
245 		.merge_3d = MERGE_3D_1,
246 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
247 		.intr_rdptr = -1,
248 	}, {
249 		.name = "pingpong_4", .id = PINGPONG_4,
250 		.base = 0x72000, .len = 0xd4,
251 		.features = PINGPONG_SM8150_MASK,
252 		.sblk = &sdm845_pp_sblk,
253 		.merge_3d = MERGE_3D_2,
254 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
255 		.intr_rdptr = -1,
256 	}, {
257 		.name = "pingpong_5", .id = PINGPONG_5,
258 		.base = 0x72800, .len = 0xd4,
259 		.features = PINGPONG_SM8150_MASK,
260 		.sblk = &sdm845_pp_sblk,
261 		.merge_3d = MERGE_3D_2,
262 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
263 		.intr_rdptr = -1,
264 	},
265 };
266 
267 static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = {
268 	{
269 		.name = "merge_3d_0", .id = MERGE_3D_0,
270 		.base = 0x83000, .len = 0x8,
271 	}, {
272 		.name = "merge_3d_1", .id = MERGE_3D_1,
273 		.base = 0x83100, .len = 0x8,
274 	}, {
275 		.name = "merge_3d_2", .id = MERGE_3D_2,
276 		.base = 0x83200, .len = 0x8,
277 	},
278 };
279 
280 static const struct dpu_dsc_cfg sm8150_dsc[] = {
281 	{
282 		.name = "dsc_0", .id = DSC_0,
283 		.base = 0x80000, .len = 0x140,
284 		.features = BIT(DPU_DSC_OUTPUT_CTRL),
285 	}, {
286 		.name = "dsc_1", .id = DSC_1,
287 		.base = 0x80400, .len = 0x140,
288 		.features = BIT(DPU_DSC_OUTPUT_CTRL),
289 	}, {
290 		.name = "dsc_2", .id = DSC_2,
291 		.base = 0x80800, .len = 0x140,
292 		.features = BIT(DPU_DSC_OUTPUT_CTRL),
293 	}, {
294 		.name = "dsc_3", .id = DSC_3,
295 		.base = 0x80c00, .len = 0x140,
296 		.features = BIT(DPU_DSC_OUTPUT_CTRL),
297 	},
298 };
299 
300 static const struct dpu_intf_cfg sm8150_intf[] = {
301 	{
302 		.name = "intf_0", .id = INTF_0,
303 		.base = 0x6a000, .len = 0x280,
304 		.features = INTF_SC7180_MASK,
305 		.type = INTF_DP,
306 		.controller_id = MSM_DP_CONTROLLER_0,
307 		.prog_fetch_lines_worst_case = 24,
308 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
309 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
310 		.intr_tear_rd_ptr = -1,
311 	}, {
312 		.name = "intf_1", .id = INTF_1,
313 		.base = 0x6a800, .len = 0x2bc,
314 		.features = INTF_SC7180_MASK,
315 		.type = INTF_DSI,
316 		.controller_id = MSM_DSI_CONTROLLER_0,
317 		.prog_fetch_lines_worst_case = 24,
318 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
319 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
320 		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
321 	}, {
322 		.name = "intf_2", .id = INTF_2,
323 		.base = 0x6b000, .len = 0x2bc,
324 		.features = INTF_SC7180_MASK,
325 		.type = INTF_DSI,
326 		.controller_id = MSM_DSI_CONTROLLER_1,
327 		.prog_fetch_lines_worst_case = 24,
328 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
329 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
330 		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
331 	}, {
332 		.name = "intf_3", .id = INTF_3,
333 		.base = 0x6b800, .len = 0x280,
334 		.features = INTF_SC7180_MASK,
335 		.type = INTF_DP,
336 		.controller_id = MSM_DP_CONTROLLER_1,
337 		.prog_fetch_lines_worst_case = 24,
338 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
339 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
340 		.intr_tear_rd_ptr = -1,
341 	},
342 };
343 
344 static const struct dpu_perf_cfg sm8150_perf_data = {
345 	.max_bw_low = 12800000,
346 	.max_bw_high = 12800000,
347 	.min_core_ib = 2400000,
348 	.min_llcc_ib = 800000,
349 	.min_dram_ib = 800000,
350 	.min_prefill_lines = 24,
351 	.danger_lut_tbl = {0xf, 0xffff, 0x0},
352 	.safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
353 	.qos_lut_tbl = {
354 		{.nentry = ARRAY_SIZE(sm8150_qos_linear),
355 		.entries = sm8150_qos_linear
356 		},
357 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
358 		.entries = sc7180_qos_macrotile
359 		},
360 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
361 		.entries = sc7180_qos_nrt
362 		},
363 		/* TODO: macrotile-qseed is different from macrotile */
364 	},
365 	.cdp_cfg = {
366 		{.rd_enable = 1, .wr_enable = 1},
367 		{.rd_enable = 1, .wr_enable = 0}
368 	},
369 	.clk_inefficiency_factor = 105,
370 	.bw_inefficiency_factor = 120,
371 };
372 
373 static const struct dpu_mdss_version sm8150_mdss_ver = {
374 	.core_major_ver = 5,
375 	.core_minor_ver = 0,
376 };
377 
378 const struct dpu_mdss_cfg dpu_sm8150_cfg = {
379 	.mdss_ver = &sm8150_mdss_ver,
380 	.caps = &sm8150_dpu_caps,
381 	.mdp = &sm8150_mdp,
382 	.ctl_count = ARRAY_SIZE(sm8150_ctl),
383 	.ctl = sm8150_ctl,
384 	.sspp_count = ARRAY_SIZE(sm8150_sspp),
385 	.sspp = sm8150_sspp,
386 	.mixer_count = ARRAY_SIZE(sm8150_lm),
387 	.mixer = sm8150_lm,
388 	.dspp_count = ARRAY_SIZE(sm8150_dspp),
389 	.dspp = sm8150_dspp,
390 	.dsc_count = ARRAY_SIZE(sm8150_dsc),
391 	.dsc = sm8150_dsc,
392 	.pingpong_count = ARRAY_SIZE(sm8150_pp),
393 	.pingpong = sm8150_pp,
394 	.merge_3d_count = ARRAY_SIZE(sm8150_merge_3d),
395 	.merge_3d = sm8150_merge_3d,
396 	.intf_count = ARRAY_SIZE(sm8150_intf),
397 	.intf = sm8150_intf,
398 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
399 	.vbif = sdm845_vbif,
400 	.perf = &sm8150_perf_data,
401 };
402 
403 #endif
404