1 // SPDX-License-Identifier: MIT
2 /*
3 * Copyright © 2020 Intel Corporation
4 */
5
6 #include <drm/drm_atomic_helper.h>
7 #include <drm/drm_blend.h>
8 #include <drm/drm_damage_helper.h>
9 #include <drm/drm_fourcc.h>
10
11 #include "i915_drv.h"
12 #include "i915_reg.h"
13 #include "intel_atomic_plane.h"
14 #include "intel_de.h"
15 #include "intel_display_irq.h"
16 #include "intel_display_types.h"
17 #include "intel_fb.h"
18 #include "intel_fbc.h"
19 #include "intel_psr.h"
20 #include "skl_scaler.h"
21 #include "skl_universal_plane.h"
22 #include "skl_watermark.h"
23 #include "gt/intel_gt.h"
24 #include "pxp/intel_pxp.h"
25
26 static const u32 skl_plane_formats[] = {
27 DRM_FORMAT_C8,
28 DRM_FORMAT_RGB565,
29 DRM_FORMAT_XRGB8888,
30 DRM_FORMAT_XBGR8888,
31 DRM_FORMAT_ARGB8888,
32 DRM_FORMAT_ABGR8888,
33 DRM_FORMAT_XRGB2101010,
34 DRM_FORMAT_XBGR2101010,
35 DRM_FORMAT_XRGB16161616F,
36 DRM_FORMAT_XBGR16161616F,
37 DRM_FORMAT_YUYV,
38 DRM_FORMAT_YVYU,
39 DRM_FORMAT_UYVY,
40 DRM_FORMAT_VYUY,
41 DRM_FORMAT_XYUV8888,
42 };
43
44 static const u32 skl_planar_formats[] = {
45 DRM_FORMAT_C8,
46 DRM_FORMAT_RGB565,
47 DRM_FORMAT_XRGB8888,
48 DRM_FORMAT_XBGR8888,
49 DRM_FORMAT_ARGB8888,
50 DRM_FORMAT_ABGR8888,
51 DRM_FORMAT_XRGB2101010,
52 DRM_FORMAT_XBGR2101010,
53 DRM_FORMAT_XRGB16161616F,
54 DRM_FORMAT_XBGR16161616F,
55 DRM_FORMAT_YUYV,
56 DRM_FORMAT_YVYU,
57 DRM_FORMAT_UYVY,
58 DRM_FORMAT_VYUY,
59 DRM_FORMAT_NV12,
60 DRM_FORMAT_XYUV8888,
61 };
62
63 static const u32 glk_planar_formats[] = {
64 DRM_FORMAT_C8,
65 DRM_FORMAT_RGB565,
66 DRM_FORMAT_XRGB8888,
67 DRM_FORMAT_XBGR8888,
68 DRM_FORMAT_ARGB8888,
69 DRM_FORMAT_ABGR8888,
70 DRM_FORMAT_XRGB2101010,
71 DRM_FORMAT_XBGR2101010,
72 DRM_FORMAT_XRGB16161616F,
73 DRM_FORMAT_XBGR16161616F,
74 DRM_FORMAT_YUYV,
75 DRM_FORMAT_YVYU,
76 DRM_FORMAT_UYVY,
77 DRM_FORMAT_VYUY,
78 DRM_FORMAT_NV12,
79 DRM_FORMAT_XYUV8888,
80 DRM_FORMAT_P010,
81 DRM_FORMAT_P012,
82 DRM_FORMAT_P016,
83 };
84
85 static const u32 icl_sdr_y_plane_formats[] = {
86 DRM_FORMAT_C8,
87 DRM_FORMAT_RGB565,
88 DRM_FORMAT_XRGB8888,
89 DRM_FORMAT_XBGR8888,
90 DRM_FORMAT_ARGB8888,
91 DRM_FORMAT_ABGR8888,
92 DRM_FORMAT_XRGB2101010,
93 DRM_FORMAT_XBGR2101010,
94 DRM_FORMAT_ARGB2101010,
95 DRM_FORMAT_ABGR2101010,
96 DRM_FORMAT_YUYV,
97 DRM_FORMAT_YVYU,
98 DRM_FORMAT_UYVY,
99 DRM_FORMAT_VYUY,
100 DRM_FORMAT_Y210,
101 DRM_FORMAT_Y212,
102 DRM_FORMAT_Y216,
103 DRM_FORMAT_XYUV8888,
104 DRM_FORMAT_XVYU2101010,
105 };
106
107 static const u32 icl_sdr_uv_plane_formats[] = {
108 DRM_FORMAT_C8,
109 DRM_FORMAT_RGB565,
110 DRM_FORMAT_XRGB8888,
111 DRM_FORMAT_XBGR8888,
112 DRM_FORMAT_ARGB8888,
113 DRM_FORMAT_ABGR8888,
114 DRM_FORMAT_XRGB2101010,
115 DRM_FORMAT_XBGR2101010,
116 DRM_FORMAT_ARGB2101010,
117 DRM_FORMAT_ABGR2101010,
118 DRM_FORMAT_YUYV,
119 DRM_FORMAT_YVYU,
120 DRM_FORMAT_UYVY,
121 DRM_FORMAT_VYUY,
122 DRM_FORMAT_NV12,
123 DRM_FORMAT_P010,
124 DRM_FORMAT_P012,
125 DRM_FORMAT_P016,
126 DRM_FORMAT_Y210,
127 DRM_FORMAT_Y212,
128 DRM_FORMAT_Y216,
129 DRM_FORMAT_XYUV8888,
130 DRM_FORMAT_XVYU2101010,
131 };
132
133 static const u32 icl_hdr_plane_formats[] = {
134 DRM_FORMAT_C8,
135 DRM_FORMAT_RGB565,
136 DRM_FORMAT_XRGB8888,
137 DRM_FORMAT_XBGR8888,
138 DRM_FORMAT_ARGB8888,
139 DRM_FORMAT_ABGR8888,
140 DRM_FORMAT_XRGB2101010,
141 DRM_FORMAT_XBGR2101010,
142 DRM_FORMAT_ARGB2101010,
143 DRM_FORMAT_ABGR2101010,
144 DRM_FORMAT_XRGB16161616F,
145 DRM_FORMAT_XBGR16161616F,
146 DRM_FORMAT_ARGB16161616F,
147 DRM_FORMAT_ABGR16161616F,
148 DRM_FORMAT_YUYV,
149 DRM_FORMAT_YVYU,
150 DRM_FORMAT_UYVY,
151 DRM_FORMAT_VYUY,
152 DRM_FORMAT_NV12,
153 DRM_FORMAT_P010,
154 DRM_FORMAT_P012,
155 DRM_FORMAT_P016,
156 DRM_FORMAT_Y210,
157 DRM_FORMAT_Y212,
158 DRM_FORMAT_Y216,
159 DRM_FORMAT_XYUV8888,
160 DRM_FORMAT_XVYU2101010,
161 DRM_FORMAT_XVYU12_16161616,
162 DRM_FORMAT_XVYU16161616,
163 };
164
skl_format_to_fourcc(int format,bool rgb_order,bool alpha)165 int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
166 {
167 switch (format) {
168 case PLANE_CTL_FORMAT_RGB_565:
169 return DRM_FORMAT_RGB565;
170 case PLANE_CTL_FORMAT_NV12:
171 return DRM_FORMAT_NV12;
172 case PLANE_CTL_FORMAT_XYUV:
173 return DRM_FORMAT_XYUV8888;
174 case PLANE_CTL_FORMAT_P010:
175 return DRM_FORMAT_P010;
176 case PLANE_CTL_FORMAT_P012:
177 return DRM_FORMAT_P012;
178 case PLANE_CTL_FORMAT_P016:
179 return DRM_FORMAT_P016;
180 case PLANE_CTL_FORMAT_Y210:
181 return DRM_FORMAT_Y210;
182 case PLANE_CTL_FORMAT_Y212:
183 return DRM_FORMAT_Y212;
184 case PLANE_CTL_FORMAT_Y216:
185 return DRM_FORMAT_Y216;
186 case PLANE_CTL_FORMAT_Y410:
187 return DRM_FORMAT_XVYU2101010;
188 case PLANE_CTL_FORMAT_Y412:
189 return DRM_FORMAT_XVYU12_16161616;
190 case PLANE_CTL_FORMAT_Y416:
191 return DRM_FORMAT_XVYU16161616;
192 default:
193 case PLANE_CTL_FORMAT_XRGB_8888:
194 if (rgb_order) {
195 if (alpha)
196 return DRM_FORMAT_ABGR8888;
197 else
198 return DRM_FORMAT_XBGR8888;
199 } else {
200 if (alpha)
201 return DRM_FORMAT_ARGB8888;
202 else
203 return DRM_FORMAT_XRGB8888;
204 }
205 case PLANE_CTL_FORMAT_XRGB_2101010:
206 if (rgb_order) {
207 if (alpha)
208 return DRM_FORMAT_ABGR2101010;
209 else
210 return DRM_FORMAT_XBGR2101010;
211 } else {
212 if (alpha)
213 return DRM_FORMAT_ARGB2101010;
214 else
215 return DRM_FORMAT_XRGB2101010;
216 }
217 case PLANE_CTL_FORMAT_XRGB_16161616F:
218 if (rgb_order) {
219 if (alpha)
220 return DRM_FORMAT_ABGR16161616F;
221 else
222 return DRM_FORMAT_XBGR16161616F;
223 } else {
224 if (alpha)
225 return DRM_FORMAT_ARGB16161616F;
226 else
227 return DRM_FORMAT_XRGB16161616F;
228 }
229 }
230 }
231
icl_nv12_y_plane_mask(struct drm_i915_private * i915)232 static u8 icl_nv12_y_plane_mask(struct drm_i915_private *i915)
233 {
234 if (DISPLAY_VER(i915) >= 13 || HAS_D12_PLANE_MINIMIZATION(i915))
235 return BIT(PLANE_SPRITE2) | BIT(PLANE_SPRITE3);
236 else
237 return BIT(PLANE_SPRITE4) | BIT(PLANE_SPRITE5);
238 }
239
icl_is_nv12_y_plane(struct drm_i915_private * dev_priv,enum plane_id plane_id)240 bool icl_is_nv12_y_plane(struct drm_i915_private *dev_priv,
241 enum plane_id plane_id)
242 {
243 return DISPLAY_VER(dev_priv) >= 11 &&
244 icl_nv12_y_plane_mask(dev_priv) & BIT(plane_id);
245 }
246
icl_hdr_plane_mask(void)247 u8 icl_hdr_plane_mask(void)
248 {
249 return BIT(PLANE_PRIMARY) | BIT(PLANE_SPRITE0) | BIT(PLANE_SPRITE1);
250 }
251
icl_is_hdr_plane(struct drm_i915_private * dev_priv,enum plane_id plane_id)252 bool icl_is_hdr_plane(struct drm_i915_private *dev_priv, enum plane_id plane_id)
253 {
254 return DISPLAY_VER(dev_priv) >= 11 &&
255 icl_hdr_plane_mask() & BIT(plane_id);
256 }
257
icl_plane_min_cdclk(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)258 static int icl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
259 const struct intel_plane_state *plane_state)
260 {
261 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
262
263 /* two pixels per clock */
264 return DIV_ROUND_UP(pixel_rate, 2);
265 }
266
267 static void
glk_plane_ratio(const struct intel_plane_state * plane_state,unsigned int * num,unsigned int * den)268 glk_plane_ratio(const struct intel_plane_state *plane_state,
269 unsigned int *num, unsigned int *den)
270 {
271 const struct drm_framebuffer *fb = plane_state->hw.fb;
272
273 if (fb->format->cpp[0] == 8) {
274 *num = 10;
275 *den = 8;
276 } else {
277 *num = 1;
278 *den = 1;
279 }
280 }
281
glk_plane_min_cdclk(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)282 static int glk_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
283 const struct intel_plane_state *plane_state)
284 {
285 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
286 unsigned int num, den;
287
288 glk_plane_ratio(plane_state, &num, &den);
289
290 /* two pixels per clock */
291 return DIV_ROUND_UP(pixel_rate * num, 2 * den);
292 }
293
294 static void
skl_plane_ratio(const struct intel_plane_state * plane_state,unsigned int * num,unsigned int * den)295 skl_plane_ratio(const struct intel_plane_state *plane_state,
296 unsigned int *num, unsigned int *den)
297 {
298 const struct drm_framebuffer *fb = plane_state->hw.fb;
299
300 if (fb->format->cpp[0] == 8) {
301 *num = 9;
302 *den = 8;
303 } else {
304 *num = 1;
305 *den = 1;
306 }
307 }
308
skl_plane_min_cdclk(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)309 static int skl_plane_min_cdclk(const struct intel_crtc_state *crtc_state,
310 const struct intel_plane_state *plane_state)
311 {
312 unsigned int pixel_rate = intel_plane_pixel_rate(crtc_state, plane_state);
313 unsigned int num, den;
314
315 skl_plane_ratio(plane_state, &num, &den);
316
317 return DIV_ROUND_UP(pixel_rate * num, den);
318 }
319
skl_plane_max_width(const struct drm_framebuffer * fb,int color_plane,unsigned int rotation)320 static int skl_plane_max_width(const struct drm_framebuffer *fb,
321 int color_plane,
322 unsigned int rotation)
323 {
324 int cpp = fb->format->cpp[color_plane];
325
326 switch (fb->modifier) {
327 case DRM_FORMAT_MOD_LINEAR:
328 case I915_FORMAT_MOD_X_TILED:
329 /*
330 * Validated limit is 4k, but has 5k should
331 * work apart from the following features:
332 * - Ytile (already limited to 4k)
333 * - FP16 (already limited to 4k)
334 * - render compression (already limited to 4k)
335 * - KVMR sprite and cursor (don't care)
336 * - horizontal panning (TODO verify this)
337 * - pipe and plane scaling (TODO verify this)
338 */
339 if (cpp == 8)
340 return 4096;
341 else
342 return 5120;
343 case I915_FORMAT_MOD_Y_TILED_CCS:
344 case I915_FORMAT_MOD_Yf_TILED_CCS:
345 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
346 /* FIXME AUX plane? */
347 case I915_FORMAT_MOD_Y_TILED:
348 case I915_FORMAT_MOD_Yf_TILED:
349 if (cpp == 8)
350 return 2048;
351 else
352 return 4096;
353 default:
354 MISSING_CASE(fb->modifier);
355 return 2048;
356 }
357 }
358
glk_plane_max_width(const struct drm_framebuffer * fb,int color_plane,unsigned int rotation)359 static int glk_plane_max_width(const struct drm_framebuffer *fb,
360 int color_plane,
361 unsigned int rotation)
362 {
363 int cpp = fb->format->cpp[color_plane];
364
365 switch (fb->modifier) {
366 case DRM_FORMAT_MOD_LINEAR:
367 case I915_FORMAT_MOD_X_TILED:
368 if (cpp == 8)
369 return 4096;
370 else
371 return 5120;
372 case I915_FORMAT_MOD_Y_TILED_CCS:
373 case I915_FORMAT_MOD_Yf_TILED_CCS:
374 /* FIXME AUX plane? */
375 case I915_FORMAT_MOD_Y_TILED:
376 case I915_FORMAT_MOD_Yf_TILED:
377 if (cpp == 8)
378 return 2048;
379 else
380 return 5120;
381 default:
382 MISSING_CASE(fb->modifier);
383 return 2048;
384 }
385 }
386
icl_plane_min_width(const struct drm_framebuffer * fb,int color_plane,unsigned int rotation)387 static int icl_plane_min_width(const struct drm_framebuffer *fb,
388 int color_plane,
389 unsigned int rotation)
390 {
391 /* Wa_14011264657, Wa_14011050563: gen11+ */
392 switch (fb->format->format) {
393 case DRM_FORMAT_C8:
394 return 18;
395 case DRM_FORMAT_RGB565:
396 return 10;
397 case DRM_FORMAT_XRGB8888:
398 case DRM_FORMAT_XBGR8888:
399 case DRM_FORMAT_ARGB8888:
400 case DRM_FORMAT_ABGR8888:
401 case DRM_FORMAT_XRGB2101010:
402 case DRM_FORMAT_XBGR2101010:
403 case DRM_FORMAT_ARGB2101010:
404 case DRM_FORMAT_ABGR2101010:
405 case DRM_FORMAT_XVYU2101010:
406 case DRM_FORMAT_Y212:
407 case DRM_FORMAT_Y216:
408 return 6;
409 case DRM_FORMAT_NV12:
410 return 20;
411 case DRM_FORMAT_P010:
412 case DRM_FORMAT_P012:
413 case DRM_FORMAT_P016:
414 return 12;
415 case DRM_FORMAT_XRGB16161616F:
416 case DRM_FORMAT_XBGR16161616F:
417 case DRM_FORMAT_ARGB16161616F:
418 case DRM_FORMAT_ABGR16161616F:
419 case DRM_FORMAT_XVYU12_16161616:
420 case DRM_FORMAT_XVYU16161616:
421 return 4;
422 default:
423 return 1;
424 }
425 }
426
icl_hdr_plane_max_width(const struct drm_framebuffer * fb,int color_plane,unsigned int rotation)427 static int icl_hdr_plane_max_width(const struct drm_framebuffer *fb,
428 int color_plane,
429 unsigned int rotation)
430 {
431 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
432 return 4096;
433 else
434 return 5120;
435 }
436
icl_sdr_plane_max_width(const struct drm_framebuffer * fb,int color_plane,unsigned int rotation)437 static int icl_sdr_plane_max_width(const struct drm_framebuffer *fb,
438 int color_plane,
439 unsigned int rotation)
440 {
441 return 5120;
442 }
443
skl_plane_max_height(const struct drm_framebuffer * fb,int color_plane,unsigned int rotation)444 static int skl_plane_max_height(const struct drm_framebuffer *fb,
445 int color_plane,
446 unsigned int rotation)
447 {
448 return 4096;
449 }
450
icl_plane_max_height(const struct drm_framebuffer * fb,int color_plane,unsigned int rotation)451 static int icl_plane_max_height(const struct drm_framebuffer *fb,
452 int color_plane,
453 unsigned int rotation)
454 {
455 return 4320;
456 }
457
458 static unsigned int
skl_plane_max_stride(struct intel_plane * plane,u32 pixel_format,u64 modifier,unsigned int rotation)459 skl_plane_max_stride(struct intel_plane *plane,
460 u32 pixel_format, u64 modifier,
461 unsigned int rotation)
462 {
463 struct drm_i915_private *i915 = to_i915(plane->base.dev);
464 const struct drm_format_info *info = drm_format_info(pixel_format);
465 int cpp = info->cpp[0];
466 int max_horizontal_pixels = 8192;
467 int max_stride_bytes;
468
469 if (DISPLAY_VER(i915) >= 13) {
470 /*
471 * The stride in bytes must not exceed of the size
472 * of 128K bytes. For pixel formats of 64bpp will allow
473 * for a 16K pixel surface.
474 */
475 max_stride_bytes = 131072;
476 if (cpp == 8)
477 max_horizontal_pixels = 16384;
478 else
479 max_horizontal_pixels = 65536;
480 } else {
481 /*
482 * "The stride in bytes must not exceed the
483 * of the size of 8K pixels and 32K bytes."
484 */
485 max_stride_bytes = 32768;
486 }
487
488 if (drm_rotation_90_or_270(rotation))
489 return min(max_horizontal_pixels, max_stride_bytes / cpp);
490 else
491 return min(max_horizontal_pixels * cpp, max_stride_bytes);
492 }
493
494
495 /* Preoffset values for YUV to RGB Conversion */
496 #define PREOFF_YUV_TO_RGB_HI 0x1800
497 #define PREOFF_YUV_TO_RGB_ME 0x0000
498 #define PREOFF_YUV_TO_RGB_LO 0x1800
499
500 #define ROFF(x) (((x) & 0xffff) << 16)
501 #define GOFF(x) (((x) & 0xffff) << 0)
502 #define BOFF(x) (((x) & 0xffff) << 16)
503
504 /*
505 * Programs the input color space conversion stage for ICL HDR planes.
506 * Note that it is assumed that this stage always happens after YUV
507 * range correction. Thus, the input to this stage is assumed to be
508 * in full-range YCbCr.
509 */
510 static void
icl_program_input_csc(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)511 icl_program_input_csc(struct intel_plane *plane,
512 const struct intel_crtc_state *crtc_state,
513 const struct intel_plane_state *plane_state)
514 {
515 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
516 enum pipe pipe = plane->pipe;
517 enum plane_id plane_id = plane->id;
518
519 static const u16 input_csc_matrix[][9] = {
520 /*
521 * BT.601 full range YCbCr -> full range RGB
522 * The matrix required is :
523 * [1.000, 0.000, 1.371,
524 * 1.000, -0.336, -0.698,
525 * 1.000, 1.732, 0.0000]
526 */
527 [DRM_COLOR_YCBCR_BT601] = {
528 0x7AF8, 0x7800, 0x0,
529 0x8B28, 0x7800, 0x9AC0,
530 0x0, 0x7800, 0x7DD8,
531 },
532 /*
533 * BT.709 full range YCbCr -> full range RGB
534 * The matrix required is :
535 * [1.000, 0.000, 1.574,
536 * 1.000, -0.187, -0.468,
537 * 1.000, 1.855, 0.0000]
538 */
539 [DRM_COLOR_YCBCR_BT709] = {
540 0x7C98, 0x7800, 0x0,
541 0x9EF8, 0x7800, 0xAC00,
542 0x0, 0x7800, 0x7ED8,
543 },
544 /*
545 * BT.2020 full range YCbCr -> full range RGB
546 * The matrix required is :
547 * [1.000, 0.000, 1.474,
548 * 1.000, -0.1645, -0.5713,
549 * 1.000, 1.8814, 0.0000]
550 */
551 [DRM_COLOR_YCBCR_BT2020] = {
552 0x7BC8, 0x7800, 0x0,
553 0x8928, 0x7800, 0xAA88,
554 0x0, 0x7800, 0x7F10,
555 },
556 };
557 const u16 *csc = input_csc_matrix[plane_state->hw.color_encoding];
558
559 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 0),
560 ROFF(csc[0]) | GOFF(csc[1]));
561 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 1),
562 BOFF(csc[2]));
563 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 2),
564 ROFF(csc[3]) | GOFF(csc[4]));
565 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 3),
566 BOFF(csc[5]));
567 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 4),
568 ROFF(csc[6]) | GOFF(csc[7]));
569 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_COEFF(pipe, plane_id, 5),
570 BOFF(csc[8]));
571
572 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 0),
573 PREOFF_YUV_TO_RGB_HI);
574 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 1),
575 PREOFF_YUV_TO_RGB_ME);
576 intel_de_write_fw(dev_priv, PLANE_INPUT_CSC_PREOFF(pipe, plane_id, 2),
577 PREOFF_YUV_TO_RGB_LO);
578 intel_de_write_fw(dev_priv,
579 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 0), 0x0);
580 intel_de_write_fw(dev_priv,
581 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 1), 0x0);
582 intel_de_write_fw(dev_priv,
583 PLANE_INPUT_CSC_POSTOFF(pipe, plane_id, 2), 0x0);
584 }
585
skl_plane_stride_mult(const struct drm_framebuffer * fb,int color_plane,unsigned int rotation)586 static unsigned int skl_plane_stride_mult(const struct drm_framebuffer *fb,
587 int color_plane, unsigned int rotation)
588 {
589 /*
590 * The stride is either expressed as a multiple of 64 bytes chunks for
591 * linear buffers or in number of tiles for tiled buffers.
592 */
593 if (is_surface_linear(fb, color_plane))
594 return 64;
595 else if (drm_rotation_90_or_270(rotation))
596 return intel_tile_height(fb, color_plane);
597 else
598 return intel_tile_width_bytes(fb, color_plane);
599 }
600
skl_plane_stride(const struct intel_plane_state * plane_state,int color_plane)601 static u32 skl_plane_stride(const struct intel_plane_state *plane_state,
602 int color_plane)
603 {
604 const struct drm_framebuffer *fb = plane_state->hw.fb;
605 unsigned int rotation = plane_state->hw.rotation;
606 u32 stride = plane_state->view.color_plane[color_plane].scanout_stride;
607
608 if (color_plane >= fb->format->num_planes)
609 return 0;
610
611 return stride / skl_plane_stride_mult(fb, color_plane, rotation);
612 }
613
614 static void
skl_plane_disable_arm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state)615 skl_plane_disable_arm(struct intel_plane *plane,
616 const struct intel_crtc_state *crtc_state)
617 {
618 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
619 enum plane_id plane_id = plane->id;
620 enum pipe pipe = plane->pipe;
621
622 skl_write_plane_wm(plane, crtc_state);
623
624 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
625 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
626 }
627
628 static void
icl_plane_disable_arm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state)629 icl_plane_disable_arm(struct intel_plane *plane,
630 const struct intel_crtc_state *crtc_state)
631 {
632 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
633 enum plane_id plane_id = plane->id;
634 enum pipe pipe = plane->pipe;
635
636 if (icl_is_hdr_plane(dev_priv, plane_id))
637 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id), 0);
638
639 skl_write_plane_wm(plane, crtc_state);
640
641 intel_psr2_disable_plane_sel_fetch_arm(plane, crtc_state);
642 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), 0);
643 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id), 0);
644 }
645
646 static bool
skl_plane_get_hw_state(struct intel_plane * plane,enum pipe * pipe)647 skl_plane_get_hw_state(struct intel_plane *plane,
648 enum pipe *pipe)
649 {
650 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
651 enum intel_display_power_domain power_domain;
652 enum plane_id plane_id = plane->id;
653 intel_wakeref_t wakeref;
654 bool ret;
655
656 power_domain = POWER_DOMAIN_PIPE(plane->pipe);
657 wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
658 if (!wakeref)
659 return false;
660
661 ret = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane_id)) & PLANE_CTL_ENABLE;
662
663 *pipe = plane->pipe;
664
665 intel_display_power_put(dev_priv, power_domain, wakeref);
666
667 return ret;
668 }
669
skl_plane_ctl_format(u32 pixel_format)670 static u32 skl_plane_ctl_format(u32 pixel_format)
671 {
672 switch (pixel_format) {
673 case DRM_FORMAT_C8:
674 return PLANE_CTL_FORMAT_INDEXED;
675 case DRM_FORMAT_RGB565:
676 return PLANE_CTL_FORMAT_RGB_565;
677 case DRM_FORMAT_XBGR8888:
678 case DRM_FORMAT_ABGR8888:
679 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
680 case DRM_FORMAT_XRGB8888:
681 case DRM_FORMAT_ARGB8888:
682 return PLANE_CTL_FORMAT_XRGB_8888;
683 case DRM_FORMAT_XBGR2101010:
684 case DRM_FORMAT_ABGR2101010:
685 return PLANE_CTL_FORMAT_XRGB_2101010 | PLANE_CTL_ORDER_RGBX;
686 case DRM_FORMAT_XRGB2101010:
687 case DRM_FORMAT_ARGB2101010:
688 return PLANE_CTL_FORMAT_XRGB_2101010;
689 case DRM_FORMAT_XBGR16161616F:
690 case DRM_FORMAT_ABGR16161616F:
691 return PLANE_CTL_FORMAT_XRGB_16161616F | PLANE_CTL_ORDER_RGBX;
692 case DRM_FORMAT_XRGB16161616F:
693 case DRM_FORMAT_ARGB16161616F:
694 return PLANE_CTL_FORMAT_XRGB_16161616F;
695 case DRM_FORMAT_XYUV8888:
696 return PLANE_CTL_FORMAT_XYUV;
697 case DRM_FORMAT_YUYV:
698 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YUYV;
699 case DRM_FORMAT_YVYU:
700 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_YVYU;
701 case DRM_FORMAT_UYVY:
702 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_UYVY;
703 case DRM_FORMAT_VYUY:
704 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_ORDER_VYUY;
705 case DRM_FORMAT_NV12:
706 return PLANE_CTL_FORMAT_NV12;
707 case DRM_FORMAT_P010:
708 return PLANE_CTL_FORMAT_P010;
709 case DRM_FORMAT_P012:
710 return PLANE_CTL_FORMAT_P012;
711 case DRM_FORMAT_P016:
712 return PLANE_CTL_FORMAT_P016;
713 case DRM_FORMAT_Y210:
714 return PLANE_CTL_FORMAT_Y210;
715 case DRM_FORMAT_Y212:
716 return PLANE_CTL_FORMAT_Y212;
717 case DRM_FORMAT_Y216:
718 return PLANE_CTL_FORMAT_Y216;
719 case DRM_FORMAT_XVYU2101010:
720 return PLANE_CTL_FORMAT_Y410;
721 case DRM_FORMAT_XVYU12_16161616:
722 return PLANE_CTL_FORMAT_Y412;
723 case DRM_FORMAT_XVYU16161616:
724 return PLANE_CTL_FORMAT_Y416;
725 default:
726 MISSING_CASE(pixel_format);
727 }
728
729 return 0;
730 }
731
skl_plane_ctl_alpha(const struct intel_plane_state * plane_state)732 static u32 skl_plane_ctl_alpha(const struct intel_plane_state *plane_state)
733 {
734 if (!plane_state->hw.fb->format->has_alpha)
735 return PLANE_CTL_ALPHA_DISABLE;
736
737 switch (plane_state->hw.pixel_blend_mode) {
738 case DRM_MODE_BLEND_PIXEL_NONE:
739 return PLANE_CTL_ALPHA_DISABLE;
740 case DRM_MODE_BLEND_PREMULTI:
741 return PLANE_CTL_ALPHA_SW_PREMULTIPLY;
742 case DRM_MODE_BLEND_COVERAGE:
743 return PLANE_CTL_ALPHA_HW_PREMULTIPLY;
744 default:
745 MISSING_CASE(plane_state->hw.pixel_blend_mode);
746 return PLANE_CTL_ALPHA_DISABLE;
747 }
748 }
749
glk_plane_color_ctl_alpha(const struct intel_plane_state * plane_state)750 static u32 glk_plane_color_ctl_alpha(const struct intel_plane_state *plane_state)
751 {
752 if (!plane_state->hw.fb->format->has_alpha)
753 return PLANE_COLOR_ALPHA_DISABLE;
754
755 switch (plane_state->hw.pixel_blend_mode) {
756 case DRM_MODE_BLEND_PIXEL_NONE:
757 return PLANE_COLOR_ALPHA_DISABLE;
758 case DRM_MODE_BLEND_PREMULTI:
759 return PLANE_COLOR_ALPHA_SW_PREMULTIPLY;
760 case DRM_MODE_BLEND_COVERAGE:
761 return PLANE_COLOR_ALPHA_HW_PREMULTIPLY;
762 default:
763 MISSING_CASE(plane_state->hw.pixel_blend_mode);
764 return PLANE_COLOR_ALPHA_DISABLE;
765 }
766 }
767
skl_plane_ctl_tiling(u64 fb_modifier)768 static u32 skl_plane_ctl_tiling(u64 fb_modifier)
769 {
770 switch (fb_modifier) {
771 case DRM_FORMAT_MOD_LINEAR:
772 break;
773 case I915_FORMAT_MOD_X_TILED:
774 return PLANE_CTL_TILED_X;
775 case I915_FORMAT_MOD_Y_TILED:
776 return PLANE_CTL_TILED_Y;
777 case I915_FORMAT_MOD_4_TILED:
778 return PLANE_CTL_TILED_4;
779 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
780 return PLANE_CTL_TILED_4 |
781 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
782 PLANE_CTL_CLEAR_COLOR_DISABLE;
783 case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
784 return PLANE_CTL_TILED_4 |
785 PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
786 PLANE_CTL_CLEAR_COLOR_DISABLE;
787 case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
788 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
789 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
790 return PLANE_CTL_TILED_4 |
791 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
792 PLANE_CTL_CLEAR_COLOR_DISABLE;
793 case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
794 return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
795 case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
796 return PLANE_CTL_TILED_4 | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
797 case I915_FORMAT_MOD_Y_TILED_CCS:
798 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
799 return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
800 case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
801 return PLANE_CTL_TILED_Y |
802 PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
803 PLANE_CTL_CLEAR_COLOR_DISABLE;
804 case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
805 return PLANE_CTL_TILED_Y | PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE;
806 case I915_FORMAT_MOD_Yf_TILED:
807 return PLANE_CTL_TILED_YF;
808 case I915_FORMAT_MOD_Yf_TILED_CCS:
809 return PLANE_CTL_TILED_YF | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
810 default:
811 MISSING_CASE(fb_modifier);
812 }
813
814 return 0;
815 }
816
skl_plane_ctl_rotate(unsigned int rotate)817 static u32 skl_plane_ctl_rotate(unsigned int rotate)
818 {
819 switch (rotate) {
820 case DRM_MODE_ROTATE_0:
821 break;
822 /*
823 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
824 * while i915 HW rotation is clockwise, thats why this swapping.
825 */
826 case DRM_MODE_ROTATE_90:
827 return PLANE_CTL_ROTATE_270;
828 case DRM_MODE_ROTATE_180:
829 return PLANE_CTL_ROTATE_180;
830 case DRM_MODE_ROTATE_270:
831 return PLANE_CTL_ROTATE_90;
832 default:
833 MISSING_CASE(rotate);
834 }
835
836 return 0;
837 }
838
icl_plane_ctl_flip(unsigned int reflect)839 static u32 icl_plane_ctl_flip(unsigned int reflect)
840 {
841 switch (reflect) {
842 case 0:
843 break;
844 case DRM_MODE_REFLECT_X:
845 return PLANE_CTL_FLIP_HORIZONTAL;
846 case DRM_MODE_REFLECT_Y:
847 default:
848 MISSING_CASE(reflect);
849 }
850
851 return 0;
852 }
853
adlp_plane_ctl_arb_slots(const struct intel_plane_state * plane_state)854 static u32 adlp_plane_ctl_arb_slots(const struct intel_plane_state *plane_state)
855 {
856 const struct drm_framebuffer *fb = plane_state->hw.fb;
857
858 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
859 switch (fb->format->cpp[0]) {
860 case 2:
861 return PLANE_CTL_ARB_SLOTS(1);
862 default:
863 return PLANE_CTL_ARB_SLOTS(0);
864 }
865 } else {
866 switch (fb->format->cpp[0]) {
867 case 8:
868 return PLANE_CTL_ARB_SLOTS(3);
869 case 4:
870 return PLANE_CTL_ARB_SLOTS(1);
871 default:
872 return PLANE_CTL_ARB_SLOTS(0);
873 }
874 }
875 }
876
skl_plane_ctl_crtc(const struct intel_crtc_state * crtc_state)877 static u32 skl_plane_ctl_crtc(const struct intel_crtc_state *crtc_state)
878 {
879 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
880 u32 plane_ctl = 0;
881
882 if (DISPLAY_VER(dev_priv) >= 10)
883 return plane_ctl;
884
885 if (crtc_state->gamma_enable)
886 plane_ctl |= PLANE_CTL_PIPE_GAMMA_ENABLE;
887
888 if (crtc_state->csc_enable)
889 plane_ctl |= PLANE_CTL_PIPE_CSC_ENABLE;
890
891 return plane_ctl;
892 }
893
skl_plane_ctl(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)894 static u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
895 const struct intel_plane_state *plane_state)
896 {
897 struct drm_i915_private *dev_priv =
898 to_i915(plane_state->uapi.plane->dev);
899 const struct drm_framebuffer *fb = plane_state->hw.fb;
900 unsigned int rotation = plane_state->hw.rotation;
901 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
902 u32 plane_ctl;
903
904 plane_ctl = PLANE_CTL_ENABLE;
905
906 if (DISPLAY_VER(dev_priv) < 10) {
907 plane_ctl |= skl_plane_ctl_alpha(plane_state);
908 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
909
910 if (plane_state->hw.color_encoding == DRM_COLOR_YCBCR_BT709)
911 plane_ctl |= PLANE_CTL_YUV_TO_RGB_CSC_FORMAT_BT709;
912
913 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
914 plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
915 }
916
917 plane_ctl |= skl_plane_ctl_format(fb->format->format);
918 plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
919 plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
920
921 if (DISPLAY_VER(dev_priv) >= 11)
922 plane_ctl |= icl_plane_ctl_flip(rotation &
923 DRM_MODE_REFLECT_MASK);
924
925 if (key->flags & I915_SET_COLORKEY_DESTINATION)
926 plane_ctl |= PLANE_CTL_KEY_ENABLE_DESTINATION;
927 else if (key->flags & I915_SET_COLORKEY_SOURCE)
928 plane_ctl |= PLANE_CTL_KEY_ENABLE_SOURCE;
929
930 /* Wa_22012358565:adl-p */
931 if (DISPLAY_VER(dev_priv) == 13)
932 plane_ctl |= adlp_plane_ctl_arb_slots(plane_state);
933
934 return plane_ctl;
935 }
936
glk_plane_color_ctl_crtc(const struct intel_crtc_state * crtc_state)937 static u32 glk_plane_color_ctl_crtc(const struct intel_crtc_state *crtc_state)
938 {
939 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
940 u32 plane_color_ctl = 0;
941
942 if (DISPLAY_VER(dev_priv) >= 11)
943 return plane_color_ctl;
944
945 if (crtc_state->gamma_enable)
946 plane_color_ctl |= PLANE_COLOR_PIPE_GAMMA_ENABLE;
947
948 if (crtc_state->csc_enable)
949 plane_color_ctl |= PLANE_COLOR_PIPE_CSC_ENABLE;
950
951 return plane_color_ctl;
952 }
953
glk_plane_color_ctl(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)954 static u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
955 const struct intel_plane_state *plane_state)
956 {
957 struct drm_i915_private *dev_priv =
958 to_i915(plane_state->uapi.plane->dev);
959 const struct drm_framebuffer *fb = plane_state->hw.fb;
960 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
961 u32 plane_color_ctl = 0;
962
963 plane_color_ctl |= PLANE_COLOR_PLANE_GAMMA_DISABLE;
964 plane_color_ctl |= glk_plane_color_ctl_alpha(plane_state);
965
966 if (fb->format->is_yuv && !icl_is_hdr_plane(dev_priv, plane->id)) {
967 switch (plane_state->hw.color_encoding) {
968 case DRM_COLOR_YCBCR_BT709:
969 plane_color_ctl |= PLANE_COLOR_CSC_MODE_YUV709_TO_RGB709;
970 break;
971 case DRM_COLOR_YCBCR_BT2020:
972 plane_color_ctl |=
973 PLANE_COLOR_CSC_MODE_YUV2020_TO_RGB2020;
974 break;
975 default:
976 plane_color_ctl |=
977 PLANE_COLOR_CSC_MODE_YUV601_TO_RGB601;
978 }
979 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
980 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
981 } else if (fb->format->is_yuv) {
982 plane_color_ctl |= PLANE_COLOR_INPUT_CSC_ENABLE;
983 if (plane_state->hw.color_range == DRM_COLOR_YCBCR_FULL_RANGE)
984 plane_color_ctl |= PLANE_COLOR_YUV_RANGE_CORRECTION_DISABLE;
985 }
986
987 if (plane_state->force_black)
988 plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE;
989
990 return plane_color_ctl;
991 }
992
skl_surf_address(const struct intel_plane_state * plane_state,int color_plane)993 static u32 skl_surf_address(const struct intel_plane_state *plane_state,
994 int color_plane)
995 {
996 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
997 const struct drm_framebuffer *fb = plane_state->hw.fb;
998 u32 offset = plane_state->view.color_plane[color_plane].offset;
999
1000 if (intel_fb_uses_dpt(fb)) {
1001 /*
1002 * The DPT object contains only one vma, so the VMA's offset
1003 * within the DPT is always 0.
1004 */
1005 drm_WARN_ON(&i915->drm, plane_state->dpt_vma->node.start);
1006 drm_WARN_ON(&i915->drm, offset & 0x1fffff);
1007 return offset >> 9;
1008 } else {
1009 drm_WARN_ON(&i915->drm, offset & 0xfff);
1010 return offset;
1011 }
1012 }
1013
skl_plane_surf(const struct intel_plane_state * plane_state,int color_plane)1014 static u32 skl_plane_surf(const struct intel_plane_state *plane_state,
1015 int color_plane)
1016 {
1017 u32 plane_surf;
1018
1019 plane_surf = intel_plane_ggtt_offset(plane_state) +
1020 skl_surf_address(plane_state, color_plane);
1021
1022 if (plane_state->decrypt)
1023 plane_surf |= PLANE_SURF_DECRYPT;
1024
1025 return plane_surf;
1026 }
1027
skl_plane_aux_dist(const struct intel_plane_state * plane_state,int color_plane)1028 static u32 skl_plane_aux_dist(const struct intel_plane_state *plane_state,
1029 int color_plane)
1030 {
1031 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1032 const struct drm_framebuffer *fb = plane_state->hw.fb;
1033 int aux_plane = skl_main_to_aux_plane(fb, color_plane);
1034 u32 aux_dist;
1035
1036 if (!aux_plane)
1037 return 0;
1038
1039 aux_dist = skl_surf_address(plane_state, aux_plane) -
1040 skl_surf_address(plane_state, color_plane);
1041
1042 if (DISPLAY_VER(i915) < 12)
1043 aux_dist |= PLANE_AUX_STRIDE(skl_plane_stride(plane_state, aux_plane));
1044
1045 return aux_dist;
1046 }
1047
skl_plane_keyval(const struct intel_plane_state * plane_state)1048 static u32 skl_plane_keyval(const struct intel_plane_state *plane_state)
1049 {
1050 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1051
1052 return key->min_value;
1053 }
1054
skl_plane_keymax(const struct intel_plane_state * plane_state)1055 static u32 skl_plane_keymax(const struct intel_plane_state *plane_state)
1056 {
1057 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1058 u8 alpha = plane_state->hw.alpha >> 8;
1059
1060 return (key->max_value & 0xffffff) | PLANE_KEYMAX_ALPHA(alpha);
1061 }
1062
skl_plane_keymsk(const struct intel_plane_state * plane_state)1063 static u32 skl_plane_keymsk(const struct intel_plane_state *plane_state)
1064 {
1065 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
1066 u8 alpha = plane_state->hw.alpha >> 8;
1067 u32 keymsk;
1068
1069 keymsk = key->channel_mask & 0x7ffffff;
1070 if (alpha < 0xff)
1071 keymsk |= PLANE_KEYMSK_ALPHA_ENABLE;
1072
1073 return keymsk;
1074 }
1075
icl_plane_csc_load_black(struct intel_plane * plane)1076 static void icl_plane_csc_load_black(struct intel_plane *plane)
1077 {
1078 struct drm_i915_private *i915 = to_i915(plane->base.dev);
1079 enum plane_id plane_id = plane->id;
1080 enum pipe pipe = plane->pipe;
1081
1082 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 0), 0);
1083 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 1), 0);
1084
1085 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 2), 0);
1086 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 3), 0);
1087
1088 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 4), 0);
1089 intel_de_write_fw(i915, PLANE_CSC_COEFF(pipe, plane_id, 5), 0);
1090
1091 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 0), 0);
1092 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 1), 0);
1093 intel_de_write_fw(i915, PLANE_CSC_PREOFF(pipe, plane_id, 2), 0);
1094
1095 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 0), 0);
1096 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 1), 0);
1097 intel_de_write_fw(i915, PLANE_CSC_POSTOFF(pipe, plane_id, 2), 0);
1098 }
1099
icl_plane_color_plane(const struct intel_plane_state * plane_state)1100 static int icl_plane_color_plane(const struct intel_plane_state *plane_state)
1101 {
1102 /* Program the UV plane on planar master */
1103 if (plane_state->planar_linked_plane && !plane_state->planar_slave)
1104 return 1;
1105 else
1106 return 0;
1107 }
1108
1109 static void
skl_plane_update_noarm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)1110 skl_plane_update_noarm(struct intel_plane *plane,
1111 const struct intel_crtc_state *crtc_state,
1112 const struct intel_plane_state *plane_state)
1113 {
1114 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1115 enum plane_id plane_id = plane->id;
1116 enum pipe pipe = plane->pipe;
1117 u32 stride = skl_plane_stride(plane_state, 0);
1118 int crtc_x = plane_state->uapi.dst.x1;
1119 int crtc_y = plane_state->uapi.dst.y1;
1120 u32 src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1121 u32 src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1122
1123 /* The scaler will handle the output position */
1124 if (plane_state->scaler_id >= 0) {
1125 crtc_x = 0;
1126 crtc_y = 0;
1127 }
1128
1129 intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
1130 PLANE_STRIDE_(stride));
1131 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
1132 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
1133 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
1134 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
1135
1136 skl_write_plane_wm(plane, crtc_state);
1137 }
1138
1139 static void
skl_plane_update_arm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)1140 skl_plane_update_arm(struct intel_plane *plane,
1141 const struct intel_crtc_state *crtc_state,
1142 const struct intel_plane_state *plane_state)
1143 {
1144 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1145 enum plane_id plane_id = plane->id;
1146 enum pipe pipe = plane->pipe;
1147 u32 x = plane_state->view.color_plane[0].x;
1148 u32 y = plane_state->view.color_plane[0].y;
1149 u32 plane_ctl, plane_color_ctl = 0;
1150
1151 plane_ctl = plane_state->ctl |
1152 skl_plane_ctl_crtc(crtc_state);
1153
1154 if (DISPLAY_VER(dev_priv) >= 10)
1155 plane_color_ctl = plane_state->color_ctl |
1156 glk_plane_color_ctl_crtc(crtc_state);
1157
1158 intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
1159 intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
1160 intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
1161
1162 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
1163 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
1164
1165 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
1166 skl_plane_aux_dist(plane_state, 0));
1167
1168 intel_de_write_fw(dev_priv, PLANE_AUX_OFFSET(pipe, plane_id),
1169 PLANE_OFFSET_Y(plane_state->view.color_plane[1].y) |
1170 PLANE_OFFSET_X(plane_state->view.color_plane[1].x));
1171
1172 if (DISPLAY_VER(dev_priv) >= 10)
1173 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
1174
1175 /*
1176 * Enable the scaler before the plane so that we don't
1177 * get a catastrophic underrun even if the two operations
1178 * end up happening in two different frames.
1179 *
1180 * TODO: split into noarm+arm pair
1181 */
1182 if (plane_state->scaler_id >= 0)
1183 skl_program_plane_scaler(plane, crtc_state, plane_state);
1184
1185 /*
1186 * The control register self-arms if the plane was previously
1187 * disabled. Try to make the plane enable atomic by writing
1188 * the control register just before the surface register.
1189 */
1190 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
1191 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
1192 skl_plane_surf(plane_state, 0));
1193 }
1194
1195 static void
icl_plane_update_noarm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)1196 icl_plane_update_noarm(struct intel_plane *plane,
1197 const struct intel_crtc_state *crtc_state,
1198 const struct intel_plane_state *plane_state)
1199 {
1200 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1201 enum plane_id plane_id = plane->id;
1202 enum pipe pipe = plane->pipe;
1203 int color_plane = icl_plane_color_plane(plane_state);
1204 u32 stride = skl_plane_stride(plane_state, color_plane);
1205 const struct drm_framebuffer *fb = plane_state->hw.fb;
1206 int crtc_x = plane_state->uapi.dst.x1;
1207 int crtc_y = plane_state->uapi.dst.y1;
1208 int x = plane_state->view.color_plane[color_plane].x;
1209 int y = plane_state->view.color_plane[color_plane].y;
1210 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1211 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
1212 u32 plane_color_ctl;
1213
1214 plane_color_ctl = plane_state->color_ctl |
1215 glk_plane_color_ctl_crtc(crtc_state);
1216
1217 /* The scaler will handle the output position */
1218 if (plane_state->scaler_id >= 0) {
1219 crtc_x = 0;
1220 crtc_y = 0;
1221 }
1222
1223 intel_de_write_fw(dev_priv, PLANE_STRIDE(pipe, plane_id),
1224 PLANE_STRIDE_(stride));
1225 intel_de_write_fw(dev_priv, PLANE_POS(pipe, plane_id),
1226 PLANE_POS_Y(crtc_y) | PLANE_POS_X(crtc_x));
1227 intel_de_write_fw(dev_priv, PLANE_SIZE(pipe, plane_id),
1228 PLANE_HEIGHT(src_h - 1) | PLANE_WIDTH(src_w - 1));
1229
1230 intel_de_write_fw(dev_priv, PLANE_KEYVAL(pipe, plane_id), skl_plane_keyval(plane_state));
1231 intel_de_write_fw(dev_priv, PLANE_KEYMSK(pipe, plane_id), skl_plane_keymsk(plane_state));
1232 intel_de_write_fw(dev_priv, PLANE_KEYMAX(pipe, plane_id), skl_plane_keymax(plane_state));
1233
1234 intel_de_write_fw(dev_priv, PLANE_OFFSET(pipe, plane_id),
1235 PLANE_OFFSET_Y(y) | PLANE_OFFSET_X(x));
1236
1237 if (intel_fb_is_rc_ccs_cc_modifier(fb->modifier)) {
1238 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 0),
1239 lower_32_bits(plane_state->ccval));
1240 intel_de_write_fw(dev_priv, PLANE_CC_VAL(pipe, plane_id, 1),
1241 upper_32_bits(plane_state->ccval));
1242 }
1243
1244 /* FLAT CCS doesn't need to program AUX_DIST */
1245 if (!HAS_FLAT_CCS(dev_priv))
1246 intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
1247 skl_plane_aux_dist(plane_state, color_plane));
1248
1249 if (icl_is_hdr_plane(dev_priv, plane_id))
1250 intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
1251 plane_state->cus_ctl);
1252
1253 intel_de_write_fw(dev_priv, PLANE_COLOR_CTL(pipe, plane_id), plane_color_ctl);
1254
1255 if (fb->format->is_yuv && icl_is_hdr_plane(dev_priv, plane_id))
1256 icl_program_input_csc(plane, crtc_state, plane_state);
1257
1258 skl_write_plane_wm(plane, crtc_state);
1259
1260 /*
1261 * FIXME: pxp session invalidation can hit any time even at time of commit
1262 * or after the commit, display content will be garbage.
1263 */
1264 if (plane_state->force_black)
1265 icl_plane_csc_load_black(plane);
1266
1267 intel_psr2_program_plane_sel_fetch_noarm(plane, crtc_state, plane_state, color_plane);
1268 }
1269
1270 static void
icl_plane_update_arm(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)1271 icl_plane_update_arm(struct intel_plane *plane,
1272 const struct intel_crtc_state *crtc_state,
1273 const struct intel_plane_state *plane_state)
1274 {
1275 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1276 enum plane_id plane_id = plane->id;
1277 enum pipe pipe = plane->pipe;
1278 int color_plane = icl_plane_color_plane(plane_state);
1279 u32 plane_ctl;
1280
1281 plane_ctl = plane_state->ctl |
1282 skl_plane_ctl_crtc(crtc_state);
1283
1284 /*
1285 * Enable the scaler before the plane so that we don't
1286 * get a catastrophic underrun even if the two operations
1287 * end up happening in two different frames.
1288 *
1289 * TODO: split into noarm+arm pair
1290 */
1291 if (plane_state->scaler_id >= 0)
1292 skl_program_plane_scaler(plane, crtc_state, plane_state);
1293
1294 intel_psr2_program_plane_sel_fetch_arm(plane, crtc_state, plane_state);
1295
1296 /*
1297 * The control register self-arms if the plane was previously
1298 * disabled. Try to make the plane enable atomic by writing
1299 * the control register just before the surface register.
1300 */
1301 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
1302 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
1303 skl_plane_surf(plane_state, color_plane));
1304 }
1305
1306 static void
skl_plane_async_flip(struct intel_plane * plane,const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state,bool async_flip)1307 skl_plane_async_flip(struct intel_plane *plane,
1308 const struct intel_crtc_state *crtc_state,
1309 const struct intel_plane_state *plane_state,
1310 bool async_flip)
1311 {
1312 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1313 enum plane_id plane_id = plane->id;
1314 enum pipe pipe = plane->pipe;
1315 u32 plane_ctl = plane_state->ctl;
1316
1317 plane_ctl |= skl_plane_ctl_crtc(crtc_state);
1318
1319 if (async_flip)
1320 plane_ctl |= PLANE_CTL_ASYNC_FLIP;
1321
1322 intel_de_write_fw(dev_priv, PLANE_CTL(pipe, plane_id), plane_ctl);
1323 intel_de_write_fw(dev_priv, PLANE_SURF(pipe, plane_id),
1324 skl_plane_surf(plane_state, 0));
1325 }
1326
intel_format_is_p01x(u32 format)1327 static bool intel_format_is_p01x(u32 format)
1328 {
1329 switch (format) {
1330 case DRM_FORMAT_P010:
1331 case DRM_FORMAT_P012:
1332 case DRM_FORMAT_P016:
1333 return true;
1334 default:
1335 return false;
1336 }
1337 }
1338
skl_plane_check_fb(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)1339 static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
1340 const struct intel_plane_state *plane_state)
1341 {
1342 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1343 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1344 const struct drm_framebuffer *fb = plane_state->hw.fb;
1345 unsigned int rotation = plane_state->hw.rotation;
1346
1347 if (!fb)
1348 return 0;
1349
1350 if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
1351 intel_fb_is_ccs_modifier(fb->modifier)) {
1352 drm_dbg_kms(&dev_priv->drm,
1353 "RC support only with 0/180 degree rotation (%x)\n",
1354 rotation);
1355 return -EINVAL;
1356 }
1357
1358 if (rotation & DRM_MODE_REFLECT_X &&
1359 fb->modifier == DRM_FORMAT_MOD_LINEAR) {
1360 drm_dbg_kms(&dev_priv->drm,
1361 "horizontal flip is not supported with linear surface formats\n");
1362 return -EINVAL;
1363 }
1364
1365 if (drm_rotation_90_or_270(rotation)) {
1366 if (!intel_fb_supports_90_270_rotation(to_intel_framebuffer(fb))) {
1367 drm_dbg_kms(&dev_priv->drm,
1368 "Y/Yf tiling required for 90/270!\n");
1369 return -EINVAL;
1370 }
1371
1372 /*
1373 * 90/270 is not allowed with RGB64 16:16:16:16 and
1374 * Indexed 8-bit. RGB 16-bit 5:6:5 is allowed gen11 onwards.
1375 */
1376 switch (fb->format->format) {
1377 case DRM_FORMAT_RGB565:
1378 if (DISPLAY_VER(dev_priv) >= 11)
1379 break;
1380 fallthrough;
1381 case DRM_FORMAT_C8:
1382 case DRM_FORMAT_XRGB16161616F:
1383 case DRM_FORMAT_XBGR16161616F:
1384 case DRM_FORMAT_ARGB16161616F:
1385 case DRM_FORMAT_ABGR16161616F:
1386 case DRM_FORMAT_Y210:
1387 case DRM_FORMAT_Y212:
1388 case DRM_FORMAT_Y216:
1389 case DRM_FORMAT_XVYU12_16161616:
1390 case DRM_FORMAT_XVYU16161616:
1391 drm_dbg_kms(&dev_priv->drm,
1392 "Unsupported pixel format %p4cc for 90/270!\n",
1393 &fb->format->format);
1394 return -EINVAL;
1395 default:
1396 break;
1397 }
1398 }
1399
1400 /* Y-tiling is not supported in IF-ID Interlace mode */
1401 if (crtc_state->hw.enable &&
1402 crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
1403 fb->modifier != DRM_FORMAT_MOD_LINEAR &&
1404 fb->modifier != I915_FORMAT_MOD_X_TILED) {
1405 drm_dbg_kms(&dev_priv->drm,
1406 "Y/Yf tiling not supported in IF-ID mode\n");
1407 return -EINVAL;
1408 }
1409
1410 /* Wa_1606054188:tgl,adl-s */
1411 if ((IS_ALDERLAKE_S(dev_priv) || IS_TIGERLAKE(dev_priv)) &&
1412 plane_state->ckey.flags & I915_SET_COLORKEY_SOURCE &&
1413 intel_format_is_p01x(fb->format->format)) {
1414 drm_dbg_kms(&dev_priv->drm,
1415 "Source color keying not supported with P01x formats\n");
1416 return -EINVAL;
1417 }
1418
1419 return 0;
1420 }
1421
skl_plane_check_dst_coordinates(const struct intel_crtc_state * crtc_state,const struct intel_plane_state * plane_state)1422 static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
1423 const struct intel_plane_state *plane_state)
1424 {
1425 struct drm_i915_private *dev_priv =
1426 to_i915(plane_state->uapi.plane->dev);
1427 int crtc_x = plane_state->uapi.dst.x1;
1428 int crtc_w = drm_rect_width(&plane_state->uapi.dst);
1429 int pipe_src_w = drm_rect_width(&crtc_state->pipe_src);
1430
1431 /*
1432 * Display WA #1175: glk
1433 * Planes other than the cursor may cause FIFO underflow and display
1434 * corruption if starting less than 4 pixels from the right edge of
1435 * the screen.
1436 * Besides the above WA fix the similar problem, where planes other
1437 * than the cursor ending less than 4 pixels from the left edge of the
1438 * screen may cause FIFO underflow and display corruption.
1439 */
1440 if (DISPLAY_VER(dev_priv) == 10 &&
1441 (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
1442 drm_dbg_kms(&dev_priv->drm,
1443 "requested plane X %s position %d invalid (valid range %d-%d)\n",
1444 crtc_x + crtc_w < 4 ? "end" : "start",
1445 crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
1446 4, pipe_src_w - 4);
1447 return -ERANGE;
1448 }
1449
1450 return 0;
1451 }
1452
skl_plane_check_nv12_rotation(const struct intel_plane_state * plane_state)1453 static int skl_plane_check_nv12_rotation(const struct intel_plane_state *plane_state)
1454 {
1455 struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
1456 const struct drm_framebuffer *fb = plane_state->hw.fb;
1457 unsigned int rotation = plane_state->hw.rotation;
1458 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
1459
1460 /* Display WA #1106 */
1461 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
1462 src_w & 3 &&
1463 (rotation == DRM_MODE_ROTATE_270 ||
1464 rotation == (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90))) {
1465 drm_dbg_kms(&i915->drm, "src width must be multiple of 4 for rotated planar YUV\n");
1466 return -EINVAL;
1467 }
1468
1469 return 0;
1470 }
1471
skl_plane_max_scale(struct drm_i915_private * dev_priv,const struct drm_framebuffer * fb)1472 static int skl_plane_max_scale(struct drm_i915_private *dev_priv,
1473 const struct drm_framebuffer *fb)
1474 {
1475 /*
1476 * We don't yet know the final source width nor
1477 * whether we can use the HQ scaler mode. Assume
1478 * the best case.
1479 * FIXME need to properly check this later.
1480 */
1481 if (DISPLAY_VER(dev_priv) >= 10 ||
1482 !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
1483 return 0x30000 - 1;
1484 else
1485 return 0x20000 - 1;
1486 }
1487
intel_plane_min_width(struct intel_plane * plane,const struct drm_framebuffer * fb,int color_plane,unsigned int rotation)1488 static int intel_plane_min_width(struct intel_plane *plane,
1489 const struct drm_framebuffer *fb,
1490 int color_plane,
1491 unsigned int rotation)
1492 {
1493 if (plane->min_width)
1494 return plane->min_width(fb, color_plane, rotation);
1495 else
1496 return 1;
1497 }
1498
intel_plane_max_width(struct intel_plane * plane,const struct drm_framebuffer * fb,int color_plane,unsigned int rotation)1499 static int intel_plane_max_width(struct intel_plane *plane,
1500 const struct drm_framebuffer *fb,
1501 int color_plane,
1502 unsigned int rotation)
1503 {
1504 if (plane->max_width)
1505 return plane->max_width(fb, color_plane, rotation);
1506 else
1507 return INT_MAX;
1508 }
1509
intel_plane_max_height(struct intel_plane * plane,const struct drm_framebuffer * fb,int color_plane,unsigned int rotation)1510 static int intel_plane_max_height(struct intel_plane *plane,
1511 const struct drm_framebuffer *fb,
1512 int color_plane,
1513 unsigned int rotation)
1514 {
1515 if (plane->max_height)
1516 return plane->max_height(fb, color_plane, rotation);
1517 else
1518 return INT_MAX;
1519 }
1520
1521 static bool
skl_check_main_ccs_coordinates(struct intel_plane_state * plane_state,int main_x,int main_y,u32 main_offset,int ccs_plane)1522 skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state,
1523 int main_x, int main_y, u32 main_offset,
1524 int ccs_plane)
1525 {
1526 const struct drm_framebuffer *fb = plane_state->hw.fb;
1527 int aux_x = plane_state->view.color_plane[ccs_plane].x;
1528 int aux_y = plane_state->view.color_plane[ccs_plane].y;
1529 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
1530 u32 alignment = intel_surf_alignment(fb, ccs_plane);
1531 int hsub;
1532 int vsub;
1533
1534 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1535 while (aux_offset >= main_offset && aux_y <= main_y) {
1536 int x, y;
1537
1538 if (aux_x == main_x && aux_y == main_y)
1539 break;
1540
1541 if (aux_offset == 0)
1542 break;
1543
1544 x = aux_x / hsub;
1545 y = aux_y / vsub;
1546 aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
1547 plane_state,
1548 ccs_plane,
1549 aux_offset,
1550 aux_offset -
1551 alignment);
1552 aux_x = x * hsub + aux_x % hsub;
1553 aux_y = y * vsub + aux_y % vsub;
1554 }
1555
1556 if (aux_x != main_x || aux_y != main_y)
1557 return false;
1558
1559 plane_state->view.color_plane[ccs_plane].offset = aux_offset;
1560 plane_state->view.color_plane[ccs_plane].x = aux_x;
1561 plane_state->view.color_plane[ccs_plane].y = aux_y;
1562
1563 return true;
1564 }
1565
1566
skl_calc_main_surface_offset(const struct intel_plane_state * plane_state,int * x,int * y,u32 * offset)1567 int skl_calc_main_surface_offset(const struct intel_plane_state *plane_state,
1568 int *x, int *y, u32 *offset)
1569 {
1570 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1571 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1572 const struct drm_framebuffer *fb = plane_state->hw.fb;
1573 const int aux_plane = skl_main_to_aux_plane(fb, 0);
1574 const u32 aux_offset = plane_state->view.color_plane[aux_plane].offset;
1575 const u32 alignment = intel_surf_alignment(fb, 0);
1576 const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
1577
1578 intel_add_fb_offsets(x, y, plane_state, 0);
1579 *offset = intel_plane_compute_aligned_offset(x, y, plane_state, 0);
1580 if (drm_WARN_ON(&dev_priv->drm, alignment && !is_power_of_2(alignment)))
1581 return -EINVAL;
1582
1583 /*
1584 * AUX surface offset is specified as the distance from the
1585 * main surface offset, and it must be non-negative. Make
1586 * sure that is what we will get.
1587 */
1588 if (aux_plane && *offset > aux_offset)
1589 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
1590 *offset,
1591 aux_offset & ~(alignment - 1));
1592
1593 /*
1594 * When using an X-tiled surface, the plane blows up
1595 * if the x offset + width exceed the stride.
1596 *
1597 * TODO: linear and Y-tiled seem fine, Yf untested,
1598 */
1599 if (fb->modifier == I915_FORMAT_MOD_X_TILED) {
1600 int cpp = fb->format->cpp[0];
1601
1602 while ((*x + w) * cpp > plane_state->view.color_plane[0].mapping_stride) {
1603 if (*offset == 0) {
1604 drm_dbg_kms(&dev_priv->drm,
1605 "Unable to find suitable display surface offset due to X-tiling\n");
1606 return -EINVAL;
1607 }
1608
1609 *offset = intel_plane_adjust_aligned_offset(x, y, plane_state, 0,
1610 *offset,
1611 *offset - alignment);
1612 }
1613 }
1614
1615 return 0;
1616 }
1617
skl_check_main_surface(struct intel_plane_state * plane_state)1618 static int skl_check_main_surface(struct intel_plane_state *plane_state)
1619 {
1620 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1621 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1622 const struct drm_framebuffer *fb = plane_state->hw.fb;
1623 const unsigned int rotation = plane_state->hw.rotation;
1624 int x = plane_state->uapi.src.x1 >> 16;
1625 int y = plane_state->uapi.src.y1 >> 16;
1626 const int w = drm_rect_width(&plane_state->uapi.src) >> 16;
1627 const int h = drm_rect_height(&plane_state->uapi.src) >> 16;
1628 const int min_width = intel_plane_min_width(plane, fb, 0, rotation);
1629 const int max_width = intel_plane_max_width(plane, fb, 0, rotation);
1630 const int max_height = intel_plane_max_height(plane, fb, 0, rotation);
1631 const int aux_plane = skl_main_to_aux_plane(fb, 0);
1632 const u32 alignment = intel_surf_alignment(fb, 0);
1633 u32 offset;
1634 int ret;
1635
1636 if (w > max_width || w < min_width || h > max_height || h < 1) {
1637 drm_dbg_kms(&dev_priv->drm,
1638 "requested Y/RGB source size %dx%d outside limits (min: %dx1 max: %dx%d)\n",
1639 w, h, min_width, max_width, max_height);
1640 return -EINVAL;
1641 }
1642
1643 ret = skl_calc_main_surface_offset(plane_state, &x, &y, &offset);
1644 if (ret)
1645 return ret;
1646
1647 /*
1648 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
1649 * they match with the main surface x/y offsets. On DG2
1650 * there's no aux plane on fb so skip this checking.
1651 */
1652 if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) {
1653 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
1654 offset, aux_plane)) {
1655 if (offset == 0)
1656 break;
1657
1658 offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
1659 offset, offset - alignment);
1660 }
1661
1662 if (x != plane_state->view.color_plane[aux_plane].x ||
1663 y != plane_state->view.color_plane[aux_plane].y) {
1664 drm_dbg_kms(&dev_priv->drm,
1665 "Unable to find suitable display surface offset due to CCS\n");
1666 return -EINVAL;
1667 }
1668 }
1669
1670 if (DISPLAY_VER(dev_priv) >= 13)
1671 drm_WARN_ON(&dev_priv->drm, x > 65535 || y > 65535);
1672 else
1673 drm_WARN_ON(&dev_priv->drm, x > 8191 || y > 8191);
1674
1675 plane_state->view.color_plane[0].offset = offset;
1676 plane_state->view.color_plane[0].x = x;
1677 plane_state->view.color_plane[0].y = y;
1678
1679 /*
1680 * Put the final coordinates back so that the src
1681 * coordinate checks will see the right values.
1682 */
1683 drm_rect_translate_to(&plane_state->uapi.src,
1684 x << 16, y << 16);
1685
1686 return 0;
1687 }
1688
skl_check_nv12_aux_surface(struct intel_plane_state * plane_state)1689 static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
1690 {
1691 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1692 struct drm_i915_private *i915 = to_i915(plane->base.dev);
1693 const struct drm_framebuffer *fb = plane_state->hw.fb;
1694 unsigned int rotation = plane_state->hw.rotation;
1695 int uv_plane = 1;
1696 int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ?
1697 skl_main_to_aux_plane(fb, uv_plane) : 0;
1698 int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);
1699 int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
1700 int x = plane_state->uapi.src.x1 >> 17;
1701 int y = plane_state->uapi.src.y1 >> 17;
1702 int w = drm_rect_width(&plane_state->uapi.src) >> 17;
1703 int h = drm_rect_height(&plane_state->uapi.src) >> 17;
1704 u32 offset;
1705
1706 /* FIXME not quite sure how/if these apply to the chroma plane */
1707 if (w > max_width || h > max_height) {
1708 drm_dbg_kms(&i915->drm,
1709 "CbCr source size %dx%d too big (limit %dx%d)\n",
1710 w, h, max_width, max_height);
1711 return -EINVAL;
1712 }
1713
1714 intel_add_fb_offsets(&x, &y, plane_state, uv_plane);
1715 offset = intel_plane_compute_aligned_offset(&x, &y,
1716 plane_state, uv_plane);
1717
1718 if (ccs_plane) {
1719 u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
1720 u32 alignment = intel_surf_alignment(fb, uv_plane);
1721
1722 if (offset > aux_offset)
1723 offset = intel_plane_adjust_aligned_offset(&x, &y,
1724 plane_state,
1725 uv_plane,
1726 offset,
1727 aux_offset & ~(alignment - 1));
1728
1729 while (!skl_check_main_ccs_coordinates(plane_state, x, y,
1730 offset, ccs_plane)) {
1731 if (offset == 0)
1732 break;
1733
1734 offset = intel_plane_adjust_aligned_offset(&x, &y,
1735 plane_state,
1736 uv_plane,
1737 offset, offset - alignment);
1738 }
1739
1740 if (x != plane_state->view.color_plane[ccs_plane].x ||
1741 y != plane_state->view.color_plane[ccs_plane].y) {
1742 drm_dbg_kms(&i915->drm,
1743 "Unable to find suitable display surface offset due to CCS\n");
1744 return -EINVAL;
1745 }
1746 }
1747
1748 if (DISPLAY_VER(i915) >= 13)
1749 drm_WARN_ON(&i915->drm, x > 65535 || y > 65535);
1750 else
1751 drm_WARN_ON(&i915->drm, x > 8191 || y > 8191);
1752
1753 plane_state->view.color_plane[uv_plane].offset = offset;
1754 plane_state->view.color_plane[uv_plane].x = x;
1755 plane_state->view.color_plane[uv_plane].y = y;
1756
1757 return 0;
1758 }
1759
skl_check_ccs_aux_surface(struct intel_plane_state * plane_state)1760 static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
1761 {
1762 const struct drm_framebuffer *fb = plane_state->hw.fb;
1763 int src_x = plane_state->uapi.src.x1 >> 16;
1764 int src_y = plane_state->uapi.src.y1 >> 16;
1765 u32 offset;
1766 int ccs_plane;
1767
1768 for (ccs_plane = 0; ccs_plane < fb->format->num_planes; ccs_plane++) {
1769 int main_hsub, main_vsub;
1770 int hsub, vsub;
1771 int x, y;
1772
1773 if (!intel_fb_is_ccs_aux_plane(fb, ccs_plane))
1774 continue;
1775
1776 intel_fb_plane_get_subsampling(&main_hsub, &main_vsub, fb,
1777 skl_ccs_to_main_plane(fb, ccs_plane));
1778 intel_fb_plane_get_subsampling(&hsub, &vsub, fb, ccs_plane);
1779
1780 hsub *= main_hsub;
1781 vsub *= main_vsub;
1782 x = src_x / hsub;
1783 y = src_y / vsub;
1784
1785 intel_add_fb_offsets(&x, &y, plane_state, ccs_plane);
1786
1787 offset = intel_plane_compute_aligned_offset(&x, &y,
1788 plane_state,
1789 ccs_plane);
1790
1791 plane_state->view.color_plane[ccs_plane].offset = offset;
1792 plane_state->view.color_plane[ccs_plane].x = (x * hsub + src_x % hsub) / main_hsub;
1793 plane_state->view.color_plane[ccs_plane].y = (y * vsub + src_y % vsub) / main_vsub;
1794 }
1795
1796 return 0;
1797 }
1798
skl_check_plane_surface(struct intel_plane_state * plane_state)1799 static int skl_check_plane_surface(struct intel_plane_state *plane_state)
1800 {
1801 const struct drm_framebuffer *fb = plane_state->hw.fb;
1802 int ret;
1803
1804 ret = intel_plane_compute_gtt(plane_state);
1805 if (ret)
1806 return ret;
1807
1808 if (!plane_state->uapi.visible)
1809 return 0;
1810
1811 /*
1812 * Handle the AUX surface first since the main surface setup depends on
1813 * it.
1814 */
1815 if (intel_fb_is_ccs_modifier(fb->modifier)) {
1816 ret = skl_check_ccs_aux_surface(plane_state);
1817 if (ret)
1818 return ret;
1819 }
1820
1821 if (intel_format_info_is_yuv_semiplanar(fb->format,
1822 fb->modifier)) {
1823 ret = skl_check_nv12_aux_surface(plane_state);
1824 if (ret)
1825 return ret;
1826 }
1827
1828 ret = skl_check_main_surface(plane_state);
1829 if (ret)
1830 return ret;
1831
1832 return 0;
1833 }
1834
skl_fb_scalable(const struct drm_framebuffer * fb)1835 static bool skl_fb_scalable(const struct drm_framebuffer *fb)
1836 {
1837 if (!fb)
1838 return false;
1839
1840 switch (fb->format->format) {
1841 case DRM_FORMAT_C8:
1842 return false;
1843 case DRM_FORMAT_XRGB16161616F:
1844 case DRM_FORMAT_ARGB16161616F:
1845 case DRM_FORMAT_XBGR16161616F:
1846 case DRM_FORMAT_ABGR16161616F:
1847 return DISPLAY_VER(to_i915(fb->dev)) >= 11;
1848 default:
1849 return true;
1850 }
1851 }
1852
bo_has_valid_encryption(struct drm_i915_gem_object * obj)1853 static bool bo_has_valid_encryption(struct drm_i915_gem_object *obj)
1854 {
1855 struct drm_i915_private *i915 = to_i915(obj->base.dev);
1856
1857 return intel_pxp_key_check(i915->pxp, obj, false) == 0;
1858 }
1859
pxp_is_borked(struct drm_i915_gem_object * obj)1860 static bool pxp_is_borked(struct drm_i915_gem_object *obj)
1861 {
1862 return i915_gem_object_is_protected(obj) && !bo_has_valid_encryption(obj);
1863 }
1864
skl_plane_check(struct intel_crtc_state * crtc_state,struct intel_plane_state * plane_state)1865 static int skl_plane_check(struct intel_crtc_state *crtc_state,
1866 struct intel_plane_state *plane_state)
1867 {
1868 struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
1869 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1870 const struct drm_framebuffer *fb = plane_state->hw.fb;
1871 int min_scale = DRM_PLANE_NO_SCALING;
1872 int max_scale = DRM_PLANE_NO_SCALING;
1873 int ret;
1874
1875 ret = skl_plane_check_fb(crtc_state, plane_state);
1876 if (ret)
1877 return ret;
1878
1879 /* use scaler when colorkey is not required */
1880 if (!plane_state->ckey.flags && skl_fb_scalable(fb)) {
1881 min_scale = 1;
1882 max_scale = skl_plane_max_scale(dev_priv, fb);
1883 }
1884
1885 ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
1886 min_scale, max_scale, true);
1887 if (ret)
1888 return ret;
1889
1890 ret = skl_check_plane_surface(plane_state);
1891 if (ret)
1892 return ret;
1893
1894 if (!plane_state->uapi.visible)
1895 return 0;
1896
1897 ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
1898 if (ret)
1899 return ret;
1900
1901 ret = intel_plane_check_src_coordinates(plane_state);
1902 if (ret)
1903 return ret;
1904
1905 ret = skl_plane_check_nv12_rotation(plane_state);
1906 if (ret)
1907 return ret;
1908
1909 if (DISPLAY_VER(dev_priv) >= 11) {
1910 plane_state->decrypt = bo_has_valid_encryption(intel_fb_obj(fb));
1911 plane_state->force_black = pxp_is_borked(intel_fb_obj(fb));
1912 }
1913
1914 /* HW only has 8 bits pixel precision, disable plane if invisible */
1915 if (!(plane_state->hw.alpha >> 8))
1916 plane_state->uapi.visible = false;
1917
1918 plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
1919
1920 if (DISPLAY_VER(dev_priv) >= 10)
1921 plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
1922 plane_state);
1923
1924 if (intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier) &&
1925 icl_is_hdr_plane(dev_priv, plane->id))
1926 /* Enable and use MPEG-2 chroma siting */
1927 plane_state->cus_ctl = PLANE_CUS_ENABLE |
1928 PLANE_CUS_HPHASE_0 |
1929 PLANE_CUS_VPHASE_SIGN_NEGATIVE | PLANE_CUS_VPHASE_0_25;
1930 else
1931 plane_state->cus_ctl = 0;
1932
1933 return 0;
1934 }
1935
skl_fbc_id_for_pipe(enum pipe pipe)1936 static enum intel_fbc_id skl_fbc_id_for_pipe(enum pipe pipe)
1937 {
1938 return pipe - PIPE_A + INTEL_FBC_A;
1939 }
1940
skl_plane_has_fbc(struct drm_i915_private * dev_priv,enum intel_fbc_id fbc_id,enum plane_id plane_id)1941 static bool skl_plane_has_fbc(struct drm_i915_private *dev_priv,
1942 enum intel_fbc_id fbc_id, enum plane_id plane_id)
1943 {
1944 if ((DISPLAY_RUNTIME_INFO(dev_priv)->fbc_mask & BIT(fbc_id)) == 0)
1945 return false;
1946
1947 return plane_id == PLANE_PRIMARY;
1948 }
1949
skl_plane_fbc(struct drm_i915_private * dev_priv,enum pipe pipe,enum plane_id plane_id)1950 static struct intel_fbc *skl_plane_fbc(struct drm_i915_private *dev_priv,
1951 enum pipe pipe, enum plane_id plane_id)
1952 {
1953 enum intel_fbc_id fbc_id = skl_fbc_id_for_pipe(pipe);
1954
1955 if (skl_plane_has_fbc(dev_priv, fbc_id, plane_id))
1956 return dev_priv->display.fbc[fbc_id];
1957 else
1958 return NULL;
1959 }
1960
skl_plane_has_planar(struct drm_i915_private * dev_priv,enum pipe pipe,enum plane_id plane_id)1961 static bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
1962 enum pipe pipe, enum plane_id plane_id)
1963 {
1964 /* Display WA #0870: skl, bxt */
1965 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
1966 return false;
1967
1968 if (DISPLAY_VER(dev_priv) == 9 && pipe == PIPE_C)
1969 return false;
1970
1971 if (plane_id != PLANE_PRIMARY && plane_id != PLANE_SPRITE0)
1972 return false;
1973
1974 return true;
1975 }
1976
skl_get_plane_formats(struct drm_i915_private * dev_priv,enum pipe pipe,enum plane_id plane_id,int * num_formats)1977 static const u32 *skl_get_plane_formats(struct drm_i915_private *dev_priv,
1978 enum pipe pipe, enum plane_id plane_id,
1979 int *num_formats)
1980 {
1981 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
1982 *num_formats = ARRAY_SIZE(skl_planar_formats);
1983 return skl_planar_formats;
1984 } else {
1985 *num_formats = ARRAY_SIZE(skl_plane_formats);
1986 return skl_plane_formats;
1987 }
1988 }
1989
glk_get_plane_formats(struct drm_i915_private * dev_priv,enum pipe pipe,enum plane_id plane_id,int * num_formats)1990 static const u32 *glk_get_plane_formats(struct drm_i915_private *dev_priv,
1991 enum pipe pipe, enum plane_id plane_id,
1992 int *num_formats)
1993 {
1994 if (skl_plane_has_planar(dev_priv, pipe, plane_id)) {
1995 *num_formats = ARRAY_SIZE(glk_planar_formats);
1996 return glk_planar_formats;
1997 } else {
1998 *num_formats = ARRAY_SIZE(skl_plane_formats);
1999 return skl_plane_formats;
2000 }
2001 }
2002
icl_get_plane_formats(struct drm_i915_private * dev_priv,enum pipe pipe,enum plane_id plane_id,int * num_formats)2003 static const u32 *icl_get_plane_formats(struct drm_i915_private *dev_priv,
2004 enum pipe pipe, enum plane_id plane_id,
2005 int *num_formats)
2006 {
2007 if (icl_is_hdr_plane(dev_priv, plane_id)) {
2008 *num_formats = ARRAY_SIZE(icl_hdr_plane_formats);
2009 return icl_hdr_plane_formats;
2010 } else if (icl_is_nv12_y_plane(dev_priv, plane_id)) {
2011 *num_formats = ARRAY_SIZE(icl_sdr_y_plane_formats);
2012 return icl_sdr_y_plane_formats;
2013 } else {
2014 *num_formats = ARRAY_SIZE(icl_sdr_uv_plane_formats);
2015 return icl_sdr_uv_plane_formats;
2016 }
2017 }
2018
skl_plane_format_mod_supported(struct drm_plane * _plane,u32 format,u64 modifier)2019 static bool skl_plane_format_mod_supported(struct drm_plane *_plane,
2020 u32 format, u64 modifier)
2021 {
2022 struct intel_plane *plane = to_intel_plane(_plane);
2023
2024 if (!intel_fb_plane_supports_modifier(plane, modifier))
2025 return false;
2026
2027 switch (format) {
2028 case DRM_FORMAT_XRGB8888:
2029 case DRM_FORMAT_XBGR8888:
2030 case DRM_FORMAT_ARGB8888:
2031 case DRM_FORMAT_ABGR8888:
2032 if (intel_fb_is_ccs_modifier(modifier))
2033 return true;
2034 fallthrough;
2035 case DRM_FORMAT_RGB565:
2036 case DRM_FORMAT_XRGB2101010:
2037 case DRM_FORMAT_XBGR2101010:
2038 case DRM_FORMAT_ARGB2101010:
2039 case DRM_FORMAT_ABGR2101010:
2040 case DRM_FORMAT_YUYV:
2041 case DRM_FORMAT_YVYU:
2042 case DRM_FORMAT_UYVY:
2043 case DRM_FORMAT_VYUY:
2044 case DRM_FORMAT_NV12:
2045 case DRM_FORMAT_XYUV8888:
2046 case DRM_FORMAT_P010:
2047 case DRM_FORMAT_P012:
2048 case DRM_FORMAT_P016:
2049 case DRM_FORMAT_XVYU2101010:
2050 if (modifier == I915_FORMAT_MOD_Yf_TILED)
2051 return true;
2052 fallthrough;
2053 case DRM_FORMAT_C8:
2054 case DRM_FORMAT_XBGR16161616F:
2055 case DRM_FORMAT_ABGR16161616F:
2056 case DRM_FORMAT_XRGB16161616F:
2057 case DRM_FORMAT_ARGB16161616F:
2058 case DRM_FORMAT_Y210:
2059 case DRM_FORMAT_Y212:
2060 case DRM_FORMAT_Y216:
2061 case DRM_FORMAT_XVYU12_16161616:
2062 case DRM_FORMAT_XVYU16161616:
2063 if (modifier == DRM_FORMAT_MOD_LINEAR ||
2064 modifier == I915_FORMAT_MOD_X_TILED ||
2065 modifier == I915_FORMAT_MOD_Y_TILED)
2066 return true;
2067 fallthrough;
2068 default:
2069 return false;
2070 }
2071 }
2072
gen12_plane_format_mod_supported(struct drm_plane * _plane,u32 format,u64 modifier)2073 static bool gen12_plane_format_mod_supported(struct drm_plane *_plane,
2074 u32 format, u64 modifier)
2075 {
2076 struct intel_plane *plane = to_intel_plane(_plane);
2077
2078 if (!intel_fb_plane_supports_modifier(plane, modifier))
2079 return false;
2080
2081 switch (format) {
2082 case DRM_FORMAT_XRGB8888:
2083 case DRM_FORMAT_XBGR8888:
2084 case DRM_FORMAT_ARGB8888:
2085 case DRM_FORMAT_ABGR8888:
2086 if (intel_fb_is_ccs_modifier(modifier))
2087 return true;
2088 fallthrough;
2089 case DRM_FORMAT_YUYV:
2090 case DRM_FORMAT_YVYU:
2091 case DRM_FORMAT_UYVY:
2092 case DRM_FORMAT_VYUY:
2093 case DRM_FORMAT_NV12:
2094 case DRM_FORMAT_XYUV8888:
2095 case DRM_FORMAT_P010:
2096 case DRM_FORMAT_P012:
2097 case DRM_FORMAT_P016:
2098 if (intel_fb_is_mc_ccs_modifier(modifier))
2099 return true;
2100 fallthrough;
2101 case DRM_FORMAT_RGB565:
2102 case DRM_FORMAT_XRGB2101010:
2103 case DRM_FORMAT_XBGR2101010:
2104 case DRM_FORMAT_ARGB2101010:
2105 case DRM_FORMAT_ABGR2101010:
2106 case DRM_FORMAT_XVYU2101010:
2107 case DRM_FORMAT_C8:
2108 case DRM_FORMAT_XBGR16161616F:
2109 case DRM_FORMAT_ABGR16161616F:
2110 case DRM_FORMAT_XRGB16161616F:
2111 case DRM_FORMAT_ARGB16161616F:
2112 case DRM_FORMAT_Y210:
2113 case DRM_FORMAT_Y212:
2114 case DRM_FORMAT_Y216:
2115 case DRM_FORMAT_XVYU12_16161616:
2116 case DRM_FORMAT_XVYU16161616:
2117 if (!intel_fb_is_ccs_modifier(modifier))
2118 return true;
2119 fallthrough;
2120 default:
2121 return false;
2122 }
2123 }
2124
2125 static const struct drm_plane_funcs skl_plane_funcs = {
2126 .update_plane = drm_atomic_helper_update_plane,
2127 .disable_plane = drm_atomic_helper_disable_plane,
2128 .destroy = intel_plane_destroy,
2129 .atomic_duplicate_state = intel_plane_duplicate_state,
2130 .atomic_destroy_state = intel_plane_destroy_state,
2131 .format_mod_supported = skl_plane_format_mod_supported,
2132 };
2133
2134 static const struct drm_plane_funcs gen12_plane_funcs = {
2135 .update_plane = drm_atomic_helper_update_plane,
2136 .disable_plane = drm_atomic_helper_disable_plane,
2137 .destroy = intel_plane_destroy,
2138 .atomic_duplicate_state = intel_plane_duplicate_state,
2139 .atomic_destroy_state = intel_plane_destroy_state,
2140 .format_mod_supported = gen12_plane_format_mod_supported,
2141 };
2142
2143 static void
skl_plane_enable_flip_done(struct intel_plane * plane)2144 skl_plane_enable_flip_done(struct intel_plane *plane)
2145 {
2146 struct drm_i915_private *i915 = to_i915(plane->base.dev);
2147 enum pipe pipe = plane->pipe;
2148
2149 spin_lock_irq(&i915->irq_lock);
2150 bdw_enable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
2151 spin_unlock_irq(&i915->irq_lock);
2152 }
2153
2154 static void
skl_plane_disable_flip_done(struct intel_plane * plane)2155 skl_plane_disable_flip_done(struct intel_plane *plane)
2156 {
2157 struct drm_i915_private *i915 = to_i915(plane->base.dev);
2158 enum pipe pipe = plane->pipe;
2159
2160 spin_lock_irq(&i915->irq_lock);
2161 bdw_disable_pipe_irq(i915, pipe, GEN9_PIPE_PLANE_FLIP_DONE(plane->id));
2162 spin_unlock_irq(&i915->irq_lock);
2163 }
2164
skl_plane_has_rc_ccs(struct drm_i915_private * i915,enum pipe pipe,enum plane_id plane_id)2165 static bool skl_plane_has_rc_ccs(struct drm_i915_private *i915,
2166 enum pipe pipe, enum plane_id plane_id)
2167 {
2168 /* Wa_14017240301 */
2169 if (IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 70), STEP_A0, STEP_B0) ||
2170 IS_GFX_GT_IP_STEP(to_gt(i915), IP_VER(12, 71), STEP_A0, STEP_B0))
2171 return false;
2172
2173 /* Wa_22011186057 */
2174 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
2175 return false;
2176
2177 if (DISPLAY_VER(i915) >= 11)
2178 return true;
2179
2180 if (IS_GEMINILAKE(i915))
2181 return pipe != PIPE_C;
2182
2183 return pipe != PIPE_C &&
2184 (plane_id == PLANE_PRIMARY ||
2185 plane_id == PLANE_SPRITE0);
2186 }
2187
gen12_plane_has_mc_ccs(struct drm_i915_private * i915,enum plane_id plane_id)2188 static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
2189 enum plane_id plane_id)
2190 {
2191 if (DISPLAY_VER(i915) < 12)
2192 return false;
2193
2194 /* Wa_14010477008 */
2195 if (IS_DG1(i915) || IS_ROCKETLAKE(i915) ||
2196 (IS_TIGERLAKE(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_D0)))
2197 return false;
2198
2199 /* Wa_22011186057 */
2200 if (IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
2201 return false;
2202
2203 /* Wa_14013215631 */
2204 if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
2205 return false;
2206
2207 return plane_id < PLANE_SPRITE4;
2208 }
2209
skl_get_plane_caps(struct drm_i915_private * i915,enum pipe pipe,enum plane_id plane_id)2210 static u8 skl_get_plane_caps(struct drm_i915_private *i915,
2211 enum pipe pipe, enum plane_id plane_id)
2212 {
2213 u8 caps = INTEL_PLANE_CAP_TILING_X;
2214
2215 if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915))
2216 caps |= INTEL_PLANE_CAP_TILING_Y;
2217 if (DISPLAY_VER(i915) < 12)
2218 caps |= INTEL_PLANE_CAP_TILING_Yf;
2219 if (HAS_4TILE(i915))
2220 caps |= INTEL_PLANE_CAP_TILING_4;
2221
2222 if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
2223 caps |= INTEL_PLANE_CAP_CCS_RC;
2224 if (DISPLAY_VER(i915) >= 12)
2225 caps |= INTEL_PLANE_CAP_CCS_RC_CC;
2226 }
2227
2228 if (gen12_plane_has_mc_ccs(i915, plane_id))
2229 caps |= INTEL_PLANE_CAP_CCS_MC;
2230
2231 return caps;
2232 }
2233
2234 struct intel_plane *
skl_universal_plane_create(struct drm_i915_private * dev_priv,enum pipe pipe,enum plane_id plane_id)2235 skl_universal_plane_create(struct drm_i915_private *dev_priv,
2236 enum pipe pipe, enum plane_id plane_id)
2237 {
2238 const struct drm_plane_funcs *plane_funcs;
2239 struct intel_plane *plane;
2240 enum drm_plane_type plane_type;
2241 unsigned int supported_rotations;
2242 unsigned int supported_csc;
2243 const u64 *modifiers;
2244 const u32 *formats;
2245 int num_formats;
2246 int ret;
2247
2248 plane = intel_plane_alloc();
2249 if (IS_ERR(plane))
2250 return plane;
2251
2252 plane->pipe = pipe;
2253 plane->id = plane_id;
2254 plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, plane_id);
2255
2256 intel_fbc_add_plane(skl_plane_fbc(dev_priv, pipe, plane_id), plane);
2257
2258 if (DISPLAY_VER(dev_priv) >= 11) {
2259 plane->min_width = icl_plane_min_width;
2260 if (icl_is_hdr_plane(dev_priv, plane_id))
2261 plane->max_width = icl_hdr_plane_max_width;
2262 else
2263 plane->max_width = icl_sdr_plane_max_width;
2264 plane->max_height = icl_plane_max_height;
2265 plane->min_cdclk = icl_plane_min_cdclk;
2266 } else if (DISPLAY_VER(dev_priv) >= 10) {
2267 plane->max_width = glk_plane_max_width;
2268 plane->max_height = skl_plane_max_height;
2269 plane->min_cdclk = glk_plane_min_cdclk;
2270 } else {
2271 plane->max_width = skl_plane_max_width;
2272 plane->max_height = skl_plane_max_height;
2273 plane->min_cdclk = skl_plane_min_cdclk;
2274 }
2275
2276 plane->max_stride = skl_plane_max_stride;
2277 if (DISPLAY_VER(dev_priv) >= 11) {
2278 plane->update_noarm = icl_plane_update_noarm;
2279 plane->update_arm = icl_plane_update_arm;
2280 plane->disable_arm = icl_plane_disable_arm;
2281 } else {
2282 plane->update_noarm = skl_plane_update_noarm;
2283 plane->update_arm = skl_plane_update_arm;
2284 plane->disable_arm = skl_plane_disable_arm;
2285 }
2286 plane->get_hw_state = skl_plane_get_hw_state;
2287 plane->check_plane = skl_plane_check;
2288
2289 if (plane_id == PLANE_PRIMARY) {
2290 plane->need_async_flip_disable_wa = IS_DISPLAY_VER(dev_priv,
2291 9, 10);
2292 plane->async_flip = skl_plane_async_flip;
2293 plane->enable_flip_done = skl_plane_enable_flip_done;
2294 plane->disable_flip_done = skl_plane_disable_flip_done;
2295 }
2296
2297 if (DISPLAY_VER(dev_priv) >= 11)
2298 formats = icl_get_plane_formats(dev_priv, pipe,
2299 plane_id, &num_formats);
2300 else if (DISPLAY_VER(dev_priv) >= 10)
2301 formats = glk_get_plane_formats(dev_priv, pipe,
2302 plane_id, &num_formats);
2303 else
2304 formats = skl_get_plane_formats(dev_priv, pipe,
2305 plane_id, &num_formats);
2306
2307 if (DISPLAY_VER(dev_priv) >= 12)
2308 plane_funcs = &gen12_plane_funcs;
2309 else
2310 plane_funcs = &skl_plane_funcs;
2311
2312 if (plane_id == PLANE_PRIMARY)
2313 plane_type = DRM_PLANE_TYPE_PRIMARY;
2314 else
2315 plane_type = DRM_PLANE_TYPE_OVERLAY;
2316
2317 modifiers = intel_fb_plane_get_modifiers(dev_priv,
2318 skl_get_plane_caps(dev_priv, pipe, plane_id));
2319
2320 ret = drm_universal_plane_init(&dev_priv->drm, &plane->base,
2321 0, plane_funcs,
2322 formats, num_formats, modifiers,
2323 plane_type,
2324 "plane %d%c", plane_id + 1,
2325 pipe_name(pipe));
2326
2327 kfree(modifiers);
2328
2329 if (ret)
2330 goto fail;
2331
2332 if (DISPLAY_VER(dev_priv) >= 13)
2333 supported_rotations = DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
2334 else
2335 supported_rotations =
2336 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
2337 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
2338
2339 if (DISPLAY_VER(dev_priv) >= 11)
2340 supported_rotations |= DRM_MODE_REFLECT_X;
2341
2342 drm_plane_create_rotation_property(&plane->base,
2343 DRM_MODE_ROTATE_0,
2344 supported_rotations);
2345
2346 supported_csc = BIT(DRM_COLOR_YCBCR_BT601) | BIT(DRM_COLOR_YCBCR_BT709);
2347
2348 if (DISPLAY_VER(dev_priv) >= 10)
2349 supported_csc |= BIT(DRM_COLOR_YCBCR_BT2020);
2350
2351 drm_plane_create_color_properties(&plane->base,
2352 supported_csc,
2353 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
2354 BIT(DRM_COLOR_YCBCR_FULL_RANGE),
2355 DRM_COLOR_YCBCR_BT709,
2356 DRM_COLOR_YCBCR_LIMITED_RANGE);
2357
2358 drm_plane_create_alpha_property(&plane->base);
2359 drm_plane_create_blend_mode_property(&plane->base,
2360 BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2361 BIT(DRM_MODE_BLEND_PREMULTI) |
2362 BIT(DRM_MODE_BLEND_COVERAGE));
2363
2364 drm_plane_create_zpos_immutable_property(&plane->base, plane_id);
2365
2366 if (DISPLAY_VER(dev_priv) >= 12)
2367 drm_plane_enable_fb_damage_clips(&plane->base);
2368
2369 if (DISPLAY_VER(dev_priv) >= 11)
2370 drm_plane_create_scaling_filter_property(&plane->base,
2371 BIT(DRM_SCALING_FILTER_DEFAULT) |
2372 BIT(DRM_SCALING_FILTER_NEAREST_NEIGHBOR));
2373
2374 intel_plane_helper_add(plane);
2375
2376 return plane;
2377
2378 fail:
2379 intel_plane_free(plane);
2380
2381 return ERR_PTR(ret);
2382 }
2383
2384 void
skl_get_initial_plane_config(struct intel_crtc * crtc,struct intel_initial_plane_config * plane_config)2385 skl_get_initial_plane_config(struct intel_crtc *crtc,
2386 struct intel_initial_plane_config *plane_config)
2387 {
2388 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
2389 struct drm_device *dev = crtc->base.dev;
2390 struct drm_i915_private *dev_priv = to_i915(dev);
2391 struct intel_plane *plane = to_intel_plane(crtc->base.primary);
2392 enum plane_id plane_id = plane->id;
2393 enum pipe pipe;
2394 u32 val, base, offset, stride_mult, tiling, alpha;
2395 int fourcc, pixel_format;
2396 unsigned int aligned_height;
2397 struct drm_framebuffer *fb;
2398 struct intel_framebuffer *intel_fb;
2399 static_assert(PLANE_CTL_TILED_YF == PLANE_CTL_TILED_4);
2400
2401 if (!plane->get_hw_state(plane, &pipe))
2402 return;
2403
2404 drm_WARN_ON(dev, pipe != crtc->pipe);
2405
2406 if (crtc_state->bigjoiner_pipes) {
2407 drm_dbg_kms(&dev_priv->drm,
2408 "Unsupported bigjoiner configuration for initial FB\n");
2409 return;
2410 }
2411
2412 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
2413 if (!intel_fb) {
2414 drm_dbg_kms(&dev_priv->drm, "failed to alloc fb\n");
2415 return;
2416 }
2417
2418 fb = &intel_fb->base;
2419
2420 fb->dev = dev;
2421
2422 val = intel_de_read(dev_priv, PLANE_CTL(pipe, plane_id));
2423
2424 if (DISPLAY_VER(dev_priv) >= 11)
2425 pixel_format = val & PLANE_CTL_FORMAT_MASK_ICL;
2426 else
2427 pixel_format = val & PLANE_CTL_FORMAT_MASK_SKL;
2428
2429 if (DISPLAY_VER(dev_priv) >= 10) {
2430 u32 color_ctl;
2431
2432 color_ctl = intel_de_read(dev_priv, PLANE_COLOR_CTL(pipe, plane_id));
2433 alpha = REG_FIELD_GET(PLANE_COLOR_ALPHA_MASK, color_ctl);
2434 } else {
2435 alpha = REG_FIELD_GET(PLANE_CTL_ALPHA_MASK, val);
2436 }
2437
2438 fourcc = skl_format_to_fourcc(pixel_format,
2439 val & PLANE_CTL_ORDER_RGBX, alpha);
2440 fb->format = drm_format_info(fourcc);
2441
2442 tiling = val & PLANE_CTL_TILED_MASK;
2443 switch (tiling) {
2444 case PLANE_CTL_TILED_LINEAR:
2445 fb->modifier = DRM_FORMAT_MOD_LINEAR;
2446 break;
2447 case PLANE_CTL_TILED_X:
2448 plane_config->tiling = I915_TILING_X;
2449 fb->modifier = I915_FORMAT_MOD_X_TILED;
2450 break;
2451 case PLANE_CTL_TILED_Y:
2452 plane_config->tiling = I915_TILING_Y;
2453 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2454 if (DISPLAY_VER(dev_priv) >= 14)
2455 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_RC_CCS;
2456 else if (DISPLAY_VER(dev_priv) >= 12)
2457 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
2458 else
2459 fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
2460 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
2461 if (DISPLAY_VER(dev_priv) >= 14)
2462 fb->modifier = I915_FORMAT_MOD_4_TILED_MTL_MC_CCS;
2463 else
2464 fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
2465 else
2466 fb->modifier = I915_FORMAT_MOD_Y_TILED;
2467 break;
2468 case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
2469 if (HAS_4TILE(dev_priv)) {
2470 u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
2471 PLANE_CTL_CLEAR_COLOR_DISABLE;
2472
2473 if ((val & rc_mask) == rc_mask)
2474 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
2475 else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
2476 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
2477 else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2478 fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
2479 else
2480 fb->modifier = I915_FORMAT_MOD_4_TILED;
2481 } else {
2482 if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
2483 fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
2484 else
2485 fb->modifier = I915_FORMAT_MOD_Yf_TILED;
2486 }
2487 break;
2488 default:
2489 MISSING_CASE(tiling);
2490 goto error;
2491 }
2492
2493 if (!dev_priv->params.enable_dpt &&
2494 intel_fb_modifier_uses_dpt(dev_priv, fb->modifier)) {
2495 drm_dbg_kms(&dev_priv->drm, "DPT disabled, skipping initial FB\n");
2496 goto error;
2497 }
2498
2499 /*
2500 * DRM_MODE_ROTATE_ is counter clockwise to stay compatible with Xrandr
2501 * while i915 HW rotation is clockwise, thats why this swapping.
2502 */
2503 switch (val & PLANE_CTL_ROTATE_MASK) {
2504 case PLANE_CTL_ROTATE_0:
2505 plane_config->rotation = DRM_MODE_ROTATE_0;
2506 break;
2507 case PLANE_CTL_ROTATE_90:
2508 plane_config->rotation = DRM_MODE_ROTATE_270;
2509 break;
2510 case PLANE_CTL_ROTATE_180:
2511 plane_config->rotation = DRM_MODE_ROTATE_180;
2512 break;
2513 case PLANE_CTL_ROTATE_270:
2514 plane_config->rotation = DRM_MODE_ROTATE_90;
2515 break;
2516 }
2517
2518 if (DISPLAY_VER(dev_priv) >= 11 && val & PLANE_CTL_FLIP_HORIZONTAL)
2519 plane_config->rotation |= DRM_MODE_REFLECT_X;
2520
2521 /* 90/270 degree rotation would require extra work */
2522 if (drm_rotation_90_or_270(plane_config->rotation))
2523 goto error;
2524
2525 base = intel_de_read(dev_priv, PLANE_SURF(pipe, plane_id)) & PLANE_SURF_ADDR_MASK;
2526 plane_config->base = base;
2527
2528 offset = intel_de_read(dev_priv, PLANE_OFFSET(pipe, plane_id));
2529 drm_WARN_ON(&dev_priv->drm, offset != 0);
2530
2531 val = intel_de_read(dev_priv, PLANE_SIZE(pipe, plane_id));
2532 fb->height = REG_FIELD_GET(PLANE_HEIGHT_MASK, val) + 1;
2533 fb->width = REG_FIELD_GET(PLANE_WIDTH_MASK, val) + 1;
2534
2535 val = intel_de_read(dev_priv, PLANE_STRIDE(pipe, plane_id));
2536 stride_mult = skl_plane_stride_mult(fb, 0, DRM_MODE_ROTATE_0);
2537
2538 fb->pitches[0] = REG_FIELD_GET(PLANE_STRIDE__MASK, val) * stride_mult;
2539
2540 aligned_height = intel_fb_align_height(fb, 0, fb->height);
2541
2542 plane_config->size = fb->pitches[0] * aligned_height;
2543
2544 drm_dbg_kms(&dev_priv->drm,
2545 "%s/%s with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
2546 crtc->base.name, plane->base.name, fb->width, fb->height,
2547 fb->format->cpp[0] * 8, base, fb->pitches[0],
2548 plane_config->size);
2549
2550 plane_config->fb = intel_fb;
2551 return;
2552
2553 error:
2554 kfree(intel_fb);
2555 }
2556