1 /*
2 * i386 helpers (without register variable usage)
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qapi/qapi-events-run-state.h"
22 #include "cpu.h"
23 #include "exec/exec-all.h"
24 #include "sysemu/runstate.h"
25 #ifndef CONFIG_USER_ONLY
26 #include "sysemu/hw_accel.h"
27 #include "monitor/monitor.h"
28 #include "kvm/kvm_i386.h"
29 #endif
30 #include "qemu/log.h"
31 #ifdef CONFIG_TCG
32 #include "tcg/insn-start-words.h"
33 #endif
34
cpu_sync_avx_hflag(CPUX86State * env)35 void cpu_sync_avx_hflag(CPUX86State *env)
36 {
37 if ((env->cr[4] & CR4_OSXSAVE_MASK)
38 && (env->xcr0 & (XSTATE_SSE_MASK | XSTATE_YMM_MASK))
39 == (XSTATE_SSE_MASK | XSTATE_YMM_MASK)) {
40 env->hflags |= HF_AVX_EN_MASK;
41 } else{
42 env->hflags &= ~HF_AVX_EN_MASK;
43 }
44 }
45
cpu_sync_bndcs_hflags(CPUX86State * env)46 void cpu_sync_bndcs_hflags(CPUX86State *env)
47 {
48 uint32_t hflags = env->hflags;
49 uint32_t hflags2 = env->hflags2;
50 uint32_t bndcsr;
51
52 if ((hflags & HF_CPL_MASK) == 3) {
53 bndcsr = env->bndcs_regs.cfgu;
54 } else {
55 bndcsr = env->msr_bndcfgs;
56 }
57
58 if ((env->cr[4] & CR4_OSXSAVE_MASK)
59 && (env->xcr0 & XSTATE_BNDCSR_MASK)
60 && (bndcsr & BNDCFG_ENABLE)) {
61 hflags |= HF_MPX_EN_MASK;
62 } else {
63 hflags &= ~HF_MPX_EN_MASK;
64 }
65
66 if (bndcsr & BNDCFG_BNDPRESERVE) {
67 hflags2 |= HF2_MPX_PR_MASK;
68 } else {
69 hflags2 &= ~HF2_MPX_PR_MASK;
70 }
71
72 env->hflags = hflags;
73 env->hflags2 = hflags2;
74 }
75
cpu_x86_version(CPUX86State * env,int * family,int * model)76 static void cpu_x86_version(CPUX86State *env, int *family, int *model)
77 {
78 int cpuver = env->cpuid_version;
79
80 if (family == NULL || model == NULL) {
81 return;
82 }
83
84 *family = (cpuver >> 8) & 0x0f;
85 *model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0x0f);
86 }
87
88 /* Broadcast MCA signal for processor version 06H_EH and above */
cpu_x86_support_mca_broadcast(CPUX86State * env)89 int cpu_x86_support_mca_broadcast(CPUX86State *env)
90 {
91 int family = 0;
92 int model = 0;
93
94 cpu_x86_version(env, &family, &model);
95 if ((family == 6 && model >= 14) || family > 6) {
96 return 1;
97 }
98
99 return 0;
100 }
101
102 /***********************************************************/
103 /* x86 mmu */
104 /* XXX: add PGE support */
105
x86_cpu_set_a20(X86CPU * cpu,int a20_state)106 void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
107 {
108 CPUX86State *env = &cpu->env;
109
110 a20_state = (a20_state != 0);
111 if (a20_state != ((env->a20_mask >> 20) & 1)) {
112 CPUState *cs = CPU(cpu);
113
114 qemu_log_mask(CPU_LOG_MMU, "A20 update: a20=%d\n", a20_state);
115 /* if the cpu is currently executing code, we must unlink it and
116 all the potentially executing TB */
117 cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
118
119 /* when a20 is changed, all the MMU mappings are invalid, so
120 we must flush everything */
121 tlb_flush(cs);
122 env->a20_mask = ~(1 << 20) | (a20_state << 20);
123 }
124 }
125
cpu_x86_update_cr0(CPUX86State * env,uint32_t new_cr0)126 void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
127 {
128 X86CPU *cpu = env_archcpu(env);
129 int pe_state;
130
131 qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
132 if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
133 (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
134 tlb_flush(CPU(cpu));
135 }
136
137 #ifdef TARGET_X86_64
138 if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
139 (env->efer & MSR_EFER_LME)) {
140 /* enter in long mode */
141 /* XXX: generate an exception */
142 if (!(env->cr[4] & CR4_PAE_MASK))
143 return;
144 env->efer |= MSR_EFER_LMA;
145 env->hflags |= HF_LMA_MASK;
146 } else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
147 (env->efer & MSR_EFER_LMA)) {
148 /* exit long mode */
149 env->efer &= ~MSR_EFER_LMA;
150 env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
151 env->eip &= 0xffffffff;
152 }
153 #endif
154 env->cr[0] = new_cr0 | CR0_ET_MASK;
155
156 /* update PE flag in hidden flags */
157 pe_state = (env->cr[0] & CR0_PE_MASK);
158 env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
159 /* ensure that ADDSEG is always set in real mode */
160 env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
161 /* update FPU flags */
162 env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
163 ((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
164 }
165
166 /* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
167 the PDPT */
cpu_x86_update_cr3(CPUX86State * env,target_ulong new_cr3)168 void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
169 {
170 env->cr[3] = new_cr3;
171 if (env->cr[0] & CR0_PG_MASK) {
172 qemu_log_mask(CPU_LOG_MMU,
173 "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
174 tlb_flush(env_cpu(env));
175 }
176 }
177
cpu_x86_update_cr4(CPUX86State * env,uint32_t new_cr4)178 void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
179 {
180 uint32_t hflags;
181
182 #if defined(DEBUG_MMU)
183 printf("CR4 update: %08x -> %08x\n", (uint32_t)env->cr[4], new_cr4);
184 #endif
185 if ((new_cr4 ^ env->cr[4]) &
186 (CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
187 CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) {
188 tlb_flush(env_cpu(env));
189 }
190
191 /* Clear bits we're going to recompute. */
192 hflags = env->hflags & ~(HF_OSFXSR_MASK | HF_SMAP_MASK | HF_UMIP_MASK);
193
194 /* SSE handling */
195 if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {
196 new_cr4 &= ~CR4_OSFXSR_MASK;
197 }
198 if (new_cr4 & CR4_OSFXSR_MASK) {
199 hflags |= HF_OSFXSR_MASK;
200 }
201
202 if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
203 new_cr4 &= ~CR4_SMAP_MASK;
204 }
205 if (new_cr4 & CR4_SMAP_MASK) {
206 hflags |= HF_SMAP_MASK;
207 }
208 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_UMIP)) {
209 new_cr4 &= ~CR4_UMIP_MASK;
210 }
211 if (new_cr4 & CR4_UMIP_MASK) {
212 hflags |= HF_UMIP_MASK;
213 }
214
215 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
216 new_cr4 &= ~CR4_PKE_MASK;
217 }
218 if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKS)) {
219 new_cr4 &= ~CR4_PKS_MASK;
220 }
221
222 env->cr[4] = new_cr4;
223 env->hflags = hflags;
224
225 cpu_sync_bndcs_hflags(env);
226 cpu_sync_avx_hflag(env);
227 }
228
229 #if !defined(CONFIG_USER_ONLY)
x86_cpu_get_phys_page_attrs_debug(CPUState * cs,vaddr addr,MemTxAttrs * attrs)230 hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
231 MemTxAttrs *attrs)
232 {
233 X86CPU *cpu = X86_CPU(cs);
234 CPUX86State *env = &cpu->env;
235 target_ulong pde_addr, pte_addr;
236 uint64_t pte;
237 int32_t a20_mask;
238 uint32_t page_offset;
239 int page_size;
240
241 *attrs = cpu_get_mem_attrs(env);
242
243 a20_mask = x86_get_a20_mask(env);
244 if (!(env->cr[0] & CR0_PG_MASK)) {
245 pte = addr & a20_mask;
246 page_size = 4096;
247 } else if (env->cr[4] & CR4_PAE_MASK) {
248 target_ulong pdpe_addr;
249 uint64_t pde, pdpe;
250
251 #ifdef TARGET_X86_64
252 if (env->hflags & HF_LMA_MASK) {
253 bool la57 = env->cr[4] & CR4_LA57_MASK;
254 uint64_t pml5e_addr, pml5e;
255 uint64_t pml4e_addr, pml4e;
256 int32_t sext;
257
258 /* test virtual address sign extension */
259 sext = la57 ? (int64_t)addr >> 56 : (int64_t)addr >> 47;
260 if (sext != 0 && sext != -1) {
261 return -1;
262 }
263
264 if (la57) {
265 pml5e_addr = ((env->cr[3] & ~0xfff) +
266 (((addr >> 48) & 0x1ff) << 3)) & a20_mask;
267 pml5e = x86_ldq_phys(cs, pml5e_addr);
268 if (!(pml5e & PG_PRESENT_MASK)) {
269 return -1;
270 }
271 } else {
272 pml5e = env->cr[3];
273 }
274
275 pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
276 (((addr >> 39) & 0x1ff) << 3)) & a20_mask;
277 pml4e = x86_ldq_phys(cs, pml4e_addr);
278 if (!(pml4e & PG_PRESENT_MASK)) {
279 return -1;
280 }
281 pdpe_addr = ((pml4e & PG_ADDRESS_MASK) +
282 (((addr >> 30) & 0x1ff) << 3)) & a20_mask;
283 pdpe = x86_ldq_phys(cs, pdpe_addr);
284 if (!(pdpe & PG_PRESENT_MASK)) {
285 return -1;
286 }
287 if (pdpe & PG_PSE_MASK) {
288 page_size = 1024 * 1024 * 1024;
289 pte = pdpe;
290 goto out;
291 }
292
293 } else
294 #endif
295 {
296 pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
297 a20_mask;
298 pdpe = x86_ldq_phys(cs, pdpe_addr);
299 if (!(pdpe & PG_PRESENT_MASK))
300 return -1;
301 }
302
303 pde_addr = ((pdpe & PG_ADDRESS_MASK) +
304 (((addr >> 21) & 0x1ff) << 3)) & a20_mask;
305 pde = x86_ldq_phys(cs, pde_addr);
306 if (!(pde & PG_PRESENT_MASK)) {
307 return -1;
308 }
309 if (pde & PG_PSE_MASK) {
310 /* 2 MB page */
311 page_size = 2048 * 1024;
312 pte = pde;
313 } else {
314 /* 4 KB page */
315 pte_addr = ((pde & PG_ADDRESS_MASK) +
316 (((addr >> 12) & 0x1ff) << 3)) & a20_mask;
317 page_size = 4096;
318 pte = x86_ldq_phys(cs, pte_addr);
319 }
320 if (!(pte & PG_PRESENT_MASK)) {
321 return -1;
322 }
323 } else {
324 uint32_t pde;
325
326 /* page directory entry */
327 pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask;
328 pde = x86_ldl_phys(cs, pde_addr);
329 if (!(pde & PG_PRESENT_MASK))
330 return -1;
331 if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
332 pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
333 page_size = 4096 * 1024;
334 } else {
335 /* page directory entry */
336 pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask;
337 pte = x86_ldl_phys(cs, pte_addr);
338 if (!(pte & PG_PRESENT_MASK)) {
339 return -1;
340 }
341 page_size = 4096;
342 }
343 pte = pte & a20_mask;
344 }
345
346 #ifdef TARGET_X86_64
347 out:
348 #endif
349 pte &= PG_ADDRESS_MASK & ~(page_size - 1);
350 page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
351 return pte | page_offset;
352 }
353
354 typedef struct MCEInjectionParams {
355 Monitor *mon;
356 int bank;
357 uint64_t status;
358 uint64_t mcg_status;
359 uint64_t addr;
360 uint64_t misc;
361 int flags;
362 } MCEInjectionParams;
363
emit_guest_memory_failure(MemoryFailureAction action,bool ar,bool recursive)364 static void emit_guest_memory_failure(MemoryFailureAction action, bool ar,
365 bool recursive)
366 {
367 MemoryFailureFlags mff = {.action_required = ar, .recursive = recursive};
368
369 qapi_event_send_memory_failure(MEMORY_FAILURE_RECIPIENT_GUEST, action,
370 &mff);
371 }
372
do_inject_x86_mce(CPUState * cs,run_on_cpu_data data)373 static void do_inject_x86_mce(CPUState *cs, run_on_cpu_data data)
374 {
375 MCEInjectionParams *params = data.host_ptr;
376 X86CPU *cpu = X86_CPU(cs);
377 CPUX86State *cenv = &cpu->env;
378 uint64_t *banks = cenv->mce_banks + 4 * params->bank;
379 g_autofree char *msg = NULL;
380 bool need_reset = false;
381 bool recursive;
382 bool ar = !!(params->status & MCI_STATUS_AR);
383
384 cpu_synchronize_state(cs);
385 recursive = !!(cenv->mcg_status & MCG_STATUS_MCIP);
386
387 /*
388 * If there is an MCE exception being processed, ignore this SRAO MCE
389 * unless unconditional injection was requested.
390 */
391 if (!(params->flags & MCE_INJECT_UNCOND_AO) && !ar && recursive) {
392 emit_guest_memory_failure(MEMORY_FAILURE_ACTION_IGNORE, ar, recursive);
393 return;
394 }
395
396 if (params->status & MCI_STATUS_UC) {
397 /*
398 * if MSR_MCG_CTL is not all 1s, the uncorrected error
399 * reporting is disabled
400 */
401 if ((cenv->mcg_cap & MCG_CTL_P) && cenv->mcg_ctl != ~(uint64_t)0) {
402 monitor_printf(params->mon,
403 "CPU %d: Uncorrected error reporting disabled\n",
404 cs->cpu_index);
405 return;
406 }
407
408 /*
409 * if MSR_MCi_CTL is not all 1s, the uncorrected error
410 * reporting is disabled for the bank
411 */
412 if (banks[0] != ~(uint64_t)0) {
413 monitor_printf(params->mon,
414 "CPU %d: Uncorrected error reporting disabled for"
415 " bank %d\n",
416 cs->cpu_index, params->bank);
417 return;
418 }
419
420 if (!(cenv->cr[4] & CR4_MCE_MASK)) {
421 need_reset = true;
422 msg = g_strdup_printf("CPU %d: MCE capability is not enabled, "
423 "raising triple fault", cs->cpu_index);
424 } else if (recursive) {
425 need_reset = true;
426 msg = g_strdup_printf("CPU %d: Previous MCE still in progress, "
427 "raising triple fault", cs->cpu_index);
428 }
429
430 if (need_reset) {
431 emit_guest_memory_failure(MEMORY_FAILURE_ACTION_RESET, ar,
432 recursive);
433 monitor_puts(params->mon, msg);
434 qemu_log_mask(CPU_LOG_RESET, "%s\n", msg);
435 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
436 return;
437 }
438
439 if (banks[1] & MCI_STATUS_VAL) {
440 params->status |= MCI_STATUS_OVER;
441 }
442 banks[2] = params->addr;
443 banks[3] = params->misc;
444 cenv->mcg_status = params->mcg_status;
445 banks[1] = params->status;
446 cpu_interrupt(cs, CPU_INTERRUPT_MCE);
447 } else if (!(banks[1] & MCI_STATUS_VAL)
448 || !(banks[1] & MCI_STATUS_UC)) {
449 if (banks[1] & MCI_STATUS_VAL) {
450 params->status |= MCI_STATUS_OVER;
451 }
452 banks[2] = params->addr;
453 banks[3] = params->misc;
454 banks[1] = params->status;
455 } else {
456 banks[1] |= MCI_STATUS_OVER;
457 }
458
459 emit_guest_memory_failure(MEMORY_FAILURE_ACTION_INJECT, ar, recursive);
460 }
461
cpu_x86_inject_mce(Monitor * mon,X86CPU * cpu,int bank,uint64_t status,uint64_t mcg_status,uint64_t addr,uint64_t misc,int flags)462 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
463 uint64_t status, uint64_t mcg_status, uint64_t addr,
464 uint64_t misc, int flags)
465 {
466 CPUState *cs = CPU(cpu);
467 CPUX86State *cenv = &cpu->env;
468 MCEInjectionParams params = {
469 .mon = mon,
470 .bank = bank,
471 .status = status,
472 .mcg_status = mcg_status,
473 .addr = addr,
474 .misc = misc,
475 .flags = flags,
476 };
477 unsigned bank_num = cenv->mcg_cap & 0xff;
478
479 if (!cenv->mcg_cap) {
480 monitor_printf(mon, "MCE injection not supported\n");
481 return;
482 }
483 if (bank >= bank_num) {
484 monitor_printf(mon, "Invalid MCE bank number\n");
485 return;
486 }
487 if (!(status & MCI_STATUS_VAL)) {
488 monitor_printf(mon, "Invalid MCE status code\n");
489 return;
490 }
491 if ((flags & MCE_INJECT_BROADCAST)
492 && !cpu_x86_support_mca_broadcast(cenv)) {
493 monitor_printf(mon, "Guest CPU does not support MCA broadcast\n");
494 return;
495 }
496
497 run_on_cpu(cs, do_inject_x86_mce, RUN_ON_CPU_HOST_PTR(¶ms));
498 if (flags & MCE_INJECT_BROADCAST) {
499 CPUState *other_cs;
500
501 params.bank = 1;
502 params.status = MCI_STATUS_VAL | MCI_STATUS_UC;
503 params.mcg_status = MCG_STATUS_MCIP | MCG_STATUS_RIPV;
504 params.addr = 0;
505 params.misc = 0;
506 CPU_FOREACH(other_cs) {
507 if (other_cs == cs) {
508 continue;
509 }
510 run_on_cpu(other_cs, do_inject_x86_mce, RUN_ON_CPU_HOST_PTR(¶ms));
511 }
512 }
513 }
514
get_memio_eip(CPUX86State * env)515 static inline target_ulong get_memio_eip(CPUX86State *env)
516 {
517 #ifdef CONFIG_TCG
518 uint64_t data[TARGET_INSN_START_WORDS];
519 CPUState *cs = env_cpu(env);
520
521 if (!cpu_unwind_state_data(cs, cs->mem_io_pc, data)) {
522 return env->eip;
523 }
524
525 /* Per x86_restore_state_to_opc. */
526 if (cs->tcg_cflags & CF_PCREL) {
527 return (env->eip & TARGET_PAGE_MASK) | data[0];
528 } else {
529 return data[0] - env->segs[R_CS].base;
530 }
531 #else
532 qemu_build_not_reached();
533 #endif
534 }
535
cpu_report_tpr_access(CPUX86State * env,TPRAccess access)536 void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
537 {
538 X86CPU *cpu = env_archcpu(env);
539 CPUState *cs = env_cpu(env);
540
541 if (kvm_enabled() || whpx_enabled() || nvmm_enabled()) {
542 env->tpr_access_type = access;
543
544 cpu_interrupt(cs, CPU_INTERRUPT_TPR);
545 } else if (tcg_enabled()) {
546 target_ulong eip = get_memio_eip(env);
547
548 apic_handle_tpr_access_report(cpu->apic_state, eip, access);
549 }
550 }
551 #endif /* !CONFIG_USER_ONLY */
552
cpu_x86_get_descr_debug(CPUX86State * env,unsigned int selector,target_ulong * base,unsigned int * limit,unsigned int * flags)553 int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
554 target_ulong *base, unsigned int *limit,
555 unsigned int *flags)
556 {
557 CPUState *cs = env_cpu(env);
558 SegmentCache *dt;
559 target_ulong ptr;
560 uint32_t e1, e2;
561 int index;
562
563 if (selector & 0x4)
564 dt = &env->ldt;
565 else
566 dt = &env->gdt;
567 index = selector & ~7;
568 ptr = dt->base + index;
569 if ((index + 7) > dt->limit
570 || cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
571 || cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
572 return 0;
573
574 *base = ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
575 *limit = (e1 & 0xffff) | (e2 & 0x000f0000);
576 if (e2 & DESC_G_MASK)
577 *limit = (*limit << 12) | 0xfff;
578 *flags = e2;
579
580 return 1;
581 }
582
do_cpu_init(X86CPU * cpu)583 void do_cpu_init(X86CPU *cpu)
584 {
585 #if !defined(CONFIG_USER_ONLY)
586 CPUState *cs = CPU(cpu);
587 CPUX86State *env = &cpu->env;
588 CPUX86State *save = g_new(CPUX86State, 1);
589 int sipi = cs->interrupt_request & CPU_INTERRUPT_SIPI;
590
591 *save = *env;
592
593 cpu_reset(cs);
594 cs->interrupt_request = sipi;
595 memcpy(&env->start_init_save, &save->start_init_save,
596 offsetof(CPUX86State, end_init_save) -
597 offsetof(CPUX86State, start_init_save));
598 g_free(save);
599
600 if (kvm_enabled()) {
601 kvm_arch_do_init_vcpu(cpu);
602 }
603 apic_init_reset(cpu->apic_state);
604 #endif /* CONFIG_USER_ONLY */
605 }
606
607 #ifndef CONFIG_USER_ONLY
608
do_cpu_sipi(X86CPU * cpu)609 void do_cpu_sipi(X86CPU *cpu)
610 {
611 apic_sipi(cpu->apic_state);
612 }
613
cpu_load_efer(CPUX86State * env,uint64_t val)614 void cpu_load_efer(CPUX86State *env, uint64_t val)
615 {
616 env->efer = val;
617 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
618 if (env->efer & MSR_EFER_LMA) {
619 env->hflags |= HF_LMA_MASK;
620 }
621 if (env->efer & MSR_EFER_SVME) {
622 env->hflags |= HF_SVME_MASK;
623 }
624 }
625
x86_ldub_phys(CPUState * cs,hwaddr addr)626 uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
627 {
628 X86CPU *cpu = X86_CPU(cs);
629 CPUX86State *env = &cpu->env;
630 MemTxAttrs attrs = cpu_get_mem_attrs(env);
631 AddressSpace *as = cpu_addressspace(cs, attrs);
632
633 return address_space_ldub(as, addr, attrs, NULL);
634 }
635
x86_lduw_phys(CPUState * cs,hwaddr addr)636 uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr)
637 {
638 X86CPU *cpu = X86_CPU(cs);
639 CPUX86State *env = &cpu->env;
640 MemTxAttrs attrs = cpu_get_mem_attrs(env);
641 AddressSpace *as = cpu_addressspace(cs, attrs);
642
643 return address_space_lduw(as, addr, attrs, NULL);
644 }
645
x86_ldl_phys(CPUState * cs,hwaddr addr)646 uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr)
647 {
648 X86CPU *cpu = X86_CPU(cs);
649 CPUX86State *env = &cpu->env;
650 MemTxAttrs attrs = cpu_get_mem_attrs(env);
651 AddressSpace *as = cpu_addressspace(cs, attrs);
652
653 return address_space_ldl(as, addr, attrs, NULL);
654 }
655
x86_ldq_phys(CPUState * cs,hwaddr addr)656 uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr)
657 {
658 X86CPU *cpu = X86_CPU(cs);
659 CPUX86State *env = &cpu->env;
660 MemTxAttrs attrs = cpu_get_mem_attrs(env);
661 AddressSpace *as = cpu_addressspace(cs, attrs);
662
663 return address_space_ldq(as, addr, attrs, NULL);
664 }
665
x86_stb_phys(CPUState * cs,hwaddr addr,uint8_t val)666 void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val)
667 {
668 X86CPU *cpu = X86_CPU(cs);
669 CPUX86State *env = &cpu->env;
670 MemTxAttrs attrs = cpu_get_mem_attrs(env);
671 AddressSpace *as = cpu_addressspace(cs, attrs);
672
673 address_space_stb(as, addr, val, attrs, NULL);
674 }
675
x86_stl_phys_notdirty(CPUState * cs,hwaddr addr,uint32_t val)676 void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val)
677 {
678 X86CPU *cpu = X86_CPU(cs);
679 CPUX86State *env = &cpu->env;
680 MemTxAttrs attrs = cpu_get_mem_attrs(env);
681 AddressSpace *as = cpu_addressspace(cs, attrs);
682
683 address_space_stl_notdirty(as, addr, val, attrs, NULL);
684 }
685
x86_stw_phys(CPUState * cs,hwaddr addr,uint32_t val)686 void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val)
687 {
688 X86CPU *cpu = X86_CPU(cs);
689 CPUX86State *env = &cpu->env;
690 MemTxAttrs attrs = cpu_get_mem_attrs(env);
691 AddressSpace *as = cpu_addressspace(cs, attrs);
692
693 address_space_stw(as, addr, val, attrs, NULL);
694 }
695
x86_stl_phys(CPUState * cs,hwaddr addr,uint32_t val)696 void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val)
697 {
698 X86CPU *cpu = X86_CPU(cs);
699 CPUX86State *env = &cpu->env;
700 MemTxAttrs attrs = cpu_get_mem_attrs(env);
701 AddressSpace *as = cpu_addressspace(cs, attrs);
702
703 address_space_stl(as, addr, val, attrs, NULL);
704 }
705
x86_stq_phys(CPUState * cs,hwaddr addr,uint64_t val)706 void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val)
707 {
708 X86CPU *cpu = X86_CPU(cs);
709 CPUX86State *env = &cpu->env;
710 MemTxAttrs attrs = cpu_get_mem_attrs(env);
711 AddressSpace *as = cpu_addressspace(cs, attrs);
712
713 address_space_stq(as, addr, val, attrs, NULL);
714 }
715 #endif
716