xref: /openbmc/u-boot/drivers/ata/sata_sil.c (revision e8f80a5a)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2011 Freescale Semiconductor, Inc.
4  * Author: Tang Yuantian <b29983@freescale.com>
5  */
6 
7 #include <common.h>
8 #include <pci.h>
9 #include <command.h>
10 #include <asm/byteorder.h>
11 #include <malloc.h>
12 #include <asm/io.h>
13 #include <fis.h>
14 #include <sata.h>
15 #include <libata.h>
16 #include <sata.h>
17 #include "sata_sil.h"
18 
19 /* Convert sectorsize to wordsize */
20 #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
21 #define virt_to_bus(devno, v)	pci_virt_to_mem(devno, (void *) (v))
22 
23 static struct sata_info sata_info;
24 
25 static struct pci_device_id supported[] = {
26 	{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3131},
27 	{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3132},
28 	{PCI_VENDOR_ID_SILICONIMAGE, PCI_DEVICE_ID_SIL3124},
29 	{}
30 };
31 
sil_sata_dump_fis(struct sata_fis_d2h * s)32 static void sil_sata_dump_fis(struct sata_fis_d2h *s)
33 {
34 	printf("Status FIS dump:\n");
35 	printf("fis_type:		%02x\n", s->fis_type);
36 	printf("pm_port_i:		%02x\n", s->pm_port_i);
37 	printf("status:			%02x\n", s->status);
38 	printf("error:			%02x\n", s->error);
39 	printf("lba_low:		%02x\n", s->lba_low);
40 	printf("lba_mid:		%02x\n", s->lba_mid);
41 	printf("lba_high:		%02x\n", s->lba_high);
42 	printf("device:			%02x\n", s->device);
43 	printf("lba_low_exp:		%02x\n", s->lba_low_exp);
44 	printf("lba_mid_exp:		%02x\n", s->lba_mid_exp);
45 	printf("lba_high_exp:		%02x\n", s->lba_high_exp);
46 	printf("res1:			%02x\n", s->res1);
47 	printf("sector_count:		%02x\n", s->sector_count);
48 	printf("sector_count_exp:	%02x\n", s->sector_count_exp);
49 }
50 
sata_spd_string(unsigned int speed)51 static const char *sata_spd_string(unsigned int speed)
52 {
53 	static const char * const spd_str[] = {
54 		"1.5 Gbps",
55 		"3.0 Gbps",
56 		"6.0 Gbps",
57 	};
58 
59 	if ((speed - 1) > 2)
60 		return "<unknown>";
61 
62 	return spd_str[speed - 1];
63 }
64 
ata_wait_register(void * reg,u32 mask,u32 val,int timeout_msec)65 static u32 ata_wait_register(void *reg, u32 mask,
66 			 u32 val, int timeout_msec)
67 {
68 	u32 tmp;
69 
70 	tmp = readl(reg);
71 	while ((tmp & mask) == val && timeout_msec > 0) {
72 		mdelay(1);
73 		timeout_msec--;
74 		tmp = readl(reg);
75 	}
76 
77 	return tmp;
78 }
79 
sil_config_port(void * port)80 static void sil_config_port(void *port)
81 {
82 	/* configure IRQ WoC */
83 	writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
84 
85 	/* zero error counters. */
86 	writew(0x8000, port + PORT_DECODE_ERR_THRESH);
87 	writew(0x8000, port + PORT_CRC_ERR_THRESH);
88 	writew(0x8000, port + PORT_HSHK_ERR_THRESH);
89 	writew(0x0000, port + PORT_DECODE_ERR_CNT);
90 	writew(0x0000, port + PORT_CRC_ERR_CNT);
91 	writew(0x0000, port + PORT_HSHK_ERR_CNT);
92 
93 	/* always use 64bit activation */
94 	writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
95 
96 	/* clear port multiplier enable and resume bits */
97 	writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
98 }
99 
sil_init_port(void * port)100 static int sil_init_port(void *port)
101 {
102 	u32 tmp;
103 
104 	writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
105 	ata_wait_register(port + PORT_CTRL_STAT,
106 			  PORT_CS_INIT, PORT_CS_INIT, 100);
107 	tmp = ata_wait_register(port + PORT_CTRL_STAT,
108 				PORT_CS_RDY, 0, 100);
109 
110 	if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
111 		return 1;
112 
113 	return 0;
114 }
115 
sil_read_fis(int dev,int tag,struct sata_fis_d2h * fis)116 static void sil_read_fis(int dev, int tag, struct sata_fis_d2h *fis)
117 {
118 	struct sil_sata *sata = sata_dev_desc[dev].priv;
119 	void *port = sata->port;
120 	struct sil_prb *prb;
121 	int i;
122 	u32 *src, *dst;
123 
124 	prb = port + PORT_LRAM + tag * PORT_LRAM_SLOT_SZ;
125 	src = (u32 *)&prb->fis;
126 	dst = (u32 *)fis;
127 	for (i = 0; i < sizeof(struct sata_fis_h2d); i += 4)
128 		*dst++ = readl(src++);
129 }
130 
sil_exec_cmd(int dev,struct sil_cmd_block * pcmd,int tag)131 static int sil_exec_cmd(int dev, struct sil_cmd_block *pcmd, int tag)
132 {
133 	struct sil_sata *sata = sata_dev_desc[dev].priv;
134 	void *port = sata->port;
135 	u64 paddr = virt_to_bus(sata->devno, pcmd);
136 	u32 irq_mask, irq_stat;
137 	int rc;
138 
139 	writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
140 
141 	/* better to add momery barrior here */
142 	writel((u32)paddr, port + PORT_CMD_ACTIVATE + tag * 8);
143 	writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + tag * 8 + 4);
144 
145 	irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
146 	irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask,
147 			0, 10000);
148 
149 	/* clear IRQs */
150 	writel(irq_mask, port + PORT_IRQ_STAT);
151 	irq_stat >>= PORT_IRQ_RAW_SHIFT;
152 
153 	if (irq_stat & PORT_IRQ_COMPLETE)
154 		rc = 0;
155 	else {
156 		/* force port into known state */
157 		sil_init_port(port);
158 		if (irq_stat & PORT_IRQ_ERROR)
159 			rc = 1; /* error */
160 		else
161 			rc = 2; /* busy */
162 	}
163 
164 	return rc;
165 }
166 
sil_cmd_set_feature(int dev)167 static int sil_cmd_set_feature(int dev)
168 {
169 	struct sil_sata *sata = sata_dev_desc[dev].priv;
170 	struct sil_cmd_block cmdb, *pcmd = &cmdb;
171 	struct sata_fis_d2h fis;
172 	u8 udma_cap;
173 	int ret;
174 
175 	memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
176 	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
177 	pcmd->prb.fis.pm_port_c = (1 << 7);
178 	pcmd->prb.fis.command = ATA_CMD_SET_FEATURES;
179 	pcmd->prb.fis.features = SETFEATURES_XFER;
180 
181 	/* First check the device capablity */
182 	udma_cap = (u8)(sata->udma & 0xff);
183 	debug("udma_cap %02x\n", udma_cap);
184 
185 	if (udma_cap == ATA_UDMA6)
186 		pcmd->prb.fis.sector_count = XFER_UDMA_6;
187 	if (udma_cap == ATA_UDMA5)
188 		pcmd->prb.fis.sector_count = XFER_UDMA_5;
189 	if (udma_cap == ATA_UDMA4)
190 		pcmd->prb.fis.sector_count = XFER_UDMA_4;
191 	if (udma_cap == ATA_UDMA3)
192 		pcmd->prb.fis.sector_count = XFER_UDMA_3;
193 
194 	ret = sil_exec_cmd(dev, pcmd, 0);
195 	if (ret) {
196 		sil_read_fis(dev, 0, &fis);
197 		printf("Err: exe cmd(0x%x).\n",
198 				readl(sata->port + PORT_SERROR));
199 		sil_sata_dump_fis(&fis);
200 		return 1;
201 	}
202 
203 	return 0;
204 }
205 
sil_cmd_identify_device(int dev,u16 * id)206 static int sil_cmd_identify_device(int dev, u16 *id)
207 {
208 	struct sil_sata *sata = sata_dev_desc[dev].priv;
209 	struct sil_cmd_block cmdb, *pcmd = &cmdb;
210 	struct sata_fis_d2h fis;
211 	int ret;
212 
213 	memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
214 	pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
215 	pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
216 	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
217 	pcmd->prb.fis.pm_port_c = (1 << 7);
218 	pcmd->prb.fis.command = ATA_CMD_ID_ATA;
219 	pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, id));
220 	pcmd->sge.cnt = cpu_to_le32(sizeof(id[0]) * ATA_ID_WORDS);
221 	pcmd->sge.flags = cpu_to_le32(SGE_TRM);
222 
223 	ret = sil_exec_cmd(dev, pcmd, 0);
224 	if (ret) {
225 		sil_read_fis(dev, 0, &fis);
226 		printf("Err: id cmd(0x%x).\n", readl(sata->port + PORT_SERROR));
227 		sil_sata_dump_fis(&fis);
228 		return 1;
229 	}
230 	ata_swap_buf_le16(id, ATA_ID_WORDS);
231 
232 	return 0;
233 }
234 
sil_cmd_soft_reset(int dev)235 static int sil_cmd_soft_reset(int dev)
236 {
237 	struct sil_cmd_block cmdb, *pcmd = &cmdb;
238 	struct sil_sata *sata = sata_dev_desc[dev].priv;
239 	struct sata_fis_d2h fis;
240 	void *port = sata->port;
241 	int ret;
242 
243 	/* put the port into known state */
244 	if (sil_init_port(port)) {
245 		printf("SRST: port %d not ready\n", dev);
246 		return 1;
247 	}
248 
249 	memset((void *)&cmdb, 0, sizeof(struct sil_cmd_block));
250 
251 	pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_SRST);
252 	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
253 	pcmd->prb.fis.pm_port_c = 0xf;
254 
255 	ret = sil_exec_cmd(dev, &cmdb, 0);
256 	if (ret) {
257 		sil_read_fis(dev, 0, &fis);
258 		printf("SRST cmd error.\n");
259 		sil_sata_dump_fis(&fis);
260 		return 1;
261 	}
262 
263 	return 0;
264 }
265 
sil_sata_rw_cmd(int dev,ulong start,ulong blkcnt,u8 * buffer,int is_write)266 static ulong sil_sata_rw_cmd(int dev, ulong start, ulong blkcnt,
267 		u8 *buffer, int is_write)
268 {
269 	struct sil_sata *sata = sata_dev_desc[dev].priv;
270 	struct sil_cmd_block cmdb, *pcmd = &cmdb;
271 	struct sata_fis_d2h fis;
272 	u64 block;
273 	int ret;
274 
275 	block = (u64)start;
276 	memset(pcmd, 0, sizeof(struct sil_cmd_block));
277 	pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
278 	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
279 	pcmd->prb.fis.pm_port_c = (1 << 7);
280 	if (is_write) {
281 		pcmd->prb.fis.command = ATA_CMD_WRITE;
282 		pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
283 	} else {
284 		pcmd->prb.fis.command = ATA_CMD_READ;
285 		pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
286 	}
287 
288 	pcmd->prb.fis.device = ATA_LBA;
289 	pcmd->prb.fis.device |= (block >> 24) & 0xf;
290 	pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
291 	pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
292 	pcmd->prb.fis.lba_low = block & 0xff;
293 	pcmd->prb.fis.sector_count = (u8)blkcnt & 0xff;
294 
295 	pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
296 	pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
297 	pcmd->sge.flags = cpu_to_le32(SGE_TRM);
298 
299 	ret = sil_exec_cmd(dev, pcmd, 0);
300 	if (ret) {
301 		sil_read_fis(dev, 0, &fis);
302 		printf("Err: rw cmd(0x%08x).\n",
303 				readl(sata->port + PORT_SERROR));
304 		sil_sata_dump_fis(&fis);
305 		return 1;
306 	}
307 
308 	return blkcnt;
309 }
310 
sil_sata_rw_cmd_ext(int dev,ulong start,ulong blkcnt,u8 * buffer,int is_write)311 static ulong sil_sata_rw_cmd_ext(int dev, ulong start, ulong blkcnt,
312 		u8 *buffer, int is_write)
313 {
314 	struct sil_sata *sata = sata_dev_desc[dev].priv;
315 	struct sil_cmd_block cmdb, *pcmd = &cmdb;
316 	struct sata_fis_d2h fis;
317 	u64 block;
318 	int ret;
319 
320 	block = (u64)start;
321 	memset(pcmd, 0, sizeof(struct sil_cmd_block));
322 	pcmd->prb.ctrl = cpu_to_le16(PRB_CTRL_PROTOCOL);
323 	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
324 	pcmd->prb.fis.pm_port_c = (1 << 7);
325 	if (is_write) {
326 		pcmd->prb.fis.command = ATA_CMD_WRITE_EXT;
327 		pcmd->prb.prot = cpu_to_le16(PRB_PROT_WRITE);
328 	} else {
329 		pcmd->prb.fis.command = ATA_CMD_READ_EXT;
330 		pcmd->prb.prot = cpu_to_le16(PRB_PROT_READ);
331 	}
332 
333 	pcmd->prb.fis.lba_high_exp = (block >> 40) & 0xff;
334 	pcmd->prb.fis.lba_mid_exp = (block >> 32) & 0xff;
335 	pcmd->prb.fis.lba_low_exp = (block >> 24) & 0xff;
336 	pcmd->prb.fis.lba_high = (block >> 16) & 0xff;
337 	pcmd->prb.fis.lba_mid = (block >> 8) & 0xff;
338 	pcmd->prb.fis.lba_low = block & 0xff;
339 	pcmd->prb.fis.device = ATA_LBA;
340 	pcmd->prb.fis.sector_count_exp = (blkcnt >> 8) & 0xff;
341 	pcmd->prb.fis.sector_count = blkcnt & 0xff;
342 
343 	pcmd->sge.addr = cpu_to_le64(virt_to_bus(sata->devno, buffer));
344 	pcmd->sge.cnt = cpu_to_le32(blkcnt * ATA_SECT_SIZE);
345 	pcmd->sge.flags = cpu_to_le32(SGE_TRM);
346 
347 	ret = sil_exec_cmd(dev, pcmd, 0);
348 	if (ret) {
349 		sil_read_fis(dev, 0, &fis);
350 		printf("Err: rw ext cmd(0x%08x).\n",
351 				readl(sata->port + PORT_SERROR));
352 		sil_sata_dump_fis(&fis);
353 		return 1;
354 	}
355 
356 	return blkcnt;
357 }
358 
sil_sata_rw_lba28(int dev,ulong blknr,lbaint_t blkcnt,const void * buffer,int is_write)359 static ulong sil_sata_rw_lba28(int dev, ulong blknr, lbaint_t blkcnt,
360 			       const void *buffer, int is_write)
361 {
362 	ulong start, blks, max_blks;
363 	u8 *addr;
364 
365 	start = blknr;
366 	blks = blkcnt;
367 	addr = (u8 *)buffer;
368 
369 	max_blks = ATA_MAX_SECTORS;
370 	do {
371 		if (blks > max_blks) {
372 			sil_sata_rw_cmd(dev, start, max_blks, addr, is_write);
373 			start += max_blks;
374 			blks -= max_blks;
375 			addr += ATA_SECT_SIZE * max_blks;
376 		} else {
377 			sil_sata_rw_cmd(dev, start, blks, addr, is_write);
378 			start += blks;
379 			blks = 0;
380 			addr += ATA_SECT_SIZE * blks;
381 		}
382 	} while (blks != 0);
383 
384 	return blkcnt;
385 }
386 
sil_sata_rw_lba48(int dev,ulong blknr,lbaint_t blkcnt,const void * buffer,int is_write)387 static ulong sil_sata_rw_lba48(int dev, ulong blknr, lbaint_t blkcnt,
388 			       const void *buffer, int is_write)
389 {
390 	ulong start, blks, max_blks;
391 	u8 *addr;
392 
393 	start = blknr;
394 	blks = blkcnt;
395 	addr = (u8 *)buffer;
396 
397 	max_blks = ATA_MAX_SECTORS_LBA48;
398 	do {
399 		if (blks > max_blks) {
400 			sil_sata_rw_cmd_ext(dev, start, max_blks,
401 					addr, is_write);
402 			start += max_blks;
403 			blks -= max_blks;
404 			addr += ATA_SECT_SIZE * max_blks;
405 		} else {
406 			sil_sata_rw_cmd_ext(dev, start, blks,
407 					addr, is_write);
408 			start += blks;
409 			blks = 0;
410 			addr += ATA_SECT_SIZE * blks;
411 		}
412 	} while (blks != 0);
413 
414 	return blkcnt;
415 }
416 
sil_sata_cmd_flush_cache(int dev)417 static void sil_sata_cmd_flush_cache(int dev)
418 {
419 	struct sil_cmd_block cmdb, *pcmd = &cmdb;
420 
421 	memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
422 	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
423 	pcmd->prb.fis.pm_port_c = (1 << 7);
424 	pcmd->prb.fis.command = ATA_CMD_FLUSH;
425 
426 	sil_exec_cmd(dev, pcmd, 0);
427 }
428 
sil_sata_cmd_flush_cache_ext(int dev)429 static void sil_sata_cmd_flush_cache_ext(int dev)
430 {
431 	struct sil_cmd_block cmdb, *pcmd = &cmdb;
432 
433 	memset((void *)pcmd, 0, sizeof(struct sil_cmd_block));
434 	pcmd->prb.fis.fis_type = SATA_FIS_TYPE_REGISTER_H2D;
435 	pcmd->prb.fis.pm_port_c = (1 << 7);
436 	pcmd->prb.fis.command = ATA_CMD_FLUSH_EXT;
437 
438 	sil_exec_cmd(dev, pcmd, 0);
439 }
440 
sil_sata_init_wcache(int dev,u16 * id)441 static void sil_sata_init_wcache(int dev, u16 *id)
442 {
443 	struct sil_sata *sata = sata_dev_desc[dev].priv;
444 
445 	if (ata_id_has_wcache(id) && ata_id_wcache_enabled(id))
446 		sata->wcache = 1;
447 	if (ata_id_has_flush(id))
448 		sata->flush = 1;
449 	if (ata_id_has_flush_ext(id))
450 		sata->flush_ext = 1;
451 }
452 
sil_sata_get_wcache(int dev)453 static int sil_sata_get_wcache(int dev)
454 {
455 	struct sil_sata *sata = sata_dev_desc[dev].priv;
456 
457 	return sata->wcache;
458 }
459 
sil_sata_get_flush(int dev)460 static int sil_sata_get_flush(int dev)
461 {
462 	struct sil_sata *sata = sata_dev_desc[dev].priv;
463 
464 	return sata->flush;
465 }
466 
sil_sata_get_flush_ext(int dev)467 static int sil_sata_get_flush_ext(int dev)
468 {
469 	struct sil_sata *sata = sata_dev_desc[dev].priv;
470 
471 	return sata->flush_ext;
472 }
473 
474 /*
475  * SATA interface between low level driver and command layer
476  */
sata_read(int dev,ulong blknr,lbaint_t blkcnt,void * buffer)477 ulong sata_read(int dev, ulong blknr, lbaint_t blkcnt, void *buffer)
478 {
479 	struct sil_sata *sata = sata_dev_desc[dev].priv;
480 	ulong rc;
481 
482 	if (sata->lba48)
483 		rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, READ_CMD);
484 	else
485 		rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, READ_CMD);
486 
487 	return rc;
488 }
489 
490 /*
491  * SATA interface between low level driver and command layer
492  */
sata_write(int dev,ulong blknr,lbaint_t blkcnt,const void * buffer)493 ulong sata_write(int dev, ulong blknr, lbaint_t blkcnt, const void *buffer)
494 {
495 	struct sil_sata *sata = sata_dev_desc[dev].priv;
496 	ulong rc;
497 
498 	if (sata->lba48) {
499 		rc = sil_sata_rw_lba48(dev, blknr, blkcnt, buffer, WRITE_CMD);
500 		if (sil_sata_get_wcache(dev) && sil_sata_get_flush_ext(dev))
501 			sil_sata_cmd_flush_cache_ext(dev);
502 	} else {
503 		rc = sil_sata_rw_lba28(dev, blknr, blkcnt, buffer, WRITE_CMD);
504 		if (sil_sata_get_wcache(dev) && sil_sata_get_flush(dev))
505 			sil_sata_cmd_flush_cache(dev);
506 	}
507 
508 	return rc;
509 }
510 
511 /*
512  * SATA interface between low level driver and command layer
513  */
init_sata(int dev)514 int init_sata(int dev)
515 {
516 	static int init_done, idx;
517 	pci_dev_t devno;
518 	u16 word;
519 
520 	if (init_done == 1 && dev < sata_info.maxport)
521 		return 0;
522 
523 	init_done = 1;
524 
525 	/* Find PCI device(s) */
526 	devno = pci_find_devices(supported, idx++);
527 	if (devno == -1)
528 		return 1;
529 
530 	pci_read_config_word(devno, PCI_DEVICE_ID, &word);
531 
532 	/* get the port count */
533 	word &= 0xf;
534 
535 	sata_info.portbase = sata_info.maxport;
536 	sata_info.maxport = sata_info.portbase + word;
537 	sata_info.devno = devno;
538 
539 	/* Read out all BARs */
540 	sata_info.iobase[0] = (ulong)pci_map_bar(devno,
541 			PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
542 	sata_info.iobase[1] = (ulong)pci_map_bar(devno,
543 			PCI_BASE_ADDRESS_2, PCI_REGION_MEM);
544 	sata_info.iobase[2] = (ulong)pci_map_bar(devno,
545 			PCI_BASE_ADDRESS_4, PCI_REGION_MEM);
546 
547 	/* mask out the unused bits */
548 	sata_info.iobase[0] &= 0xffffff80;
549 	sata_info.iobase[1] &= 0xfffffc00;
550 	sata_info.iobase[2] &= 0xffffff80;
551 
552 	/* Enable Bus Mastering and memory region */
553 	pci_write_config_word(devno, PCI_COMMAND,
554 			PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
555 
556 	/* Check if mem accesses and Bus Mastering are enabled. */
557 	pci_read_config_word(devno, PCI_COMMAND, &word);
558 	if (!(word & PCI_COMMAND_MEMORY) ||
559 			(!(word & PCI_COMMAND_MASTER))) {
560 		printf("Error: Can not enable MEM access or Bus Mastering.\n");
561 		debug("PCI command: %04x\n", word);
562 		return 1;
563 	}
564 
565 	/* GPIO off */
566 	writel(0, (void *)(sata_info.iobase[0] + HOST_FLASH_CMD));
567 	/* clear global reset & mask interrupts during initialization */
568 	writel(0, (void *)(sata_info.iobase[0] + HOST_CTRL));
569 
570 	return 0;
571 }
572 
reset_sata(int dev)573 int reset_sata(int dev)
574 {
575 	return 0;
576 }
577 
578 /*
579  * SATA interface between low level driver and command layer
580  */
scan_sata(int dev)581 int scan_sata(int dev)
582 {
583 	unsigned char serial[ATA_ID_SERNO_LEN + 1];
584 	unsigned char firmware[ATA_ID_FW_REV_LEN + 1];
585 	unsigned char product[ATA_ID_PROD_LEN + 1];
586 	struct sil_sata *sata;
587 	void *port;
588 	int cnt;
589 	u16 *id;
590 	u32 tmp;
591 
592 	if (dev >= sata_info.maxport) {
593 		printf("SATA#%d is not present\n", dev);
594 		return 1;
595 	}
596 
597 	printf("SATA#%d\n", dev);
598 	port = (void *)sata_info.iobase[1] +
599 		PORT_REGS_SIZE * (dev - sata_info.portbase);
600 
601 	/* Initial PHY setting */
602 	writel(0x20c, port + PORT_PHY_CFG);
603 
604 	/* clear port RST */
605 	tmp = readl(port + PORT_CTRL_STAT);
606 	if (tmp & PORT_CS_PORT_RST) {
607 		writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
608 		tmp = ata_wait_register(port + PORT_CTRL_STAT,
609 				PORT_CS_PORT_RST, PORT_CS_PORT_RST, 100);
610 		if (tmp & PORT_CS_PORT_RST)
611 			printf("Err: Failed to clear port RST\n");
612 	}
613 
614 	/* Check if device is present */
615 	for (cnt = 0; cnt < 100; cnt++) {
616 		tmp = readl(port + PORT_SSTATUS);
617 		if ((tmp & 0xF) == 0x3)
618 			break;
619 		mdelay(1);
620 	}
621 
622 	tmp = readl(port + PORT_SSTATUS);
623 	if ((tmp & 0xf) != 0x3) {
624 		printf("	(No RDY)\n");
625 		return 1;
626 	}
627 
628 	/* Wait for port ready */
629 	tmp = ata_wait_register(port + PORT_CTRL_STAT,
630 				PORT_CS_RDY, PORT_CS_RDY, 100);
631 	if ((tmp & PORT_CS_RDY) != PORT_CS_RDY) {
632 		printf("%d port not ready.\n", dev);
633 		return 1;
634 	}
635 
636 	/* configure port */
637 	sil_config_port(port);
638 
639 	/* Reset port */
640 	writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
641 	readl(port + PORT_CTRL_STAT);
642 	tmp = ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_DEV_RST,
643 				PORT_CS_DEV_RST, 100);
644 	if (tmp & PORT_CS_DEV_RST) {
645 		printf("%d port reset failed.\n", dev);
646 		return 1;
647 	}
648 
649 	sata = (struct sil_sata *)malloc(sizeof(struct sil_sata));
650 	if (!sata) {
651 		printf("%d no memory.\n", dev);
652 		return 1;
653 	}
654 	memset((void *)sata, 0, sizeof(struct sil_sata));
655 
656 	/* turn on port interrupt */
657 	tmp = readl((void *)(sata_info.iobase[0] + HOST_CTRL));
658 	tmp |= (1 << (dev - sata_info.portbase));
659 	writel(tmp, (void *)(sata_info.iobase[0] + HOST_CTRL));
660 
661 	/* Save the private struct to block device struct */
662 	sata_dev_desc[dev].priv = (void *)sata;
663 	sata->port = port;
664 	sata->devno = sata_info.devno;
665 	sprintf(sata->name, "SATA#%d", dev);
666 	sil_cmd_soft_reset(dev);
667 	tmp = readl(port + PORT_SSTATUS);
668 	tmp = (tmp >> 4) & 0xf;
669 	printf("	(%s)\n", sata_spd_string(tmp));
670 
671 	id = (u16 *)malloc(ATA_ID_WORDS * 2);
672 	if (!id) {
673 		printf("Id malloc failed\n");
674 		free((void *)sata);
675 		return 1;
676 	}
677 	sil_cmd_identify_device(dev, id);
678 
679 #ifdef CONFIG_LBA48
680 	/* Check if support LBA48 */
681 	if (ata_id_has_lba48(id)) {
682 		sata_dev_desc[dev].lba48 = 1;
683 		sata->lba48 = 1;
684 		debug("Device supports LBA48\n");
685 	} else
686 		debug("Device supports LBA28\n");
687 #endif
688 
689 	/* Serial number */
690 	ata_id_c_string(id, serial, ATA_ID_SERNO, sizeof(serial));
691 	memcpy(sata_dev_desc[dev].product, serial, sizeof(serial));
692 
693 	/* Firmware version */
694 	ata_id_c_string(id, firmware, ATA_ID_FW_REV, sizeof(firmware));
695 	memcpy(sata_dev_desc[dev].revision, firmware, sizeof(firmware));
696 
697 	/* Product model */
698 	ata_id_c_string(id, product, ATA_ID_PROD, sizeof(product));
699 	memcpy(sata_dev_desc[dev].vendor, product, sizeof(product));
700 
701 	/* Totoal sectors */
702 	sata_dev_desc[dev].lba = ata_id_n_sectors(id);
703 
704 	sil_sata_init_wcache(dev, id);
705 	sil_cmd_set_feature(dev);
706 
707 #ifdef DEBUG
708 	sil_cmd_identify_device(dev, id);
709 	ata_dump_id(id);
710 #endif
711 	free((void *)id);
712 
713 	return 0;
714 }
715