xref: /openbmc/qemu/hw/intc/sifive_plic.c (revision 45b1f81d)
1 /*
2  * SiFive PLIC (Platform Level Interrupt Controller)
3  *
4  * Copyright (c) 2017 SiFive, Inc.
5  *
6  * This provides a parameterizable interrupt controller based on SiFive's PLIC.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2 or later, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program.  If not, see <http://www.gnu.org/licenses/>.
19  */
20 
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "qemu/log.h"
24 #include "qemu/module.h"
25 #include "qemu/error-report.h"
26 #include "hw/sysbus.h"
27 #include "hw/pci/msi.h"
28 #include "hw/qdev-properties.h"
29 #include "hw/intc/sifive_plic.h"
30 #include "target/riscv/cpu.h"
31 #include "migration/vmstate.h"
32 #include "hw/irq.h"
33 #include "sysemu/kvm.h"
34 
addr_between(uint32_t addr,uint32_t base,uint32_t num)35 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
36 {
37     return addr >= base && addr - base < num;
38 }
39 
char_to_mode(char c)40 static PLICMode char_to_mode(char c)
41 {
42     switch (c) {
43     case 'U': return PLICMode_U;
44     case 'S': return PLICMode_S;
45     case 'M': return PLICMode_M;
46     default:
47         error_report("plic: invalid mode '%c'", c);
48         exit(1);
49     }
50 }
51 
atomic_set_masked(uint32_t * a,uint32_t mask,uint32_t value)52 static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
53 {
54     uint32_t old, new, cmp = qatomic_read(a);
55 
56     do {
57         old = cmp;
58         new = (old & ~mask) | (value & mask);
59         cmp = qatomic_cmpxchg(a, old, new);
60     } while (old != cmp);
61 
62     return old;
63 }
64 
sifive_plic_set_pending(SiFivePLICState * plic,int irq,bool level)65 static void sifive_plic_set_pending(SiFivePLICState *plic, int irq, bool level)
66 {
67     atomic_set_masked(&plic->pending[irq >> 5], 1 << (irq & 31), -!!level);
68 }
69 
sifive_plic_set_claimed(SiFivePLICState * plic,int irq,bool level)70 static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
71 {
72     atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
73 }
74 
sifive_plic_claimed(SiFivePLICState * plic,uint32_t addrid)75 static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
76 {
77     uint32_t max_irq = 0;
78     uint32_t max_prio = plic->target_priority[addrid];
79     int i, j;
80     int num_irq_in_word = 32;
81 
82     for (i = 0; i < plic->bitfield_words; i++) {
83         uint32_t pending_enabled_not_claimed =
84                         (plic->pending[i] & ~plic->claimed[i]) &
85                             plic->enable[addrid * plic->bitfield_words + i];
86 
87         if (!pending_enabled_not_claimed) {
88             continue;
89         }
90 
91         if (i == (plic->bitfield_words - 1)) {
92             /*
93              * If plic->num_sources is not multiple of 32, num-of-irq in last
94              * word is not 32. Compute the num-of-irq of last word to avoid
95              * out-of-bound access of source_priority array.
96              */
97             num_irq_in_word = plic->num_sources - ((plic->bitfield_words - 1) << 5);
98         }
99 
100         for (j = 0; j < num_irq_in_word; j++) {
101             int irq = (i << 5) + j;
102             uint32_t prio = plic->source_priority[irq];
103             int enabled = pending_enabled_not_claimed & (1 << j);
104 
105             if (enabled && prio > max_prio) {
106                 max_irq = irq;
107                 max_prio = prio;
108             }
109         }
110     }
111 
112     return max_irq;
113 }
114 
sifive_plic_update(SiFivePLICState * plic)115 static void sifive_plic_update(SiFivePLICState *plic)
116 {
117     int addrid;
118 
119     /* raise irq on harts where this irq is enabled */
120     for (addrid = 0; addrid < plic->num_addrs; addrid++) {
121         uint32_t hartid = plic->addr_config[addrid].hartid;
122         PLICMode mode = plic->addr_config[addrid].mode;
123         bool level = !!sifive_plic_claimed(plic, addrid);
124 
125         switch (mode) {
126         case PLICMode_M:
127             qemu_set_irq(plic->m_external_irqs[hartid - plic->hartid_base], level);
128             break;
129         case PLICMode_S:
130             qemu_set_irq(plic->s_external_irqs[hartid - plic->hartid_base], level);
131             break;
132         default:
133             break;
134         }
135     }
136 }
137 
sifive_plic_read(void * opaque,hwaddr addr,unsigned size)138 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
139 {
140     SiFivePLICState *plic = opaque;
141 
142     if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
143         uint32_t irq = (addr - plic->priority_base) >> 2;
144 
145         return plic->source_priority[irq];
146     } else if (addr_between(addr, plic->pending_base,
147                             (plic->num_sources + 31) >> 3)) {
148         uint32_t word = (addr - plic->pending_base) >> 2;
149 
150         return plic->pending[word];
151     } else if (addr_between(addr, plic->enable_base,
152                             plic->num_addrs * plic->enable_stride)) {
153         uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
154         uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
155 
156         if (wordid < plic->bitfield_words) {
157             return plic->enable[addrid * plic->bitfield_words + wordid];
158         }
159     } else if (addr_between(addr, plic->context_base,
160                             plic->num_addrs * plic->context_stride)) {
161         uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
162         uint32_t contextid = (addr & (plic->context_stride - 1));
163 
164         if (contextid == 0) {
165             return plic->target_priority[addrid];
166         } else if (contextid == 4) {
167             uint32_t max_irq = sifive_plic_claimed(plic, addrid);
168 
169             if (max_irq) {
170                 sifive_plic_set_pending(plic, max_irq, false);
171                 sifive_plic_set_claimed(plic, max_irq, true);
172             }
173 
174             sifive_plic_update(plic);
175             return max_irq;
176         }
177     }
178 
179     qemu_log_mask(LOG_GUEST_ERROR,
180                   "%s: Invalid register read 0x%" HWADDR_PRIx "\n",
181                   __func__, addr);
182     return 0;
183 }
184 
sifive_plic_write(void * opaque,hwaddr addr,uint64_t value,unsigned size)185 static void sifive_plic_write(void *opaque, hwaddr addr, uint64_t value,
186         unsigned size)
187 {
188     SiFivePLICState *plic = opaque;
189 
190     if (addr_between(addr, plic->priority_base, plic->num_sources << 2)) {
191         uint32_t irq = (addr - plic->priority_base) >> 2;
192 
193         if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
194             /*
195              * if "num_priorities + 1" is power-of-2, make each register bit of
196              * interrupt priority WARL (Write-Any-Read-Legal). Just filter
197              * out the access to unsupported priority bits.
198              */
199             plic->source_priority[irq] = value % (plic->num_priorities + 1);
200             sifive_plic_update(plic);
201         } else if (value <= plic->num_priorities) {
202             plic->source_priority[irq] = value;
203             sifive_plic_update(plic);
204         }
205     } else if (addr_between(addr, plic->pending_base,
206                             (plic->num_sources + 31) >> 3)) {
207         qemu_log_mask(LOG_GUEST_ERROR,
208                       "%s: invalid pending write: 0x%" HWADDR_PRIx "",
209                       __func__, addr);
210     } else if (addr_between(addr, plic->enable_base,
211                             plic->num_addrs * plic->enable_stride)) {
212         uint32_t addrid = (addr - plic->enable_base) / plic->enable_stride;
213         uint32_t wordid = (addr & (plic->enable_stride - 1)) >> 2;
214 
215         if (wordid < plic->bitfield_words) {
216             plic->enable[addrid * plic->bitfield_words + wordid] = value;
217         } else {
218             qemu_log_mask(LOG_GUEST_ERROR,
219                           "%s: Invalid enable write 0x%" HWADDR_PRIx "\n",
220                           __func__, addr);
221         }
222     } else if (addr_between(addr, plic->context_base,
223                             plic->num_addrs * plic->context_stride)) {
224         uint32_t addrid = (addr - plic->context_base) / plic->context_stride;
225         uint32_t contextid = (addr & (plic->context_stride - 1));
226 
227         if (contextid == 0) {
228             if (((plic->num_priorities + 1) & plic->num_priorities) == 0) {
229                 /*
230                  * if "num_priorities + 1" is power-of-2, each register bit of
231                  * interrupt priority is WARL (Write-Any-Read-Legal). Just
232                  * filter out the access to unsupported priority bits.
233                  */
234                 plic->target_priority[addrid] = value %
235                                                 (plic->num_priorities + 1);
236                 sifive_plic_update(plic);
237             } else if (value <= plic->num_priorities) {
238                 plic->target_priority[addrid] = value;
239                 sifive_plic_update(plic);
240             }
241         } else if (contextid == 4) {
242             if (value < plic->num_sources) {
243                 sifive_plic_set_claimed(plic, value, false);
244                 sifive_plic_update(plic);
245             }
246         } else {
247             qemu_log_mask(LOG_GUEST_ERROR,
248                           "%s: Invalid context write 0x%" HWADDR_PRIx "\n",
249                           __func__, addr);
250         }
251     } else {
252         qemu_log_mask(LOG_GUEST_ERROR,
253                       "%s: Invalid register write 0x%" HWADDR_PRIx "\n",
254                       __func__, addr);
255     }
256 }
257 
258 static const MemoryRegionOps sifive_plic_ops = {
259     .read = sifive_plic_read,
260     .write = sifive_plic_write,
261     .endianness = DEVICE_LITTLE_ENDIAN,
262     .valid = {
263         .min_access_size = 4,
264         .max_access_size = 4
265     }
266 };
267 
sifive_plic_reset(DeviceState * dev)268 static void sifive_plic_reset(DeviceState *dev)
269 {
270     SiFivePLICState *s = SIFIVE_PLIC(dev);
271     int i;
272 
273     memset(s->source_priority, 0, sizeof(uint32_t) * s->num_sources);
274     memset(s->target_priority, 0, sizeof(uint32_t) * s->num_addrs);
275     memset(s->pending, 0, sizeof(uint32_t) * s->bitfield_words);
276     memset(s->claimed, 0, sizeof(uint32_t) * s->bitfield_words);
277     memset(s->enable, 0, sizeof(uint32_t) * s->num_enables);
278 
279     for (i = 0; i < s->num_harts; i++) {
280         qemu_set_irq(s->m_external_irqs[i], 0);
281         qemu_set_irq(s->s_external_irqs[i], 0);
282     }
283 }
284 
285 /*
286  * parse PLIC hart/mode address offset config
287  *
288  * "M"              1 hart with M mode
289  * "MS,MS"          2 harts, 0-1 with M and S mode
290  * "M,MS,MS,MS,MS"  5 harts, 0 with M mode, 1-5 with M and S mode
291  */
parse_hart_config(SiFivePLICState * plic)292 static void parse_hart_config(SiFivePLICState *plic)
293 {
294     int addrid, hartid, modes, m;
295     const char *p;
296     char c;
297 
298     /* count and validate hart/mode combinations */
299     addrid = 0, hartid = 0, modes = 0;
300     p = plic->hart_config;
301     while ((c = *p++)) {
302         if (c == ',') {
303             if (modes) {
304                 addrid += ctpop8(modes);
305                 hartid++;
306                 modes = 0;
307             }
308         } else {
309             m = 1 << char_to_mode(c);
310             if (modes == (modes | m)) {
311                 error_report("plic: duplicate mode '%c' in config: %s",
312                              c, plic->hart_config);
313                 exit(1);
314             }
315             modes |= m;
316         }
317     }
318     if (modes) {
319         addrid += ctpop8(modes);
320         hartid++;
321         modes = 0;
322     }
323 
324     plic->num_addrs = addrid;
325     plic->num_harts = hartid;
326 
327     /* store hart/mode combinations */
328     plic->addr_config = g_new(PLICAddr, plic->num_addrs);
329     addrid = 0, hartid = plic->hartid_base;
330     p = plic->hart_config;
331     while ((c = *p++)) {
332         if (c == ',') {
333             if (modes) {
334                 hartid++;
335                 modes = 0;
336             }
337         } else {
338             m = char_to_mode(c);
339             plic->addr_config[addrid].addrid = addrid;
340             plic->addr_config[addrid].hartid = hartid;
341             plic->addr_config[addrid].mode = m;
342             modes |= (1 << m);
343             addrid++;
344         }
345     }
346 }
347 
sifive_plic_irq_request(void * opaque,int irq,int level)348 static void sifive_plic_irq_request(void *opaque, int irq, int level)
349 {
350     SiFivePLICState *s = opaque;
351 
352     sifive_plic_set_pending(s, irq, level > 0);
353     sifive_plic_update(s);
354 }
355 
sifive_plic_realize(DeviceState * dev,Error ** errp)356 static void sifive_plic_realize(DeviceState *dev, Error **errp)
357 {
358     SiFivePLICState *s = SIFIVE_PLIC(dev);
359     int i;
360 
361     memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_plic_ops, s,
362                           TYPE_SIFIVE_PLIC, s->aperture_size);
363     sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio);
364 
365     parse_hart_config(s);
366 
367     if (!s->num_sources) {
368         error_setg(errp, "plic: invalid number of interrupt sources");
369         return;
370     }
371 
372     s->bitfield_words = (s->num_sources + 31) >> 5;
373     s->num_enables = s->bitfield_words * s->num_addrs;
374     s->source_priority = g_new0(uint32_t, s->num_sources);
375     s->target_priority = g_new(uint32_t, s->num_addrs);
376     s->pending = g_new0(uint32_t, s->bitfield_words);
377     s->claimed = g_new0(uint32_t, s->bitfield_words);
378     s->enable = g_new0(uint32_t, s->num_enables);
379 
380     qdev_init_gpio_in(dev, sifive_plic_irq_request, s->num_sources);
381 
382     s->s_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
383     qdev_init_gpio_out(dev, s->s_external_irqs, s->num_harts);
384 
385     s->m_external_irqs = g_malloc(sizeof(qemu_irq) * s->num_harts);
386     qdev_init_gpio_out(dev, s->m_external_irqs, s->num_harts);
387 
388     /*
389      * We can't allow the supervisor to control SEIP as this would allow the
390      * supervisor to clear a pending external interrupt which will result in
391      * lost a interrupt in the case a PLIC is attached. The SEIP bit must be
392      * hardware controlled when a PLIC is attached.
393      */
394     for (i = 0; i < s->num_harts; i++) {
395         RISCVCPU *cpu = RISCV_CPU(qemu_get_cpu(s->hartid_base + i));
396         if (riscv_cpu_claim_interrupts(cpu, MIP_SEIP) < 0) {
397             error_setg(errp, "SEIP already claimed");
398             return;
399         }
400     }
401 
402     msi_nonbroken = true;
403 }
404 
405 static const VMStateDescription vmstate_sifive_plic = {
406     .name = "riscv_sifive_plic",
407     .version_id = 1,
408     .minimum_version_id = 1,
409     .fields = (const VMStateField[]) {
410             VMSTATE_VARRAY_UINT32(source_priority, SiFivePLICState,
411                                   num_sources, 0,
412                                   vmstate_info_uint32, uint32_t),
413             VMSTATE_VARRAY_UINT32(target_priority, SiFivePLICState,
414                                   num_addrs, 0,
415                                   vmstate_info_uint32, uint32_t),
416             VMSTATE_VARRAY_UINT32(pending, SiFivePLICState, bitfield_words, 0,
417                                   vmstate_info_uint32, uint32_t),
418             VMSTATE_VARRAY_UINT32(claimed, SiFivePLICState, bitfield_words, 0,
419                                   vmstate_info_uint32, uint32_t),
420             VMSTATE_VARRAY_UINT32(enable, SiFivePLICState, num_enables, 0,
421                                   vmstate_info_uint32, uint32_t),
422             VMSTATE_END_OF_LIST()
423         }
424 };
425 
426 static Property sifive_plic_properties[] = {
427     DEFINE_PROP_STRING("hart-config", SiFivePLICState, hart_config),
428     DEFINE_PROP_UINT32("hartid-base", SiFivePLICState, hartid_base, 0),
429     /* number of interrupt sources including interrupt source 0 */
430     DEFINE_PROP_UINT32("num-sources", SiFivePLICState, num_sources, 1),
431     DEFINE_PROP_UINT32("num-priorities", SiFivePLICState, num_priorities, 0),
432     /* interrupt priority register base starting from source 0 */
433     DEFINE_PROP_UINT32("priority-base", SiFivePLICState, priority_base, 0),
434     DEFINE_PROP_UINT32("pending-base", SiFivePLICState, pending_base, 0),
435     DEFINE_PROP_UINT32("enable-base", SiFivePLICState, enable_base, 0),
436     DEFINE_PROP_UINT32("enable-stride", SiFivePLICState, enable_stride, 0),
437     DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0),
438     DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0),
439     DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0),
440     DEFINE_PROP_END_OF_LIST(),
441 };
442 
sifive_plic_class_init(ObjectClass * klass,void * data)443 static void sifive_plic_class_init(ObjectClass *klass, void *data)
444 {
445     DeviceClass *dc = DEVICE_CLASS(klass);
446 
447     dc->reset = sifive_plic_reset;
448     device_class_set_props(dc, sifive_plic_properties);
449     dc->realize = sifive_plic_realize;
450     dc->vmsd = &vmstate_sifive_plic;
451 }
452 
453 static const TypeInfo sifive_plic_info = {
454     .name          = TYPE_SIFIVE_PLIC,
455     .parent        = TYPE_SYS_BUS_DEVICE,
456     .instance_size = sizeof(SiFivePLICState),
457     .class_init    = sifive_plic_class_init,
458 };
459 
sifive_plic_register_types(void)460 static void sifive_plic_register_types(void)
461 {
462     type_register_static(&sifive_plic_info);
463 }
464 
type_init(sifive_plic_register_types)465 type_init(sifive_plic_register_types)
466 
467 /*
468  * Create PLIC device.
469  */
470 DeviceState *sifive_plic_create(hwaddr addr, char *hart_config,
471     uint32_t num_harts,
472     uint32_t hartid_base, uint32_t num_sources,
473     uint32_t num_priorities, uint32_t priority_base,
474     uint32_t pending_base, uint32_t enable_base,
475     uint32_t enable_stride, uint32_t context_base,
476     uint32_t context_stride, uint32_t aperture_size)
477 {
478     DeviceState *dev = qdev_new(TYPE_SIFIVE_PLIC);
479     int i;
480     SiFivePLICState *plic;
481 
482     assert(enable_stride == (enable_stride & -enable_stride));
483     assert(context_stride == (context_stride & -context_stride));
484     qdev_prop_set_string(dev, "hart-config", hart_config);
485     qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
486     qdev_prop_set_uint32(dev, "num-sources", num_sources);
487     qdev_prop_set_uint32(dev, "num-priorities", num_priorities);
488     qdev_prop_set_uint32(dev, "priority-base", priority_base);
489     qdev_prop_set_uint32(dev, "pending-base", pending_base);
490     qdev_prop_set_uint32(dev, "enable-base", enable_base);
491     qdev_prop_set_uint32(dev, "enable-stride", enable_stride);
492     qdev_prop_set_uint32(dev, "context-base", context_base);
493     qdev_prop_set_uint32(dev, "context-stride", context_stride);
494     qdev_prop_set_uint32(dev, "aperture-size", aperture_size);
495     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
496     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr);
497 
498     plic = SIFIVE_PLIC(dev);
499 
500     for (i = 0; i < plic->num_addrs; i++) {
501         int cpu_num = plic->addr_config[i].hartid;
502         CPUState *cpu = qemu_get_cpu(cpu_num);
503 
504         if (plic->addr_config[i].mode == PLICMode_M) {
505             qdev_connect_gpio_out(dev, cpu_num - hartid_base + num_harts,
506                                   qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
507         }
508         if (plic->addr_config[i].mode == PLICMode_S) {
509             qdev_connect_gpio_out(dev, cpu_num - hartid_base,
510                                   qdev_get_gpio_in(DEVICE(cpu), IRQ_S_EXT));
511         }
512     }
513 
514     return dev;
515 }
516