1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28
29 #include <linux/console.h>
30 #include <linux/pci.h>
31 #include <linux/vgaarb.h>
32
33 #include <drm/radeon_drm.h>
34
35 #include "atom.h"
36 #include "radeon.h"
37 #include "radeon_asic.h"
38 #include "radeon_reg.h"
39
40 /*
41 * Registers accessors functions.
42 */
43 /**
44 * radeon_invalid_rreg - dummy reg read function
45 *
46 * @rdev: radeon device pointer
47 * @reg: offset of register
48 *
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
52 */
radeon_invalid_rreg(struct radeon_device * rdev,uint32_t reg)53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
54 {
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
56 BUG_ON(1);
57 return 0;
58 }
59
60 /**
61 * radeon_invalid_wreg - dummy reg write function
62 *
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
66 *
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
69 */
radeon_invalid_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
71 {
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
73 reg, v);
74 BUG_ON(1);
75 }
76
77 /**
78 * radeon_register_accessor_init - sets up the register accessor callbacks
79 *
80 * @rdev: radeon device pointer
81 *
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
84 */
radeon_register_accessor_init(struct radeon_device * rdev)85 static void radeon_register_accessor_init(struct radeon_device *rdev)
86 {
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
93
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
97 } else {
98 rdev->pcie_reg_mask = 0x7ff;
99 }
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
104 }
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
108 }
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
112 }
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
116 }
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
120 }
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
124 }
125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
128 }
129
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
136 }
137 }
138
radeon_invalid_get_allowed_info_register(struct radeon_device * rdev,u32 reg,u32 * val)139 static int radeon_invalid_get_allowed_info_register(struct radeon_device *rdev,
140 u32 reg, u32 *val)
141 {
142 return -EINVAL;
143 }
144
145 /* helper to disable agp */
146 /**
147 * radeon_agp_disable - AGP disable helper function
148 *
149 * @rdev: radeon device pointer
150 *
151 * Removes AGP flags and changes the gart callbacks on AGP
152 * cards when using the internal gart rather than AGP (all asics).
153 */
radeon_agp_disable(struct radeon_device * rdev)154 void radeon_agp_disable(struct radeon_device *rdev)
155 {
156 rdev->flags &= ~RADEON_IS_AGP;
157 if (rdev->family >= CHIP_R600) {
158 DRM_INFO("Forcing AGP to PCIE mode\n");
159 rdev->flags |= RADEON_IS_PCIE;
160 } else if (rdev->family >= CHIP_RV515 ||
161 rdev->family == CHIP_RV380 ||
162 rdev->family == CHIP_RV410 ||
163 rdev->family == CHIP_R423) {
164 DRM_INFO("Forcing AGP to PCIE mode\n");
165 rdev->flags |= RADEON_IS_PCIE;
166 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
167 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
168 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
169 } else {
170 DRM_INFO("Forcing AGP to PCI mode\n");
171 rdev->flags |= RADEON_IS_PCI;
172 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
173 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
174 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
175 }
176 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
177 }
178
179 /*
180 * ASIC
181 */
182
183 static const struct radeon_asic_ring r100_gfx_ring = {
184 .ib_execute = &r100_ring_ib_execute,
185 .emit_fence = &r100_fence_ring_emit,
186 .emit_semaphore = &r100_semaphore_ring_emit,
187 .cs_parse = &r100_cs_parse,
188 .ring_start = &r100_ring_start,
189 .ring_test = &r100_ring_test,
190 .ib_test = &r100_ib_test,
191 .is_lockup = &r100_gpu_is_lockup,
192 .get_rptr = &r100_gfx_get_rptr,
193 .get_wptr = &r100_gfx_get_wptr,
194 .set_wptr = &r100_gfx_set_wptr,
195 };
196
197 static struct radeon_asic r100_asic = {
198 .init = &r100_init,
199 .fini = &r100_fini,
200 .suspend = &r100_suspend,
201 .resume = &r100_resume,
202 .vga_set_state = &r100_vga_set_state,
203 .asic_reset = &r100_asic_reset,
204 .mmio_hdp_flush = NULL,
205 .gui_idle = &r100_gui_idle,
206 .mc_wait_for_idle = &r100_mc_wait_for_idle,
207 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
208 .gart = {
209 .tlb_flush = &r100_pci_gart_tlb_flush,
210 .get_page_entry = &r100_pci_gart_get_page_entry,
211 .set_page = &r100_pci_gart_set_page,
212 },
213 .ring = {
214 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
215 },
216 .irq = {
217 .set = &r100_irq_set,
218 .process = &r100_irq_process,
219 },
220 .display = {
221 .bandwidth_update = &r100_bandwidth_update,
222 .get_vblank_counter = &r100_get_vblank_counter,
223 .wait_for_vblank = &r100_wait_for_vblank,
224 .set_backlight_level = &radeon_legacy_set_backlight_level,
225 .get_backlight_level = &radeon_legacy_get_backlight_level,
226 },
227 .copy = {
228 .blit = &r100_copy_blit,
229 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
230 .dma = NULL,
231 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
232 .copy = &r100_copy_blit,
233 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
234 },
235 .surface = {
236 .set_reg = r100_set_surface_reg,
237 .clear_reg = r100_clear_surface_reg,
238 },
239 .hpd = {
240 .init = &r100_hpd_init,
241 .fini = &r100_hpd_fini,
242 .sense = &r100_hpd_sense,
243 .set_polarity = &r100_hpd_set_polarity,
244 },
245 .pm = {
246 .misc = &r100_pm_misc,
247 .prepare = &r100_pm_prepare,
248 .finish = &r100_pm_finish,
249 .init_profile = &r100_pm_init_profile,
250 .get_dynpm_state = &r100_pm_get_dynpm_state,
251 .get_engine_clock = &radeon_legacy_get_engine_clock,
252 .set_engine_clock = &radeon_legacy_set_engine_clock,
253 .get_memory_clock = &radeon_legacy_get_memory_clock,
254 .set_memory_clock = NULL,
255 .get_pcie_lanes = NULL,
256 .set_pcie_lanes = NULL,
257 .set_clock_gating = &radeon_legacy_set_clock_gating,
258 },
259 .pflip = {
260 .page_flip = &r100_page_flip,
261 .page_flip_pending = &r100_page_flip_pending,
262 },
263 };
264
265 static struct radeon_asic r200_asic = {
266 .init = &r100_init,
267 .fini = &r100_fini,
268 .suspend = &r100_suspend,
269 .resume = &r100_resume,
270 .vga_set_state = &r100_vga_set_state,
271 .asic_reset = &r100_asic_reset,
272 .mmio_hdp_flush = NULL,
273 .gui_idle = &r100_gui_idle,
274 .mc_wait_for_idle = &r100_mc_wait_for_idle,
275 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
276 .gart = {
277 .tlb_flush = &r100_pci_gart_tlb_flush,
278 .get_page_entry = &r100_pci_gart_get_page_entry,
279 .set_page = &r100_pci_gart_set_page,
280 },
281 .ring = {
282 [RADEON_RING_TYPE_GFX_INDEX] = &r100_gfx_ring
283 },
284 .irq = {
285 .set = &r100_irq_set,
286 .process = &r100_irq_process,
287 },
288 .display = {
289 .bandwidth_update = &r100_bandwidth_update,
290 .get_vblank_counter = &r100_get_vblank_counter,
291 .wait_for_vblank = &r100_wait_for_vblank,
292 .set_backlight_level = &radeon_legacy_set_backlight_level,
293 .get_backlight_level = &radeon_legacy_get_backlight_level,
294 },
295 .copy = {
296 .blit = &r100_copy_blit,
297 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
298 .dma = &r200_copy_dma,
299 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
300 .copy = &r100_copy_blit,
301 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
302 },
303 .surface = {
304 .set_reg = r100_set_surface_reg,
305 .clear_reg = r100_clear_surface_reg,
306 },
307 .hpd = {
308 .init = &r100_hpd_init,
309 .fini = &r100_hpd_fini,
310 .sense = &r100_hpd_sense,
311 .set_polarity = &r100_hpd_set_polarity,
312 },
313 .pm = {
314 .misc = &r100_pm_misc,
315 .prepare = &r100_pm_prepare,
316 .finish = &r100_pm_finish,
317 .init_profile = &r100_pm_init_profile,
318 .get_dynpm_state = &r100_pm_get_dynpm_state,
319 .get_engine_clock = &radeon_legacy_get_engine_clock,
320 .set_engine_clock = &radeon_legacy_set_engine_clock,
321 .get_memory_clock = &radeon_legacy_get_memory_clock,
322 .set_memory_clock = NULL,
323 .get_pcie_lanes = NULL,
324 .set_pcie_lanes = NULL,
325 .set_clock_gating = &radeon_legacy_set_clock_gating,
326 },
327 .pflip = {
328 .page_flip = &r100_page_flip,
329 .page_flip_pending = &r100_page_flip_pending,
330 },
331 };
332
333 static const struct radeon_asic_ring r300_gfx_ring = {
334 .ib_execute = &r100_ring_ib_execute,
335 .emit_fence = &r300_fence_ring_emit,
336 .emit_semaphore = &r100_semaphore_ring_emit,
337 .cs_parse = &r300_cs_parse,
338 .ring_start = &r300_ring_start,
339 .ring_test = &r100_ring_test,
340 .ib_test = &r100_ib_test,
341 .is_lockup = &r100_gpu_is_lockup,
342 .get_rptr = &r100_gfx_get_rptr,
343 .get_wptr = &r100_gfx_get_wptr,
344 .set_wptr = &r100_gfx_set_wptr,
345 };
346
347 static const struct radeon_asic_ring rv515_gfx_ring = {
348 .ib_execute = &r100_ring_ib_execute,
349 .emit_fence = &r300_fence_ring_emit,
350 .emit_semaphore = &r100_semaphore_ring_emit,
351 .cs_parse = &r300_cs_parse,
352 .ring_start = &rv515_ring_start,
353 .ring_test = &r100_ring_test,
354 .ib_test = &r100_ib_test,
355 .is_lockup = &r100_gpu_is_lockup,
356 .get_rptr = &r100_gfx_get_rptr,
357 .get_wptr = &r100_gfx_get_wptr,
358 .set_wptr = &r100_gfx_set_wptr,
359 };
360
361 static struct radeon_asic r300_asic = {
362 .init = &r300_init,
363 .fini = &r300_fini,
364 .suspend = &r300_suspend,
365 .resume = &r300_resume,
366 .vga_set_state = &r100_vga_set_state,
367 .asic_reset = &r300_asic_reset,
368 .mmio_hdp_flush = NULL,
369 .gui_idle = &r100_gui_idle,
370 .mc_wait_for_idle = &r300_mc_wait_for_idle,
371 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
372 .gart = {
373 .tlb_flush = &r100_pci_gart_tlb_flush,
374 .get_page_entry = &r100_pci_gart_get_page_entry,
375 .set_page = &r100_pci_gart_set_page,
376 },
377 .ring = {
378 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
379 },
380 .irq = {
381 .set = &r100_irq_set,
382 .process = &r100_irq_process,
383 },
384 .display = {
385 .bandwidth_update = &r100_bandwidth_update,
386 .get_vblank_counter = &r100_get_vblank_counter,
387 .wait_for_vblank = &r100_wait_for_vblank,
388 .set_backlight_level = &radeon_legacy_set_backlight_level,
389 .get_backlight_level = &radeon_legacy_get_backlight_level,
390 },
391 .copy = {
392 .blit = &r100_copy_blit,
393 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
394 .dma = &r200_copy_dma,
395 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
396 .copy = &r100_copy_blit,
397 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
398 },
399 .surface = {
400 .set_reg = r100_set_surface_reg,
401 .clear_reg = r100_clear_surface_reg,
402 },
403 .hpd = {
404 .init = &r100_hpd_init,
405 .fini = &r100_hpd_fini,
406 .sense = &r100_hpd_sense,
407 .set_polarity = &r100_hpd_set_polarity,
408 },
409 .pm = {
410 .misc = &r100_pm_misc,
411 .prepare = &r100_pm_prepare,
412 .finish = &r100_pm_finish,
413 .init_profile = &r100_pm_init_profile,
414 .get_dynpm_state = &r100_pm_get_dynpm_state,
415 .get_engine_clock = &radeon_legacy_get_engine_clock,
416 .set_engine_clock = &radeon_legacy_set_engine_clock,
417 .get_memory_clock = &radeon_legacy_get_memory_clock,
418 .set_memory_clock = NULL,
419 .get_pcie_lanes = &rv370_get_pcie_lanes,
420 .set_pcie_lanes = &rv370_set_pcie_lanes,
421 .set_clock_gating = &radeon_legacy_set_clock_gating,
422 },
423 .pflip = {
424 .page_flip = &r100_page_flip,
425 .page_flip_pending = &r100_page_flip_pending,
426 },
427 };
428
429 static struct radeon_asic r300_asic_pcie = {
430 .init = &r300_init,
431 .fini = &r300_fini,
432 .suspend = &r300_suspend,
433 .resume = &r300_resume,
434 .vga_set_state = &r100_vga_set_state,
435 .asic_reset = &r300_asic_reset,
436 .mmio_hdp_flush = NULL,
437 .gui_idle = &r100_gui_idle,
438 .mc_wait_for_idle = &r300_mc_wait_for_idle,
439 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
440 .gart = {
441 .tlb_flush = &rv370_pcie_gart_tlb_flush,
442 .get_page_entry = &rv370_pcie_gart_get_page_entry,
443 .set_page = &rv370_pcie_gart_set_page,
444 },
445 .ring = {
446 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
447 },
448 .irq = {
449 .set = &r100_irq_set,
450 .process = &r100_irq_process,
451 },
452 .display = {
453 .bandwidth_update = &r100_bandwidth_update,
454 .get_vblank_counter = &r100_get_vblank_counter,
455 .wait_for_vblank = &r100_wait_for_vblank,
456 .set_backlight_level = &radeon_legacy_set_backlight_level,
457 .get_backlight_level = &radeon_legacy_get_backlight_level,
458 },
459 .copy = {
460 .blit = &r100_copy_blit,
461 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
462 .dma = &r200_copy_dma,
463 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
464 .copy = &r100_copy_blit,
465 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
466 },
467 .surface = {
468 .set_reg = r100_set_surface_reg,
469 .clear_reg = r100_clear_surface_reg,
470 },
471 .hpd = {
472 .init = &r100_hpd_init,
473 .fini = &r100_hpd_fini,
474 .sense = &r100_hpd_sense,
475 .set_polarity = &r100_hpd_set_polarity,
476 },
477 .pm = {
478 .misc = &r100_pm_misc,
479 .prepare = &r100_pm_prepare,
480 .finish = &r100_pm_finish,
481 .init_profile = &r100_pm_init_profile,
482 .get_dynpm_state = &r100_pm_get_dynpm_state,
483 .get_engine_clock = &radeon_legacy_get_engine_clock,
484 .set_engine_clock = &radeon_legacy_set_engine_clock,
485 .get_memory_clock = &radeon_legacy_get_memory_clock,
486 .set_memory_clock = NULL,
487 .get_pcie_lanes = &rv370_get_pcie_lanes,
488 .set_pcie_lanes = &rv370_set_pcie_lanes,
489 .set_clock_gating = &radeon_legacy_set_clock_gating,
490 },
491 .pflip = {
492 .page_flip = &r100_page_flip,
493 .page_flip_pending = &r100_page_flip_pending,
494 },
495 };
496
497 static struct radeon_asic r420_asic = {
498 .init = &r420_init,
499 .fini = &r420_fini,
500 .suspend = &r420_suspend,
501 .resume = &r420_resume,
502 .vga_set_state = &r100_vga_set_state,
503 .asic_reset = &r300_asic_reset,
504 .mmio_hdp_flush = NULL,
505 .gui_idle = &r100_gui_idle,
506 .mc_wait_for_idle = &r300_mc_wait_for_idle,
507 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
508 .gart = {
509 .tlb_flush = &rv370_pcie_gart_tlb_flush,
510 .get_page_entry = &rv370_pcie_gart_get_page_entry,
511 .set_page = &rv370_pcie_gart_set_page,
512 },
513 .ring = {
514 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
515 },
516 .irq = {
517 .set = &r100_irq_set,
518 .process = &r100_irq_process,
519 },
520 .display = {
521 .bandwidth_update = &r100_bandwidth_update,
522 .get_vblank_counter = &r100_get_vblank_counter,
523 .wait_for_vblank = &r100_wait_for_vblank,
524 .set_backlight_level = &atombios_set_backlight_level,
525 .get_backlight_level = &atombios_get_backlight_level,
526 },
527 .copy = {
528 .blit = &r100_copy_blit,
529 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
530 .dma = &r200_copy_dma,
531 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
532 .copy = &r100_copy_blit,
533 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
534 },
535 .surface = {
536 .set_reg = r100_set_surface_reg,
537 .clear_reg = r100_clear_surface_reg,
538 },
539 .hpd = {
540 .init = &r100_hpd_init,
541 .fini = &r100_hpd_fini,
542 .sense = &r100_hpd_sense,
543 .set_polarity = &r100_hpd_set_polarity,
544 },
545 .pm = {
546 .misc = &r100_pm_misc,
547 .prepare = &r100_pm_prepare,
548 .finish = &r100_pm_finish,
549 .init_profile = &r420_pm_init_profile,
550 .get_dynpm_state = &r100_pm_get_dynpm_state,
551 .get_engine_clock = &radeon_atom_get_engine_clock,
552 .set_engine_clock = &radeon_atom_set_engine_clock,
553 .get_memory_clock = &radeon_atom_get_memory_clock,
554 .set_memory_clock = &radeon_atom_set_memory_clock,
555 .get_pcie_lanes = &rv370_get_pcie_lanes,
556 .set_pcie_lanes = &rv370_set_pcie_lanes,
557 .set_clock_gating = &radeon_atom_set_clock_gating,
558 },
559 .pflip = {
560 .page_flip = &r100_page_flip,
561 .page_flip_pending = &r100_page_flip_pending,
562 },
563 };
564
565 static struct radeon_asic rs400_asic = {
566 .init = &rs400_init,
567 .fini = &rs400_fini,
568 .suspend = &rs400_suspend,
569 .resume = &rs400_resume,
570 .vga_set_state = &r100_vga_set_state,
571 .asic_reset = &r300_asic_reset,
572 .mmio_hdp_flush = NULL,
573 .gui_idle = &r100_gui_idle,
574 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
575 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
576 .gart = {
577 .tlb_flush = &rs400_gart_tlb_flush,
578 .get_page_entry = &rs400_gart_get_page_entry,
579 .set_page = &rs400_gart_set_page,
580 },
581 .ring = {
582 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
583 },
584 .irq = {
585 .set = &r100_irq_set,
586 .process = &r100_irq_process,
587 },
588 .display = {
589 .bandwidth_update = &r100_bandwidth_update,
590 .get_vblank_counter = &r100_get_vblank_counter,
591 .wait_for_vblank = &r100_wait_for_vblank,
592 .set_backlight_level = &radeon_legacy_set_backlight_level,
593 .get_backlight_level = &radeon_legacy_get_backlight_level,
594 },
595 .copy = {
596 .blit = &r100_copy_blit,
597 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
598 .dma = &r200_copy_dma,
599 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
600 .copy = &r100_copy_blit,
601 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
602 },
603 .surface = {
604 .set_reg = r100_set_surface_reg,
605 .clear_reg = r100_clear_surface_reg,
606 },
607 .hpd = {
608 .init = &r100_hpd_init,
609 .fini = &r100_hpd_fini,
610 .sense = &r100_hpd_sense,
611 .set_polarity = &r100_hpd_set_polarity,
612 },
613 .pm = {
614 .misc = &r100_pm_misc,
615 .prepare = &r100_pm_prepare,
616 .finish = &r100_pm_finish,
617 .init_profile = &r100_pm_init_profile,
618 .get_dynpm_state = &r100_pm_get_dynpm_state,
619 .get_engine_clock = &radeon_legacy_get_engine_clock,
620 .set_engine_clock = &radeon_legacy_set_engine_clock,
621 .get_memory_clock = &radeon_legacy_get_memory_clock,
622 .set_memory_clock = NULL,
623 .get_pcie_lanes = NULL,
624 .set_pcie_lanes = NULL,
625 .set_clock_gating = &radeon_legacy_set_clock_gating,
626 },
627 .pflip = {
628 .page_flip = &r100_page_flip,
629 .page_flip_pending = &r100_page_flip_pending,
630 },
631 };
632
633 static struct radeon_asic rs600_asic = {
634 .init = &rs600_init,
635 .fini = &rs600_fini,
636 .suspend = &rs600_suspend,
637 .resume = &rs600_resume,
638 .vga_set_state = &r100_vga_set_state,
639 .asic_reset = &rs600_asic_reset,
640 .mmio_hdp_flush = NULL,
641 .gui_idle = &r100_gui_idle,
642 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
643 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
644 .gart = {
645 .tlb_flush = &rs600_gart_tlb_flush,
646 .get_page_entry = &rs600_gart_get_page_entry,
647 .set_page = &rs600_gart_set_page,
648 },
649 .ring = {
650 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
651 },
652 .irq = {
653 .set = &rs600_irq_set,
654 .process = &rs600_irq_process,
655 },
656 .display = {
657 .bandwidth_update = &rs600_bandwidth_update,
658 .get_vblank_counter = &rs600_get_vblank_counter,
659 .wait_for_vblank = &avivo_wait_for_vblank,
660 .set_backlight_level = &atombios_set_backlight_level,
661 .get_backlight_level = &atombios_get_backlight_level,
662 },
663 .copy = {
664 .blit = &r100_copy_blit,
665 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
666 .dma = &r200_copy_dma,
667 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
668 .copy = &r100_copy_blit,
669 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
670 },
671 .surface = {
672 .set_reg = r100_set_surface_reg,
673 .clear_reg = r100_clear_surface_reg,
674 },
675 .hpd = {
676 .init = &rs600_hpd_init,
677 .fini = &rs600_hpd_fini,
678 .sense = &rs600_hpd_sense,
679 .set_polarity = &rs600_hpd_set_polarity,
680 },
681 .pm = {
682 .misc = &rs600_pm_misc,
683 .prepare = &rs600_pm_prepare,
684 .finish = &rs600_pm_finish,
685 .init_profile = &r420_pm_init_profile,
686 .get_dynpm_state = &r100_pm_get_dynpm_state,
687 .get_engine_clock = &radeon_atom_get_engine_clock,
688 .set_engine_clock = &radeon_atom_set_engine_clock,
689 .get_memory_clock = &radeon_atom_get_memory_clock,
690 .set_memory_clock = &radeon_atom_set_memory_clock,
691 .get_pcie_lanes = NULL,
692 .set_pcie_lanes = NULL,
693 .set_clock_gating = &radeon_atom_set_clock_gating,
694 },
695 .pflip = {
696 .page_flip = &rs600_page_flip,
697 .page_flip_pending = &rs600_page_flip_pending,
698 },
699 };
700
701 static struct radeon_asic rs690_asic = {
702 .init = &rs690_init,
703 .fini = &rs690_fini,
704 .suspend = &rs690_suspend,
705 .resume = &rs690_resume,
706 .vga_set_state = &r100_vga_set_state,
707 .asic_reset = &rs600_asic_reset,
708 .mmio_hdp_flush = NULL,
709 .gui_idle = &r100_gui_idle,
710 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
711 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
712 .gart = {
713 .tlb_flush = &rs400_gart_tlb_flush,
714 .get_page_entry = &rs400_gart_get_page_entry,
715 .set_page = &rs400_gart_set_page,
716 },
717 .ring = {
718 [RADEON_RING_TYPE_GFX_INDEX] = &r300_gfx_ring
719 },
720 .irq = {
721 .set = &rs600_irq_set,
722 .process = &rs600_irq_process,
723 },
724 .display = {
725 .get_vblank_counter = &rs600_get_vblank_counter,
726 .bandwidth_update = &rs690_bandwidth_update,
727 .wait_for_vblank = &avivo_wait_for_vblank,
728 .set_backlight_level = &atombios_set_backlight_level,
729 .get_backlight_level = &atombios_get_backlight_level,
730 },
731 .copy = {
732 .blit = &r100_copy_blit,
733 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
734 .dma = &r200_copy_dma,
735 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
736 .copy = &r200_copy_dma,
737 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
738 },
739 .surface = {
740 .set_reg = r100_set_surface_reg,
741 .clear_reg = r100_clear_surface_reg,
742 },
743 .hpd = {
744 .init = &rs600_hpd_init,
745 .fini = &rs600_hpd_fini,
746 .sense = &rs600_hpd_sense,
747 .set_polarity = &rs600_hpd_set_polarity,
748 },
749 .pm = {
750 .misc = &rs600_pm_misc,
751 .prepare = &rs600_pm_prepare,
752 .finish = &rs600_pm_finish,
753 .init_profile = &r420_pm_init_profile,
754 .get_dynpm_state = &r100_pm_get_dynpm_state,
755 .get_engine_clock = &radeon_atom_get_engine_clock,
756 .set_engine_clock = &radeon_atom_set_engine_clock,
757 .get_memory_clock = &radeon_atom_get_memory_clock,
758 .set_memory_clock = &radeon_atom_set_memory_clock,
759 .get_pcie_lanes = NULL,
760 .set_pcie_lanes = NULL,
761 .set_clock_gating = &radeon_atom_set_clock_gating,
762 },
763 .pflip = {
764 .page_flip = &rs600_page_flip,
765 .page_flip_pending = &rs600_page_flip_pending,
766 },
767 };
768
769 static struct radeon_asic rv515_asic = {
770 .init = &rv515_init,
771 .fini = &rv515_fini,
772 .suspend = &rv515_suspend,
773 .resume = &rv515_resume,
774 .vga_set_state = &r100_vga_set_state,
775 .asic_reset = &rs600_asic_reset,
776 .mmio_hdp_flush = NULL,
777 .gui_idle = &r100_gui_idle,
778 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
779 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
780 .gart = {
781 .tlb_flush = &rv370_pcie_gart_tlb_flush,
782 .get_page_entry = &rv370_pcie_gart_get_page_entry,
783 .set_page = &rv370_pcie_gart_set_page,
784 },
785 .ring = {
786 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
787 },
788 .irq = {
789 .set = &rs600_irq_set,
790 .process = &rs600_irq_process,
791 },
792 .display = {
793 .get_vblank_counter = &rs600_get_vblank_counter,
794 .bandwidth_update = &rv515_bandwidth_update,
795 .wait_for_vblank = &avivo_wait_for_vblank,
796 .set_backlight_level = &atombios_set_backlight_level,
797 .get_backlight_level = &atombios_get_backlight_level,
798 },
799 .copy = {
800 .blit = &r100_copy_blit,
801 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
802 .dma = &r200_copy_dma,
803 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
804 .copy = &r100_copy_blit,
805 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
806 },
807 .surface = {
808 .set_reg = r100_set_surface_reg,
809 .clear_reg = r100_clear_surface_reg,
810 },
811 .hpd = {
812 .init = &rs600_hpd_init,
813 .fini = &rs600_hpd_fini,
814 .sense = &rs600_hpd_sense,
815 .set_polarity = &rs600_hpd_set_polarity,
816 },
817 .pm = {
818 .misc = &rs600_pm_misc,
819 .prepare = &rs600_pm_prepare,
820 .finish = &rs600_pm_finish,
821 .init_profile = &r420_pm_init_profile,
822 .get_dynpm_state = &r100_pm_get_dynpm_state,
823 .get_engine_clock = &radeon_atom_get_engine_clock,
824 .set_engine_clock = &radeon_atom_set_engine_clock,
825 .get_memory_clock = &radeon_atom_get_memory_clock,
826 .set_memory_clock = &radeon_atom_set_memory_clock,
827 .get_pcie_lanes = &rv370_get_pcie_lanes,
828 .set_pcie_lanes = &rv370_set_pcie_lanes,
829 .set_clock_gating = &radeon_atom_set_clock_gating,
830 },
831 .pflip = {
832 .page_flip = &rs600_page_flip,
833 .page_flip_pending = &rs600_page_flip_pending,
834 },
835 };
836
837 static struct radeon_asic r520_asic = {
838 .init = &r520_init,
839 .fini = &rv515_fini,
840 .suspend = &rv515_suspend,
841 .resume = &r520_resume,
842 .vga_set_state = &r100_vga_set_state,
843 .asic_reset = &rs600_asic_reset,
844 .mmio_hdp_flush = NULL,
845 .gui_idle = &r100_gui_idle,
846 .mc_wait_for_idle = &r520_mc_wait_for_idle,
847 .get_allowed_info_register = radeon_invalid_get_allowed_info_register,
848 .gart = {
849 .tlb_flush = &rv370_pcie_gart_tlb_flush,
850 .get_page_entry = &rv370_pcie_gart_get_page_entry,
851 .set_page = &rv370_pcie_gart_set_page,
852 },
853 .ring = {
854 [RADEON_RING_TYPE_GFX_INDEX] = &rv515_gfx_ring
855 },
856 .irq = {
857 .set = &rs600_irq_set,
858 .process = &rs600_irq_process,
859 },
860 .display = {
861 .bandwidth_update = &rv515_bandwidth_update,
862 .get_vblank_counter = &rs600_get_vblank_counter,
863 .wait_for_vblank = &avivo_wait_for_vblank,
864 .set_backlight_level = &atombios_set_backlight_level,
865 .get_backlight_level = &atombios_get_backlight_level,
866 },
867 .copy = {
868 .blit = &r100_copy_blit,
869 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
870 .dma = &r200_copy_dma,
871 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
872 .copy = &r100_copy_blit,
873 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
874 },
875 .surface = {
876 .set_reg = r100_set_surface_reg,
877 .clear_reg = r100_clear_surface_reg,
878 },
879 .hpd = {
880 .init = &rs600_hpd_init,
881 .fini = &rs600_hpd_fini,
882 .sense = &rs600_hpd_sense,
883 .set_polarity = &rs600_hpd_set_polarity,
884 },
885 .pm = {
886 .misc = &rs600_pm_misc,
887 .prepare = &rs600_pm_prepare,
888 .finish = &rs600_pm_finish,
889 .init_profile = &r420_pm_init_profile,
890 .get_dynpm_state = &r100_pm_get_dynpm_state,
891 .get_engine_clock = &radeon_atom_get_engine_clock,
892 .set_engine_clock = &radeon_atom_set_engine_clock,
893 .get_memory_clock = &radeon_atom_get_memory_clock,
894 .set_memory_clock = &radeon_atom_set_memory_clock,
895 .get_pcie_lanes = &rv370_get_pcie_lanes,
896 .set_pcie_lanes = &rv370_set_pcie_lanes,
897 .set_clock_gating = &radeon_atom_set_clock_gating,
898 },
899 .pflip = {
900 .page_flip = &rs600_page_flip,
901 .page_flip_pending = &rs600_page_flip_pending,
902 },
903 };
904
905 static const struct radeon_asic_ring r600_gfx_ring = {
906 .ib_execute = &r600_ring_ib_execute,
907 .emit_fence = &r600_fence_ring_emit,
908 .emit_semaphore = &r600_semaphore_ring_emit,
909 .cs_parse = &r600_cs_parse,
910 .ring_test = &r600_ring_test,
911 .ib_test = &r600_ib_test,
912 .is_lockup = &r600_gfx_is_lockup,
913 .get_rptr = &r600_gfx_get_rptr,
914 .get_wptr = &r600_gfx_get_wptr,
915 .set_wptr = &r600_gfx_set_wptr,
916 };
917
918 static const struct radeon_asic_ring r600_dma_ring = {
919 .ib_execute = &r600_dma_ring_ib_execute,
920 .emit_fence = &r600_dma_fence_ring_emit,
921 .emit_semaphore = &r600_dma_semaphore_ring_emit,
922 .cs_parse = &r600_dma_cs_parse,
923 .ring_test = &r600_dma_ring_test,
924 .ib_test = &r600_dma_ib_test,
925 .is_lockup = &r600_dma_is_lockup,
926 .get_rptr = &r600_dma_get_rptr,
927 .get_wptr = &r600_dma_get_wptr,
928 .set_wptr = &r600_dma_set_wptr,
929 };
930
931 static struct radeon_asic r600_asic = {
932 .init = &r600_init,
933 .fini = &r600_fini,
934 .suspend = &r600_suspend,
935 .resume = &r600_resume,
936 .vga_set_state = &r600_vga_set_state,
937 .asic_reset = &r600_asic_reset,
938 .mmio_hdp_flush = r600_mmio_hdp_flush,
939 .gui_idle = &r600_gui_idle,
940 .mc_wait_for_idle = &r600_mc_wait_for_idle,
941 .get_xclk = &r600_get_xclk,
942 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
943 .get_allowed_info_register = r600_get_allowed_info_register,
944 .gart = {
945 .tlb_flush = &r600_pcie_gart_tlb_flush,
946 .get_page_entry = &rs600_gart_get_page_entry,
947 .set_page = &rs600_gart_set_page,
948 },
949 .ring = {
950 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
951 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
952 },
953 .irq = {
954 .set = &r600_irq_set,
955 .process = &r600_irq_process,
956 },
957 .display = {
958 .bandwidth_update = &rv515_bandwidth_update,
959 .get_vblank_counter = &rs600_get_vblank_counter,
960 .wait_for_vblank = &avivo_wait_for_vblank,
961 .set_backlight_level = &atombios_set_backlight_level,
962 .get_backlight_level = &atombios_get_backlight_level,
963 },
964 .copy = {
965 .blit = &r600_copy_cpdma,
966 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
967 .dma = &r600_copy_dma,
968 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
969 .copy = &r600_copy_cpdma,
970 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
971 },
972 .surface = {
973 .set_reg = r600_set_surface_reg,
974 .clear_reg = r600_clear_surface_reg,
975 },
976 .hpd = {
977 .init = &r600_hpd_init,
978 .fini = &r600_hpd_fini,
979 .sense = &r600_hpd_sense,
980 .set_polarity = &r600_hpd_set_polarity,
981 },
982 .pm = {
983 .misc = &r600_pm_misc,
984 .prepare = &rs600_pm_prepare,
985 .finish = &rs600_pm_finish,
986 .init_profile = &r600_pm_init_profile,
987 .get_dynpm_state = &r600_pm_get_dynpm_state,
988 .get_engine_clock = &radeon_atom_get_engine_clock,
989 .set_engine_clock = &radeon_atom_set_engine_clock,
990 .get_memory_clock = &radeon_atom_get_memory_clock,
991 .set_memory_clock = &radeon_atom_set_memory_clock,
992 .get_pcie_lanes = &r600_get_pcie_lanes,
993 .set_pcie_lanes = &r600_set_pcie_lanes,
994 .set_clock_gating = NULL,
995 .get_temperature = &rv6xx_get_temp,
996 },
997 .pflip = {
998 .page_flip = &rs600_page_flip,
999 .page_flip_pending = &rs600_page_flip_pending,
1000 },
1001 };
1002
1003 static const struct radeon_asic_ring rv6xx_uvd_ring = {
1004 .ib_execute = &uvd_v1_0_ib_execute,
1005 .emit_fence = &uvd_v1_0_fence_emit,
1006 .emit_semaphore = &uvd_v1_0_semaphore_emit,
1007 .cs_parse = &radeon_uvd_cs_parse,
1008 .ring_test = &uvd_v1_0_ring_test,
1009 .ib_test = &uvd_v1_0_ib_test,
1010 .is_lockup = &radeon_ring_test_lockup,
1011 .get_rptr = &uvd_v1_0_get_rptr,
1012 .get_wptr = &uvd_v1_0_get_wptr,
1013 .set_wptr = &uvd_v1_0_set_wptr,
1014 };
1015
1016 static struct radeon_asic rv6xx_asic = {
1017 .init = &r600_init,
1018 .fini = &r600_fini,
1019 .suspend = &r600_suspend,
1020 .resume = &r600_resume,
1021 .vga_set_state = &r600_vga_set_state,
1022 .asic_reset = &r600_asic_reset,
1023 .mmio_hdp_flush = r600_mmio_hdp_flush,
1024 .gui_idle = &r600_gui_idle,
1025 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1026 .get_xclk = &r600_get_xclk,
1027 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1028 .get_allowed_info_register = r600_get_allowed_info_register,
1029 .gart = {
1030 .tlb_flush = &r600_pcie_gart_tlb_flush,
1031 .get_page_entry = &rs600_gart_get_page_entry,
1032 .set_page = &rs600_gart_set_page,
1033 },
1034 .ring = {
1035 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1036 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1037 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1038 },
1039 .irq = {
1040 .set = &r600_irq_set,
1041 .process = &r600_irq_process,
1042 },
1043 .display = {
1044 .bandwidth_update = &rv515_bandwidth_update,
1045 .get_vblank_counter = &rs600_get_vblank_counter,
1046 .wait_for_vblank = &avivo_wait_for_vblank,
1047 .set_backlight_level = &atombios_set_backlight_level,
1048 .get_backlight_level = &atombios_get_backlight_level,
1049 },
1050 .copy = {
1051 .blit = &r600_copy_cpdma,
1052 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1053 .dma = &r600_copy_dma,
1054 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1055 .copy = &r600_copy_cpdma,
1056 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1057 },
1058 .surface = {
1059 .set_reg = r600_set_surface_reg,
1060 .clear_reg = r600_clear_surface_reg,
1061 },
1062 .hpd = {
1063 .init = &r600_hpd_init,
1064 .fini = &r600_hpd_fini,
1065 .sense = &r600_hpd_sense,
1066 .set_polarity = &r600_hpd_set_polarity,
1067 },
1068 .pm = {
1069 .misc = &r600_pm_misc,
1070 .prepare = &rs600_pm_prepare,
1071 .finish = &rs600_pm_finish,
1072 .init_profile = &r600_pm_init_profile,
1073 .get_dynpm_state = &r600_pm_get_dynpm_state,
1074 .get_engine_clock = &radeon_atom_get_engine_clock,
1075 .set_engine_clock = &radeon_atom_set_engine_clock,
1076 .get_memory_clock = &radeon_atom_get_memory_clock,
1077 .set_memory_clock = &radeon_atom_set_memory_clock,
1078 .get_pcie_lanes = &r600_get_pcie_lanes,
1079 .set_pcie_lanes = &r600_set_pcie_lanes,
1080 .set_clock_gating = NULL,
1081 .get_temperature = &rv6xx_get_temp,
1082 .set_uvd_clocks = &r600_set_uvd_clocks,
1083 },
1084 .dpm = {
1085 .init = &rv6xx_dpm_init,
1086 .setup_asic = &rv6xx_setup_asic,
1087 .enable = &rv6xx_dpm_enable,
1088 .late_enable = &r600_dpm_late_enable,
1089 .disable = &rv6xx_dpm_disable,
1090 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1091 .set_power_state = &rv6xx_dpm_set_power_state,
1092 .post_set_power_state = &r600_dpm_post_set_power_state,
1093 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1094 .fini = &rv6xx_dpm_fini,
1095 .get_sclk = &rv6xx_dpm_get_sclk,
1096 .get_mclk = &rv6xx_dpm_get_mclk,
1097 .print_power_state = &rv6xx_dpm_print_power_state,
1098 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1099 .force_performance_level = &rv6xx_dpm_force_performance_level,
1100 .get_current_sclk = &rv6xx_dpm_get_current_sclk,
1101 .get_current_mclk = &rv6xx_dpm_get_current_mclk,
1102 },
1103 .pflip = {
1104 .page_flip = &rs600_page_flip,
1105 .page_flip_pending = &rs600_page_flip_pending,
1106 },
1107 };
1108
1109 static struct radeon_asic rs780_asic = {
1110 .init = &r600_init,
1111 .fini = &r600_fini,
1112 .suspend = &r600_suspend,
1113 .resume = &r600_resume,
1114 .vga_set_state = &r600_vga_set_state,
1115 .asic_reset = &r600_asic_reset,
1116 .mmio_hdp_flush = r600_mmio_hdp_flush,
1117 .gui_idle = &r600_gui_idle,
1118 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1119 .get_xclk = &r600_get_xclk,
1120 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1121 .get_allowed_info_register = r600_get_allowed_info_register,
1122 .gart = {
1123 .tlb_flush = &r600_pcie_gart_tlb_flush,
1124 .get_page_entry = &rs600_gart_get_page_entry,
1125 .set_page = &rs600_gart_set_page,
1126 },
1127 .ring = {
1128 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1129 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1130 [R600_RING_TYPE_UVD_INDEX] = &rv6xx_uvd_ring,
1131 },
1132 .irq = {
1133 .set = &r600_irq_set,
1134 .process = &r600_irq_process,
1135 },
1136 .display = {
1137 .bandwidth_update = &rs690_bandwidth_update,
1138 .get_vblank_counter = &rs600_get_vblank_counter,
1139 .wait_for_vblank = &avivo_wait_for_vblank,
1140 .set_backlight_level = &atombios_set_backlight_level,
1141 .get_backlight_level = &atombios_get_backlight_level,
1142 },
1143 .copy = {
1144 .blit = &r600_copy_cpdma,
1145 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1146 .dma = &r600_copy_dma,
1147 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1148 .copy = &r600_copy_cpdma,
1149 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1150 },
1151 .surface = {
1152 .set_reg = r600_set_surface_reg,
1153 .clear_reg = r600_clear_surface_reg,
1154 },
1155 .hpd = {
1156 .init = &r600_hpd_init,
1157 .fini = &r600_hpd_fini,
1158 .sense = &r600_hpd_sense,
1159 .set_polarity = &r600_hpd_set_polarity,
1160 },
1161 .pm = {
1162 .misc = &r600_pm_misc,
1163 .prepare = &rs600_pm_prepare,
1164 .finish = &rs600_pm_finish,
1165 .init_profile = &rs780_pm_init_profile,
1166 .get_dynpm_state = &r600_pm_get_dynpm_state,
1167 .get_engine_clock = &radeon_atom_get_engine_clock,
1168 .set_engine_clock = &radeon_atom_set_engine_clock,
1169 .get_memory_clock = NULL,
1170 .set_memory_clock = NULL,
1171 .get_pcie_lanes = NULL,
1172 .set_pcie_lanes = NULL,
1173 .set_clock_gating = NULL,
1174 .get_temperature = &rv6xx_get_temp,
1175 .set_uvd_clocks = &r600_set_uvd_clocks,
1176 },
1177 .dpm = {
1178 .init = &rs780_dpm_init,
1179 .setup_asic = &rs780_dpm_setup_asic,
1180 .enable = &rs780_dpm_enable,
1181 .late_enable = &r600_dpm_late_enable,
1182 .disable = &rs780_dpm_disable,
1183 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1184 .set_power_state = &rs780_dpm_set_power_state,
1185 .post_set_power_state = &r600_dpm_post_set_power_state,
1186 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1187 .fini = &rs780_dpm_fini,
1188 .get_sclk = &rs780_dpm_get_sclk,
1189 .get_mclk = &rs780_dpm_get_mclk,
1190 .print_power_state = &rs780_dpm_print_power_state,
1191 .debugfs_print_current_performance_level = &rs780_dpm_debugfs_print_current_performance_level,
1192 .force_performance_level = &rs780_dpm_force_performance_level,
1193 .get_current_sclk = &rs780_dpm_get_current_sclk,
1194 .get_current_mclk = &rs780_dpm_get_current_mclk,
1195 },
1196 .pflip = {
1197 .page_flip = &rs600_page_flip,
1198 .page_flip_pending = &rs600_page_flip_pending,
1199 },
1200 };
1201
1202 static const struct radeon_asic_ring rv770_uvd_ring = {
1203 .ib_execute = &uvd_v1_0_ib_execute,
1204 .emit_fence = &uvd_v2_2_fence_emit,
1205 .emit_semaphore = &uvd_v2_2_semaphore_emit,
1206 .cs_parse = &radeon_uvd_cs_parse,
1207 .ring_test = &uvd_v1_0_ring_test,
1208 .ib_test = &uvd_v1_0_ib_test,
1209 .is_lockup = &radeon_ring_test_lockup,
1210 .get_rptr = &uvd_v1_0_get_rptr,
1211 .get_wptr = &uvd_v1_0_get_wptr,
1212 .set_wptr = &uvd_v1_0_set_wptr,
1213 };
1214
1215 static struct radeon_asic rv770_asic = {
1216 .init = &rv770_init,
1217 .fini = &rv770_fini,
1218 .suspend = &rv770_suspend,
1219 .resume = &rv770_resume,
1220 .asic_reset = &r600_asic_reset,
1221 .vga_set_state = &r600_vga_set_state,
1222 .mmio_hdp_flush = r600_mmio_hdp_flush,
1223 .gui_idle = &r600_gui_idle,
1224 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1225 .get_xclk = &rv770_get_xclk,
1226 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1227 .get_allowed_info_register = r600_get_allowed_info_register,
1228 .gart = {
1229 .tlb_flush = &r600_pcie_gart_tlb_flush,
1230 .get_page_entry = &rs600_gart_get_page_entry,
1231 .set_page = &rs600_gart_set_page,
1232 },
1233 .ring = {
1234 [RADEON_RING_TYPE_GFX_INDEX] = &r600_gfx_ring,
1235 [R600_RING_TYPE_DMA_INDEX] = &r600_dma_ring,
1236 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1237 },
1238 .irq = {
1239 .set = &r600_irq_set,
1240 .process = &r600_irq_process,
1241 },
1242 .display = {
1243 .bandwidth_update = &rv515_bandwidth_update,
1244 .get_vblank_counter = &rs600_get_vblank_counter,
1245 .wait_for_vblank = &avivo_wait_for_vblank,
1246 .set_backlight_level = &atombios_set_backlight_level,
1247 .get_backlight_level = &atombios_get_backlight_level,
1248 },
1249 .copy = {
1250 .blit = &r600_copy_cpdma,
1251 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1252 .dma = &rv770_copy_dma,
1253 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1254 .copy = &rv770_copy_dma,
1255 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1256 },
1257 .surface = {
1258 .set_reg = r600_set_surface_reg,
1259 .clear_reg = r600_clear_surface_reg,
1260 },
1261 .hpd = {
1262 .init = &r600_hpd_init,
1263 .fini = &r600_hpd_fini,
1264 .sense = &r600_hpd_sense,
1265 .set_polarity = &r600_hpd_set_polarity,
1266 },
1267 .pm = {
1268 .misc = &rv770_pm_misc,
1269 .prepare = &rs600_pm_prepare,
1270 .finish = &rs600_pm_finish,
1271 .init_profile = &r600_pm_init_profile,
1272 .get_dynpm_state = &r600_pm_get_dynpm_state,
1273 .get_engine_clock = &radeon_atom_get_engine_clock,
1274 .set_engine_clock = &radeon_atom_set_engine_clock,
1275 .get_memory_clock = &radeon_atom_get_memory_clock,
1276 .set_memory_clock = &radeon_atom_set_memory_clock,
1277 .get_pcie_lanes = &r600_get_pcie_lanes,
1278 .set_pcie_lanes = &r600_set_pcie_lanes,
1279 .set_clock_gating = &radeon_atom_set_clock_gating,
1280 .set_uvd_clocks = &rv770_set_uvd_clocks,
1281 .get_temperature = &rv770_get_temp,
1282 },
1283 .dpm = {
1284 .init = &rv770_dpm_init,
1285 .setup_asic = &rv770_dpm_setup_asic,
1286 .enable = &rv770_dpm_enable,
1287 .late_enable = &rv770_dpm_late_enable,
1288 .disable = &rv770_dpm_disable,
1289 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1290 .set_power_state = &rv770_dpm_set_power_state,
1291 .post_set_power_state = &r600_dpm_post_set_power_state,
1292 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1293 .fini = &rv770_dpm_fini,
1294 .get_sclk = &rv770_dpm_get_sclk,
1295 .get_mclk = &rv770_dpm_get_mclk,
1296 .print_power_state = &rv770_dpm_print_power_state,
1297 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1298 .force_performance_level = &rv770_dpm_force_performance_level,
1299 .vblank_too_short = &rv770_dpm_vblank_too_short,
1300 .get_current_sclk = &rv770_dpm_get_current_sclk,
1301 .get_current_mclk = &rv770_dpm_get_current_mclk,
1302 },
1303 .pflip = {
1304 .page_flip = &rv770_page_flip,
1305 .page_flip_pending = &rv770_page_flip_pending,
1306 },
1307 };
1308
1309 static const struct radeon_asic_ring evergreen_gfx_ring = {
1310 .ib_execute = &evergreen_ring_ib_execute,
1311 .emit_fence = &r600_fence_ring_emit,
1312 .emit_semaphore = &r600_semaphore_ring_emit,
1313 .cs_parse = &evergreen_cs_parse,
1314 .ring_test = &r600_ring_test,
1315 .ib_test = &r600_ib_test,
1316 .is_lockup = &evergreen_gfx_is_lockup,
1317 .get_rptr = &r600_gfx_get_rptr,
1318 .get_wptr = &r600_gfx_get_wptr,
1319 .set_wptr = &r600_gfx_set_wptr,
1320 };
1321
1322 static const struct radeon_asic_ring evergreen_dma_ring = {
1323 .ib_execute = &evergreen_dma_ring_ib_execute,
1324 .emit_fence = &evergreen_dma_fence_ring_emit,
1325 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1326 .cs_parse = &evergreen_dma_cs_parse,
1327 .ring_test = &r600_dma_ring_test,
1328 .ib_test = &r600_dma_ib_test,
1329 .is_lockup = &evergreen_dma_is_lockup,
1330 .get_rptr = &r600_dma_get_rptr,
1331 .get_wptr = &r600_dma_get_wptr,
1332 .set_wptr = &r600_dma_set_wptr,
1333 };
1334
1335 static struct radeon_asic evergreen_asic = {
1336 .init = &evergreen_init,
1337 .fini = &evergreen_fini,
1338 .suspend = &evergreen_suspend,
1339 .resume = &evergreen_resume,
1340 .asic_reset = &evergreen_asic_reset,
1341 .vga_set_state = &r600_vga_set_state,
1342 .mmio_hdp_flush = r600_mmio_hdp_flush,
1343 .gui_idle = &r600_gui_idle,
1344 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1345 .get_xclk = &rv770_get_xclk,
1346 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1347 .get_allowed_info_register = evergreen_get_allowed_info_register,
1348 .gart = {
1349 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1350 .get_page_entry = &rs600_gart_get_page_entry,
1351 .set_page = &rs600_gart_set_page,
1352 },
1353 .ring = {
1354 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1355 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1356 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1357 },
1358 .irq = {
1359 .set = &evergreen_irq_set,
1360 .process = &evergreen_irq_process,
1361 },
1362 .display = {
1363 .bandwidth_update = &evergreen_bandwidth_update,
1364 .get_vblank_counter = &evergreen_get_vblank_counter,
1365 .wait_for_vblank = &dce4_wait_for_vblank,
1366 .set_backlight_level = &atombios_set_backlight_level,
1367 .get_backlight_level = &atombios_get_backlight_level,
1368 },
1369 .copy = {
1370 .blit = &r600_copy_cpdma,
1371 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1372 .dma = &evergreen_copy_dma,
1373 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1374 .copy = &evergreen_copy_dma,
1375 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1376 },
1377 .surface = {
1378 .set_reg = r600_set_surface_reg,
1379 .clear_reg = r600_clear_surface_reg,
1380 },
1381 .hpd = {
1382 .init = &evergreen_hpd_init,
1383 .fini = &evergreen_hpd_fini,
1384 .sense = &evergreen_hpd_sense,
1385 .set_polarity = &evergreen_hpd_set_polarity,
1386 },
1387 .pm = {
1388 .misc = &evergreen_pm_misc,
1389 .prepare = &evergreen_pm_prepare,
1390 .finish = &evergreen_pm_finish,
1391 .init_profile = &r600_pm_init_profile,
1392 .get_dynpm_state = &r600_pm_get_dynpm_state,
1393 .get_engine_clock = &radeon_atom_get_engine_clock,
1394 .set_engine_clock = &radeon_atom_set_engine_clock,
1395 .get_memory_clock = &radeon_atom_get_memory_clock,
1396 .set_memory_clock = &radeon_atom_set_memory_clock,
1397 .get_pcie_lanes = &r600_get_pcie_lanes,
1398 .set_pcie_lanes = &r600_set_pcie_lanes,
1399 .set_clock_gating = NULL,
1400 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1401 .get_temperature = &evergreen_get_temp,
1402 },
1403 .dpm = {
1404 .init = &cypress_dpm_init,
1405 .setup_asic = &cypress_dpm_setup_asic,
1406 .enable = &cypress_dpm_enable,
1407 .late_enable = &rv770_dpm_late_enable,
1408 .disable = &cypress_dpm_disable,
1409 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1410 .set_power_state = &cypress_dpm_set_power_state,
1411 .post_set_power_state = &r600_dpm_post_set_power_state,
1412 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1413 .fini = &cypress_dpm_fini,
1414 .get_sclk = &rv770_dpm_get_sclk,
1415 .get_mclk = &rv770_dpm_get_mclk,
1416 .print_power_state = &rv770_dpm_print_power_state,
1417 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1418 .force_performance_level = &rv770_dpm_force_performance_level,
1419 .vblank_too_short = &cypress_dpm_vblank_too_short,
1420 .get_current_sclk = &rv770_dpm_get_current_sclk,
1421 .get_current_mclk = &rv770_dpm_get_current_mclk,
1422 },
1423 .pflip = {
1424 .page_flip = &evergreen_page_flip,
1425 .page_flip_pending = &evergreen_page_flip_pending,
1426 },
1427 };
1428
1429 static struct radeon_asic sumo_asic = {
1430 .init = &evergreen_init,
1431 .fini = &evergreen_fini,
1432 .suspend = &evergreen_suspend,
1433 .resume = &evergreen_resume,
1434 .asic_reset = &evergreen_asic_reset,
1435 .vga_set_state = &r600_vga_set_state,
1436 .mmio_hdp_flush = r600_mmio_hdp_flush,
1437 .gui_idle = &r600_gui_idle,
1438 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1439 .get_xclk = &r600_get_xclk,
1440 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1441 .get_allowed_info_register = evergreen_get_allowed_info_register,
1442 .gart = {
1443 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1444 .get_page_entry = &rs600_gart_get_page_entry,
1445 .set_page = &rs600_gart_set_page,
1446 },
1447 .ring = {
1448 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1449 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1450 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1451 },
1452 .irq = {
1453 .set = &evergreen_irq_set,
1454 .process = &evergreen_irq_process,
1455 },
1456 .display = {
1457 .bandwidth_update = &evergreen_bandwidth_update,
1458 .get_vblank_counter = &evergreen_get_vblank_counter,
1459 .wait_for_vblank = &dce4_wait_for_vblank,
1460 .set_backlight_level = &atombios_set_backlight_level,
1461 .get_backlight_level = &atombios_get_backlight_level,
1462 },
1463 .copy = {
1464 .blit = &r600_copy_cpdma,
1465 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1466 .dma = &evergreen_copy_dma,
1467 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1468 .copy = &evergreen_copy_dma,
1469 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1470 },
1471 .surface = {
1472 .set_reg = r600_set_surface_reg,
1473 .clear_reg = r600_clear_surface_reg,
1474 },
1475 .hpd = {
1476 .init = &evergreen_hpd_init,
1477 .fini = &evergreen_hpd_fini,
1478 .sense = &evergreen_hpd_sense,
1479 .set_polarity = &evergreen_hpd_set_polarity,
1480 },
1481 .pm = {
1482 .misc = &evergreen_pm_misc,
1483 .prepare = &evergreen_pm_prepare,
1484 .finish = &evergreen_pm_finish,
1485 .init_profile = &sumo_pm_init_profile,
1486 .get_dynpm_state = &r600_pm_get_dynpm_state,
1487 .get_engine_clock = &radeon_atom_get_engine_clock,
1488 .set_engine_clock = &radeon_atom_set_engine_clock,
1489 .get_memory_clock = NULL,
1490 .set_memory_clock = NULL,
1491 .get_pcie_lanes = NULL,
1492 .set_pcie_lanes = NULL,
1493 .set_clock_gating = NULL,
1494 .set_uvd_clocks = &sumo_set_uvd_clocks,
1495 .get_temperature = &sumo_get_temp,
1496 },
1497 .dpm = {
1498 .init = &sumo_dpm_init,
1499 .setup_asic = &sumo_dpm_setup_asic,
1500 .enable = &sumo_dpm_enable,
1501 .late_enable = &sumo_dpm_late_enable,
1502 .disable = &sumo_dpm_disable,
1503 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1504 .set_power_state = &sumo_dpm_set_power_state,
1505 .post_set_power_state = &sumo_dpm_post_set_power_state,
1506 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1507 .fini = &sumo_dpm_fini,
1508 .get_sclk = &sumo_dpm_get_sclk,
1509 .get_mclk = &sumo_dpm_get_mclk,
1510 .print_power_state = &sumo_dpm_print_power_state,
1511 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1512 .force_performance_level = &sumo_dpm_force_performance_level,
1513 .get_current_sclk = &sumo_dpm_get_current_sclk,
1514 .get_current_mclk = &sumo_dpm_get_current_mclk,
1515 .get_current_vddc = &sumo_dpm_get_current_vddc,
1516 },
1517 .pflip = {
1518 .page_flip = &evergreen_page_flip,
1519 .page_flip_pending = &evergreen_page_flip_pending,
1520 },
1521 };
1522
1523 static struct radeon_asic btc_asic = {
1524 .init = &evergreen_init,
1525 .fini = &evergreen_fini,
1526 .suspend = &evergreen_suspend,
1527 .resume = &evergreen_resume,
1528 .asic_reset = &evergreen_asic_reset,
1529 .vga_set_state = &r600_vga_set_state,
1530 .mmio_hdp_flush = r600_mmio_hdp_flush,
1531 .gui_idle = &r600_gui_idle,
1532 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1533 .get_xclk = &rv770_get_xclk,
1534 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1535 .get_allowed_info_register = evergreen_get_allowed_info_register,
1536 .gart = {
1537 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1538 .get_page_entry = &rs600_gart_get_page_entry,
1539 .set_page = &rs600_gart_set_page,
1540 },
1541 .ring = {
1542 [RADEON_RING_TYPE_GFX_INDEX] = &evergreen_gfx_ring,
1543 [R600_RING_TYPE_DMA_INDEX] = &evergreen_dma_ring,
1544 [R600_RING_TYPE_UVD_INDEX] = &rv770_uvd_ring,
1545 },
1546 .irq = {
1547 .set = &evergreen_irq_set,
1548 .process = &evergreen_irq_process,
1549 },
1550 .display = {
1551 .bandwidth_update = &evergreen_bandwidth_update,
1552 .get_vblank_counter = &evergreen_get_vblank_counter,
1553 .wait_for_vblank = &dce4_wait_for_vblank,
1554 .set_backlight_level = &atombios_set_backlight_level,
1555 .get_backlight_level = &atombios_get_backlight_level,
1556 },
1557 .copy = {
1558 .blit = &r600_copy_cpdma,
1559 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1560 .dma = &evergreen_copy_dma,
1561 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1562 .copy = &evergreen_copy_dma,
1563 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1564 },
1565 .surface = {
1566 .set_reg = r600_set_surface_reg,
1567 .clear_reg = r600_clear_surface_reg,
1568 },
1569 .hpd = {
1570 .init = &evergreen_hpd_init,
1571 .fini = &evergreen_hpd_fini,
1572 .sense = &evergreen_hpd_sense,
1573 .set_polarity = &evergreen_hpd_set_polarity,
1574 },
1575 .pm = {
1576 .misc = &evergreen_pm_misc,
1577 .prepare = &evergreen_pm_prepare,
1578 .finish = &evergreen_pm_finish,
1579 .init_profile = &btc_pm_init_profile,
1580 .get_dynpm_state = &r600_pm_get_dynpm_state,
1581 .get_engine_clock = &radeon_atom_get_engine_clock,
1582 .set_engine_clock = &radeon_atom_set_engine_clock,
1583 .get_memory_clock = &radeon_atom_get_memory_clock,
1584 .set_memory_clock = &radeon_atom_set_memory_clock,
1585 .get_pcie_lanes = &r600_get_pcie_lanes,
1586 .set_pcie_lanes = &r600_set_pcie_lanes,
1587 .set_clock_gating = NULL,
1588 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1589 .get_temperature = &evergreen_get_temp,
1590 },
1591 .dpm = {
1592 .init = &btc_dpm_init,
1593 .setup_asic = &btc_dpm_setup_asic,
1594 .enable = &btc_dpm_enable,
1595 .late_enable = &rv770_dpm_late_enable,
1596 .disable = &btc_dpm_disable,
1597 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1598 .set_power_state = &btc_dpm_set_power_state,
1599 .post_set_power_state = &btc_dpm_post_set_power_state,
1600 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1601 .fini = &btc_dpm_fini,
1602 .get_sclk = &btc_dpm_get_sclk,
1603 .get_mclk = &btc_dpm_get_mclk,
1604 .print_power_state = &rv770_dpm_print_power_state,
1605 .debugfs_print_current_performance_level = &btc_dpm_debugfs_print_current_performance_level,
1606 .force_performance_level = &rv770_dpm_force_performance_level,
1607 .vblank_too_short = &btc_dpm_vblank_too_short,
1608 .get_current_sclk = &btc_dpm_get_current_sclk,
1609 .get_current_mclk = &btc_dpm_get_current_mclk,
1610 },
1611 .pflip = {
1612 .page_flip = &evergreen_page_flip,
1613 .page_flip_pending = &evergreen_page_flip_pending,
1614 },
1615 };
1616
1617 static const struct radeon_asic_ring cayman_gfx_ring = {
1618 .ib_execute = &cayman_ring_ib_execute,
1619 .ib_parse = &evergreen_ib_parse,
1620 .emit_fence = &cayman_fence_ring_emit,
1621 .emit_semaphore = &r600_semaphore_ring_emit,
1622 .cs_parse = &evergreen_cs_parse,
1623 .ring_test = &r600_ring_test,
1624 .ib_test = &r600_ib_test,
1625 .is_lockup = &cayman_gfx_is_lockup,
1626 .vm_flush = &cayman_vm_flush,
1627 .get_rptr = &cayman_gfx_get_rptr,
1628 .get_wptr = &cayman_gfx_get_wptr,
1629 .set_wptr = &cayman_gfx_set_wptr,
1630 };
1631
1632 static const struct radeon_asic_ring cayman_dma_ring = {
1633 .ib_execute = &cayman_dma_ring_ib_execute,
1634 .ib_parse = &evergreen_dma_ib_parse,
1635 .emit_fence = &evergreen_dma_fence_ring_emit,
1636 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1637 .cs_parse = &evergreen_dma_cs_parse,
1638 .ring_test = &r600_dma_ring_test,
1639 .ib_test = &r600_dma_ib_test,
1640 .is_lockup = &cayman_dma_is_lockup,
1641 .vm_flush = &cayman_dma_vm_flush,
1642 .get_rptr = &cayman_dma_get_rptr,
1643 .get_wptr = &cayman_dma_get_wptr,
1644 .set_wptr = &cayman_dma_set_wptr
1645 };
1646
1647 static const struct radeon_asic_ring cayman_uvd_ring = {
1648 .ib_execute = &uvd_v1_0_ib_execute,
1649 .emit_fence = &uvd_v2_2_fence_emit,
1650 .emit_semaphore = &uvd_v3_1_semaphore_emit,
1651 .cs_parse = &radeon_uvd_cs_parse,
1652 .ring_test = &uvd_v1_0_ring_test,
1653 .ib_test = &uvd_v1_0_ib_test,
1654 .is_lockup = &radeon_ring_test_lockup,
1655 .get_rptr = &uvd_v1_0_get_rptr,
1656 .get_wptr = &uvd_v1_0_get_wptr,
1657 .set_wptr = &uvd_v1_0_set_wptr,
1658 };
1659
1660 static struct radeon_asic cayman_asic = {
1661 .init = &cayman_init,
1662 .fini = &cayman_fini,
1663 .suspend = &cayman_suspend,
1664 .resume = &cayman_resume,
1665 .asic_reset = &cayman_asic_reset,
1666 .vga_set_state = &r600_vga_set_state,
1667 .mmio_hdp_flush = r600_mmio_hdp_flush,
1668 .gui_idle = &r600_gui_idle,
1669 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1670 .get_xclk = &rv770_get_xclk,
1671 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1672 .get_allowed_info_register = cayman_get_allowed_info_register,
1673 .gart = {
1674 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1675 .get_page_entry = &rs600_gart_get_page_entry,
1676 .set_page = &rs600_gart_set_page,
1677 },
1678 .vm = {
1679 .init = &cayman_vm_init,
1680 .fini = &cayman_vm_fini,
1681 .copy_pages = &cayman_dma_vm_copy_pages,
1682 .write_pages = &cayman_dma_vm_write_pages,
1683 .set_pages = &cayman_dma_vm_set_pages,
1684 .pad_ib = &cayman_dma_vm_pad_ib,
1685 },
1686 .ring = {
1687 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1688 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1689 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1690 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1691 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1692 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1693 },
1694 .irq = {
1695 .set = &evergreen_irq_set,
1696 .process = &evergreen_irq_process,
1697 },
1698 .display = {
1699 .bandwidth_update = &evergreen_bandwidth_update,
1700 .get_vblank_counter = &evergreen_get_vblank_counter,
1701 .wait_for_vblank = &dce4_wait_for_vblank,
1702 .set_backlight_level = &atombios_set_backlight_level,
1703 .get_backlight_level = &atombios_get_backlight_level,
1704 },
1705 .copy = {
1706 .blit = &r600_copy_cpdma,
1707 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1708 .dma = &evergreen_copy_dma,
1709 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1710 .copy = &evergreen_copy_dma,
1711 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1712 },
1713 .surface = {
1714 .set_reg = r600_set_surface_reg,
1715 .clear_reg = r600_clear_surface_reg,
1716 },
1717 .hpd = {
1718 .init = &evergreen_hpd_init,
1719 .fini = &evergreen_hpd_fini,
1720 .sense = &evergreen_hpd_sense,
1721 .set_polarity = &evergreen_hpd_set_polarity,
1722 },
1723 .pm = {
1724 .misc = &evergreen_pm_misc,
1725 .prepare = &evergreen_pm_prepare,
1726 .finish = &evergreen_pm_finish,
1727 .init_profile = &btc_pm_init_profile,
1728 .get_dynpm_state = &r600_pm_get_dynpm_state,
1729 .get_engine_clock = &radeon_atom_get_engine_clock,
1730 .set_engine_clock = &radeon_atom_set_engine_clock,
1731 .get_memory_clock = &radeon_atom_get_memory_clock,
1732 .set_memory_clock = &radeon_atom_set_memory_clock,
1733 .get_pcie_lanes = &r600_get_pcie_lanes,
1734 .set_pcie_lanes = &r600_set_pcie_lanes,
1735 .set_clock_gating = NULL,
1736 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1737 .get_temperature = &evergreen_get_temp,
1738 },
1739 .dpm = {
1740 .init = &ni_dpm_init,
1741 .setup_asic = &ni_dpm_setup_asic,
1742 .enable = &ni_dpm_enable,
1743 .late_enable = &rv770_dpm_late_enable,
1744 .disable = &ni_dpm_disable,
1745 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1746 .set_power_state = &ni_dpm_set_power_state,
1747 .post_set_power_state = &ni_dpm_post_set_power_state,
1748 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1749 .fini = &ni_dpm_fini,
1750 .get_sclk = &ni_dpm_get_sclk,
1751 .get_mclk = &ni_dpm_get_mclk,
1752 .print_power_state = &ni_dpm_print_power_state,
1753 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1754 .force_performance_level = &ni_dpm_force_performance_level,
1755 .vblank_too_short = &ni_dpm_vblank_too_short,
1756 .get_current_sclk = &ni_dpm_get_current_sclk,
1757 .get_current_mclk = &ni_dpm_get_current_mclk,
1758 },
1759 .pflip = {
1760 .page_flip = &evergreen_page_flip,
1761 .page_flip_pending = &evergreen_page_flip_pending,
1762 },
1763 };
1764
1765 static const struct radeon_asic_ring trinity_vce_ring = {
1766 .ib_execute = &radeon_vce_ib_execute,
1767 .emit_fence = &radeon_vce_fence_emit,
1768 .emit_semaphore = &radeon_vce_semaphore_emit,
1769 .cs_parse = &radeon_vce_cs_parse,
1770 .ring_test = &radeon_vce_ring_test,
1771 .ib_test = &radeon_vce_ib_test,
1772 .is_lockup = &radeon_ring_test_lockup,
1773 .get_rptr = &vce_v1_0_get_rptr,
1774 .get_wptr = &vce_v1_0_get_wptr,
1775 .set_wptr = &vce_v1_0_set_wptr,
1776 };
1777
1778 static struct radeon_asic trinity_asic = {
1779 .init = &cayman_init,
1780 .fini = &cayman_fini,
1781 .suspend = &cayman_suspend,
1782 .resume = &cayman_resume,
1783 .asic_reset = &cayman_asic_reset,
1784 .vga_set_state = &r600_vga_set_state,
1785 .mmio_hdp_flush = r600_mmio_hdp_flush,
1786 .gui_idle = &r600_gui_idle,
1787 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1788 .get_xclk = &r600_get_xclk,
1789 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1790 .get_allowed_info_register = cayman_get_allowed_info_register,
1791 .gart = {
1792 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1793 .get_page_entry = &rs600_gart_get_page_entry,
1794 .set_page = &rs600_gart_set_page,
1795 },
1796 .vm = {
1797 .init = &cayman_vm_init,
1798 .fini = &cayman_vm_fini,
1799 .copy_pages = &cayman_dma_vm_copy_pages,
1800 .write_pages = &cayman_dma_vm_write_pages,
1801 .set_pages = &cayman_dma_vm_set_pages,
1802 .pad_ib = &cayman_dma_vm_pad_ib,
1803 },
1804 .ring = {
1805 [RADEON_RING_TYPE_GFX_INDEX] = &cayman_gfx_ring,
1806 [CAYMAN_RING_TYPE_CP1_INDEX] = &cayman_gfx_ring,
1807 [CAYMAN_RING_TYPE_CP2_INDEX] = &cayman_gfx_ring,
1808 [R600_RING_TYPE_DMA_INDEX] = &cayman_dma_ring,
1809 [CAYMAN_RING_TYPE_DMA1_INDEX] = &cayman_dma_ring,
1810 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1811 [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
1812 [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
1813 },
1814 .irq = {
1815 .set = &evergreen_irq_set,
1816 .process = &evergreen_irq_process,
1817 },
1818 .display = {
1819 .bandwidth_update = &dce6_bandwidth_update,
1820 .get_vblank_counter = &evergreen_get_vblank_counter,
1821 .wait_for_vblank = &dce4_wait_for_vblank,
1822 .set_backlight_level = &atombios_set_backlight_level,
1823 .get_backlight_level = &atombios_get_backlight_level,
1824 },
1825 .copy = {
1826 .blit = &r600_copy_cpdma,
1827 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1828 .dma = &evergreen_copy_dma,
1829 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1830 .copy = &evergreen_copy_dma,
1831 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1832 },
1833 .surface = {
1834 .set_reg = r600_set_surface_reg,
1835 .clear_reg = r600_clear_surface_reg,
1836 },
1837 .hpd = {
1838 .init = &evergreen_hpd_init,
1839 .fini = &evergreen_hpd_fini,
1840 .sense = &evergreen_hpd_sense,
1841 .set_polarity = &evergreen_hpd_set_polarity,
1842 },
1843 .pm = {
1844 .misc = &evergreen_pm_misc,
1845 .prepare = &evergreen_pm_prepare,
1846 .finish = &evergreen_pm_finish,
1847 .init_profile = &sumo_pm_init_profile,
1848 .get_dynpm_state = &r600_pm_get_dynpm_state,
1849 .get_engine_clock = &radeon_atom_get_engine_clock,
1850 .set_engine_clock = &radeon_atom_set_engine_clock,
1851 .get_memory_clock = NULL,
1852 .set_memory_clock = NULL,
1853 .get_pcie_lanes = NULL,
1854 .set_pcie_lanes = NULL,
1855 .set_clock_gating = NULL,
1856 .set_uvd_clocks = &sumo_set_uvd_clocks,
1857 .set_vce_clocks = &tn_set_vce_clocks,
1858 .get_temperature = &tn_get_temp,
1859 },
1860 .dpm = {
1861 .init = &trinity_dpm_init,
1862 .setup_asic = &trinity_dpm_setup_asic,
1863 .enable = &trinity_dpm_enable,
1864 .late_enable = &trinity_dpm_late_enable,
1865 .disable = &trinity_dpm_disable,
1866 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
1867 .set_power_state = &trinity_dpm_set_power_state,
1868 .post_set_power_state = &trinity_dpm_post_set_power_state,
1869 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
1870 .fini = &trinity_dpm_fini,
1871 .get_sclk = &trinity_dpm_get_sclk,
1872 .get_mclk = &trinity_dpm_get_mclk,
1873 .print_power_state = &trinity_dpm_print_power_state,
1874 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
1875 .force_performance_level = &trinity_dpm_force_performance_level,
1876 .enable_bapm = &trinity_dpm_enable_bapm,
1877 .get_current_sclk = &trinity_dpm_get_current_sclk,
1878 .get_current_mclk = &trinity_dpm_get_current_mclk,
1879 },
1880 .pflip = {
1881 .page_flip = &evergreen_page_flip,
1882 .page_flip_pending = &evergreen_page_flip_pending,
1883 },
1884 };
1885
1886 static const struct radeon_asic_ring si_gfx_ring = {
1887 .ib_execute = &si_ring_ib_execute,
1888 .ib_parse = &si_ib_parse,
1889 .emit_fence = &si_fence_ring_emit,
1890 .emit_semaphore = &r600_semaphore_ring_emit,
1891 .cs_parse = NULL,
1892 .ring_test = &r600_ring_test,
1893 .ib_test = &r600_ib_test,
1894 .is_lockup = &si_gfx_is_lockup,
1895 .vm_flush = &si_vm_flush,
1896 .get_rptr = &cayman_gfx_get_rptr,
1897 .get_wptr = &cayman_gfx_get_wptr,
1898 .set_wptr = &cayman_gfx_set_wptr,
1899 };
1900
1901 static const struct radeon_asic_ring si_dma_ring = {
1902 .ib_execute = &cayman_dma_ring_ib_execute,
1903 .ib_parse = &evergreen_dma_ib_parse,
1904 .emit_fence = &evergreen_dma_fence_ring_emit,
1905 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1906 .cs_parse = NULL,
1907 .ring_test = &r600_dma_ring_test,
1908 .ib_test = &r600_dma_ib_test,
1909 .is_lockup = &si_dma_is_lockup,
1910 .vm_flush = &si_dma_vm_flush,
1911 .get_rptr = &cayman_dma_get_rptr,
1912 .get_wptr = &cayman_dma_get_wptr,
1913 .set_wptr = &cayman_dma_set_wptr,
1914 };
1915
1916 static struct radeon_asic si_asic = {
1917 .init = &si_init,
1918 .fini = &si_fini,
1919 .suspend = &si_suspend,
1920 .resume = &si_resume,
1921 .asic_reset = &si_asic_reset,
1922 .vga_set_state = &r600_vga_set_state,
1923 .mmio_hdp_flush = r600_mmio_hdp_flush,
1924 .gui_idle = &r600_gui_idle,
1925 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1926 .get_xclk = &si_get_xclk,
1927 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1928 .get_allowed_info_register = si_get_allowed_info_register,
1929 .gart = {
1930 .tlb_flush = &si_pcie_gart_tlb_flush,
1931 .get_page_entry = &rs600_gart_get_page_entry,
1932 .set_page = &rs600_gart_set_page,
1933 },
1934 .vm = {
1935 .init = &si_vm_init,
1936 .fini = &si_vm_fini,
1937 .copy_pages = &si_dma_vm_copy_pages,
1938 .write_pages = &si_dma_vm_write_pages,
1939 .set_pages = &si_dma_vm_set_pages,
1940 .pad_ib = &cayman_dma_vm_pad_ib,
1941 },
1942 .ring = {
1943 [RADEON_RING_TYPE_GFX_INDEX] = &si_gfx_ring,
1944 [CAYMAN_RING_TYPE_CP1_INDEX] = &si_gfx_ring,
1945 [CAYMAN_RING_TYPE_CP2_INDEX] = &si_gfx_ring,
1946 [R600_RING_TYPE_DMA_INDEX] = &si_dma_ring,
1947 [CAYMAN_RING_TYPE_DMA1_INDEX] = &si_dma_ring,
1948 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
1949 [TN_RING_TYPE_VCE1_INDEX] = &trinity_vce_ring,
1950 [TN_RING_TYPE_VCE2_INDEX] = &trinity_vce_ring,
1951 },
1952 .irq = {
1953 .set = &si_irq_set,
1954 .process = &si_irq_process,
1955 },
1956 .display = {
1957 .bandwidth_update = &dce6_bandwidth_update,
1958 .get_vblank_counter = &evergreen_get_vblank_counter,
1959 .wait_for_vblank = &dce4_wait_for_vblank,
1960 .set_backlight_level = &atombios_set_backlight_level,
1961 .get_backlight_level = &atombios_get_backlight_level,
1962 },
1963 .copy = {
1964 .blit = &r600_copy_cpdma,
1965 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1966 .dma = &si_copy_dma,
1967 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1968 .copy = &si_copy_dma,
1969 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1970 },
1971 .surface = {
1972 .set_reg = r600_set_surface_reg,
1973 .clear_reg = r600_clear_surface_reg,
1974 },
1975 .hpd = {
1976 .init = &evergreen_hpd_init,
1977 .fini = &evergreen_hpd_fini,
1978 .sense = &evergreen_hpd_sense,
1979 .set_polarity = &evergreen_hpd_set_polarity,
1980 },
1981 .pm = {
1982 .misc = &evergreen_pm_misc,
1983 .prepare = &evergreen_pm_prepare,
1984 .finish = &evergreen_pm_finish,
1985 .init_profile = &sumo_pm_init_profile,
1986 .get_dynpm_state = &r600_pm_get_dynpm_state,
1987 .get_engine_clock = &radeon_atom_get_engine_clock,
1988 .set_engine_clock = &radeon_atom_set_engine_clock,
1989 .get_memory_clock = &radeon_atom_get_memory_clock,
1990 .set_memory_clock = &radeon_atom_set_memory_clock,
1991 .get_pcie_lanes = &r600_get_pcie_lanes,
1992 .set_pcie_lanes = &r600_set_pcie_lanes,
1993 .set_clock_gating = NULL,
1994 .set_uvd_clocks = &si_set_uvd_clocks,
1995 .set_vce_clocks = &si_set_vce_clocks,
1996 .get_temperature = &si_get_temp,
1997 },
1998 .dpm = {
1999 .init = &si_dpm_init,
2000 .setup_asic = &si_dpm_setup_asic,
2001 .enable = &si_dpm_enable,
2002 .late_enable = &si_dpm_late_enable,
2003 .disable = &si_dpm_disable,
2004 .pre_set_power_state = &si_dpm_pre_set_power_state,
2005 .set_power_state = &si_dpm_set_power_state,
2006 .post_set_power_state = &si_dpm_post_set_power_state,
2007 .display_configuration_changed = &si_dpm_display_configuration_changed,
2008 .fini = &si_dpm_fini,
2009 .get_sclk = &ni_dpm_get_sclk,
2010 .get_mclk = &ni_dpm_get_mclk,
2011 .print_power_state = &ni_dpm_print_power_state,
2012 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
2013 .force_performance_level = &si_dpm_force_performance_level,
2014 .vblank_too_short = &ni_dpm_vblank_too_short,
2015 .fan_ctrl_set_mode = &si_fan_ctrl_set_mode,
2016 .fan_ctrl_get_mode = &si_fan_ctrl_get_mode,
2017 .get_fan_speed_percent = &si_fan_ctrl_get_fan_speed_percent,
2018 .set_fan_speed_percent = &si_fan_ctrl_set_fan_speed_percent,
2019 .get_current_sclk = &si_dpm_get_current_sclk,
2020 .get_current_mclk = &si_dpm_get_current_mclk,
2021 },
2022 .pflip = {
2023 .page_flip = &evergreen_page_flip,
2024 .page_flip_pending = &evergreen_page_flip_pending,
2025 },
2026 };
2027
2028 static const struct radeon_asic_ring ci_gfx_ring = {
2029 .ib_execute = &cik_ring_ib_execute,
2030 .ib_parse = &cik_ib_parse,
2031 .emit_fence = &cik_fence_gfx_ring_emit,
2032 .emit_semaphore = &cik_semaphore_ring_emit,
2033 .cs_parse = NULL,
2034 .ring_test = &cik_ring_test,
2035 .ib_test = &cik_ib_test,
2036 .is_lockup = &cik_gfx_is_lockup,
2037 .vm_flush = &cik_vm_flush,
2038 .get_rptr = &cik_gfx_get_rptr,
2039 .get_wptr = &cik_gfx_get_wptr,
2040 .set_wptr = &cik_gfx_set_wptr,
2041 };
2042
2043 static const struct radeon_asic_ring ci_cp_ring = {
2044 .ib_execute = &cik_ring_ib_execute,
2045 .ib_parse = &cik_ib_parse,
2046 .emit_fence = &cik_fence_compute_ring_emit,
2047 .emit_semaphore = &cik_semaphore_ring_emit,
2048 .cs_parse = NULL,
2049 .ring_test = &cik_ring_test,
2050 .ib_test = &cik_ib_test,
2051 .is_lockup = &cik_gfx_is_lockup,
2052 .vm_flush = &cik_vm_flush,
2053 .get_rptr = &cik_compute_get_rptr,
2054 .get_wptr = &cik_compute_get_wptr,
2055 .set_wptr = &cik_compute_set_wptr,
2056 };
2057
2058 static const struct radeon_asic_ring ci_dma_ring = {
2059 .ib_execute = &cik_sdma_ring_ib_execute,
2060 .ib_parse = &cik_ib_parse,
2061 .emit_fence = &cik_sdma_fence_ring_emit,
2062 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2063 .cs_parse = NULL,
2064 .ring_test = &cik_sdma_ring_test,
2065 .ib_test = &cik_sdma_ib_test,
2066 .is_lockup = &cik_sdma_is_lockup,
2067 .vm_flush = &cik_dma_vm_flush,
2068 .get_rptr = &cik_sdma_get_rptr,
2069 .get_wptr = &cik_sdma_get_wptr,
2070 .set_wptr = &cik_sdma_set_wptr,
2071 };
2072
2073 static const struct radeon_asic_ring ci_vce_ring = {
2074 .ib_execute = &radeon_vce_ib_execute,
2075 .emit_fence = &radeon_vce_fence_emit,
2076 .emit_semaphore = &radeon_vce_semaphore_emit,
2077 .cs_parse = &radeon_vce_cs_parse,
2078 .ring_test = &radeon_vce_ring_test,
2079 .ib_test = &radeon_vce_ib_test,
2080 .is_lockup = &radeon_ring_test_lockup,
2081 .get_rptr = &vce_v1_0_get_rptr,
2082 .get_wptr = &vce_v1_0_get_wptr,
2083 .set_wptr = &vce_v1_0_set_wptr,
2084 };
2085
2086 static struct radeon_asic ci_asic = {
2087 .init = &cik_init,
2088 .fini = &cik_fini,
2089 .suspend = &cik_suspend,
2090 .resume = &cik_resume,
2091 .asic_reset = &cik_asic_reset,
2092 .vga_set_state = &r600_vga_set_state,
2093 .mmio_hdp_flush = &r600_mmio_hdp_flush,
2094 .gui_idle = &r600_gui_idle,
2095 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2096 .get_xclk = &cik_get_xclk,
2097 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2098 .get_allowed_info_register = cik_get_allowed_info_register,
2099 .gart = {
2100 .tlb_flush = &cik_pcie_gart_tlb_flush,
2101 .get_page_entry = &rs600_gart_get_page_entry,
2102 .set_page = &rs600_gart_set_page,
2103 },
2104 .vm = {
2105 .init = &cik_vm_init,
2106 .fini = &cik_vm_fini,
2107 .copy_pages = &cik_sdma_vm_copy_pages,
2108 .write_pages = &cik_sdma_vm_write_pages,
2109 .set_pages = &cik_sdma_vm_set_pages,
2110 .pad_ib = &cik_sdma_vm_pad_ib,
2111 },
2112 .ring = {
2113 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2114 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2115 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2116 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2117 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2118 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2119 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2120 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2121 },
2122 .irq = {
2123 .set = &cik_irq_set,
2124 .process = &cik_irq_process,
2125 },
2126 .display = {
2127 .bandwidth_update = &dce8_bandwidth_update,
2128 .get_vblank_counter = &evergreen_get_vblank_counter,
2129 .wait_for_vblank = &dce4_wait_for_vblank,
2130 .set_backlight_level = &atombios_set_backlight_level,
2131 .get_backlight_level = &atombios_get_backlight_level,
2132 },
2133 .copy = {
2134 .blit = &cik_copy_cpdma,
2135 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2136 .dma = &cik_copy_dma,
2137 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2138 .copy = &cik_copy_dma,
2139 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2140 },
2141 .surface = {
2142 .set_reg = r600_set_surface_reg,
2143 .clear_reg = r600_clear_surface_reg,
2144 },
2145 .hpd = {
2146 .init = &evergreen_hpd_init,
2147 .fini = &evergreen_hpd_fini,
2148 .sense = &evergreen_hpd_sense,
2149 .set_polarity = &evergreen_hpd_set_polarity,
2150 },
2151 .pm = {
2152 .misc = &evergreen_pm_misc,
2153 .prepare = &evergreen_pm_prepare,
2154 .finish = &evergreen_pm_finish,
2155 .init_profile = &sumo_pm_init_profile,
2156 .get_dynpm_state = &r600_pm_get_dynpm_state,
2157 .get_engine_clock = &radeon_atom_get_engine_clock,
2158 .set_engine_clock = &radeon_atom_set_engine_clock,
2159 .get_memory_clock = &radeon_atom_get_memory_clock,
2160 .set_memory_clock = &radeon_atom_set_memory_clock,
2161 .get_pcie_lanes = NULL,
2162 .set_pcie_lanes = NULL,
2163 .set_clock_gating = NULL,
2164 .set_uvd_clocks = &cik_set_uvd_clocks,
2165 .set_vce_clocks = &cik_set_vce_clocks,
2166 .get_temperature = &ci_get_temp,
2167 },
2168 .dpm = {
2169 .init = &ci_dpm_init,
2170 .setup_asic = &ci_dpm_setup_asic,
2171 .enable = &ci_dpm_enable,
2172 .late_enable = &ci_dpm_late_enable,
2173 .disable = &ci_dpm_disable,
2174 .pre_set_power_state = &ci_dpm_pre_set_power_state,
2175 .set_power_state = &ci_dpm_set_power_state,
2176 .post_set_power_state = &ci_dpm_post_set_power_state,
2177 .display_configuration_changed = &ci_dpm_display_configuration_changed,
2178 .fini = &ci_dpm_fini,
2179 .get_sclk = &ci_dpm_get_sclk,
2180 .get_mclk = &ci_dpm_get_mclk,
2181 .print_power_state = &ci_dpm_print_power_state,
2182 .debugfs_print_current_performance_level = &ci_dpm_debugfs_print_current_performance_level,
2183 .force_performance_level = &ci_dpm_force_performance_level,
2184 .vblank_too_short = &ci_dpm_vblank_too_short,
2185 .powergate_uvd = &ci_dpm_powergate_uvd,
2186 .fan_ctrl_set_mode = &ci_fan_ctrl_set_mode,
2187 .fan_ctrl_get_mode = &ci_fan_ctrl_get_mode,
2188 .get_fan_speed_percent = &ci_fan_ctrl_get_fan_speed_percent,
2189 .set_fan_speed_percent = &ci_fan_ctrl_set_fan_speed_percent,
2190 .get_current_sclk = &ci_dpm_get_current_sclk,
2191 .get_current_mclk = &ci_dpm_get_current_mclk,
2192 },
2193 .pflip = {
2194 .page_flip = &evergreen_page_flip,
2195 .page_flip_pending = &evergreen_page_flip_pending,
2196 },
2197 };
2198
2199 static struct radeon_asic kv_asic = {
2200 .init = &cik_init,
2201 .fini = &cik_fini,
2202 .suspend = &cik_suspend,
2203 .resume = &cik_resume,
2204 .asic_reset = &cik_asic_reset,
2205 .vga_set_state = &r600_vga_set_state,
2206 .mmio_hdp_flush = &r600_mmio_hdp_flush,
2207 .gui_idle = &r600_gui_idle,
2208 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2209 .get_xclk = &cik_get_xclk,
2210 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2211 .get_allowed_info_register = cik_get_allowed_info_register,
2212 .gart = {
2213 .tlb_flush = &cik_pcie_gart_tlb_flush,
2214 .get_page_entry = &rs600_gart_get_page_entry,
2215 .set_page = &rs600_gart_set_page,
2216 },
2217 .vm = {
2218 .init = &cik_vm_init,
2219 .fini = &cik_vm_fini,
2220 .copy_pages = &cik_sdma_vm_copy_pages,
2221 .write_pages = &cik_sdma_vm_write_pages,
2222 .set_pages = &cik_sdma_vm_set_pages,
2223 .pad_ib = &cik_sdma_vm_pad_ib,
2224 },
2225 .ring = {
2226 [RADEON_RING_TYPE_GFX_INDEX] = &ci_gfx_ring,
2227 [CAYMAN_RING_TYPE_CP1_INDEX] = &ci_cp_ring,
2228 [CAYMAN_RING_TYPE_CP2_INDEX] = &ci_cp_ring,
2229 [R600_RING_TYPE_DMA_INDEX] = &ci_dma_ring,
2230 [CAYMAN_RING_TYPE_DMA1_INDEX] = &ci_dma_ring,
2231 [R600_RING_TYPE_UVD_INDEX] = &cayman_uvd_ring,
2232 [TN_RING_TYPE_VCE1_INDEX] = &ci_vce_ring,
2233 [TN_RING_TYPE_VCE2_INDEX] = &ci_vce_ring,
2234 },
2235 .irq = {
2236 .set = &cik_irq_set,
2237 .process = &cik_irq_process,
2238 },
2239 .display = {
2240 .bandwidth_update = &dce8_bandwidth_update,
2241 .get_vblank_counter = &evergreen_get_vblank_counter,
2242 .wait_for_vblank = &dce4_wait_for_vblank,
2243 .set_backlight_level = &atombios_set_backlight_level,
2244 .get_backlight_level = &atombios_get_backlight_level,
2245 },
2246 .copy = {
2247 .blit = &cik_copy_cpdma,
2248 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2249 .dma = &cik_copy_dma,
2250 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2251 .copy = &cik_copy_dma,
2252 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2253 },
2254 .surface = {
2255 .set_reg = r600_set_surface_reg,
2256 .clear_reg = r600_clear_surface_reg,
2257 },
2258 .hpd = {
2259 .init = &evergreen_hpd_init,
2260 .fini = &evergreen_hpd_fini,
2261 .sense = &evergreen_hpd_sense,
2262 .set_polarity = &evergreen_hpd_set_polarity,
2263 },
2264 .pm = {
2265 .misc = &evergreen_pm_misc,
2266 .prepare = &evergreen_pm_prepare,
2267 .finish = &evergreen_pm_finish,
2268 .init_profile = &sumo_pm_init_profile,
2269 .get_dynpm_state = &r600_pm_get_dynpm_state,
2270 .get_engine_clock = &radeon_atom_get_engine_clock,
2271 .set_engine_clock = &radeon_atom_set_engine_clock,
2272 .get_memory_clock = &radeon_atom_get_memory_clock,
2273 .set_memory_clock = &radeon_atom_set_memory_clock,
2274 .get_pcie_lanes = NULL,
2275 .set_pcie_lanes = NULL,
2276 .set_clock_gating = NULL,
2277 .set_uvd_clocks = &cik_set_uvd_clocks,
2278 .set_vce_clocks = &cik_set_vce_clocks,
2279 .get_temperature = &kv_get_temp,
2280 },
2281 .dpm = {
2282 .init = &kv_dpm_init,
2283 .setup_asic = &kv_dpm_setup_asic,
2284 .enable = &kv_dpm_enable,
2285 .late_enable = &kv_dpm_late_enable,
2286 .disable = &kv_dpm_disable,
2287 .pre_set_power_state = &kv_dpm_pre_set_power_state,
2288 .set_power_state = &kv_dpm_set_power_state,
2289 .post_set_power_state = &kv_dpm_post_set_power_state,
2290 .display_configuration_changed = &kv_dpm_display_configuration_changed,
2291 .fini = &kv_dpm_fini,
2292 .get_sclk = &kv_dpm_get_sclk,
2293 .get_mclk = &kv_dpm_get_mclk,
2294 .print_power_state = &kv_dpm_print_power_state,
2295 .debugfs_print_current_performance_level = &kv_dpm_debugfs_print_current_performance_level,
2296 .force_performance_level = &kv_dpm_force_performance_level,
2297 .powergate_uvd = &kv_dpm_powergate_uvd,
2298 .enable_bapm = &kv_dpm_enable_bapm,
2299 .get_current_sclk = &kv_dpm_get_current_sclk,
2300 .get_current_mclk = &kv_dpm_get_current_mclk,
2301 },
2302 .pflip = {
2303 .page_flip = &evergreen_page_flip,
2304 .page_flip_pending = &evergreen_page_flip_pending,
2305 },
2306 };
2307
2308 /**
2309 * radeon_asic_init - register asic specific callbacks
2310 *
2311 * @rdev: radeon device pointer
2312 *
2313 * Registers the appropriate asic specific callbacks for each
2314 * chip family. Also sets other asics specific info like the number
2315 * of crtcs and the register aperture accessors (all asics).
2316 * Returns 0 for success.
2317 */
radeon_asic_init(struct radeon_device * rdev)2318 int radeon_asic_init(struct radeon_device *rdev)
2319 {
2320 radeon_register_accessor_init(rdev);
2321
2322 /* set the number of crtcs */
2323 if (rdev->flags & RADEON_SINGLE_CRTC)
2324 rdev->num_crtc = 1;
2325 else
2326 rdev->num_crtc = 2;
2327
2328 rdev->has_uvd = false;
2329 rdev->has_vce = false;
2330
2331 switch (rdev->family) {
2332 case CHIP_R100:
2333 case CHIP_RV100:
2334 case CHIP_RS100:
2335 case CHIP_RV200:
2336 case CHIP_RS200:
2337 rdev->asic = &r100_asic;
2338 break;
2339 case CHIP_R200:
2340 case CHIP_RV250:
2341 case CHIP_RS300:
2342 case CHIP_RV280:
2343 rdev->asic = &r200_asic;
2344 break;
2345 case CHIP_R300:
2346 case CHIP_R350:
2347 case CHIP_RV350:
2348 case CHIP_RV380:
2349 if (rdev->flags & RADEON_IS_PCIE)
2350 rdev->asic = &r300_asic_pcie;
2351 else
2352 rdev->asic = &r300_asic;
2353 break;
2354 case CHIP_R420:
2355 case CHIP_R423:
2356 case CHIP_RV410:
2357 rdev->asic = &r420_asic;
2358 /* handle macs */
2359 if (rdev->bios == NULL) {
2360 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2361 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2362 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2363 rdev->asic->pm.set_memory_clock = NULL;
2364 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2365 }
2366 break;
2367 case CHIP_RS400:
2368 case CHIP_RS480:
2369 rdev->asic = &rs400_asic;
2370 break;
2371 case CHIP_RS600:
2372 rdev->asic = &rs600_asic;
2373 break;
2374 case CHIP_RS690:
2375 case CHIP_RS740:
2376 rdev->asic = &rs690_asic;
2377 break;
2378 case CHIP_RV515:
2379 rdev->asic = &rv515_asic;
2380 break;
2381 case CHIP_R520:
2382 case CHIP_RV530:
2383 case CHIP_RV560:
2384 case CHIP_RV570:
2385 case CHIP_R580:
2386 rdev->asic = &r520_asic;
2387 break;
2388 case CHIP_R600:
2389 rdev->asic = &r600_asic;
2390 break;
2391 case CHIP_RV610:
2392 case CHIP_RV630:
2393 case CHIP_RV620:
2394 case CHIP_RV635:
2395 case CHIP_RV670:
2396 rdev->asic = &rv6xx_asic;
2397 rdev->has_uvd = true;
2398 break;
2399 case CHIP_RS780:
2400 case CHIP_RS880:
2401 rdev->asic = &rs780_asic;
2402 /* 760G/780V/880V don't have UVD */
2403 if ((rdev->pdev->device == 0x9616)||
2404 (rdev->pdev->device == 0x9611)||
2405 (rdev->pdev->device == 0x9613)||
2406 (rdev->pdev->device == 0x9711)||
2407 (rdev->pdev->device == 0x9713))
2408 rdev->has_uvd = false;
2409 else
2410 rdev->has_uvd = true;
2411 break;
2412 case CHIP_RV770:
2413 case CHIP_RV730:
2414 case CHIP_RV710:
2415 case CHIP_RV740:
2416 rdev->asic = &rv770_asic;
2417 rdev->has_uvd = true;
2418 break;
2419 case CHIP_CEDAR:
2420 case CHIP_REDWOOD:
2421 case CHIP_JUNIPER:
2422 case CHIP_CYPRESS:
2423 case CHIP_HEMLOCK:
2424 /* set num crtcs */
2425 if (rdev->family == CHIP_CEDAR)
2426 rdev->num_crtc = 4;
2427 else
2428 rdev->num_crtc = 6;
2429 rdev->asic = &evergreen_asic;
2430 rdev->has_uvd = true;
2431 break;
2432 case CHIP_PALM:
2433 case CHIP_SUMO:
2434 case CHIP_SUMO2:
2435 rdev->asic = &sumo_asic;
2436 rdev->has_uvd = true;
2437 break;
2438 case CHIP_BARTS:
2439 case CHIP_TURKS:
2440 case CHIP_CAICOS:
2441 /* set num crtcs */
2442 if (rdev->family == CHIP_CAICOS)
2443 rdev->num_crtc = 4;
2444 else
2445 rdev->num_crtc = 6;
2446 rdev->asic = &btc_asic;
2447 rdev->has_uvd = true;
2448 break;
2449 case CHIP_CAYMAN:
2450 rdev->asic = &cayman_asic;
2451 /* set num crtcs */
2452 rdev->num_crtc = 6;
2453 rdev->has_uvd = true;
2454 break;
2455 case CHIP_ARUBA:
2456 rdev->asic = &trinity_asic;
2457 /* set num crtcs */
2458 rdev->num_crtc = 4;
2459 rdev->has_uvd = true;
2460 rdev->has_vce = true;
2461 rdev->cg_flags =
2462 RADEON_CG_SUPPORT_VCE_MGCG;
2463 break;
2464 case CHIP_TAHITI:
2465 case CHIP_PITCAIRN:
2466 case CHIP_VERDE:
2467 case CHIP_OLAND:
2468 case CHIP_HAINAN:
2469 rdev->asic = &si_asic;
2470 /* set num crtcs */
2471 if (rdev->family == CHIP_HAINAN)
2472 rdev->num_crtc = 0;
2473 else if (rdev->family == CHIP_OLAND)
2474 rdev->num_crtc = 2;
2475 else
2476 rdev->num_crtc = 6;
2477 if (rdev->family == CHIP_HAINAN) {
2478 rdev->has_uvd = false;
2479 rdev->has_vce = false;
2480 } else if (rdev->family == CHIP_OLAND) {
2481 rdev->has_uvd = true;
2482 rdev->has_vce = false;
2483 } else {
2484 rdev->has_uvd = true;
2485 rdev->has_vce = true;
2486 }
2487 switch (rdev->family) {
2488 case CHIP_TAHITI:
2489 rdev->cg_flags =
2490 RADEON_CG_SUPPORT_GFX_MGCG |
2491 RADEON_CG_SUPPORT_GFX_MGLS |
2492 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2493 RADEON_CG_SUPPORT_GFX_CGLS |
2494 RADEON_CG_SUPPORT_GFX_CGTS |
2495 RADEON_CG_SUPPORT_GFX_CP_LS |
2496 RADEON_CG_SUPPORT_MC_MGCG |
2497 RADEON_CG_SUPPORT_SDMA_MGCG |
2498 RADEON_CG_SUPPORT_BIF_LS |
2499 RADEON_CG_SUPPORT_VCE_MGCG |
2500 RADEON_CG_SUPPORT_UVD_MGCG |
2501 RADEON_CG_SUPPORT_HDP_LS |
2502 RADEON_CG_SUPPORT_HDP_MGCG;
2503 rdev->pg_flags = 0;
2504 break;
2505 case CHIP_PITCAIRN:
2506 rdev->cg_flags =
2507 RADEON_CG_SUPPORT_GFX_MGCG |
2508 RADEON_CG_SUPPORT_GFX_MGLS |
2509 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2510 RADEON_CG_SUPPORT_GFX_CGLS |
2511 RADEON_CG_SUPPORT_GFX_CGTS |
2512 RADEON_CG_SUPPORT_GFX_CP_LS |
2513 RADEON_CG_SUPPORT_GFX_RLC_LS |
2514 RADEON_CG_SUPPORT_MC_LS |
2515 RADEON_CG_SUPPORT_MC_MGCG |
2516 RADEON_CG_SUPPORT_SDMA_MGCG |
2517 RADEON_CG_SUPPORT_BIF_LS |
2518 RADEON_CG_SUPPORT_VCE_MGCG |
2519 RADEON_CG_SUPPORT_UVD_MGCG |
2520 RADEON_CG_SUPPORT_HDP_LS |
2521 RADEON_CG_SUPPORT_HDP_MGCG;
2522 rdev->pg_flags = 0;
2523 break;
2524 case CHIP_VERDE:
2525 rdev->cg_flags =
2526 RADEON_CG_SUPPORT_GFX_MGCG |
2527 RADEON_CG_SUPPORT_GFX_MGLS |
2528 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2529 RADEON_CG_SUPPORT_GFX_CGLS |
2530 RADEON_CG_SUPPORT_GFX_CGTS |
2531 RADEON_CG_SUPPORT_GFX_CP_LS |
2532 RADEON_CG_SUPPORT_GFX_RLC_LS |
2533 RADEON_CG_SUPPORT_MC_LS |
2534 RADEON_CG_SUPPORT_MC_MGCG |
2535 RADEON_CG_SUPPORT_SDMA_MGCG |
2536 RADEON_CG_SUPPORT_BIF_LS |
2537 RADEON_CG_SUPPORT_VCE_MGCG |
2538 RADEON_CG_SUPPORT_UVD_MGCG |
2539 RADEON_CG_SUPPORT_HDP_LS |
2540 RADEON_CG_SUPPORT_HDP_MGCG;
2541 rdev->pg_flags = 0 |
2542 /*RADEON_PG_SUPPORT_GFX_PG | */
2543 RADEON_PG_SUPPORT_SDMA;
2544 break;
2545 case CHIP_OLAND:
2546 rdev->cg_flags =
2547 RADEON_CG_SUPPORT_GFX_MGCG |
2548 RADEON_CG_SUPPORT_GFX_MGLS |
2549 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2550 RADEON_CG_SUPPORT_GFX_CGLS |
2551 RADEON_CG_SUPPORT_GFX_CGTS |
2552 RADEON_CG_SUPPORT_GFX_CP_LS |
2553 RADEON_CG_SUPPORT_GFX_RLC_LS |
2554 RADEON_CG_SUPPORT_MC_LS |
2555 RADEON_CG_SUPPORT_MC_MGCG |
2556 RADEON_CG_SUPPORT_SDMA_MGCG |
2557 RADEON_CG_SUPPORT_BIF_LS |
2558 RADEON_CG_SUPPORT_UVD_MGCG |
2559 RADEON_CG_SUPPORT_HDP_LS |
2560 RADEON_CG_SUPPORT_HDP_MGCG;
2561 rdev->pg_flags = 0;
2562 break;
2563 case CHIP_HAINAN:
2564 rdev->cg_flags =
2565 RADEON_CG_SUPPORT_GFX_MGCG |
2566 RADEON_CG_SUPPORT_GFX_MGLS |
2567 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2568 RADEON_CG_SUPPORT_GFX_CGLS |
2569 RADEON_CG_SUPPORT_GFX_CGTS |
2570 RADEON_CG_SUPPORT_GFX_CP_LS |
2571 RADEON_CG_SUPPORT_GFX_RLC_LS |
2572 RADEON_CG_SUPPORT_MC_LS |
2573 RADEON_CG_SUPPORT_MC_MGCG |
2574 RADEON_CG_SUPPORT_SDMA_MGCG |
2575 RADEON_CG_SUPPORT_BIF_LS |
2576 RADEON_CG_SUPPORT_HDP_LS |
2577 RADEON_CG_SUPPORT_HDP_MGCG;
2578 rdev->pg_flags = 0;
2579 break;
2580 default:
2581 rdev->cg_flags = 0;
2582 rdev->pg_flags = 0;
2583 break;
2584 }
2585 break;
2586 case CHIP_BONAIRE:
2587 case CHIP_HAWAII:
2588 rdev->asic = &ci_asic;
2589 rdev->num_crtc = 6;
2590 rdev->has_uvd = true;
2591 rdev->has_vce = true;
2592 if (rdev->family == CHIP_BONAIRE) {
2593 rdev->cg_flags =
2594 RADEON_CG_SUPPORT_GFX_MGCG |
2595 RADEON_CG_SUPPORT_GFX_MGLS |
2596 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2597 RADEON_CG_SUPPORT_GFX_CGLS |
2598 RADEON_CG_SUPPORT_GFX_CGTS |
2599 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2600 RADEON_CG_SUPPORT_GFX_CP_LS |
2601 RADEON_CG_SUPPORT_MC_LS |
2602 RADEON_CG_SUPPORT_MC_MGCG |
2603 RADEON_CG_SUPPORT_SDMA_MGCG |
2604 RADEON_CG_SUPPORT_SDMA_LS |
2605 RADEON_CG_SUPPORT_BIF_LS |
2606 RADEON_CG_SUPPORT_VCE_MGCG |
2607 RADEON_CG_SUPPORT_UVD_MGCG |
2608 RADEON_CG_SUPPORT_HDP_LS |
2609 RADEON_CG_SUPPORT_HDP_MGCG;
2610 rdev->pg_flags = 0;
2611 } else {
2612 rdev->cg_flags =
2613 RADEON_CG_SUPPORT_GFX_MGCG |
2614 RADEON_CG_SUPPORT_GFX_MGLS |
2615 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2616 RADEON_CG_SUPPORT_GFX_CGLS |
2617 RADEON_CG_SUPPORT_GFX_CGTS |
2618 RADEON_CG_SUPPORT_GFX_CP_LS |
2619 RADEON_CG_SUPPORT_MC_LS |
2620 RADEON_CG_SUPPORT_MC_MGCG |
2621 RADEON_CG_SUPPORT_SDMA_MGCG |
2622 RADEON_CG_SUPPORT_SDMA_LS |
2623 RADEON_CG_SUPPORT_BIF_LS |
2624 RADEON_CG_SUPPORT_VCE_MGCG |
2625 RADEON_CG_SUPPORT_UVD_MGCG |
2626 RADEON_CG_SUPPORT_HDP_LS |
2627 RADEON_CG_SUPPORT_HDP_MGCG;
2628 rdev->pg_flags = 0;
2629 }
2630 break;
2631 case CHIP_KAVERI:
2632 case CHIP_KABINI:
2633 case CHIP_MULLINS:
2634 rdev->asic = &kv_asic;
2635 /* set num crtcs */
2636 if (rdev->family == CHIP_KAVERI) {
2637 rdev->num_crtc = 4;
2638 rdev->cg_flags =
2639 RADEON_CG_SUPPORT_GFX_MGCG |
2640 RADEON_CG_SUPPORT_GFX_MGLS |
2641 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2642 RADEON_CG_SUPPORT_GFX_CGLS |
2643 RADEON_CG_SUPPORT_GFX_CGTS |
2644 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2645 RADEON_CG_SUPPORT_GFX_CP_LS |
2646 RADEON_CG_SUPPORT_SDMA_MGCG |
2647 RADEON_CG_SUPPORT_SDMA_LS |
2648 RADEON_CG_SUPPORT_BIF_LS |
2649 RADEON_CG_SUPPORT_VCE_MGCG |
2650 RADEON_CG_SUPPORT_UVD_MGCG |
2651 RADEON_CG_SUPPORT_HDP_LS |
2652 RADEON_CG_SUPPORT_HDP_MGCG;
2653 rdev->pg_flags = 0;
2654 /*RADEON_PG_SUPPORT_GFX_PG |
2655 RADEON_PG_SUPPORT_GFX_SMG |
2656 RADEON_PG_SUPPORT_GFX_DMG |
2657 RADEON_PG_SUPPORT_UVD |
2658 RADEON_PG_SUPPORT_VCE |
2659 RADEON_PG_SUPPORT_CP |
2660 RADEON_PG_SUPPORT_GDS |
2661 RADEON_PG_SUPPORT_RLC_SMU_HS |
2662 RADEON_PG_SUPPORT_ACP |
2663 RADEON_PG_SUPPORT_SAMU;*/
2664 } else {
2665 rdev->num_crtc = 2;
2666 rdev->cg_flags =
2667 RADEON_CG_SUPPORT_GFX_MGCG |
2668 RADEON_CG_SUPPORT_GFX_MGLS |
2669 /*RADEON_CG_SUPPORT_GFX_CGCG |*/
2670 RADEON_CG_SUPPORT_GFX_CGLS |
2671 RADEON_CG_SUPPORT_GFX_CGTS |
2672 RADEON_CG_SUPPORT_GFX_CGTS_LS |
2673 RADEON_CG_SUPPORT_GFX_CP_LS |
2674 RADEON_CG_SUPPORT_SDMA_MGCG |
2675 RADEON_CG_SUPPORT_SDMA_LS |
2676 RADEON_CG_SUPPORT_BIF_LS |
2677 RADEON_CG_SUPPORT_VCE_MGCG |
2678 RADEON_CG_SUPPORT_UVD_MGCG |
2679 RADEON_CG_SUPPORT_HDP_LS |
2680 RADEON_CG_SUPPORT_HDP_MGCG;
2681 rdev->pg_flags = 0;
2682 /*RADEON_PG_SUPPORT_GFX_PG |
2683 RADEON_PG_SUPPORT_GFX_SMG |
2684 RADEON_PG_SUPPORT_UVD |
2685 RADEON_PG_SUPPORT_VCE |
2686 RADEON_PG_SUPPORT_CP |
2687 RADEON_PG_SUPPORT_GDS |
2688 RADEON_PG_SUPPORT_RLC_SMU_HS |
2689 RADEON_PG_SUPPORT_SAMU;*/
2690 }
2691 rdev->has_uvd = true;
2692 rdev->has_vce = true;
2693 break;
2694 default:
2695 /* FIXME: not supported yet */
2696 return -EINVAL;
2697 }
2698
2699 if (rdev->flags & RADEON_IS_IGP) {
2700 rdev->asic->pm.get_memory_clock = NULL;
2701 rdev->asic->pm.set_memory_clock = NULL;
2702 }
2703
2704 if (!radeon_uvd)
2705 rdev->has_uvd = false;
2706 if (!radeon_vce)
2707 rdev->has_vce = false;
2708
2709 return 0;
2710 }
2711
2712