xref: /openbmc/linux/drivers/clk/clk-si5351.c (revision a96cbb14)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * clk-si5351.c: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
4  *
5  * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6  * Rabeeh Khoury <rabeeh@solid-run.com>
7  *
8  * References:
9  * [1] "Si5351A/B/C Data Sheet"
10  *     https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
11  * [2] "AN619: Manually Generating an Si5351 Register Map"
12  *     https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf
13  */
14 
15 #include <linux/module.h>
16 #include <linux/kernel.h>
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/rational.h>
23 #include <linux/i2c.h>
24 #include <linux/of.h>
25 #include <linux/platform_data/si5351.h>
26 #include <linux/regmap.h>
27 #include <linux/slab.h>
28 #include <linux/string.h>
29 #include <asm/div64.h>
30 
31 #include "clk-si5351.h"
32 
33 struct si5351_driver_data;
34 
35 struct si5351_parameters {
36 	unsigned long	p1;
37 	unsigned long	p2;
38 	unsigned long	p3;
39 	int		valid;
40 };
41 
42 struct si5351_hw_data {
43 	struct clk_hw			hw;
44 	struct si5351_driver_data	*drvdata;
45 	struct si5351_parameters	params;
46 	unsigned char			num;
47 };
48 
49 struct si5351_driver_data {
50 	enum si5351_variant	variant;
51 	struct i2c_client	*client;
52 	struct regmap		*regmap;
53 
54 	struct clk		*pxtal;
55 	const char		*pxtal_name;
56 	struct clk_hw		xtal;
57 	struct clk		*pclkin;
58 	const char		*pclkin_name;
59 	struct clk_hw		clkin;
60 
61 	struct si5351_hw_data	pll[2];
62 	struct si5351_hw_data	*msynth;
63 	struct si5351_hw_data	*clkout;
64 	size_t			num_clkout;
65 };
66 
67 static const char * const si5351_input_names[] = {
68 	"xtal", "clkin"
69 };
70 static const char * const si5351_pll_names[] = {
71 	"si5351_plla", "si5351_pllb", "si5351_vxco"
72 };
73 static const char * const si5351_msynth_names[] = {
74 	"ms0", "ms1", "ms2", "ms3", "ms4", "ms5", "ms6", "ms7"
75 };
76 static const char * const si5351_clkout_names[] = {
77 	"clk0", "clk1", "clk2", "clk3", "clk4", "clk5", "clk6", "clk7"
78 };
79 
80 /*
81  * Si5351 i2c regmap
82  */
si5351_reg_read(struct si5351_driver_data * drvdata,u8 reg)83 static inline u8 si5351_reg_read(struct si5351_driver_data *drvdata, u8 reg)
84 {
85 	u32 val;
86 	int ret;
87 
88 	ret = regmap_read(drvdata->regmap, reg, &val);
89 	if (ret) {
90 		dev_err(&drvdata->client->dev,
91 			"unable to read from reg%02x\n", reg);
92 		return 0;
93 	}
94 
95 	return (u8)val;
96 }
97 
si5351_bulk_read(struct si5351_driver_data * drvdata,u8 reg,u8 count,u8 * buf)98 static inline int si5351_bulk_read(struct si5351_driver_data *drvdata,
99 				   u8 reg, u8 count, u8 *buf)
100 {
101 	return regmap_bulk_read(drvdata->regmap, reg, buf, count);
102 }
103 
si5351_reg_write(struct si5351_driver_data * drvdata,u8 reg,u8 val)104 static inline int si5351_reg_write(struct si5351_driver_data *drvdata,
105 				   u8 reg, u8 val)
106 {
107 	return regmap_write(drvdata->regmap, reg, val);
108 }
109 
si5351_bulk_write(struct si5351_driver_data * drvdata,u8 reg,u8 count,const u8 * buf)110 static inline int si5351_bulk_write(struct si5351_driver_data *drvdata,
111 				    u8 reg, u8 count, const u8 *buf)
112 {
113 	return regmap_raw_write(drvdata->regmap, reg, buf, count);
114 }
115 
si5351_set_bits(struct si5351_driver_data * drvdata,u8 reg,u8 mask,u8 val)116 static inline int si5351_set_bits(struct si5351_driver_data *drvdata,
117 				  u8 reg, u8 mask, u8 val)
118 {
119 	return regmap_update_bits(drvdata->regmap, reg, mask, val);
120 }
121 
si5351_msynth_params_address(int num)122 static inline u8 si5351_msynth_params_address(int num)
123 {
124 	if (num > 5)
125 		return SI5351_CLK6_PARAMETERS + (num - 6);
126 	return SI5351_CLK0_PARAMETERS + (SI5351_PARAMETERS_LENGTH * num);
127 }
128 
si5351_read_parameters(struct si5351_driver_data * drvdata,u8 reg,struct si5351_parameters * params)129 static void si5351_read_parameters(struct si5351_driver_data *drvdata,
130 				   u8 reg, struct si5351_parameters *params)
131 {
132 	u8 buf[SI5351_PARAMETERS_LENGTH];
133 
134 	switch (reg) {
135 	case SI5351_CLK6_PARAMETERS:
136 	case SI5351_CLK7_PARAMETERS:
137 		buf[0] = si5351_reg_read(drvdata, reg);
138 		params->p1 = buf[0];
139 		params->p2 = 0;
140 		params->p3 = 1;
141 		break;
142 	default:
143 		si5351_bulk_read(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
144 		params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4];
145 		params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7];
146 		params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1];
147 	}
148 	params->valid = 1;
149 }
150 
si5351_write_parameters(struct si5351_driver_data * drvdata,u8 reg,struct si5351_parameters * params)151 static void si5351_write_parameters(struct si5351_driver_data *drvdata,
152 				    u8 reg, struct si5351_parameters *params)
153 {
154 	u8 buf[SI5351_PARAMETERS_LENGTH];
155 
156 	switch (reg) {
157 	case SI5351_CLK6_PARAMETERS:
158 	case SI5351_CLK7_PARAMETERS:
159 		buf[0] = params->p1 & 0xff;
160 		si5351_reg_write(drvdata, reg, buf[0]);
161 		break;
162 	default:
163 		buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff;
164 		buf[1] = params->p3 & 0xff;
165 		/* save rdiv and divby4 */
166 		buf[2] = si5351_reg_read(drvdata, reg + 2) & ~0x03;
167 		buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03;
168 		buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff;
169 		buf[4] = params->p1 & 0xff;
170 		buf[5] = ((params->p3 & 0xf0000) >> 12) |
171 			((params->p2 & 0xf0000) >> 16);
172 		buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff;
173 		buf[7] = params->p2 & 0xff;
174 		si5351_bulk_write(drvdata, reg, SI5351_PARAMETERS_LENGTH, buf);
175 	}
176 }
177 
si5351_regmap_is_volatile(struct device * dev,unsigned int reg)178 static bool si5351_regmap_is_volatile(struct device *dev, unsigned int reg)
179 {
180 	switch (reg) {
181 	case SI5351_DEVICE_STATUS:
182 	case SI5351_INTERRUPT_STATUS:
183 	case SI5351_PLL_RESET:
184 		return true;
185 	}
186 	return false;
187 }
188 
si5351_regmap_is_writeable(struct device * dev,unsigned int reg)189 static bool si5351_regmap_is_writeable(struct device *dev, unsigned int reg)
190 {
191 	/* reserved registers */
192 	if (reg >= 4 && reg <= 8)
193 		return false;
194 	if (reg >= 10 && reg <= 14)
195 		return false;
196 	if (reg >= 173 && reg <= 176)
197 		return false;
198 	if (reg >= 178 && reg <= 182)
199 		return false;
200 	/* read-only */
201 	if (reg == SI5351_DEVICE_STATUS)
202 		return false;
203 	return true;
204 }
205 
206 static const struct regmap_config si5351_regmap_config = {
207 	.reg_bits = 8,
208 	.val_bits = 8,
209 	.cache_type = REGCACHE_RBTREE,
210 	.max_register = 187,
211 	.writeable_reg = si5351_regmap_is_writeable,
212 	.volatile_reg = si5351_regmap_is_volatile,
213 };
214 
215 /*
216  * Si5351 xtal clock input
217  */
si5351_xtal_prepare(struct clk_hw * hw)218 static int si5351_xtal_prepare(struct clk_hw *hw)
219 {
220 	struct si5351_driver_data *drvdata =
221 		container_of(hw, struct si5351_driver_data, xtal);
222 	si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
223 			SI5351_XTAL_ENABLE, SI5351_XTAL_ENABLE);
224 	return 0;
225 }
226 
si5351_xtal_unprepare(struct clk_hw * hw)227 static void si5351_xtal_unprepare(struct clk_hw *hw)
228 {
229 	struct si5351_driver_data *drvdata =
230 		container_of(hw, struct si5351_driver_data, xtal);
231 	si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
232 			SI5351_XTAL_ENABLE, 0);
233 }
234 
235 static const struct clk_ops si5351_xtal_ops = {
236 	.prepare = si5351_xtal_prepare,
237 	.unprepare = si5351_xtal_unprepare,
238 };
239 
240 /*
241  * Si5351 clkin clock input (Si5351C only)
242  */
si5351_clkin_prepare(struct clk_hw * hw)243 static int si5351_clkin_prepare(struct clk_hw *hw)
244 {
245 	struct si5351_driver_data *drvdata =
246 		container_of(hw, struct si5351_driver_data, clkin);
247 	si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
248 			SI5351_CLKIN_ENABLE, SI5351_CLKIN_ENABLE);
249 	return 0;
250 }
251 
si5351_clkin_unprepare(struct clk_hw * hw)252 static void si5351_clkin_unprepare(struct clk_hw *hw)
253 {
254 	struct si5351_driver_data *drvdata =
255 		container_of(hw, struct si5351_driver_data, clkin);
256 	si5351_set_bits(drvdata, SI5351_FANOUT_ENABLE,
257 			SI5351_CLKIN_ENABLE, 0);
258 }
259 
260 /*
261  * CMOS clock source constraints:
262  * The input frequency range of the PLL is 10Mhz to 40MHz.
263  * If CLKIN is >40MHz, the input divider must be used.
264  */
si5351_clkin_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)265 static unsigned long si5351_clkin_recalc_rate(struct clk_hw *hw,
266 					      unsigned long parent_rate)
267 {
268 	struct si5351_driver_data *drvdata =
269 		container_of(hw, struct si5351_driver_data, clkin);
270 	unsigned long rate;
271 	unsigned char idiv;
272 
273 	rate = parent_rate;
274 	if (parent_rate > 160000000) {
275 		idiv = SI5351_CLKIN_DIV_8;
276 		rate /= 8;
277 	} else if (parent_rate > 80000000) {
278 		idiv = SI5351_CLKIN_DIV_4;
279 		rate /= 4;
280 	} else if (parent_rate > 40000000) {
281 		idiv = SI5351_CLKIN_DIV_2;
282 		rate /= 2;
283 	} else {
284 		idiv = SI5351_CLKIN_DIV_1;
285 	}
286 
287 	si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
288 			SI5351_CLKIN_DIV_MASK, idiv);
289 
290 	dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n",
291 		__func__, (1 << (idiv >> 6)), rate);
292 
293 	return rate;
294 }
295 
296 static const struct clk_ops si5351_clkin_ops = {
297 	.prepare = si5351_clkin_prepare,
298 	.unprepare = si5351_clkin_unprepare,
299 	.recalc_rate = si5351_clkin_recalc_rate,
300 };
301 
302 /*
303  * Si5351 vxco clock input (Si5351B only)
304  */
305 
si5351_vxco_prepare(struct clk_hw * hw)306 static int si5351_vxco_prepare(struct clk_hw *hw)
307 {
308 	struct si5351_hw_data *hwdata =
309 		container_of(hw, struct si5351_hw_data, hw);
310 
311 	dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n");
312 
313 	return 0;
314 }
315 
si5351_vxco_unprepare(struct clk_hw * hw)316 static void si5351_vxco_unprepare(struct clk_hw *hw)
317 {
318 }
319 
si5351_vxco_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)320 static unsigned long si5351_vxco_recalc_rate(struct clk_hw *hw,
321 					     unsigned long parent_rate)
322 {
323 	return 0;
324 }
325 
si5351_vxco_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent)326 static int si5351_vxco_set_rate(struct clk_hw *hw, unsigned long rate,
327 				unsigned long parent)
328 {
329 	return 0;
330 }
331 
332 static const struct clk_ops si5351_vxco_ops = {
333 	.prepare = si5351_vxco_prepare,
334 	.unprepare = si5351_vxco_unprepare,
335 	.recalc_rate = si5351_vxco_recalc_rate,
336 	.set_rate = si5351_vxco_set_rate,
337 };
338 
339 /*
340  * Si5351 pll a/b
341  *
342  * Feedback Multisynth Divider Equations [2]
343  *
344  * fVCO = fIN * (a + b/c)
345  *
346  * with 15 + 0/1048575 <= (a + b/c) <= 90 + 0/1048575 and
347  * fIN = fXTAL or fIN = fCLKIN/CLKIN_DIV
348  *
349  * Feedback Multisynth Register Equations
350  *
351  * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
352  * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
353  * (3) MSNx_P3[19:0] = c
354  *
355  * Transposing (2) yields: (4) floor(128 * b/c) = (128 * b / MSNx_P2)/c
356  *
357  * Using (4) on (1) yields:
358  * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512
359  * MSNx_P1 + 512 + MSNx_P2/c = 128 * a + 128 * b/c
360  *
361  * a + b/c = (MSNx_P1 + MSNx_P2/MSNx_P3 + 512)/128
362  *         = (MSNx_P1*MSNx_P3 + MSNx_P2 + 512*MSNx_P3)/(128*MSNx_P3)
363  *
364  */
_si5351_pll_reparent(struct si5351_driver_data * drvdata,int num,enum si5351_pll_src parent)365 static int _si5351_pll_reparent(struct si5351_driver_data *drvdata,
366 				int num, enum si5351_pll_src parent)
367 {
368 	u8 mask = (num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
369 
370 	if (parent == SI5351_PLL_SRC_DEFAULT)
371 		return 0;
372 
373 	if (num > 2)
374 		return -EINVAL;
375 
376 	if (drvdata->variant != SI5351_VARIANT_C &&
377 	    parent != SI5351_PLL_SRC_XTAL)
378 		return -EINVAL;
379 
380 	si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE, mask,
381 			(parent == SI5351_PLL_SRC_XTAL) ? 0 : mask);
382 	return 0;
383 }
384 
si5351_pll_get_parent(struct clk_hw * hw)385 static unsigned char si5351_pll_get_parent(struct clk_hw *hw)
386 {
387 	struct si5351_hw_data *hwdata =
388 		container_of(hw, struct si5351_hw_data, hw);
389 	u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE;
390 	u8 val;
391 
392 	val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE);
393 
394 	return (val & mask) ? 1 : 0;
395 }
396 
si5351_pll_set_parent(struct clk_hw * hw,u8 index)397 static int si5351_pll_set_parent(struct clk_hw *hw, u8 index)
398 {
399 	struct si5351_hw_data *hwdata =
400 		container_of(hw, struct si5351_hw_data, hw);
401 
402 	if (hwdata->drvdata->variant != SI5351_VARIANT_C &&
403 	    index > 0)
404 		return -EPERM;
405 
406 	if (index > 1)
407 		return -EINVAL;
408 
409 	return _si5351_pll_reparent(hwdata->drvdata, hwdata->num,
410 			     (index == 0) ? SI5351_PLL_SRC_XTAL :
411 			     SI5351_PLL_SRC_CLKIN);
412 }
413 
si5351_pll_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)414 static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw,
415 					    unsigned long parent_rate)
416 {
417 	struct si5351_hw_data *hwdata =
418 		container_of(hw, struct si5351_hw_data, hw);
419 	u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
420 		SI5351_PLLB_PARAMETERS;
421 	unsigned long long rate;
422 
423 	if (!hwdata->params.valid)
424 		si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
425 
426 	if (hwdata->params.p3 == 0)
427 		return parent_rate;
428 
429 	/* fVCO = fIN * (P1*P3 + 512*P3 + P2)/(128*P3) */
430 	rate  = hwdata->params.p1 * hwdata->params.p3;
431 	rate += 512 * hwdata->params.p3;
432 	rate += hwdata->params.p2;
433 	rate *= parent_rate;
434 	do_div(rate, 128 * hwdata->params.p3);
435 
436 	dev_dbg(&hwdata->drvdata->client->dev,
437 		"%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
438 		__func__, clk_hw_get_name(hw),
439 		hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
440 		parent_rate, (unsigned long)rate);
441 
442 	return (unsigned long)rate;
443 }
444 
si5351_pll_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)445 static int si5351_pll_determine_rate(struct clk_hw *hw,
446 				     struct clk_rate_request *req)
447 {
448 	struct si5351_hw_data *hwdata =
449 		container_of(hw, struct si5351_hw_data, hw);
450 	unsigned long rate = req->rate;
451 	unsigned long rfrac, denom, a, b, c;
452 	unsigned long long lltmp;
453 
454 	if (rate < SI5351_PLL_VCO_MIN)
455 		rate = SI5351_PLL_VCO_MIN;
456 	if (rate > SI5351_PLL_VCO_MAX)
457 		rate = SI5351_PLL_VCO_MAX;
458 
459 	/* determine integer part of feedback equation */
460 	a = rate / req->best_parent_rate;
461 
462 	if (a < SI5351_PLL_A_MIN)
463 		rate = req->best_parent_rate * SI5351_PLL_A_MIN;
464 	if (a > SI5351_PLL_A_MAX)
465 		rate = req->best_parent_rate * SI5351_PLL_A_MAX;
466 
467 	/* find best approximation for b/c = fVCO mod fIN */
468 	denom = 1000 * 1000;
469 	lltmp = rate % (req->best_parent_rate);
470 	lltmp *= denom;
471 	do_div(lltmp, req->best_parent_rate);
472 	rfrac = (unsigned long)lltmp;
473 
474 	b = 0;
475 	c = 1;
476 	if (rfrac)
477 		rational_best_approximation(rfrac, denom,
478 				    SI5351_PLL_B_MAX, SI5351_PLL_C_MAX, &b, &c);
479 
480 	/* calculate parameters */
481 	hwdata->params.p3  = c;
482 	hwdata->params.p2  = (128 * b) % c;
483 	hwdata->params.p1  = 128 * a;
484 	hwdata->params.p1 += (128 * b / c);
485 	hwdata->params.p1 -= 512;
486 
487 	/* recalculate rate by fIN * (a + b/c) */
488 	lltmp  = req->best_parent_rate;
489 	lltmp *= b;
490 	do_div(lltmp, c);
491 
492 	rate  = (unsigned long)lltmp;
493 	rate += req->best_parent_rate * a;
494 
495 	dev_dbg(&hwdata->drvdata->client->dev,
496 		"%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n",
497 		__func__, clk_hw_get_name(hw), a, b, c,
498 		req->best_parent_rate, rate);
499 
500 	req->rate = rate;
501 	return 0;
502 }
503 
si5351_pll_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)504 static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate,
505 			       unsigned long parent_rate)
506 {
507 	struct si5351_hw_data *hwdata =
508 		container_of(hw, struct si5351_hw_data, hw);
509 	u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS :
510 		SI5351_PLLB_PARAMETERS;
511 
512 	/* write multisynth parameters */
513 	si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
514 
515 	/* plla/pllb ctrl is in clk6/clk7 ctrl registers */
516 	si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num,
517 		SI5351_CLK_INTEGER_MODE,
518 		(hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
519 
520 	/* Do a pll soft reset on the affected pll */
521 	si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET,
522 			 hwdata->num == 0 ? SI5351_PLL_RESET_A :
523 					    SI5351_PLL_RESET_B);
524 
525 	dev_dbg(&hwdata->drvdata->client->dev,
526 		"%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n",
527 		__func__, clk_hw_get_name(hw),
528 		hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
529 		parent_rate, rate);
530 
531 	return 0;
532 }
533 
534 static const struct clk_ops si5351_pll_ops = {
535 	.set_parent = si5351_pll_set_parent,
536 	.get_parent = si5351_pll_get_parent,
537 	.recalc_rate = si5351_pll_recalc_rate,
538 	.determine_rate = si5351_pll_determine_rate,
539 	.set_rate = si5351_pll_set_rate,
540 };
541 
542 /*
543  * Si5351 multisync divider
544  *
545  * for fOUT <= 150 MHz:
546  *
547  * fOUT = (fIN * (a + b/c)) / CLKOUTDIV
548  *
549  * with 6 + 0/1048575 <= (a + b/c) <= 1800 + 0/1048575 and
550  * fIN = fVCO0, fVCO1
551  *
552  * Output Clock Multisynth Register Equations
553  *
554  * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
555  * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
556  * MSx_P3[19:0] = c
557  *
558  * MS[6,7] are integer (P1) divide only, P1 = divide value,
559  * P2 and P3 are not applicable
560  *
561  * for 150MHz < fOUT <= 160MHz:
562  *
563  * MSx_P1 = 0, MSx_P2 = 0, MSx_P3 = 1, MSx_INT = 1, MSx_DIVBY4 = 11b
564  */
_si5351_msynth_reparent(struct si5351_driver_data * drvdata,int num,enum si5351_multisynth_src parent)565 static int _si5351_msynth_reparent(struct si5351_driver_data *drvdata,
566 				   int num, enum si5351_multisynth_src parent)
567 {
568 	if (parent == SI5351_MULTISYNTH_SRC_DEFAULT)
569 		return 0;
570 
571 	if (num > 8)
572 		return -EINVAL;
573 
574 	si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num, SI5351_CLK_PLL_SELECT,
575 			(parent == SI5351_MULTISYNTH_SRC_VCO0) ? 0 :
576 			SI5351_CLK_PLL_SELECT);
577 	return 0;
578 }
579 
si5351_msynth_get_parent(struct clk_hw * hw)580 static unsigned char si5351_msynth_get_parent(struct clk_hw *hw)
581 {
582 	struct si5351_hw_data *hwdata =
583 		container_of(hw, struct si5351_hw_data, hw);
584 	u8 val;
585 
586 	val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
587 
588 	return (val & SI5351_CLK_PLL_SELECT) ? 1 : 0;
589 }
590 
si5351_msynth_set_parent(struct clk_hw * hw,u8 index)591 static int si5351_msynth_set_parent(struct clk_hw *hw, u8 index)
592 {
593 	struct si5351_hw_data *hwdata =
594 		container_of(hw, struct si5351_hw_data, hw);
595 
596 	return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num,
597 			       (index == 0) ? SI5351_MULTISYNTH_SRC_VCO0 :
598 			       SI5351_MULTISYNTH_SRC_VCO1);
599 }
600 
si5351_msynth_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)601 static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
602 					       unsigned long parent_rate)
603 {
604 	struct si5351_hw_data *hwdata =
605 		container_of(hw, struct si5351_hw_data, hw);
606 	u8 reg = si5351_msynth_params_address(hwdata->num);
607 	unsigned long long rate;
608 	unsigned long m;
609 
610 	if (!hwdata->params.valid)
611 		si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params);
612 
613 	/*
614 	 * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3)
615 	 * multisync6-7: fOUT = fIN / P1
616 	 */
617 	rate = parent_rate;
618 	if (hwdata->num > 5) {
619 		m = hwdata->params.p1;
620 	} else if (hwdata->params.p3 == 0) {
621 		return parent_rate;
622 	} else if ((si5351_reg_read(hwdata->drvdata, reg + 2) &
623 		    SI5351_OUTPUT_CLK_DIVBY4) == SI5351_OUTPUT_CLK_DIVBY4) {
624 		m = 4;
625 	} else {
626 		rate *= 128 * hwdata->params.p3;
627 		m = hwdata->params.p1 * hwdata->params.p3;
628 		m += hwdata->params.p2;
629 		m += 512 * hwdata->params.p3;
630 	}
631 
632 	if (m == 0)
633 		return 0;
634 	do_div(rate, m);
635 
636 	dev_dbg(&hwdata->drvdata->client->dev,
637 		"%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n",
638 		__func__, clk_hw_get_name(hw),
639 		hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
640 		m, parent_rate, (unsigned long)rate);
641 
642 	return (unsigned long)rate;
643 }
644 
si5351_msynth_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)645 static int si5351_msynth_determine_rate(struct clk_hw *hw,
646 					struct clk_rate_request *req)
647 {
648 	struct si5351_hw_data *hwdata =
649 		container_of(hw, struct si5351_hw_data, hw);
650 	unsigned long rate = req->rate;
651 	unsigned long long lltmp;
652 	unsigned long a, b, c;
653 	int divby4;
654 
655 	/* multisync6-7 can only handle freqencies < 150MHz */
656 	if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ)
657 		rate = SI5351_MULTISYNTH67_MAX_FREQ;
658 
659 	/* multisync frequency is 1MHz .. 160MHz */
660 	if (rate > SI5351_MULTISYNTH_MAX_FREQ)
661 		rate = SI5351_MULTISYNTH_MAX_FREQ;
662 	if (rate < SI5351_MULTISYNTH_MIN_FREQ)
663 		rate = SI5351_MULTISYNTH_MIN_FREQ;
664 
665 	divby4 = 0;
666 	if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
667 		divby4 = 1;
668 
669 	/* multisync can set pll */
670 	if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
671 		/*
672 		 * find largest integer divider for max
673 		 * vco frequency and given target rate
674 		 */
675 		if (divby4 == 0) {
676 			lltmp = SI5351_PLL_VCO_MAX;
677 			do_div(lltmp, rate);
678 			a = (unsigned long)lltmp;
679 		} else
680 			a = 4;
681 
682 		b = 0;
683 		c = 1;
684 
685 		req->best_parent_rate = a * rate;
686 	} else if (hwdata->num >= 6) {
687 		/* determine the closest integer divider */
688 		a = DIV_ROUND_CLOSEST(req->best_parent_rate, rate);
689 		if (a < SI5351_MULTISYNTH_A_MIN)
690 			a = SI5351_MULTISYNTH_A_MIN;
691 		if (a > SI5351_MULTISYNTH67_A_MAX)
692 			a = SI5351_MULTISYNTH67_A_MAX;
693 
694 		b = 0;
695 		c = 1;
696 	} else {
697 		unsigned long rfrac, denom;
698 
699 		/* disable divby4 */
700 		if (divby4) {
701 			rate = SI5351_MULTISYNTH_DIVBY4_FREQ;
702 			divby4 = 0;
703 		}
704 
705 		/* determine integer part of divider equation */
706 		a = req->best_parent_rate / rate;
707 		if (a < SI5351_MULTISYNTH_A_MIN)
708 			a = SI5351_MULTISYNTH_A_MIN;
709 		if (a > SI5351_MULTISYNTH_A_MAX)
710 			a = SI5351_MULTISYNTH_A_MAX;
711 
712 		/* find best approximation for b/c = fVCO mod fOUT */
713 		denom = 1000 * 1000;
714 		lltmp = req->best_parent_rate % rate;
715 		lltmp *= denom;
716 		do_div(lltmp, rate);
717 		rfrac = (unsigned long)lltmp;
718 
719 		b = 0;
720 		c = 1;
721 		if (rfrac)
722 			rational_best_approximation(rfrac, denom,
723 			    SI5351_MULTISYNTH_B_MAX, SI5351_MULTISYNTH_C_MAX,
724 			    &b, &c);
725 	}
726 
727 	/* recalculate rate by fOUT = fIN / (a + b/c) */
728 	lltmp  = req->best_parent_rate;
729 	lltmp *= c;
730 	do_div(lltmp, a * c + b);
731 	rate  = (unsigned long)lltmp;
732 
733 	/* calculate parameters */
734 	if (divby4) {
735 		hwdata->params.p3 = 1;
736 		hwdata->params.p2 = 0;
737 		hwdata->params.p1 = 0;
738 	} else if (hwdata->num >= 6) {
739 		hwdata->params.p3 = 0;
740 		hwdata->params.p2 = 0;
741 		hwdata->params.p1 = a;
742 	} else {
743 		hwdata->params.p3  = c;
744 		hwdata->params.p2  = (128 * b) % c;
745 		hwdata->params.p1  = 128 * a;
746 		hwdata->params.p1 += (128 * b / c);
747 		hwdata->params.p1 -= 512;
748 	}
749 
750 	dev_dbg(&hwdata->drvdata->client->dev,
751 		"%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
752 		__func__, clk_hw_get_name(hw), a, b, c, divby4,
753 		req->best_parent_rate, rate);
754 
755 	req->rate = rate;
756 
757 	return 0;
758 }
759 
si5351_msynth_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)760 static int si5351_msynth_set_rate(struct clk_hw *hw, unsigned long rate,
761 				  unsigned long parent_rate)
762 {
763 	struct si5351_hw_data *hwdata =
764 		container_of(hw, struct si5351_hw_data, hw);
765 	u8 reg = si5351_msynth_params_address(hwdata->num);
766 	int divby4 = 0;
767 
768 	/* write multisynth parameters */
769 	si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params);
770 
771 	if (rate > SI5351_MULTISYNTH_DIVBY4_FREQ)
772 		divby4 = 1;
773 
774 	/* enable/disable integer mode and divby4 on multisynth0-5 */
775 	if (hwdata->num < 6) {
776 		si5351_set_bits(hwdata->drvdata, reg + 2,
777 				SI5351_OUTPUT_CLK_DIVBY4,
778 				(divby4) ? SI5351_OUTPUT_CLK_DIVBY4 : 0);
779 		si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
780 			SI5351_CLK_INTEGER_MODE,
781 			(hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0);
782 	}
783 
784 	dev_dbg(&hwdata->drvdata->client->dev,
785 		"%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n",
786 		__func__, clk_hw_get_name(hw),
787 		hwdata->params.p1, hwdata->params.p2, hwdata->params.p3,
788 		divby4, parent_rate, rate);
789 
790 	return 0;
791 }
792 
793 static const struct clk_ops si5351_msynth_ops = {
794 	.set_parent = si5351_msynth_set_parent,
795 	.get_parent = si5351_msynth_get_parent,
796 	.recalc_rate = si5351_msynth_recalc_rate,
797 	.determine_rate = si5351_msynth_determine_rate,
798 	.set_rate = si5351_msynth_set_rate,
799 };
800 
801 /*
802  * Si5351 clkout divider
803  */
_si5351_clkout_reparent(struct si5351_driver_data * drvdata,int num,enum si5351_clkout_src parent)804 static int _si5351_clkout_reparent(struct si5351_driver_data *drvdata,
805 				   int num, enum si5351_clkout_src parent)
806 {
807 	u8 val;
808 
809 	if (num > 8)
810 		return -EINVAL;
811 
812 	switch (parent) {
813 	case SI5351_CLKOUT_SRC_MSYNTH_N:
814 		val = SI5351_CLK_INPUT_MULTISYNTH_N;
815 		break;
816 	case SI5351_CLKOUT_SRC_MSYNTH_0_4:
817 		/* clk0/clk4 can only connect to its own multisync */
818 		if (num == 0 || num == 4)
819 			val = SI5351_CLK_INPUT_MULTISYNTH_N;
820 		else
821 			val = SI5351_CLK_INPUT_MULTISYNTH_0_4;
822 		break;
823 	case SI5351_CLKOUT_SRC_XTAL:
824 		val = SI5351_CLK_INPUT_XTAL;
825 		break;
826 	case SI5351_CLKOUT_SRC_CLKIN:
827 		if (drvdata->variant != SI5351_VARIANT_C)
828 			return -EINVAL;
829 
830 		val = SI5351_CLK_INPUT_CLKIN;
831 		break;
832 	default:
833 		return 0;
834 	}
835 
836 	si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
837 			SI5351_CLK_INPUT_MASK, val);
838 	return 0;
839 }
840 
_si5351_clkout_set_drive_strength(struct si5351_driver_data * drvdata,int num,enum si5351_drive_strength drive)841 static int _si5351_clkout_set_drive_strength(
842 	struct si5351_driver_data *drvdata, int num,
843 	enum si5351_drive_strength drive)
844 {
845 	u8 mask;
846 
847 	if (num > 8)
848 		return -EINVAL;
849 
850 	switch (drive) {
851 	case SI5351_DRIVE_2MA:
852 		mask = SI5351_CLK_DRIVE_STRENGTH_2MA;
853 		break;
854 	case SI5351_DRIVE_4MA:
855 		mask = SI5351_CLK_DRIVE_STRENGTH_4MA;
856 		break;
857 	case SI5351_DRIVE_6MA:
858 		mask = SI5351_CLK_DRIVE_STRENGTH_6MA;
859 		break;
860 	case SI5351_DRIVE_8MA:
861 		mask = SI5351_CLK_DRIVE_STRENGTH_8MA;
862 		break;
863 	default:
864 		return 0;
865 	}
866 
867 	si5351_set_bits(drvdata, SI5351_CLK0_CTRL + num,
868 			SI5351_CLK_DRIVE_STRENGTH_MASK, mask);
869 	return 0;
870 }
871 
_si5351_clkout_set_disable_state(struct si5351_driver_data * drvdata,int num,enum si5351_disable_state state)872 static int _si5351_clkout_set_disable_state(
873 	struct si5351_driver_data *drvdata, int num,
874 	enum si5351_disable_state state)
875 {
876 	u8 reg = (num < 4) ? SI5351_CLK3_0_DISABLE_STATE :
877 		SI5351_CLK7_4_DISABLE_STATE;
878 	u8 shift = (num < 4) ? (2 * num) : (2 * (num-4));
879 	u8 mask = SI5351_CLK_DISABLE_STATE_MASK << shift;
880 	u8 val;
881 
882 	if (num > 8)
883 		return -EINVAL;
884 
885 	switch (state) {
886 	case SI5351_DISABLE_LOW:
887 		val = SI5351_CLK_DISABLE_STATE_LOW;
888 		break;
889 	case SI5351_DISABLE_HIGH:
890 		val = SI5351_CLK_DISABLE_STATE_HIGH;
891 		break;
892 	case SI5351_DISABLE_FLOATING:
893 		val = SI5351_CLK_DISABLE_STATE_FLOAT;
894 		break;
895 	case SI5351_DISABLE_NEVER:
896 		val = SI5351_CLK_DISABLE_STATE_NEVER;
897 		break;
898 	default:
899 		return 0;
900 	}
901 
902 	si5351_set_bits(drvdata, reg, mask, val << shift);
903 
904 	return 0;
905 }
906 
_si5351_clkout_reset_pll(struct si5351_driver_data * drvdata,int num)907 static void _si5351_clkout_reset_pll(struct si5351_driver_data *drvdata, int num)
908 {
909 	u8 val = si5351_reg_read(drvdata, SI5351_CLK0_CTRL + num);
910 	u8 mask = val & SI5351_CLK_PLL_SELECT ? SI5351_PLL_RESET_B :
911 						       SI5351_PLL_RESET_A;
912 	unsigned int v;
913 	int err;
914 
915 	switch (val & SI5351_CLK_INPUT_MASK) {
916 	case SI5351_CLK_INPUT_XTAL:
917 	case SI5351_CLK_INPUT_CLKIN:
918 		return;  /* pll not used, no need to reset */
919 	}
920 
921 	si5351_reg_write(drvdata, SI5351_PLL_RESET, mask);
922 
923 	err = regmap_read_poll_timeout(drvdata->regmap, SI5351_PLL_RESET, v,
924 				 !(v & mask), 0, 20000);
925 	if (err < 0)
926 		dev_err(&drvdata->client->dev, "Reset bit didn't clear\n");
927 
928 	dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n",
929 		__func__, clk_hw_get_name(&drvdata->clkout[num].hw),
930 		(val & SI5351_CLK_PLL_SELECT) ? 1 : 0);
931 }
932 
si5351_clkout_prepare(struct clk_hw * hw)933 static int si5351_clkout_prepare(struct clk_hw *hw)
934 {
935 	struct si5351_hw_data *hwdata =
936 		container_of(hw, struct si5351_hw_data, hw);
937 	struct si5351_platform_data *pdata =
938 		hwdata->drvdata->client->dev.platform_data;
939 
940 	si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
941 			SI5351_CLK_POWERDOWN, 0);
942 
943 	/*
944 	 * Do a pll soft reset on the parent pll -- needed to get a
945 	 * deterministic phase relationship between the output clocks.
946 	 */
947 	if (pdata->clkout[hwdata->num].pll_reset)
948 		_si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num);
949 
950 	si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
951 			(1 << hwdata->num), 0);
952 	return 0;
953 }
954 
si5351_clkout_unprepare(struct clk_hw * hw)955 static void si5351_clkout_unprepare(struct clk_hw *hw)
956 {
957 	struct si5351_hw_data *hwdata =
958 		container_of(hw, struct si5351_hw_data, hw);
959 
960 	si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
961 			SI5351_CLK_POWERDOWN, SI5351_CLK_POWERDOWN);
962 	si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL,
963 			(1 << hwdata->num), (1 << hwdata->num));
964 }
965 
si5351_clkout_get_parent(struct clk_hw * hw)966 static u8 si5351_clkout_get_parent(struct clk_hw *hw)
967 {
968 	struct si5351_hw_data *hwdata =
969 		container_of(hw, struct si5351_hw_data, hw);
970 	int index = 0;
971 	unsigned char val;
972 
973 	val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num);
974 	switch (val & SI5351_CLK_INPUT_MASK) {
975 	case SI5351_CLK_INPUT_MULTISYNTH_N:
976 		index = 0;
977 		break;
978 	case SI5351_CLK_INPUT_MULTISYNTH_0_4:
979 		index = 1;
980 		break;
981 	case SI5351_CLK_INPUT_XTAL:
982 		index = 2;
983 		break;
984 	case SI5351_CLK_INPUT_CLKIN:
985 		index = 3;
986 		break;
987 	}
988 
989 	return index;
990 }
991 
si5351_clkout_set_parent(struct clk_hw * hw,u8 index)992 static int si5351_clkout_set_parent(struct clk_hw *hw, u8 index)
993 {
994 	struct si5351_hw_data *hwdata =
995 		container_of(hw, struct si5351_hw_data, hw);
996 	enum si5351_clkout_src parent = SI5351_CLKOUT_SRC_DEFAULT;
997 
998 	switch (index) {
999 	case 0:
1000 		parent = SI5351_CLKOUT_SRC_MSYNTH_N;
1001 		break;
1002 	case 1:
1003 		parent = SI5351_CLKOUT_SRC_MSYNTH_0_4;
1004 		break;
1005 	case 2:
1006 		parent = SI5351_CLKOUT_SRC_XTAL;
1007 		break;
1008 	case 3:
1009 		parent = SI5351_CLKOUT_SRC_CLKIN;
1010 		break;
1011 	}
1012 
1013 	return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent);
1014 }
1015 
si5351_clkout_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1016 static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
1017 					       unsigned long parent_rate)
1018 {
1019 	struct si5351_hw_data *hwdata =
1020 		container_of(hw, struct si5351_hw_data, hw);
1021 	unsigned char reg;
1022 	unsigned char rdiv;
1023 
1024 	if (hwdata->num <= 5)
1025 		reg = si5351_msynth_params_address(hwdata->num) + 2;
1026 	else
1027 		reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
1028 
1029 	rdiv = si5351_reg_read(hwdata->drvdata, reg);
1030 	if (hwdata->num == 6) {
1031 		rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK;
1032 	} else {
1033 		rdiv &= SI5351_OUTPUT_CLK_DIV_MASK;
1034 		rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT;
1035 	}
1036 
1037 	return parent_rate >> rdiv;
1038 }
1039 
si5351_clkout_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)1040 static int si5351_clkout_determine_rate(struct clk_hw *hw,
1041 					struct clk_rate_request *req)
1042 {
1043 	struct si5351_hw_data *hwdata =
1044 		container_of(hw, struct si5351_hw_data, hw);
1045 	unsigned long rate = req->rate;
1046 	unsigned char rdiv;
1047 
1048 	/* clkout6/7 can only handle output freqencies < 150MHz */
1049 	if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ)
1050 		rate = SI5351_CLKOUT67_MAX_FREQ;
1051 
1052 	/* clkout freqency is 8kHz - 160MHz */
1053 	if (rate > SI5351_CLKOUT_MAX_FREQ)
1054 		rate = SI5351_CLKOUT_MAX_FREQ;
1055 	if (rate < SI5351_CLKOUT_MIN_FREQ)
1056 		rate = SI5351_CLKOUT_MIN_FREQ;
1057 
1058 	/* request frequency if multisync master */
1059 	if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
1060 		/* use r divider for frequencies below 1MHz */
1061 		rdiv = SI5351_OUTPUT_CLK_DIV_1;
1062 		while (rate < SI5351_MULTISYNTH_MIN_FREQ &&
1063 		       rdiv < SI5351_OUTPUT_CLK_DIV_128) {
1064 			rdiv += 1;
1065 			rate *= 2;
1066 		}
1067 		req->best_parent_rate = rate;
1068 	} else {
1069 		unsigned long new_rate, new_err, err;
1070 
1071 		/* round to closed rdiv */
1072 		rdiv = SI5351_OUTPUT_CLK_DIV_1;
1073 		new_rate = req->best_parent_rate;
1074 		err = abs(new_rate - rate);
1075 		do {
1076 			new_rate >>= 1;
1077 			new_err = abs(new_rate - rate);
1078 			if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
1079 				break;
1080 			rdiv++;
1081 			err = new_err;
1082 		} while (1);
1083 	}
1084 	rate = req->best_parent_rate >> rdiv;
1085 
1086 	dev_dbg(&hwdata->drvdata->client->dev,
1087 		"%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1088 		__func__, clk_hw_get_name(hw), (1 << rdiv),
1089 		req->best_parent_rate, rate);
1090 
1091 	req->rate = rate;
1092 	return 0;
1093 }
1094 
si5351_clkout_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1095 static int si5351_clkout_set_rate(struct clk_hw *hw, unsigned long rate,
1096 				  unsigned long parent_rate)
1097 {
1098 	struct si5351_hw_data *hwdata =
1099 		container_of(hw, struct si5351_hw_data, hw);
1100 	unsigned long new_rate, new_err, err;
1101 	unsigned char rdiv;
1102 
1103 	/* round to closed rdiv */
1104 	rdiv = SI5351_OUTPUT_CLK_DIV_1;
1105 	new_rate = parent_rate;
1106 	err = abs(new_rate - rate);
1107 	do {
1108 		new_rate >>= 1;
1109 		new_err = abs(new_rate - rate);
1110 		if (new_err > err || rdiv == SI5351_OUTPUT_CLK_DIV_128)
1111 			break;
1112 		rdiv++;
1113 		err = new_err;
1114 	} while (1);
1115 
1116 	/* write output divider */
1117 	switch (hwdata->num) {
1118 	case 6:
1119 		si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
1120 				SI5351_OUTPUT_CLK6_DIV_MASK, rdiv);
1121 		break;
1122 	case 7:
1123 		si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER,
1124 				SI5351_OUTPUT_CLK_DIV_MASK,
1125 				rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
1126 		break;
1127 	default:
1128 		si5351_set_bits(hwdata->drvdata,
1129 				si5351_msynth_params_address(hwdata->num) + 2,
1130 				SI5351_OUTPUT_CLK_DIV_MASK,
1131 				rdiv << SI5351_OUTPUT_CLK_DIV_SHIFT);
1132 	}
1133 
1134 	/* powerup clkout */
1135 	si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num,
1136 			SI5351_CLK_POWERDOWN, 0);
1137 
1138 	dev_dbg(&hwdata->drvdata->client->dev,
1139 		"%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n",
1140 		__func__, clk_hw_get_name(hw), (1 << rdiv),
1141 		parent_rate, rate);
1142 
1143 	return 0;
1144 }
1145 
1146 static const struct clk_ops si5351_clkout_ops = {
1147 	.prepare = si5351_clkout_prepare,
1148 	.unprepare = si5351_clkout_unprepare,
1149 	.set_parent = si5351_clkout_set_parent,
1150 	.get_parent = si5351_clkout_get_parent,
1151 	.recalc_rate = si5351_clkout_recalc_rate,
1152 	.determine_rate = si5351_clkout_determine_rate,
1153 	.set_rate = si5351_clkout_set_rate,
1154 };
1155 
1156 /*
1157  * Si5351 i2c probe and DT
1158  */
1159 #ifdef CONFIG_OF
1160 static const struct of_device_id si5351_dt_ids[] = {
1161 	{ .compatible = "silabs,si5351a", .data = (void *)SI5351_VARIANT_A, },
1162 	{ .compatible = "silabs,si5351a-msop",
1163 					 .data = (void *)SI5351_VARIANT_A3, },
1164 	{ .compatible = "silabs,si5351b", .data = (void *)SI5351_VARIANT_B, },
1165 	{ .compatible = "silabs,si5351c", .data = (void *)SI5351_VARIANT_C, },
1166 	{ }
1167 };
1168 MODULE_DEVICE_TABLE(of, si5351_dt_ids);
1169 
si5351_dt_parse(struct i2c_client * client,enum si5351_variant variant)1170 static int si5351_dt_parse(struct i2c_client *client,
1171 			   enum si5351_variant variant)
1172 {
1173 	struct device_node *child, *np = client->dev.of_node;
1174 	struct si5351_platform_data *pdata;
1175 	struct property *prop;
1176 	const __be32 *p;
1177 	int num = 0;
1178 	u32 val;
1179 
1180 	if (np == NULL)
1181 		return 0;
1182 
1183 	pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
1184 	if (!pdata)
1185 		return -ENOMEM;
1186 
1187 	/*
1188 	 * property silabs,pll-source : <num src>, [<..>]
1189 	 * allow to selectively set pll source
1190 	 */
1191 	of_property_for_each_u32(np, "silabs,pll-source", prop, p, num) {
1192 		if (num >= 2) {
1193 			dev_err(&client->dev,
1194 				"invalid pll %d on pll-source prop\n", num);
1195 			return -EINVAL;
1196 		}
1197 
1198 		p = of_prop_next_u32(prop, p, &val);
1199 		if (!p) {
1200 			dev_err(&client->dev,
1201 				"missing pll-source for pll %d\n", num);
1202 			return -EINVAL;
1203 		}
1204 
1205 		switch (val) {
1206 		case 0:
1207 			pdata->pll_src[num] = SI5351_PLL_SRC_XTAL;
1208 			break;
1209 		case 1:
1210 			if (variant != SI5351_VARIANT_C) {
1211 				dev_err(&client->dev,
1212 					"invalid parent %d for pll %d\n",
1213 					val, num);
1214 				return -EINVAL;
1215 			}
1216 			pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN;
1217 			break;
1218 		default:
1219 			dev_err(&client->dev,
1220 				 "invalid parent %d for pll %d\n", val, num);
1221 			return -EINVAL;
1222 		}
1223 	}
1224 
1225 	/* per clkout properties */
1226 	for_each_child_of_node(np, child) {
1227 		if (of_property_read_u32(child, "reg", &num)) {
1228 			dev_err(&client->dev, "missing reg property of %pOFn\n",
1229 				child);
1230 			goto put_child;
1231 		}
1232 
1233 		if (num >= 8 ||
1234 		    (variant == SI5351_VARIANT_A3 && num >= 3)) {
1235 			dev_err(&client->dev, "invalid clkout %d\n", num);
1236 			goto put_child;
1237 		}
1238 
1239 		if (!of_property_read_u32(child, "silabs,multisynth-source",
1240 					  &val)) {
1241 			switch (val) {
1242 			case 0:
1243 				pdata->clkout[num].multisynth_src =
1244 					SI5351_MULTISYNTH_SRC_VCO0;
1245 				break;
1246 			case 1:
1247 				pdata->clkout[num].multisynth_src =
1248 					SI5351_MULTISYNTH_SRC_VCO1;
1249 				break;
1250 			default:
1251 				dev_err(&client->dev,
1252 					"invalid parent %d for multisynth %d\n",
1253 					val, num);
1254 				goto put_child;
1255 			}
1256 		}
1257 
1258 		if (!of_property_read_u32(child, "silabs,clock-source", &val)) {
1259 			switch (val) {
1260 			case 0:
1261 				pdata->clkout[num].clkout_src =
1262 					SI5351_CLKOUT_SRC_MSYNTH_N;
1263 				break;
1264 			case 1:
1265 				pdata->clkout[num].clkout_src =
1266 					SI5351_CLKOUT_SRC_MSYNTH_0_4;
1267 				break;
1268 			case 2:
1269 				pdata->clkout[num].clkout_src =
1270 					SI5351_CLKOUT_SRC_XTAL;
1271 				break;
1272 			case 3:
1273 				if (variant != SI5351_VARIANT_C) {
1274 					dev_err(&client->dev,
1275 						"invalid parent %d for clkout %d\n",
1276 						val, num);
1277 					goto put_child;
1278 				}
1279 				pdata->clkout[num].clkout_src =
1280 					SI5351_CLKOUT_SRC_CLKIN;
1281 				break;
1282 			default:
1283 				dev_err(&client->dev,
1284 					"invalid parent %d for clkout %d\n",
1285 					val, num);
1286 				goto put_child;
1287 			}
1288 		}
1289 
1290 		if (!of_property_read_u32(child, "silabs,drive-strength",
1291 					  &val)) {
1292 			switch (val) {
1293 			case SI5351_DRIVE_2MA:
1294 			case SI5351_DRIVE_4MA:
1295 			case SI5351_DRIVE_6MA:
1296 			case SI5351_DRIVE_8MA:
1297 				pdata->clkout[num].drive = val;
1298 				break;
1299 			default:
1300 				dev_err(&client->dev,
1301 					"invalid drive strength %d for clkout %d\n",
1302 					val, num);
1303 				goto put_child;
1304 			}
1305 		}
1306 
1307 		if (!of_property_read_u32(child, "silabs,disable-state",
1308 					  &val)) {
1309 			switch (val) {
1310 			case 0:
1311 				pdata->clkout[num].disable_state =
1312 					SI5351_DISABLE_LOW;
1313 				break;
1314 			case 1:
1315 				pdata->clkout[num].disable_state =
1316 					SI5351_DISABLE_HIGH;
1317 				break;
1318 			case 2:
1319 				pdata->clkout[num].disable_state =
1320 					SI5351_DISABLE_FLOATING;
1321 				break;
1322 			case 3:
1323 				pdata->clkout[num].disable_state =
1324 					SI5351_DISABLE_NEVER;
1325 				break;
1326 			default:
1327 				dev_err(&client->dev,
1328 					"invalid disable state %d for clkout %d\n",
1329 					val, num);
1330 				goto put_child;
1331 			}
1332 		}
1333 
1334 		if (!of_property_read_u32(child, "clock-frequency", &val))
1335 			pdata->clkout[num].rate = val;
1336 
1337 		pdata->clkout[num].pll_master =
1338 			of_property_read_bool(child, "silabs,pll-master");
1339 
1340 		pdata->clkout[num].pll_reset =
1341 			of_property_read_bool(child, "silabs,pll-reset");
1342 	}
1343 	client->dev.platform_data = pdata;
1344 
1345 	return 0;
1346 put_child:
1347 	of_node_put(child);
1348 	return -EINVAL;
1349 }
1350 
1351 static struct clk_hw *
si53351_of_clk_get(struct of_phandle_args * clkspec,void * data)1352 si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
1353 {
1354 	struct si5351_driver_data *drvdata = data;
1355 	unsigned int idx = clkspec->args[0];
1356 
1357 	if (idx >= drvdata->num_clkout) {
1358 		pr_err("%s: invalid index %u\n", __func__, idx);
1359 		return ERR_PTR(-EINVAL);
1360 	}
1361 
1362 	return &drvdata->clkout[idx].hw;
1363 }
1364 #else
si5351_dt_parse(struct i2c_client * client,enum si5351_variant variant)1365 static int si5351_dt_parse(struct i2c_client *client, enum si5351_variant variant)
1366 {
1367 	return 0;
1368 }
1369 
1370 static struct clk_hw *
si53351_of_clk_get(struct of_phandle_args * clkspec,void * data)1371 si53351_of_clk_get(struct of_phandle_args *clkspec, void *data)
1372 {
1373 	return NULL;
1374 }
1375 #endif /* CONFIG_OF */
1376 
1377 static const struct i2c_device_id si5351_i2c_ids[] = {
1378 	{ "si5351a", SI5351_VARIANT_A },
1379 	{ "si5351a-msop", SI5351_VARIANT_A3 },
1380 	{ "si5351b", SI5351_VARIANT_B },
1381 	{ "si5351c", SI5351_VARIANT_C },
1382 	{ }
1383 };
1384 MODULE_DEVICE_TABLE(i2c, si5351_i2c_ids);
1385 
si5351_i2c_probe(struct i2c_client * client)1386 static int si5351_i2c_probe(struct i2c_client *client)
1387 {
1388 	const struct i2c_device_id *id = i2c_match_id(si5351_i2c_ids, client);
1389 	enum si5351_variant variant = (enum si5351_variant)id->driver_data;
1390 	struct si5351_platform_data *pdata;
1391 	struct si5351_driver_data *drvdata;
1392 	struct clk_init_data init;
1393 	const char *parent_names[4];
1394 	u8 num_parents, num_clocks;
1395 	int ret, n;
1396 
1397 	ret = si5351_dt_parse(client, variant);
1398 	if (ret)
1399 		return ret;
1400 
1401 	pdata = client->dev.platform_data;
1402 	if (!pdata)
1403 		return -EINVAL;
1404 
1405 	drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL);
1406 	if (!drvdata)
1407 		return -ENOMEM;
1408 
1409 	i2c_set_clientdata(client, drvdata);
1410 	drvdata->client = client;
1411 	drvdata->variant = variant;
1412 	drvdata->pxtal = devm_clk_get(&client->dev, "xtal");
1413 	drvdata->pclkin = devm_clk_get(&client->dev, "clkin");
1414 
1415 	if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER ||
1416 	    PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER)
1417 		return -EPROBE_DEFER;
1418 
1419 	/*
1420 	 * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL,
1421 	 *   VARIANT_C can have CLKIN instead.
1422 	 */
1423 	if (IS_ERR(drvdata->pxtal) &&
1424 	    (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) {
1425 		dev_err(&client->dev, "missing parent clock\n");
1426 		return -EINVAL;
1427 	}
1428 
1429 	drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config);
1430 	if (IS_ERR(drvdata->regmap)) {
1431 		dev_err(&client->dev, "failed to allocate register map\n");
1432 		return PTR_ERR(drvdata->regmap);
1433 	}
1434 
1435 	/* Disable interrupts */
1436 	si5351_reg_write(drvdata, SI5351_INTERRUPT_MASK, 0xf0);
1437 	/* Ensure pll select is on XTAL for Si5351A/B */
1438 	if (drvdata->variant != SI5351_VARIANT_C)
1439 		si5351_set_bits(drvdata, SI5351_PLL_INPUT_SOURCE,
1440 				SI5351_PLLA_SOURCE | SI5351_PLLB_SOURCE, 0);
1441 
1442 	/* setup clock configuration */
1443 	for (n = 0; n < 2; n++) {
1444 		ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]);
1445 		if (ret) {
1446 			dev_err(&client->dev,
1447 				"failed to reparent pll %d to %d\n",
1448 				n, pdata->pll_src[n]);
1449 			return ret;
1450 		}
1451 	}
1452 
1453 	for (n = 0; n < 8; n++) {
1454 		ret = _si5351_msynth_reparent(drvdata, n,
1455 					      pdata->clkout[n].multisynth_src);
1456 		if (ret) {
1457 			dev_err(&client->dev,
1458 				"failed to reparent multisynth %d to %d\n",
1459 				n, pdata->clkout[n].multisynth_src);
1460 			return ret;
1461 		}
1462 
1463 		ret = _si5351_clkout_reparent(drvdata, n,
1464 					      pdata->clkout[n].clkout_src);
1465 		if (ret) {
1466 			dev_err(&client->dev,
1467 				"failed to reparent clkout %d to %d\n",
1468 				n, pdata->clkout[n].clkout_src);
1469 			return ret;
1470 		}
1471 
1472 		ret = _si5351_clkout_set_drive_strength(drvdata, n,
1473 							pdata->clkout[n].drive);
1474 		if (ret) {
1475 			dev_err(&client->dev,
1476 				"failed set drive strength of clkout%d to %d\n",
1477 				n, pdata->clkout[n].drive);
1478 			return ret;
1479 		}
1480 
1481 		ret = _si5351_clkout_set_disable_state(drvdata, n,
1482 						pdata->clkout[n].disable_state);
1483 		if (ret) {
1484 			dev_err(&client->dev,
1485 				"failed set disable state of clkout%d to %d\n",
1486 				n, pdata->clkout[n].disable_state);
1487 			return ret;
1488 		}
1489 	}
1490 
1491 	/* register xtal input clock gate */
1492 	memset(&init, 0, sizeof(init));
1493 	init.name = si5351_input_names[0];
1494 	init.ops = &si5351_xtal_ops;
1495 	init.flags = 0;
1496 	if (!IS_ERR(drvdata->pxtal)) {
1497 		drvdata->pxtal_name = __clk_get_name(drvdata->pxtal);
1498 		init.parent_names = &drvdata->pxtal_name;
1499 		init.num_parents = 1;
1500 	}
1501 	drvdata->xtal.init = &init;
1502 	ret = devm_clk_hw_register(&client->dev, &drvdata->xtal);
1503 	if (ret) {
1504 		dev_err(&client->dev, "unable to register %s\n", init.name);
1505 		return ret;
1506 	}
1507 
1508 	/* register clkin input clock gate */
1509 	if (drvdata->variant == SI5351_VARIANT_C) {
1510 		memset(&init, 0, sizeof(init));
1511 		init.name = si5351_input_names[1];
1512 		init.ops = &si5351_clkin_ops;
1513 		if (!IS_ERR(drvdata->pclkin)) {
1514 			drvdata->pclkin_name = __clk_get_name(drvdata->pclkin);
1515 			init.parent_names = &drvdata->pclkin_name;
1516 			init.num_parents = 1;
1517 		}
1518 		drvdata->clkin.init = &init;
1519 		ret = devm_clk_hw_register(&client->dev, &drvdata->clkin);
1520 		if (ret) {
1521 			dev_err(&client->dev, "unable to register %s\n",
1522 				init.name);
1523 			return ret;
1524 		}
1525 	}
1526 
1527 	/* Si5351C allows to mux either xtal or clkin to PLL input */
1528 	num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1;
1529 	parent_names[0] = si5351_input_names[0];
1530 	parent_names[1] = si5351_input_names[1];
1531 
1532 	/* register PLLA */
1533 	drvdata->pll[0].num = 0;
1534 	drvdata->pll[0].drvdata = drvdata;
1535 	drvdata->pll[0].hw.init = &init;
1536 	memset(&init, 0, sizeof(init));
1537 	init.name = si5351_pll_names[0];
1538 	init.ops = &si5351_pll_ops;
1539 	init.flags = 0;
1540 	init.parent_names = parent_names;
1541 	init.num_parents = num_parents;
1542 	ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw);
1543 	if (ret) {
1544 		dev_err(&client->dev, "unable to register %s\n", init.name);
1545 		return ret;
1546 	}
1547 
1548 	/* register PLLB or VXCO (Si5351B) */
1549 	drvdata->pll[1].num = 1;
1550 	drvdata->pll[1].drvdata = drvdata;
1551 	drvdata->pll[1].hw.init = &init;
1552 	memset(&init, 0, sizeof(init));
1553 	if (drvdata->variant == SI5351_VARIANT_B) {
1554 		init.name = si5351_pll_names[2];
1555 		init.ops = &si5351_vxco_ops;
1556 		init.flags = 0;
1557 		init.parent_names = NULL;
1558 		init.num_parents = 0;
1559 	} else {
1560 		init.name = si5351_pll_names[1];
1561 		init.ops = &si5351_pll_ops;
1562 		init.flags = 0;
1563 		init.parent_names = parent_names;
1564 		init.num_parents = num_parents;
1565 	}
1566 	ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw);
1567 	if (ret) {
1568 		dev_err(&client->dev, "unable to register %s\n", init.name);
1569 		return ret;
1570 	}
1571 
1572 	/* register clk multisync and clk out divider */
1573 	num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8;
1574 	parent_names[0] = si5351_pll_names[0];
1575 	if (drvdata->variant == SI5351_VARIANT_B)
1576 		parent_names[1] = si5351_pll_names[2];
1577 	else
1578 		parent_names[1] = si5351_pll_names[1];
1579 
1580 	drvdata->msynth = devm_kcalloc(&client->dev, num_clocks,
1581 				       sizeof(*drvdata->msynth), GFP_KERNEL);
1582 	drvdata->clkout = devm_kcalloc(&client->dev, num_clocks,
1583 				       sizeof(*drvdata->clkout), GFP_KERNEL);
1584 	drvdata->num_clkout = num_clocks;
1585 
1586 	if (WARN_ON(!drvdata->msynth || !drvdata->clkout)) {
1587 		ret = -ENOMEM;
1588 		return ret;
1589 	}
1590 
1591 	for (n = 0; n < num_clocks; n++) {
1592 		drvdata->msynth[n].num = n;
1593 		drvdata->msynth[n].drvdata = drvdata;
1594 		drvdata->msynth[n].hw.init = &init;
1595 		memset(&init, 0, sizeof(init));
1596 		init.name = si5351_msynth_names[n];
1597 		init.ops = &si5351_msynth_ops;
1598 		init.flags = 0;
1599 		if (pdata->clkout[n].pll_master)
1600 			init.flags |= CLK_SET_RATE_PARENT;
1601 		init.parent_names = parent_names;
1602 		init.num_parents = 2;
1603 		ret = devm_clk_hw_register(&client->dev,
1604 					   &drvdata->msynth[n].hw);
1605 		if (ret) {
1606 			dev_err(&client->dev, "unable to register %s\n",
1607 				init.name);
1608 			return ret;
1609 		}
1610 	}
1611 
1612 	num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3;
1613 	parent_names[2] = si5351_input_names[0];
1614 	parent_names[3] = si5351_input_names[1];
1615 	for (n = 0; n < num_clocks; n++) {
1616 		parent_names[0] = si5351_msynth_names[n];
1617 		parent_names[1] = (n < 4) ? si5351_msynth_names[0] :
1618 			si5351_msynth_names[4];
1619 
1620 		drvdata->clkout[n].num = n;
1621 		drvdata->clkout[n].drvdata = drvdata;
1622 		drvdata->clkout[n].hw.init = &init;
1623 		memset(&init, 0, sizeof(init));
1624 		init.name = si5351_clkout_names[n];
1625 		init.ops = &si5351_clkout_ops;
1626 		init.flags = 0;
1627 		if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N)
1628 			init.flags |= CLK_SET_RATE_PARENT;
1629 		init.parent_names = parent_names;
1630 		init.num_parents = num_parents;
1631 		ret = devm_clk_hw_register(&client->dev,
1632 					   &drvdata->clkout[n].hw);
1633 		if (ret) {
1634 			dev_err(&client->dev, "unable to register %s\n",
1635 				init.name);
1636 			return ret;
1637 		}
1638 
1639 		/* set initial clkout rate */
1640 		if (pdata->clkout[n].rate != 0) {
1641 			int ret;
1642 			ret = clk_set_rate(drvdata->clkout[n].hw.clk,
1643 					   pdata->clkout[n].rate);
1644 			if (ret != 0) {
1645 				dev_err(&client->dev, "Cannot set rate : %d\n",
1646 					ret);
1647 			}
1648 		}
1649 	}
1650 
1651 	ret = devm_of_clk_add_hw_provider(&client->dev, si53351_of_clk_get,
1652 					  drvdata);
1653 	if (ret) {
1654 		dev_err(&client->dev, "unable to add clk provider\n");
1655 		return ret;
1656 	}
1657 
1658 	return 0;
1659 }
1660 
1661 static struct i2c_driver si5351_driver = {
1662 	.driver = {
1663 		.name = "si5351",
1664 		.of_match_table = of_match_ptr(si5351_dt_ids),
1665 	},
1666 	.probe = si5351_i2c_probe,
1667 	.id_table = si5351_i2c_ids,
1668 };
1669 module_i2c_driver(si5351_driver);
1670 
1671 MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com");
1672 MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver");
1673 MODULE_LICENSE("GPL");
1674