xref: /openbmc/u-boot/include/linux/immap_qe.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * QUICC Engine (QE) Internal Memory Map.
4  * The Internal Memory Map for devices with QE on them. This
5  * is the superset of all QE devices (8360, etc.).
6  *
7  * Copyright (c) 2006-2009, 2011 Freescale Semiconductor, Inc.
8  * Author: Shlomi Gridih <gridish@freescale.com>
9  */
10 
11 #ifndef __IMMAP_QE_H__
12 #define __IMMAP_QE_H__
13 
14 #ifdef CONFIG_MPC83xx
15 #if defined(CONFIG_MPC8360)
16 #define QE_MURAM_SIZE		0xc000UL
17 #define MAX_QE_RISC		2
18 #define QE_NUM_OF_SNUM		28
19 #elif defined(CONFIG_MPC832x) || defined(CONFIG_MPC8309)
20 #define QE_MURAM_SIZE		0x4000UL
21 #define MAX_QE_RISC		1
22 #define QE_NUM_OF_SNUM		28
23 #endif
24 #endif
25 
26 #ifdef CONFIG_ARCH_LS1021A
27 #define QE_MURAM_SIZE          0x6000UL
28 #define MAX_QE_RISC            1
29 #define QE_NUM_OF_SNUM         28
30 #endif
31 
32 #ifdef CONFIG_PPC
33 #define QE_IMMR_OFFSET		0x00140000
34 #else
35 #define QE_IMMR_OFFSET		0x01400000
36 #endif
37 
38 /* QE I-RAM */
39 typedef struct qe_iram {
40 	u32 iadd;		/* I-RAM Address Register */
41 	u32 idata;		/* I-RAM Data Register    */
42 	u8 res0[0x4];
43 	u32 iready;
44 	u8 res1[0x70];
45 } __attribute__ ((packed)) qe_iram_t;
46 
47 /* QE Interrupt Controller */
48 typedef struct qe_ic {
49 	u32 qicr;
50 	u32 qivec;
51 	u32 qripnr;
52 	u32 qipnr;
53 	u32 qipxcc;
54 	u32 qipycc;
55 	u32 qipwcc;
56 	u32 qipzcc;
57 	u32 qimr;
58 	u32 qrimr;
59 	u32 qicnr;
60 	u8 res0[0x4];
61 	u32 qiprta;
62 	u32 qiprtb;
63 	u8 res1[0x4];
64 	u32 qricr;
65 	u8 res2[0x20];
66 	u32 qhivec;
67 	u8 res3[0x1C];
68 } __attribute__ ((packed)) qe_ic_t;
69 
70 /* Communications Processor */
71 typedef struct cp_qe {
72 	u32 cecr;		/* QE command register */
73 	u32 ceccr;		/* QE controller configuration register */
74 	u32 cecdr;		/* QE command data register */
75 	u8 res0[0xA];
76 	u16 ceter;		/* QE timer event register */
77 	u8 res1[0x2];
78 	u16 cetmr;		/* QE timers mask register */
79 	u32 cetscr;		/* QE time-stamp timer control register */
80 	u32 cetsr1;		/* QE time-stamp register 1 */
81 	u32 cetsr2;		/* QE time-stamp register 2 */
82 	u8 res2[0x8];
83 	u32 cevter;		/* QE virtual tasks event register */
84 	u32 cevtmr;		/* QE virtual tasks mask register */
85 	u16 cercr;		/* QE RAM control register */
86 	u8 res3[0x2];
87 	u8 res4[0x24];
88 	u16 ceexe1;		/* QE external request 1 event register */
89 	u8 res5[0x2];
90 	u16 ceexm1;		/* QE external request 1 mask register */
91 	u8 res6[0x2];
92 	u16 ceexe2;		/* QE external request 2 event register */
93 	u8 res7[0x2];
94 	u16 ceexm2;		/* QE external request 2 mask register */
95 	u8 res8[0x2];
96 	u16 ceexe3;		/* QE external request 3 event register */
97 	u8 res9[0x2];
98 	u16 ceexm3;		/* QE external request 3 mask register */
99 	u8 res10[0x2];
100 	u16 ceexe4;		/* QE external request 4 event register */
101 	u8 res11[0x2];
102 	u16 ceexm4;		/* QE external request 4 mask register */
103 	u8 res12[0x2];
104 	u8 res13[0x280];
105 } __attribute__ ((packed)) cp_qe_t;
106 
107 /* QE Multiplexer */
108 typedef struct qe_mux {
109 	u32 cmxgcr;		/* CMX general clock route register    */
110 	u32 cmxsi1cr_l;		/* CMX SI1 clock route low register    */
111 	u32 cmxsi1cr_h;		/* CMX SI1 clock route high register   */
112 	u32 cmxsi1syr;		/* CMX SI1 SYNC route register         */
113 	u32 cmxucr1;		/* CMX UCC1, UCC3 clock route register */
114 	u32 cmxucr2;		/* CMX UCC5, UCC7 clock route register */
115 	u32 cmxucr3;		/* CMX UCC2, UCC4 clock route register */
116 	u32 cmxucr4;		/* CMX UCC6, UCC8 clock route register */
117 	u32 cmxupcr;		/* CMX UPC clock route register        */
118 	u8 res0[0x1C];
119 } __attribute__ ((packed)) qe_mux_t;
120 
121 /* QE Timers */
122 typedef struct qe_timers {
123 	u8 gtcfr1;		/* Timer 1 2 global configuration register */
124 	u8 res0[0x3];
125 	u8 gtcfr2;		/* Timer 3 4 global configuration register */
126 	u8 res1[0xB];
127 	u16 gtmdr1;		/* Timer 1 mode register */
128 	u16 gtmdr2;		/* Timer 2 mode register */
129 	u16 gtrfr1;		/* Timer 1 reference register */
130 	u16 gtrfr2;		/* Timer 2 reference register */
131 	u16 gtcpr1;		/* Timer 1 capture register */
132 	u16 gtcpr2;		/* Timer 2 capture register */
133 	u16 gtcnr1;		/* Timer 1 counter */
134 	u16 gtcnr2;		/* Timer 2 counter */
135 	u16 gtmdr3;		/* Timer 3 mode register */
136 	u16 gtmdr4;		/* Timer 4 mode register */
137 	u16 gtrfr3;		/* Timer 3 reference register */
138 	u16 gtrfr4;		/* Timer 4 reference register */
139 	u16 gtcpr3;		/* Timer 3 capture register */
140 	u16 gtcpr4;		/* Timer 4 capture register */
141 	u16 gtcnr3;		/* Timer 3 counter */
142 	u16 gtcnr4;		/* Timer 4 counter */
143 	u16 gtevr1;		/* Timer 1 event register */
144 	u16 gtevr2;		/* Timer 2 event register */
145 	u16 gtevr3;		/* Timer 3 event register */
146 	u16 gtevr4;		/* Timer 4 event register */
147 	u16 gtps;		/* Timer 1 prescale register */
148 	u8 res2[0x46];
149 } __attribute__ ((packed)) qe_timers_t;
150 
151 /* BRG */
152 typedef struct qe_brg {
153 	u32 brgc1;		/* BRG1 configuration register  */
154 	u32 brgc2;		/* BRG2 configuration register  */
155 	u32 brgc3;		/* BRG3 configuration register  */
156 	u32 brgc4;		/* BRG4 configuration register  */
157 	u32 brgc5;		/* BRG5 configuration register  */
158 	u32 brgc6;		/* BRG6 configuration register  */
159 	u32 brgc7;		/* BRG7 configuration register  */
160 	u32 brgc8;		/* BRG8 configuration register  */
161 	u32 brgc9;		/* BRG9 configuration register  */
162 	u32 brgc10;		/* BRG10 configuration register */
163 	u32 brgc11;		/* BRG11 configuration register */
164 	u32 brgc12;		/* BRG12 configuration register */
165 	u32 brgc13;		/* BRG13 configuration register */
166 	u32 brgc14;		/* BRG14 configuration register */
167 	u32 brgc15;		/* BRG15 configuration register */
168 	u32 brgc16;		/* BRG16 configuration register */
169 	u8 res0[0x40];
170 } __attribute__ ((packed)) qe_brg_t;
171 
172 /* SPI */
173 typedef struct spi {
174 	u8 res0[0x20];
175 	u32 spmode;		/* SPI mode register */
176 	u8 res1[0x2];
177 	u8 spie;		/* SPI event register */
178 	u8 res2[0x1];
179 	u8 res3[0x2];
180 	u8 spim;		/* SPI mask register */
181 	u8 res4[0x1];
182 	u8 res5[0x1];
183 	u8 spcom;		/* SPI command register  */
184 	u8 res6[0x2];
185 	u32 spitd;		/* SPI transmit data register (cpu mode) */
186 	u32 spird;		/* SPI receive data register (cpu mode) */
187 	u8 res7[0x8];
188 } __attribute__ ((packed)) spi_t;
189 
190 /* SI */
191 typedef struct si1 {
192 	u16 siamr1;		/* SI1 TDMA mode register */
193 	u16 sibmr1;		/* SI1 TDMB mode register */
194 	u16 sicmr1;		/* SI1 TDMC mode register */
195 	u16 sidmr1;		/* SI1 TDMD mode register */
196 	u8 siglmr1_h;		/* SI1 global mode register high */
197 	u8 res0[0x1];
198 	u8 sicmdr1_h;		/* SI1 command register high */
199 	u8 res2[0x1];
200 	u8 sistr1_h;		/* SI1 status register high */
201 	u8 res3[0x1];
202 	u16 sirsr1_h;		/* SI1 RAM shadow address register high */
203 	u8 sitarc1;		/* SI1 RAM counter Tx TDMA */
204 	u8 sitbrc1;		/* SI1 RAM counter Tx TDMB */
205 	u8 sitcrc1;		/* SI1 RAM counter Tx TDMC */
206 	u8 sitdrc1;		/* SI1 RAM counter Tx TDMD */
207 	u8 sirarc1;		/* SI1 RAM counter Rx TDMA */
208 	u8 sirbrc1;		/* SI1 RAM counter Rx TDMB */
209 	u8 sircrc1;		/* SI1 RAM counter Rx TDMC */
210 	u8 sirdrc1;		/* SI1 RAM counter Rx TDMD */
211 	u8 res4[0x8];
212 	u16 siemr1;		/* SI1 TDME mode register 16 bits */
213 	u16 sifmr1;		/* SI1 TDMF mode register 16 bits */
214 	u16 sigmr1;		/* SI1 TDMG mode register 16 bits */
215 	u16 sihmr1;		/* SI1 TDMH mode register 16 bits */
216 	u8 siglmg1_l;		/* SI1 global mode register low 8 bits */
217 	u8 res5[0x1];
218 	u8 sicmdr1_l;		/* SI1 command register low 8 bits */
219 	u8 res6[0x1];
220 	u8 sistr1_l;		/* SI1 status register low 8 bits */
221 	u8 res7[0x1];
222 	u16 sirsr1_l;		/* SI1 RAM shadow address register low 16 bits */
223 	u8 siterc1;		/* SI1 RAM counter Tx TDME 8 bits */
224 	u8 sitfrc1;		/* SI1 RAM counter Tx TDMF 8 bits */
225 	u8 sitgrc1;		/* SI1 RAM counter Tx TDMG 8 bits */
226 	u8 sithrc1;		/* SI1 RAM counter Tx TDMH 8 bits */
227 	u8 sirerc1;		/* SI1 RAM counter Rx TDME 8 bits */
228 	u8 sirfrc1;		/* SI1 RAM counter Rx TDMF 8 bits */
229 	u8 sirgrc1;		/* SI1 RAM counter Rx TDMG 8 bits */
230 	u8 sirhrc1;		/* SI1 RAM counter Rx TDMH 8 bits */
231 	u8 res8[0x8];
232 	u32 siml1;		/* SI1 multiframe limit register */
233 	u8 siedm1;		/* SI1 extended diagnostic mode register */
234 	u8 res9[0xBB];
235 } __attribute__ ((packed)) si1_t;
236 
237 /* SI Routing Tables */
238 typedef struct sir {
239 	u8 tx[0x400];
240 	u8 rx[0x400];
241 	u8 res0[0x800];
242 } __attribute__ ((packed)) sir_t;
243 
244 /* USB Controller.  */
245 typedef struct usb_ctlr {
246 	u8 usb_usmod;
247 	u8 usb_usadr;
248 	u8 usb_uscom;
249 	u8 res1[1];
250 	u16 usb_usep1;
251 	u16 usb_usep2;
252 	u16 usb_usep3;
253 	u16 usb_usep4;
254 	u8 res2[4];
255 	u16 usb_usber;
256 	u8 res3[2];
257 	u16 usb_usbmr;
258 	u8 res4[1];
259 	u8 usb_usbs;
260 	u16 usb_ussft;
261 	u8 res5[2];
262 	u16 usb_usfrn;
263 	u8 res6[0x22];
264 } __attribute__ ((packed)) usb_t;
265 
266 /* MCC */
267 typedef struct mcc {
268 	u32 mcce;		/* MCC event register */
269 	u32 mccm;		/* MCC mask register */
270 	u32 mccf;		/* MCC configuration register */
271 	u32 merl;		/* MCC emergency request level register */
272 	u8 res0[0xF0];
273 } __attribute__ ((packed)) mcc_t;
274 
275 /* QE UCC Slow */
276 typedef struct ucc_slow {
277 	u32 gumr_l;		/* UCCx general mode register (low) */
278 	u32 gumr_h;		/* UCCx general mode register (high) */
279 	u16 upsmr;		/* UCCx protocol-specific mode register */
280 	u8 res0[0x2];
281 	u16 utodr;		/* UCCx transmit on demand register */
282 	u16 udsr;		/* UCCx data synchronization register */
283 	u16 ucce;		/* UCCx event register */
284 	u8 res1[0x2];
285 	u16 uccm;		/* UCCx mask register */
286 	u8 res2[0x1];
287 	u8 uccs;		/* UCCx status register */
288 	u8 res3[0x24];
289 	u16 utpt;
290 	u8 guemr;		/* UCC general extended mode register */
291 	u8 res4[0x200 - 0x091];
292 } __attribute__ ((packed)) ucc_slow_t;
293 
294 typedef struct ucc_mii_mng {
295 	u32 miimcfg;		/* MII management configuration reg    */
296 	u32 miimcom;		/* MII management command reg          */
297 	u32 miimadd;		/* MII management address reg          */
298 	u32 miimcon;		/* MII management control reg          */
299 	u32 miimstat;		/* MII management status reg           */
300 	u32 miimind;		/* MII management indication reg       */
301 	u32 ifctl;		/* interface control reg               */
302 	u32 ifstat;		/* interface statux reg                */
303 } __attribute__ ((packed))uec_mii_t;
304 
305 typedef struct ucc_ethernet {
306 	u32 maccfg1;		/* mac configuration reg. 1            */
307 	u32 maccfg2;		/* mac configuration reg. 2            */
308 	u32 ipgifg;		/* interframe gap reg.                 */
309 	u32 hafdup;		/* half-duplex reg.                    */
310 	u8 res1[0x10];
311 	u32 miimcfg;		/* MII management configuration reg    */
312 	u32 miimcom;		/* MII management command reg          */
313 	u32 miimadd;		/* MII management address reg          */
314 	u32 miimcon;		/* MII management control reg          */
315 	u32 miimstat;		/* MII management status reg           */
316 	u32 miimind;		/* MII management indication reg       */
317 	u32 ifctl;		/* interface control reg               */
318 	u32 ifstat;		/* interface statux reg                */
319 	u32 macstnaddr1;	/* mac station address part 1 reg      */
320 	u32 macstnaddr2;	/* mac station address part 2 reg      */
321 	u8 res2[0x8];
322 	u32 uempr;		/* UCC Ethernet Mac parameter reg      */
323 	u32 utbipar;		/* UCC tbi address reg                 */
324 	u16 uescr;		/* UCC Ethernet statistics control reg */
325 	u8 res3[0x180 - 0x15A];
326 	u32 tx64;		/* Total number of frames (including bad
327 				 * frames) transmitted that were exactly
328 				 * of the minimal length (64 for un tagged,
329 				 * 68 for tagged, or with length exactly
330 				 * equal to the parameter MINLength */
331 	u32 tx127;		/* Total number of frames (including bad
332 				 * frames) transmitted that were between
333 				 * MINLength (Including FCS length==4)
334 				 * and 127 octets */
335 	u32 tx255;		/* Total number of frames (including bad
336 				 * frames) transmitted that were between
337 				 * 128 (Including FCS length==4) and 255
338 				 * octets */
339 	u32 rx64;		/* Total number of frames received including
340 				 * bad frames that were exactly of the
341 				 * mninimal length (64 bytes) */
342 	u32 rx127;		/* Total number of frames (including bad
343 				 * frames) received that were between
344 				 * MINLength (Including FCS length==4)
345 				 * and 127 octets */
346 	u32 rx255;		/* Total number of frames (including
347 				 * bad frames) received that were between
348 				 * 128 (Including FCS length==4) and 255
349 				 * octets */
350 	u32 txok;		/* Total number of octets residing in frames
351 				 * that where involved in succesfull
352 				 * transmission */
353 	u16 txcf;		/* Total number of PAUSE control frames
354 				 *  transmitted by this MAC */
355 	u8 res4[0x2];
356 	u32 tmca;		/* Total number of frames that were transmitted
357 				 * succesfully with the group address bit set
358 				 * that are not broadcast frames */
359 	u32 tbca;		/* Total number of frames transmitted
360 				 * succesfully that had destination address
361 				 * field equal to the broadcast address */
362 	u32 rxfok;		/* Total number of frames received OK */
363 	u32 rxbok;		/* Total number of octets received OK */
364 	u32 rbyt;		/* Total number of octets received including
365 				 * octets in bad frames. Must be implemented
366 				 * in HW because it includes octets in frames
367 				 * that never even reach the UCC */
368 	u32 rmca;		/* Total number of frames that were received
369 				 * succesfully with the group address bit set
370 				 * that are not broadcast frames */
371 	u32 rbca;		/* Total number of frames received succesfully
372 				 * that had destination address equal to the
373 				 * broadcast address */
374 	u32 scar;		/* Statistics carry register */
375 	u32 scam;		/* Statistics caryy mask register */
376 	u8 res5[0x200 - 0x1c4];
377 } __attribute__ ((packed)) uec_t;
378 
379 /* QE UCC Fast */
380 typedef struct ucc_fast {
381 	u32 gumr;		/* UCCx general mode register */
382 	u32 upsmr;		/* UCCx protocol-specific mode register  */
383 	u16 utodr;		/* UCCx transmit on demand register  */
384 	u8 res0[0x2];
385 	u16 udsr;		/* UCCx data synchronization register  */
386 	u8 res1[0x2];
387 	u32 ucce;		/* UCCx event register */
388 	u32 uccm;		/* UCCx mask register.  */
389 	u8 uccs;		/* UCCx status register */
390 	u8 res2[0x7];
391 	u32 urfb;		/* UCC receive FIFO base */
392 	u16 urfs;		/* UCC receive FIFO size */
393 	u8 res3[0x2];
394 	u16 urfet;		/* UCC receive FIFO emergency threshold */
395 	u16 urfset;		/* UCC receive FIFO special emergency
396 				 * threshold */
397 	u32 utfb;		/* UCC transmit FIFO base */
398 	u16 utfs;		/* UCC transmit FIFO size */
399 	u8 res4[0x2];
400 	u16 utfet;		/* UCC transmit FIFO emergency threshold */
401 	u8 res5[0x2];
402 	u16 utftt;		/* UCC transmit FIFO transmit threshold */
403 	u8 res6[0x2];
404 	u16 utpt;		/* UCC transmit polling timer */
405 	u8 res7[0x2];
406 	u32 urtry;		/* UCC retry counter register */
407 	u8 res8[0x4C];
408 	u8 guemr;		/* UCC general extended mode register */
409 	u8 res9[0x100 - 0x091];
410 	uec_t ucc_eth;
411 } __attribute__ ((packed)) ucc_fast_t;
412 
413 /* QE UCC */
414 typedef struct ucc_common {
415 	u8 res1[0x90];
416 	u8 guemr;
417 	u8 res2[0x200 - 0x091];
418 } __attribute__ ((packed)) ucc_common_t;
419 
420 typedef struct ucc {
421 	union {
422 		ucc_slow_t slow;
423 		ucc_fast_t fast;
424 		ucc_common_t common;
425 	};
426 } __attribute__ ((packed)) ucc_t;
427 
428 /* MultiPHY UTOPIA POS Controllers (UPC) */
429 typedef struct upc {
430 	u32 upgcr;		/* UTOPIA/POS general configuration register */
431 	u32 uplpa;		/* UTOPIA/POS last PHY address */
432 	u32 uphec;		/* ATM HEC register */
433 	u32 upuc;		/* UTOPIA/POS UCC configuration */
434 	u32 updc1;		/* UTOPIA/POS device 1 configuration */
435 	u32 updc2;		/* UTOPIA/POS device 2 configuration  */
436 	u32 updc3;		/* UTOPIA/POS device 3 configuration */
437 	u32 updc4;		/* UTOPIA/POS device 4 configuration  */
438 	u32 upstpa;		/* UTOPIA/POS STPA threshold  */
439 	u8 res0[0xC];
440 	u32 updrs1_h;		/* UTOPIA/POS device 1 rate select  */
441 	u32 updrs1_l;		/* UTOPIA/POS device 1 rate select  */
442 	u32 updrs2_h;		/* UTOPIA/POS device 2 rate select  */
443 	u32 updrs2_l;		/* UTOPIA/POS device 2 rate select */
444 	u32 updrs3_h;		/* UTOPIA/POS device 3 rate select */
445 	u32 updrs3_l;		/* UTOPIA/POS device 3 rate select */
446 	u32 updrs4_h;		/* UTOPIA/POS device 4 rate select */
447 	u32 updrs4_l;		/* UTOPIA/POS device 4 rate select */
448 	u32 updrp1;		/* UTOPIA/POS device 1 receive priority low  */
449 	u32 updrp2;		/* UTOPIA/POS device 2 receive priority low  */
450 	u32 updrp3;		/* UTOPIA/POS device 3 receive priority low  */
451 	u32 updrp4;		/* UTOPIA/POS device 4 receive priority low  */
452 	u32 upde1;		/* UTOPIA/POS device 1 event */
453 	u32 upde2;		/* UTOPIA/POS device 2 event */
454 	u32 upde3;		/* UTOPIA/POS device 3 event */
455 	u32 upde4;		/* UTOPIA/POS device 4 event */
456 	u16 uprp1;
457 	u16 uprp2;
458 	u16 uprp3;
459 	u16 uprp4;
460 	u8 res1[0x8];
461 	u16 uptirr1_0;		/* Device 1 transmit internal rate 0 */
462 	u16 uptirr1_1;		/* Device 1 transmit internal rate 1 */
463 	u16 uptirr1_2;		/* Device 1 transmit internal rate 2 */
464 	u16 uptirr1_3;		/* Device 1 transmit internal rate 3 */
465 	u16 uptirr2_0;		/* Device 2 transmit internal rate 0 */
466 	u16 uptirr2_1;		/* Device 2 transmit internal rate 1 */
467 	u16 uptirr2_2;		/* Device 2 transmit internal rate 2 */
468 	u16 uptirr2_3;		/* Device 2 transmit internal rate 3 */
469 	u16 uptirr3_0;		/* Device 3 transmit internal rate 0 */
470 	u16 uptirr3_1;		/* Device 3 transmit internal rate 1 */
471 	u16 uptirr3_2;		/* Device 3 transmit internal rate 2 */
472 	u16 uptirr3_3;		/* Device 3 transmit internal rate 3 */
473 	u16 uptirr4_0;		/* Device 4 transmit internal rate 0 */
474 	u16 uptirr4_1;		/* Device 4 transmit internal rate 1 */
475 	u16 uptirr4_2;		/* Device 4 transmit internal rate 2 */
476 	u16 uptirr4_3;		/* Device 4 transmit internal rate 3 */
477 	u32 uper1;		/* Device 1 port enable register */
478 	u32 uper2;		/* Device 2 port enable register */
479 	u32 uper3;		/* Device 3 port enable register */
480 	u32 uper4;		/* Device 4 port enable register */
481 	u8 res2[0x150];
482 } __attribute__ ((packed)) upc_t;
483 
484 /* SDMA */
485 typedef struct sdma {
486 	u32 sdsr;		/* Serial DMA status register */
487 	u32 sdmr;		/* Serial DMA mode register */
488 	u32 sdtr1;		/* SDMA system bus threshold register */
489 	u32 sdtr2;		/* SDMA secondary bus threshold register */
490 	u32 sdhy1;		/* SDMA system bus hysteresis register */
491 	u32 sdhy2;		/* SDMA secondary bus hysteresis register */
492 	u32 sdta1;		/* SDMA system bus address register */
493 	u32 sdta2;		/* SDMA secondary bus address register */
494 	u32 sdtm1;		/* SDMA system bus MSNUM register */
495 	u32 sdtm2;		/* SDMA secondary bus MSNUM register */
496 	u8 res0[0x10];
497 	u32 sdaqr;		/* SDMA address bus qualify register */
498 	u32 sdaqmr;		/* SDMA address bus qualify mask register */
499 	u8 res1[0x4];
500 	u32 sdwbcr;		/* SDMA CAM entries base register */
501 	u8 res2[0x38];
502 } __attribute__ ((packed)) sdma_t;
503 
504 /* Debug Space */
505 typedef struct dbg {
506 	u32 bpdcr;		/* Breakpoint debug command register */
507 	u32 bpdsr;		/* Breakpoint debug status register */
508 	u32 bpdmr;		/* Breakpoint debug mask register */
509 	u32 bprmrr0;		/* Breakpoint request mode risc register 0 */
510 	u32 bprmrr1;		/* Breakpoint request mode risc register 1 */
511 	u8 res0[0x8];
512 	u32 bprmtr0;		/* Breakpoint request mode trb register 0 */
513 	u32 bprmtr1;		/* Breakpoint request mode trb register 1 */
514 	u8 res1[0x8];
515 	u32 bprmir;		/* Breakpoint request mode immediate register */
516 	u32 bprmsr;		/* Breakpoint request mode serial register */
517 	u32 bpemr;		/* Breakpoint exit mode register */
518 	u8 res2[0x48];
519 } __attribute__ ((packed)) dbg_t;
520 
521 /*
522  * RISC Special Registers (Trap and Breakpoint).  These are described in
523  * the QE Developer's Handbook.
524 */
525 typedef struct rsp {
526 	u32 tibcr[16];	/* Trap/instruction breakpoint control regs */
527 	u8 res0[64];
528 	u32 ibcr0;
529 	u32 ibs0;
530 	u32 ibcnr0;
531 	u8 res1[4];
532 	u32 ibcr1;
533 	u32 ibs1;
534 	u32 ibcnr1;
535 	u32 npcr;
536 	u32 dbcr;
537 	u32 dbar;
538 	u32 dbamr;
539 	u32 dbsr;
540 	u32 dbcnr;
541 	u8 res2[12];
542 	u32 dbdr_h;
543 	u32 dbdr_l;
544 	u32 dbdmr_h;
545 	u32 dbdmr_l;
546 	u32 bsr;
547 	u32 bor;
548 	u32 bior;
549 	u8 res3[4];
550 	u32 iatr[4];
551 	u32 eccr;		/* Exception control configuration register */
552 	u32 eicr;
553 	u8 res4[0x100-0xf8];
554 } __attribute__ ((packed)) rsp_t;
555 
556 typedef struct qe_immap {
557 	qe_iram_t iram;		/* I-RAM */
558 	qe_ic_t ic;		/* Interrupt Controller */
559 	cp_qe_t cp;		/* Communications Processor */
560 	qe_mux_t qmx;		/* QE Multiplexer */
561 	qe_timers_t qet;	/* QE Timers */
562 	spi_t spi[0x2];		/* spi  */
563 	mcc_t mcc;		/* mcc */
564 	qe_brg_t brg;		/* brg */
565 	usb_t usb;		/* USB */
566 	si1_t si1;		/* SI */
567 	u8 res11[0x800];
568 	sir_t sir;		/* SI Routing Tables  */
569 	ucc_t ucc1;		/* ucc1 */
570 	ucc_t ucc3;		/* ucc3 */
571 	ucc_t ucc5;		/* ucc5 */
572 	ucc_t ucc7;		/* ucc7 */
573 	u8 res12[0x600];
574 	upc_t upc1;		/* MultiPHY UTOPIA POS Controller 1 */
575 	ucc_t ucc2;		/* ucc2 */
576 	ucc_t ucc4;		/* ucc4 */
577 	ucc_t ucc6;		/* ucc6 */
578 	ucc_t ucc8;		/* ucc8 */
579 	u8 res13[0x600];
580 	upc_t upc2;		/* MultiPHY UTOPIA POS Controller 2 */
581 	sdma_t sdma;		/* SDMA */
582 	dbg_t dbg;		/* Debug Space */
583 	rsp_t rsp[0x2];		/* RISC Special Registers
584 				 * (Trap and Breakpoint) */
585 	u8 res14[0x300];
586 	u8 res15[0x3A00];
587 	u8 res16[0x8000];	/* 0x108000 -  0x110000 */
588 	u8 muram[QE_MURAM_SIZE];
589 } __attribute__ ((packed)) qe_map_t;
590 
591 extern qe_map_t *qe_immr;
592 
593 #endif				/* __IMMAP_QE_H__ */
594