1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * SuperH SCIF device driver. 4 * Copyright (C) 2013 Renesas Electronics Corporation 5 * Copyright (C) 2007,2008,2010, 2014 Nobuhiro Iwamatsu 6 * Copyright (C) 2002 - 2008 Paul Mundt 7 */ 8 9 #include <common.h> 10 #include <errno.h> 11 #include <clk.h> 12 #include <dm.h> 13 #include <asm/io.h> 14 #include <asm/processor.h> 15 #include <serial.h> 16 #include <linux/compiler.h> 17 #include <dm/platform_data/serial_sh.h> 18 #include "serial_sh.h" 19 20 DECLARE_GLOBAL_DATA_PTR; 21 22 #if defined(CONFIG_CPU_SH7760) || \ 23 defined(CONFIG_CPU_SH7780) || \ 24 defined(CONFIG_CPU_SH7785) || \ 25 defined(CONFIG_CPU_SH7786) scif_rxfill(struct uart_port * port)26 static int scif_rxfill(struct uart_port *port) 27 { 28 return sci_in(port, SCRFDR) & 0xff; 29 } 30 #elif defined(CONFIG_CPU_SH7763) scif_rxfill(struct uart_port * port)31 static int scif_rxfill(struct uart_port *port) 32 { 33 if ((port->mapbase == 0xffe00000) || 34 (port->mapbase == 0xffe08000)) { 35 /* SCIF0/1*/ 36 return sci_in(port, SCRFDR) & 0xff; 37 } else { 38 /* SCIF2 */ 39 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; 40 } 41 } 42 #elif defined(CONFIG_ARCH_SH7372) scif_rxfill(struct uart_port * port)43 static int scif_rxfill(struct uart_port *port) 44 { 45 if (port->type == PORT_SCIFA) 46 return sci_in(port, SCFDR) & SCIF_RFDC_MASK; 47 else 48 return sci_in(port, SCRFDR); 49 } 50 #else scif_rxfill(struct uart_port * port)51 static int scif_rxfill(struct uart_port *port) 52 { 53 return sci_in(port, SCFDR) & SCIF_RFDC_MASK; 54 } 55 #endif 56 sh_serial_init_generic(struct uart_port * port)57 static void sh_serial_init_generic(struct uart_port *port) 58 { 59 sci_out(port, SCSCR , SCSCR_INIT(port)); 60 sci_out(port, SCSCR , SCSCR_INIT(port)); 61 sci_out(port, SCSMR, 0); 62 sci_out(port, SCSMR, 0); 63 sci_out(port, SCFCR, SCFCR_RFRST|SCFCR_TFRST); 64 sci_in(port, SCFCR); 65 sci_out(port, SCFCR, 0); 66 } 67 68 static void sh_serial_setbrg_generic(struct uart_port * port,int clk,int baudrate)69 sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate) 70 { 71 if (port->clk_mode == EXT_CLK) { 72 unsigned short dl = DL_VALUE(baudrate, clk); 73 sci_out(port, DL, dl); 74 /* Need wait: Clock * 1/dl * 1/16 */ 75 udelay((1000000 * dl * 16 / clk) * 1000 + 1); 76 } else { 77 sci_out(port, SCBRR, SCBRR_VALUE(baudrate, clk)); 78 } 79 } 80 handle_error(struct uart_port * port)81 static void handle_error(struct uart_port *port) 82 { 83 sci_in(port, SCxSR); 84 sci_out(port, SCxSR, SCxSR_ERROR_CLEAR(port)); 85 sci_in(port, SCLSR); 86 sci_out(port, SCLSR, 0x00); 87 } 88 serial_raw_putc(struct uart_port * port,const char c)89 static int serial_raw_putc(struct uart_port *port, const char c) 90 { 91 /* Tx fifo is empty */ 92 if (!(sci_in(port, SCxSR) & SCxSR_TEND(port))) 93 return -EAGAIN; 94 95 sci_out(port, SCxTDR, c); 96 sci_out(port, SCxSR, sci_in(port, SCxSR) & ~SCxSR_TEND(port)); 97 98 return 0; 99 } 100 serial_rx_fifo_level(struct uart_port * port)101 static int serial_rx_fifo_level(struct uart_port *port) 102 { 103 return scif_rxfill(port); 104 } 105 sh_serial_tstc_generic(struct uart_port * port)106 static int sh_serial_tstc_generic(struct uart_port *port) 107 { 108 if (sci_in(port, SCxSR) & SCIF_ERRORS) { 109 handle_error(port); 110 return 0; 111 } 112 113 return serial_rx_fifo_level(port) ? 1 : 0; 114 } 115 serial_getc_check(struct uart_port * port)116 static int serial_getc_check(struct uart_port *port) 117 { 118 unsigned short status; 119 120 status = sci_in(port, SCxSR); 121 122 if (status & SCIF_ERRORS) 123 handle_error(port); 124 if (sci_in(port, SCLSR) & SCxSR_ORER(port)) 125 handle_error(port); 126 return status & (SCIF_DR | SCxSR_RDxF(port)); 127 } 128 sh_serial_getc_generic(struct uart_port * port)129 static int sh_serial_getc_generic(struct uart_port *port) 130 { 131 unsigned short status; 132 char ch; 133 134 if (!serial_getc_check(port)) 135 return -EAGAIN; 136 137 ch = sci_in(port, SCxRDR); 138 status = sci_in(port, SCxSR); 139 140 sci_out(port, SCxSR, SCxSR_RDxF_CLEAR(port)); 141 142 if (status & SCIF_ERRORS) 143 handle_error(port); 144 145 if (sci_in(port, SCLSR) & SCxSR_ORER(port)) 146 handle_error(port); 147 148 return ch; 149 } 150 151 #if CONFIG_IS_ENABLED(DM_SERIAL) 152 sh_serial_pending(struct udevice * dev,bool input)153 static int sh_serial_pending(struct udevice *dev, bool input) 154 { 155 struct uart_port *priv = dev_get_priv(dev); 156 157 return sh_serial_tstc_generic(priv); 158 } 159 sh_serial_putc(struct udevice * dev,const char ch)160 static int sh_serial_putc(struct udevice *dev, const char ch) 161 { 162 struct uart_port *priv = dev_get_priv(dev); 163 164 return serial_raw_putc(priv, ch); 165 } 166 sh_serial_getc(struct udevice * dev)167 static int sh_serial_getc(struct udevice *dev) 168 { 169 struct uart_port *priv = dev_get_priv(dev); 170 171 return sh_serial_getc_generic(priv); 172 } 173 sh_serial_setbrg(struct udevice * dev,int baudrate)174 static int sh_serial_setbrg(struct udevice *dev, int baudrate) 175 { 176 struct sh_serial_platdata *plat = dev_get_platdata(dev); 177 struct uart_port *priv = dev_get_priv(dev); 178 179 sh_serial_setbrg_generic(priv, plat->clk, baudrate); 180 181 return 0; 182 } 183 sh_serial_probe(struct udevice * dev)184 static int sh_serial_probe(struct udevice *dev) 185 { 186 struct sh_serial_platdata *plat = dev_get_platdata(dev); 187 struct uart_port *priv = dev_get_priv(dev); 188 189 priv->membase = (unsigned char *)plat->base; 190 priv->mapbase = plat->base; 191 priv->type = plat->type; 192 priv->clk_mode = plat->clk_mode; 193 194 sh_serial_init_generic(priv); 195 196 return 0; 197 } 198 199 static const struct dm_serial_ops sh_serial_ops = { 200 .putc = sh_serial_putc, 201 .pending = sh_serial_pending, 202 .getc = sh_serial_getc, 203 .setbrg = sh_serial_setbrg, 204 }; 205 206 #if CONFIG_IS_ENABLED(OF_CONTROL) 207 static const struct udevice_id sh_serial_id[] ={ 208 {.compatible = "renesas,sci", .data = PORT_SCI}, 209 {.compatible = "renesas,scif", .data = PORT_SCIF}, 210 {.compatible = "renesas,scifa", .data = PORT_SCIFA}, 211 {} 212 }; 213 sh_serial_ofdata_to_platdata(struct udevice * dev)214 static int sh_serial_ofdata_to_platdata(struct udevice *dev) 215 { 216 struct sh_serial_platdata *plat = dev_get_platdata(dev); 217 struct clk sh_serial_clk; 218 fdt_addr_t addr; 219 int ret; 220 221 addr = devfdt_get_addr(dev); 222 if (!addr) 223 return -EINVAL; 224 225 plat->base = addr; 226 227 ret = clk_get_by_name(dev, "fck", &sh_serial_clk); 228 if (!ret) { 229 ret = clk_enable(&sh_serial_clk); 230 if (!ret) 231 plat->clk = clk_get_rate(&sh_serial_clk); 232 } else { 233 plat->clk = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), 234 "clock", 1); 235 } 236 237 plat->type = dev_get_driver_data(dev); 238 return 0; 239 } 240 #endif 241 242 U_BOOT_DRIVER(serial_sh) = { 243 .name = "serial_sh", 244 .id = UCLASS_SERIAL, 245 .of_match = of_match_ptr(sh_serial_id), 246 .ofdata_to_platdata = of_match_ptr(sh_serial_ofdata_to_platdata), 247 .platdata_auto_alloc_size = sizeof(struct sh_serial_platdata), 248 .probe = sh_serial_probe, 249 .ops = &sh_serial_ops, 250 #if !CONFIG_IS_ENABLED(OF_CONTROL) 251 .flags = DM_FLAG_PRE_RELOC, 252 #endif 253 .priv_auto_alloc_size = sizeof(struct uart_port), 254 }; 255 256 #else /* CONFIG_DM_SERIAL */ 257 258 #if defined(CONFIG_CONS_SCIF0) 259 # define SCIF_BASE SCIF0_BASE 260 #elif defined(CONFIG_CONS_SCIF1) 261 # define SCIF_BASE SCIF1_BASE 262 #elif defined(CONFIG_CONS_SCIF2) 263 # define SCIF_BASE SCIF2_BASE 264 #elif defined(CONFIG_CONS_SCIF3) 265 # define SCIF_BASE SCIF3_BASE 266 #elif defined(CONFIG_CONS_SCIF4) 267 # define SCIF_BASE SCIF4_BASE 268 #elif defined(CONFIG_CONS_SCIF5) 269 # define SCIF_BASE SCIF5_BASE 270 #elif defined(CONFIG_CONS_SCIF6) 271 # define SCIF_BASE SCIF6_BASE 272 #elif defined(CONFIG_CONS_SCIF7) 273 # define SCIF_BASE SCIF7_BASE 274 #elif defined(CONFIG_CONS_SCIFA0) 275 # define SCIF_BASE SCIFA0_BASE 276 #else 277 # error "Default SCIF doesn't set....." 278 #endif 279 280 #if defined(CONFIG_SCIF_A) 281 #define SCIF_BASE_PORT PORT_SCIFA 282 #elif defined(CONFIG_SCI) 283 #define SCIF_BASE_PORT PORT_SCI 284 #else 285 #define SCIF_BASE_PORT PORT_SCIF 286 #endif 287 288 static struct uart_port sh_sci = { 289 .membase = (unsigned char *)SCIF_BASE, 290 .mapbase = SCIF_BASE, 291 .type = SCIF_BASE_PORT, 292 #ifdef CONFIG_SCIF_USE_EXT_CLK 293 .clk_mode = EXT_CLK, 294 #endif 295 }; 296 sh_serial_setbrg(void)297 static void sh_serial_setbrg(void) 298 { 299 DECLARE_GLOBAL_DATA_PTR; 300 struct uart_port *port = &sh_sci; 301 302 sh_serial_setbrg_generic(port, CONFIG_SH_SCIF_CLK_FREQ, gd->baudrate); 303 } 304 sh_serial_init(void)305 static int sh_serial_init(void) 306 { 307 struct uart_port *port = &sh_sci; 308 309 sh_serial_init_generic(port); 310 serial_setbrg(); 311 312 return 0; 313 } 314 sh_serial_putc(const char c)315 static void sh_serial_putc(const char c) 316 { 317 struct uart_port *port = &sh_sci; 318 319 if (c == '\n') { 320 while (1) { 321 if (serial_raw_putc(port, '\r') != -EAGAIN) 322 break; 323 } 324 } 325 while (1) { 326 if (serial_raw_putc(port, c) != -EAGAIN) 327 break; 328 } 329 } 330 sh_serial_tstc(void)331 static int sh_serial_tstc(void) 332 { 333 struct uart_port *port = &sh_sci; 334 335 return sh_serial_tstc_generic(port); 336 } 337 sh_serial_getc(void)338 static int sh_serial_getc(void) 339 { 340 struct uart_port *port = &sh_sci; 341 int ch; 342 343 while (1) { 344 ch = sh_serial_getc_generic(port); 345 if (ch != -EAGAIN) 346 break; 347 } 348 349 return ch; 350 } 351 352 static struct serial_device sh_serial_drv = { 353 .name = "sh_serial", 354 .start = sh_serial_init, 355 .stop = NULL, 356 .setbrg = sh_serial_setbrg, 357 .putc = sh_serial_putc, 358 .puts = default_serial_puts, 359 .getc = sh_serial_getc, 360 .tstc = sh_serial_tstc, 361 }; 362 sh_serial_initialize(void)363 void sh_serial_initialize(void) 364 { 365 serial_register(&sh_serial_drv); 366 } 367 default_serial_console(void)368 __weak struct serial_device *default_serial_console(void) 369 { 370 return &sh_serial_drv; 371 } 372 #endif /* CONFIG_DM_SERIAL */ 373