1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * arch/sh/kernel/cpu/sh2/clock-sh7619.c
4 *
5 * SH7619 support for the clock framework
6 *
7 * Copyright (C) 2006 Yoshinori Sato
8 *
9 * Based on clock-sh4.c
10 * Copyright (C) 2005 Paul Mundt
11 */
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/io.h>
15 #include <asm/clock.h>
16 #include <asm/freq.h>
17 #include <asm/processor.h>
18
19 static const int pll1rate[] = {1,2};
20 static const int pfc_divisors[] = {1,2,0,4};
21 static unsigned int pll2_mult;
22
master_clk_init(struct clk * clk)23 static void master_clk_init(struct clk *clk)
24 {
25 clk->rate *= pll2_mult * pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
26 }
27
28 static struct sh_clk_ops sh7619_master_clk_ops = {
29 .init = master_clk_init,
30 };
31
module_clk_recalc(struct clk * clk)32 static unsigned long module_clk_recalc(struct clk *clk)
33 {
34 int idx = (__raw_readw(FREQCR) & 0x0007);
35 return clk->parent->rate / pfc_divisors[idx];
36 }
37
38 static struct sh_clk_ops sh7619_module_clk_ops = {
39 .recalc = module_clk_recalc,
40 };
41
bus_clk_recalc(struct clk * clk)42 static unsigned long bus_clk_recalc(struct clk *clk)
43 {
44 return clk->parent->rate / pll1rate[(__raw_readw(FREQCR) >> 8) & 7];
45 }
46
47 static struct sh_clk_ops sh7619_bus_clk_ops = {
48 .recalc = bus_clk_recalc,
49 };
50
51 static struct sh_clk_ops sh7619_cpu_clk_ops = {
52 .recalc = followparent_recalc,
53 };
54
55 static struct sh_clk_ops *sh7619_clk_ops[] = {
56 &sh7619_master_clk_ops,
57 &sh7619_module_clk_ops,
58 &sh7619_bus_clk_ops,
59 &sh7619_cpu_clk_ops,
60 };
61
arch_init_clk_ops(struct sh_clk_ops ** ops,int idx)62 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
63 {
64 if (test_mode_pin(MODE_PIN2 | MODE_PIN0) ||
65 test_mode_pin(MODE_PIN2 | MODE_PIN1))
66 pll2_mult = 2;
67 else if (test_mode_pin(MODE_PIN0) || test_mode_pin(MODE_PIN1))
68 pll2_mult = 4;
69
70 BUG_ON(!pll2_mult);
71
72 if (idx < ARRAY_SIZE(sh7619_clk_ops))
73 *ops = sh7619_clk_ops[idx];
74 }
75