1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
5 *
6 * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x)
7 * Author: Markus Niebel <markus.niebel@tq-group.com>
8 *
9 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
10 */
11
12 #include <asm/io.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/mx6-pins.h>
15 #include <asm/arch/imx-regs.h>
16 #include <asm/arch/iomux.h>
17 #include <asm/arch/sys_proto.h>
18 #include <linux/errno.h>
19 #include <asm/gpio.h>
20 #include <asm/mach-imx/boot_mode.h>
21 #include <asm/mach-imx/mxc_i2c.h>
22
23 #include <common.h>
24 #include <fsl_esdhc.h>
25 #include <linux/libfdt.h>
26 #include <malloc.h>
27 #include <i2c.h>
28 #include <micrel.h>
29 #include <miiphy.h>
30 #include <mmc.h>
31 #include <netdev.h>
32
33 #include "tqma6_bb.h"
34
35 /* UART */
36 #define UART4_PAD_CTRL ( \
37 PAD_CTL_HYS | \
38 PAD_CTL_PUS_100K_UP | \
39 PAD_CTL_PUE | \
40 PAD_CTL_PKE | \
41 PAD_CTL_SPEED_MED | \
42 PAD_CTL_DSE_40ohm | \
43 PAD_CTL_SRE_SLOW \
44 )
45
46 static iomux_v3_cfg_t const uart4_pads[] = {
47 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT17__UART4_CTS_B, UART4_PAD_CTRL),
48 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT16__UART4_RTS_B, UART4_PAD_CTRL),
49 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT13__UART4_RX_DATA, UART4_PAD_CTRL),
50 NEW_PAD_CTRL(MX6_PAD_CSI0_DAT12__UART4_TX_DATA, UART4_PAD_CTRL),
51 };
52
setup_iomuxc_uart4(void)53 static void setup_iomuxc_uart4(void)
54 {
55 imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
56 }
57
58 /* MMC */
59 #define USDHC2_PAD_CTRL ( \
60 PAD_CTL_HYS | \
61 PAD_CTL_PUS_47K_UP | \
62 PAD_CTL_SPEED_LOW | \
63 PAD_CTL_DSE_80ohm | \
64 PAD_CTL_SRE_FAST \
65 )
66
67 #define USDHC2_CLK_PAD_CTRL ( \
68 PAD_CTL_HYS | \
69 PAD_CTL_PUS_47K_UP | \
70 PAD_CTL_SPEED_LOW | \
71 PAD_CTL_DSE_40ohm | \
72 PAD_CTL_SRE_FAST \
73 )
74
75 static iomux_v3_cfg_t const usdhc2_pads[] = {
76 NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC2_CLK_PAD_CTRL),
77 NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC2_PAD_CTRL),
78 NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC2_PAD_CTRL),
79 NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC2_PAD_CTRL),
80 NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC2_PAD_CTRL),
81 NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC2_PAD_CTRL),
82
83 NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, USDHC2_PAD_CTRL), /* CD */
84 NEW_PAD_CTRL(MX6_PAD_GPIO_2__SD2_WP, USDHC2_PAD_CTRL), /* WP */
85 };
86
87 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4)
88 #define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2)
89
90 static struct fsl_esdhc_cfg usdhc2_cfg = {
91 .esdhc_base = USDHC2_BASE_ADDR,
92 .max_bus_width = 4,
93 };
94
tqma6_bb_board_mmc_getcd(struct mmc * mmc)95 int tqma6_bb_board_mmc_getcd(struct mmc *mmc)
96 {
97 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
98 int ret = 0;
99
100 if (cfg->esdhc_base == USDHC2_BASE_ADDR)
101 ret = !gpio_get_value(USDHC2_CD_GPIO);
102
103 return ret;
104 }
105
tqma6_bb_board_mmc_getwp(struct mmc * mmc)106 int tqma6_bb_board_mmc_getwp(struct mmc *mmc)
107 {
108 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
109 int ret = 0;
110
111 if (cfg->esdhc_base == USDHC2_BASE_ADDR)
112 ret = gpio_get_value(USDHC2_WP_GPIO);
113
114 return ret;
115 }
116
tqma6_bb_board_mmc_init(bd_t * bis)117 int tqma6_bb_board_mmc_init(bd_t *bis)
118 {
119 int ret;
120
121 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
122
123 ret = gpio_request(USDHC2_CD_GPIO, "mmc-cd");
124 if (!ret)
125 gpio_direction_input(USDHC2_CD_GPIO);
126 ret = gpio_request(USDHC2_WP_GPIO, "mmc-wp");
127 if (!ret)
128 gpio_direction_input(USDHC2_WP_GPIO);
129
130 usdhc2_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
131 if(fsl_esdhc_initialize(bis, &usdhc2_cfg))
132 puts("WARNING: failed to initialize SD\n");
133
134 return 0;
135 }
136
137 /* Ethernet */
138 #define ENET_PAD_CTRL ( \
139 PAD_CTL_HYS | \
140 PAD_CTL_PUS_100K_UP | \
141 PAD_CTL_PUE | \
142 PAD_CTL_PKE | \
143 PAD_CTL_SPEED_MED | \
144 PAD_CTL_DSE_40ohm | \
145 PAD_CTL_SRE_SLOW \
146 )
147
148 static iomux_v3_cfg_t const enet_pads[] = {
149 NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_PAD_CTRL),
150 NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_PAD_CTRL),
151 NEW_PAD_CTRL(MX6_PAD_GPIO_16__ENET_REF_CLK, ENET_PAD_CTRL),
152 NEW_PAD_CTRL(MX6_PAD_ENET_RXD0__ENET_RX_DATA0, ENET_PAD_CTRL),
153 NEW_PAD_CTRL(MX6_PAD_ENET_RXD1__ENET_RX_DATA1, ENET_PAD_CTRL),
154 NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__ENET_RX_EN, ENET_PAD_CTRL),
155 NEW_PAD_CTRL(MX6_PAD_ENET_RX_ER__ENET_RX_ER, ENET_PAD_CTRL),
156 NEW_PAD_CTRL(MX6_PAD_ENET_TXD0__ENET_TX_DATA0, ENET_PAD_CTRL),
157 NEW_PAD_CTRL(MX6_PAD_ENET_TXD1__ENET_TX_DATA1, ENET_PAD_CTRL),
158 NEW_PAD_CTRL(MX6_PAD_ENET_TX_EN__ENET_TX_EN, ENET_PAD_CTRL),
159 NEW_PAD_CTRL(MX6_PAD_GPIO_19__ENET_TX_ER, ENET_PAD_CTRL),
160
161 /* ENET1 reset */
162 NEW_PAD_CTRL(MX6_PAD_GPIO_8__GPIO1_IO08, ENET_PAD_CTRL),
163 /* ENET1 interrupt */
164 NEW_PAD_CTRL(MX6_PAD_GPIO_9__GPIO1_IO09, ENET_PAD_CTRL),
165 };
166
167 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 8)
168
setup_iomuxc_enet(void)169 static void setup_iomuxc_enet(void)
170 {
171 int ret;
172
173 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
174
175 /* Reset LAN8720 PHY */
176 ret = gpio_request(ENET_PHY_RESET_GPIO, "phy-reset");
177 if (!ret)
178 gpio_direction_output(ENET_PHY_RESET_GPIO , 0);
179 udelay(25000);
180 gpio_set_value(ENET_PHY_RESET_GPIO, 1);
181 }
182
board_eth_init(bd_t * bis)183 int board_eth_init(bd_t *bis)
184 {
185 return cpu_eth_init(bis);
186 }
187
188 /* GPIO */
189 #define GPIO_PAD_CTRL ( \
190 PAD_CTL_HYS | \
191 PAD_CTL_PUS_100K_UP | \
192 PAD_CTL_PUE | \
193 PAD_CTL_SPEED_MED | \
194 PAD_CTL_DSE_40ohm | \
195 PAD_CTL_SRE_SLOW \
196 )
197
198 #define GPIO_OD_PAD_CTRL ( \
199 PAD_CTL_HYS | \
200 PAD_CTL_PUS_100K_UP | \
201 PAD_CTL_PUE | \
202 PAD_CTL_ODE | \
203 PAD_CTL_SPEED_MED | \
204 PAD_CTL_DSE_40ohm | \
205 PAD_CTL_SRE_SLOW \
206 )
207
208 static iomux_v3_cfg_t const gpio_pads[] = {
209 /* USB_H_PWR */
210 NEW_PAD_CTRL(MX6_PAD_GPIO_0__GPIO1_IO00, GPIO_PAD_CTRL),
211 /* USB_OTG_PWR */
212 NEW_PAD_CTRL(MX6_PAD_EIM_D22__GPIO3_IO22, GPIO_PAD_CTRL),
213 /* PCIE_RST */
214 NEW_PAD_CTRL(MX6_PAD_NANDF_CLE__GPIO6_IO07, GPIO_OD_PAD_CTRL),
215 /* UART1_PWRON */
216 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT14__GPIO5_IO08, GPIO_PAD_CTRL),
217 /* UART2_PWRON */
218 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT16__GPIO5_IO10, GPIO_PAD_CTRL),
219 /* UART3_PWRON */
220 NEW_PAD_CTRL(MX6_PAD_DISP0_DAT18__GPIO5_IO12, GPIO_PAD_CTRL),
221 };
222
223 #define GPIO_USB_H_PWR IMX_GPIO_NR(1, 0)
224 #define GPIO_USB_OTG_PWR IMX_GPIO_NR(3, 22)
225 #define GPIO_PCIE_RST IMX_GPIO_NR(6, 7)
226 #define GPIO_UART1_PWRON IMX_GPIO_NR(5, 8)
227 #define GPIO_UART2_PWRON IMX_GPIO_NR(5, 10)
228 #define GPIO_UART3_PWRON IMX_GPIO_NR(5, 12)
229
gpio_init(void)230 static void gpio_init(void)
231 {
232 int ret;
233
234 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
235
236 ret = gpio_request(GPIO_USB_H_PWR, "usb-h-pwr");
237 if (!ret)
238 gpio_direction_output(GPIO_USB_H_PWR, 1);
239 ret = gpio_request(GPIO_USB_OTG_PWR, "usb-otg-pwr");
240 if (!ret)
241 gpio_direction_output(GPIO_USB_OTG_PWR, 1);
242 ret = gpio_request(GPIO_PCIE_RST, "pcie-reset");
243 if (!ret)
244 gpio_direction_output(GPIO_PCIE_RST, 1);
245 ret = gpio_request(GPIO_UART1_PWRON, "uart1-pwr");
246 if (!ret)
247 gpio_direction_output(GPIO_UART1_PWRON, 0);
248 ret = gpio_request(GPIO_UART2_PWRON, "uart2-pwr");
249 if (!ret)
250 gpio_direction_output(GPIO_UART2_PWRON, 0);
251 ret = gpio_request(GPIO_UART3_PWRON, "uart3-pwr");
252 if (!ret)
253 gpio_direction_output(GPIO_UART3_PWRON, 0);
254 }
255
tqma6_iomuxc_spi(void)256 void tqma6_iomuxc_spi(void)
257 {
258 /* No SPI on this baseboard */
259 }
260
tqma6_bb_board_early_init_f(void)261 int tqma6_bb_board_early_init_f(void)
262 {
263 setup_iomuxc_uart4();
264
265 return 0;
266 }
267
tqma6_bb_board_init(void)268 int tqma6_bb_board_init(void)
269 {
270 setup_iomuxc_enet();
271
272 gpio_init();
273
274 /* Turn the UART-couplers on one-after-another */
275 gpio_set_value(GPIO_UART1_PWRON, 1);
276 mdelay(10);
277 gpio_set_value(GPIO_UART2_PWRON, 1);
278 mdelay(10);
279 gpio_set_value(GPIO_UART3_PWRON, 1);
280
281 return 0;
282 }
283
tqma6_bb_board_late_init(void)284 int tqma6_bb_board_late_init(void)
285 {
286 return 0;
287 }
288
tqma6_bb_get_boardname(void)289 const char *tqma6_bb_get_boardname(void)
290 {
291 return "WRU-IV";
292 }
293
294 static const struct boot_mode board_boot_modes[] = {
295 /* 4 bit bus width */
296 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
297 /* 8 bit bus width */
298 {"emmc", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
299 { NULL, 0 },
300 };
301
misc_init_r(void)302 int misc_init_r(void)
303 {
304 add_board_boot_modes(board_boot_modes);
305
306 return 0;
307 }
308
309 #define WRU4_USB_H1_PWR IMX_GPIO_NR(1, 0)
310 #define WRU4_USB_OTG_PWR IMX_GPIO_NR(3, 22)
311
board_ehci_hcd_init(int port)312 int board_ehci_hcd_init(int port)
313 {
314 int ret;
315
316 ret = gpio_request(WRU4_USB_H1_PWR, "usb-h1-pwr");
317 if (!ret)
318 gpio_direction_output(WRU4_USB_H1_PWR, 1);
319
320 ret = gpio_request(WRU4_USB_OTG_PWR, "usb-OTG-pwr");
321 if (!ret)
322 gpio_direction_output(WRU4_USB_OTG_PWR, 1);
323
324 return 0;
325 }
326
board_ehci_power(int port,int on)327 int board_ehci_power(int port, int on)
328 {
329 if (port)
330 gpio_set_value(WRU4_USB_OTG_PWR, on);
331 else
332 gpio_set_value(WRU4_USB_H1_PWR, on);
333
334 return 0;
335 }
336
337 /*
338 * Device Tree Support
339 */
340 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
tqma6_bb_ft_board_setup(void * blob,bd_t * bd)341 void tqma6_bb_ft_board_setup(void *blob, bd_t *bd)
342 {
343 /* TBD */
344 }
345 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
346