1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 *
5 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 */
7
8 #include <common.h>
9 #include <asm/io.h>
10 #include <asm/arch/clock.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux.h>
13 #include <asm/arch/mx6-pins.h>
14 #include <linux/errno.h>
15 #include <asm/gpio.h>
16 #include <asm/mach-imx/iomux-v3.h>
17 #include <asm/mach-imx/mxc_i2c.h>
18 #include <asm/mach-imx/boot_mode.h>
19 #include <asm/mach-imx/spi.h>
20 #include <mmc.h>
21 #include <fsl_esdhc.h>
22 #include <miiphy.h>
23 #include <netdev.h>
24 #include <asm/arch/sys_proto.h>
25 #include <i2c.h>
26 #include <input.h>
27 #include <asm/arch/mxc_hdmi.h>
28 #include <asm/mach-imx/video.h>
29 #include <asm/arch/crm_regs.h>
30 #include <pca953x.h>
31 #include <power/pmic.h>
32 #include <power/pfuze100_pmic.h>
33 #include "../common/pfuze.h"
34
35 DECLARE_GLOBAL_DATA_PTR;
36
37 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
38 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40
41 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
42 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
43 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
44
45 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
46 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
47
48 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
50 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
51
52 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
53 #define GPMI_PAD_CTRL1 (PAD_CTL_DSE_40ohm | PAD_CTL_SPEED_MED | \
54 PAD_CTL_SRE_FAST)
55 #define GPMI_PAD_CTRL2 (GPMI_PAD_CTRL0 | GPMI_PAD_CTRL1)
56
57 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
58
59 #define WEIM_NOR_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
60 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
61 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
62
63 #define I2C_PMIC 1
64
dram_init(void)65 int dram_init(void)
66 {
67 gd->ram_size = imx_ddr_size();
68
69 return 0;
70 }
71
72 static iomux_v3_cfg_t const uart4_pads[] = {
73 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
74 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
75 };
76
77 static iomux_v3_cfg_t const enet_pads[] = {
78 IOMUX_PADS(PAD_KEY_COL1__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)),
79 IOMUX_PADS(PAD_KEY_COL2__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
80 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
81 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
82 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
83 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
84 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
85 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
86 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)),
87 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)),
88 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
89 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
90 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
91 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
92 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)),
93 };
94
95 /* I2C2 PMIC, iPod, Tuner, Codec, Touch, HDMI EDID, MIPI CSI2 card */
96 static struct i2c_pads_info mx6q_i2c_pad_info1 = {
97 .scl = {
98 .i2c_mode = MX6Q_PAD_EIM_EB2__I2C2_SCL | PC,
99 .gpio_mode = MX6Q_PAD_EIM_EB2__GPIO2_IO30 | PC,
100 .gp = IMX_GPIO_NR(2, 30)
101 },
102 .sda = {
103 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
104 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
105 .gp = IMX_GPIO_NR(4, 13)
106 }
107 };
108
109 static struct i2c_pads_info mx6dl_i2c_pad_info1 = {
110 .scl = {
111 .i2c_mode = MX6DL_PAD_EIM_EB2__I2C2_SCL | PC,
112 .gpio_mode = MX6DL_PAD_EIM_EB2__GPIO2_IO30 | PC,
113 .gp = IMX_GPIO_NR(2, 30)
114 },
115 .sda = {
116 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
117 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
118 .gp = IMX_GPIO_NR(4, 13)
119 }
120 };
121
122 #ifndef CONFIG_SYS_FLASH_CFI
123 /*
124 * I2C3 MLB, Port Expanders (A, B, C), Video ADC, Light Sensor,
125 * Compass Sensor, Accelerometer, Res Touch
126 */
127 static struct i2c_pads_info mx6q_i2c_pad_info2 = {
128 .scl = {
129 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
130 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
131 .gp = IMX_GPIO_NR(1, 3)
132 },
133 .sda = {
134 .i2c_mode = MX6Q_PAD_EIM_D18__I2C3_SDA | PC,
135 .gpio_mode = MX6Q_PAD_EIM_D18__GPIO3_IO18 | PC,
136 .gp = IMX_GPIO_NR(3, 18)
137 }
138 };
139
140 static struct i2c_pads_info mx6dl_i2c_pad_info2 = {
141 .scl = {
142 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
143 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
144 .gp = IMX_GPIO_NR(1, 3)
145 },
146 .sda = {
147 .i2c_mode = MX6DL_PAD_EIM_D18__I2C3_SDA | PC,
148 .gpio_mode = MX6DL_PAD_EIM_D18__GPIO3_IO18 | PC,
149 .gp = IMX_GPIO_NR(3, 18)
150 }
151 };
152 #endif
153
154 static iomux_v3_cfg_t const i2c3_pads[] = {
155 IOMUX_PADS(PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL)),
156 };
157
158 static iomux_v3_cfg_t const port_exp[] = {
159 IOMUX_PADS(PAD_SD2_DAT0__GPIO1_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
160 };
161
162 #ifdef CONFIG_MTD_NOR_FLASH
163 static iomux_v3_cfg_t const eimnor_pads[] = {
164 IOMUX_PADS(PAD_EIM_D16__EIM_DATA16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
165 IOMUX_PADS(PAD_EIM_D17__EIM_DATA17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
166 IOMUX_PADS(PAD_EIM_D18__EIM_DATA18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
167 IOMUX_PADS(PAD_EIM_D19__EIM_DATA19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
168 IOMUX_PADS(PAD_EIM_D20__EIM_DATA20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
169 IOMUX_PADS(PAD_EIM_D21__EIM_DATA21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
170 IOMUX_PADS(PAD_EIM_D22__EIM_DATA22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
171 IOMUX_PADS(PAD_EIM_D23__EIM_DATA23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
172 IOMUX_PADS(PAD_EIM_D24__EIM_DATA24 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
173 IOMUX_PADS(PAD_EIM_D25__EIM_DATA25 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
174 IOMUX_PADS(PAD_EIM_D26__EIM_DATA26 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
175 IOMUX_PADS(PAD_EIM_D27__EIM_DATA27 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
176 IOMUX_PADS(PAD_EIM_D28__EIM_DATA28 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
177 IOMUX_PADS(PAD_EIM_D29__EIM_DATA29 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
178 IOMUX_PADS(PAD_EIM_D30__EIM_DATA30 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
179 IOMUX_PADS(PAD_EIM_D31__EIM_DATA31 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
180 IOMUX_PADS(PAD_EIM_DA0__EIM_AD00 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
181 IOMUX_PADS(PAD_EIM_DA1__EIM_AD01 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
182 IOMUX_PADS(PAD_EIM_DA2__EIM_AD02 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
183 IOMUX_PADS(PAD_EIM_DA3__EIM_AD03 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
184 IOMUX_PADS(PAD_EIM_DA4__EIM_AD04 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
185 IOMUX_PADS(PAD_EIM_DA5__EIM_AD05 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
186 IOMUX_PADS(PAD_EIM_DA6__EIM_AD06 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
187 IOMUX_PADS(PAD_EIM_DA7__EIM_AD07 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
188 IOMUX_PADS(PAD_EIM_DA8__EIM_AD08 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
189 IOMUX_PADS(PAD_EIM_DA9__EIM_AD09 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
190 IOMUX_PADS(PAD_EIM_DA10__EIM_AD10 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
191 IOMUX_PADS(PAD_EIM_DA11__EIM_AD11 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
192 IOMUX_PADS(PAD_EIM_DA12__EIM_AD12 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
193 IOMUX_PADS(PAD_EIM_DA13__EIM_AD13 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
194 IOMUX_PADS(PAD_EIM_DA14__EIM_AD14 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
195 IOMUX_PADS(PAD_EIM_DA15__EIM_AD15 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
196 IOMUX_PADS(PAD_EIM_A16__EIM_ADDR16 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
197 IOMUX_PADS(PAD_EIM_A17__EIM_ADDR17 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
198 IOMUX_PADS(PAD_EIM_A18__EIM_ADDR18 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
199 IOMUX_PADS(PAD_EIM_A19__EIM_ADDR19 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
200 IOMUX_PADS(PAD_EIM_A20__EIM_ADDR20 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
201 IOMUX_PADS(PAD_EIM_A21__EIM_ADDR21 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
202 IOMUX_PADS(PAD_EIM_A22__EIM_ADDR22 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
203 IOMUX_PADS(PAD_EIM_A23__EIM_ADDR23 | MUX_PAD_CTRL(WEIM_NOR_PAD_CTRL)),
204 IOMUX_PADS(PAD_EIM_OE__EIM_OE_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
205 IOMUX_PADS(PAD_EIM_RW__EIM_RW | MUX_PAD_CTRL(NO_PAD_CTRL)),
206 IOMUX_PADS(PAD_EIM_CS0__EIM_CS0_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
207 };
208
eimnor_cs_setup(void)209 static void eimnor_cs_setup(void)
210 {
211 struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
212
213 writel(0x00020181, &weim_regs->cs0gcr1);
214 writel(0x00000001, &weim_regs->cs0gcr2);
215 writel(0x0a020000, &weim_regs->cs0rcr1);
216 writel(0x0000c000, &weim_regs->cs0rcr2);
217 writel(0x0804a240, &weim_regs->cs0wcr1);
218 writel(0x00000120, &weim_regs->wcr);
219
220 set_chipselect_size(CS0_128);
221 }
222
eim_clk_setup(void)223 static void eim_clk_setup(void)
224 {
225 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
226 int cscmr1, ccgr6;
227
228
229 /* Turn off EIM clock */
230 ccgr6 = readl(&imx_ccm->CCGR6);
231 ccgr6 &= ~(0x3 << 10);
232 writel(ccgr6, &imx_ccm->CCGR6);
233
234 /*
235 * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
236 * and aclk_eim_slow_podf = 01 --> divide by 2
237 * so that we can have EIM at the maximum clock of 132MHz
238 */
239 cscmr1 = readl(&imx_ccm->cscmr1);
240 cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
241 MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
242 cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
243 writel(cscmr1, &imx_ccm->cscmr1);
244
245 /* Turn on EIM clock */
246 ccgr6 |= (0x3 << 10);
247 writel(ccgr6, &imx_ccm->CCGR6);
248 }
249
setup_iomux_eimnor(void)250 static void setup_iomux_eimnor(void)
251 {
252 SETUP_IOMUX_PADS(eimnor_pads);
253
254 gpio_direction_output(IMX_GPIO_NR(5, 4), 0);
255
256 eimnor_cs_setup();
257 }
258 #endif
259
setup_iomux_enet(void)260 static void setup_iomux_enet(void)
261 {
262 SETUP_IOMUX_PADS(enet_pads);
263 }
264
265 static iomux_v3_cfg_t const usdhc3_pads[] = {
266 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
267 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
268 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
269 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
270 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
271 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
272 IOMUX_PADS(PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
273 IOMUX_PADS(PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
274 IOMUX_PADS(PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
275 IOMUX_PADS(PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
276 IOMUX_PADS(PAD_GPIO_18__SD3_VSELECT | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
277 IOMUX_PADS(PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
278 };
279
setup_iomux_uart(void)280 static void setup_iomux_uart(void)
281 {
282 SETUP_IOMUX_PADS(uart4_pads);
283 }
284
285 #ifdef CONFIG_FSL_ESDHC
286 static struct fsl_esdhc_cfg usdhc_cfg[1] = {
287 {USDHC3_BASE_ADDR},
288 };
289
board_mmc_getcd(struct mmc * mmc)290 int board_mmc_getcd(struct mmc *mmc)
291 {
292 gpio_direction_input(IMX_GPIO_NR(6, 15));
293 return !gpio_get_value(IMX_GPIO_NR(6, 15));
294 }
295
board_mmc_init(bd_t * bis)296 int board_mmc_init(bd_t *bis)
297 {
298 SETUP_IOMUX_PADS(usdhc3_pads);
299
300 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
301 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
302 }
303 #endif
304
305 #ifdef CONFIG_NAND_MXS
306 static iomux_v3_cfg_t gpmi_pads[] = {
307 IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
308 IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
309 IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
310 IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(GPMI_PAD_CTRL0)),
311 IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
312 IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
313 IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
314 IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
315 IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
316 IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
317 IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
318 IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
319 IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
320 IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
321 IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(GPMI_PAD_CTRL2)),
322 IOMUX_PADS(PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(GPMI_PAD_CTRL1)),
323 };
324
setup_gpmi_nand(void)325 static void setup_gpmi_nand(void)
326 {
327 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
328
329 /* config gpmi nand iomux */
330 SETUP_IOMUX_PADS(gpmi_pads);
331
332 setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
333 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
334 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)));
335
336 /* enable apbh clock gating */
337 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
338 }
339 #endif
340
setup_fec(void)341 static void setup_fec(void)
342 {
343 if (is_mx6dqp()) {
344 /*
345 * select ENET MAC0 TX clock from PLL
346 */
347 imx_iomux_set_gpr_register(5, 9, 1, 1);
348 enable_fec_anatop_clock(0, ENET_125MHZ);
349 }
350
351 setup_iomux_enet();
352 }
353
board_eth_init(bd_t * bis)354 int board_eth_init(bd_t *bis)
355 {
356 setup_fec();
357
358 return cpu_eth_init(bis);
359 }
360
get_board_rev(void)361 u32 get_board_rev(void)
362 {
363 int rev = nxp_board_rev();
364
365 return (get_cpu_rev() & ~(0xF << 8)) | rev;
366 }
367
ar8031_phy_fixup(struct phy_device * phydev)368 static int ar8031_phy_fixup(struct phy_device *phydev)
369 {
370 unsigned short val;
371
372 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
373 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
374 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
375 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
376
377 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
378 val &= 0xffe3;
379 val |= 0x18;
380 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
381
382 /* introduce tx clock delay */
383 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
384 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
385 val |= 0x0100;
386 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
387
388 return 0;
389 }
390
board_phy_config(struct phy_device * phydev)391 int board_phy_config(struct phy_device *phydev)
392 {
393 ar8031_phy_fixup(phydev);
394
395 if (phydev->drv->config)
396 phydev->drv->config(phydev);
397
398 return 0;
399 }
400
401 #if defined(CONFIG_VIDEO_IPUV3)
disable_lvds(struct display_info_t const * dev)402 static void disable_lvds(struct display_info_t const *dev)
403 {
404 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
405
406 clrbits_le32(&iomux->gpr[2],
407 IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
408 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
409 }
410
do_enable_hdmi(struct display_info_t const * dev)411 static void do_enable_hdmi(struct display_info_t const *dev)
412 {
413 disable_lvds(dev);
414 imx_enable_hdmi_phy();
415 }
416
417 struct display_info_t const displays[] = {{
418 .bus = -1,
419 .addr = 0,
420 .pixfmt = IPU_PIX_FMT_RGB666,
421 .detect = NULL,
422 .enable = NULL,
423 .mode = {
424 .name = "Hannstar-XGA",
425 .refresh = 60,
426 .xres = 1024,
427 .yres = 768,
428 .pixclock = 15385,
429 .left_margin = 220,
430 .right_margin = 40,
431 .upper_margin = 21,
432 .lower_margin = 7,
433 .hsync_len = 60,
434 .vsync_len = 10,
435 .sync = FB_SYNC_EXT,
436 .vmode = FB_VMODE_NONINTERLACED
437 } }, {
438 .bus = -1,
439 .addr = 0,
440 .pixfmt = IPU_PIX_FMT_RGB24,
441 .detect = detect_hdmi,
442 .enable = do_enable_hdmi,
443 .mode = {
444 .name = "HDMI",
445 .refresh = 60,
446 .xres = 1024,
447 .yres = 768,
448 .pixclock = 15385,
449 .left_margin = 220,
450 .right_margin = 40,
451 .upper_margin = 21,
452 .lower_margin = 7,
453 .hsync_len = 60,
454 .vsync_len = 10,
455 .sync = FB_SYNC_EXT,
456 .vmode = FB_VMODE_NONINTERLACED,
457 } } };
458 size_t display_count = ARRAY_SIZE(displays);
459
460 iomux_v3_cfg_t const backlight_pads[] = {
461 IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(ENET_PAD_CTRL)),
462 };
463
setup_iomux_backlight(void)464 static void setup_iomux_backlight(void)
465 {
466 gpio_request(IMX_GPIO_NR(2, 9), "backlight");
467 gpio_direction_output(IMX_GPIO_NR(2, 9), 1);
468 SETUP_IOMUX_PADS(backlight_pads);
469 }
470
setup_display(void)471 static void setup_display(void)
472 {
473 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
474 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
475 int reg;
476
477 setup_iomux_backlight();
478 enable_ipu_clock();
479 imx_setup_hdmi();
480
481 /* Turn on LDB_DI0 and LDB_DI1 clocks */
482 reg = readl(&mxc_ccm->CCGR3);
483 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
484 writel(reg, &mxc_ccm->CCGR3);
485
486 /* Set LDB_DI0 and LDB_DI1 clk select to 3b'011 */
487 reg = readl(&mxc_ccm->cs2cdr);
488 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK |
489 MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
490 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) |
491 (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
492 writel(reg, &mxc_ccm->cs2cdr);
493
494 reg = readl(&mxc_ccm->cscmr2);
495 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
496 writel(reg, &mxc_ccm->cscmr2);
497
498 reg = readl(&mxc_ccm->chsccdr);
499 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
500 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
501 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 <<
502 MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
503 writel(reg, &mxc_ccm->chsccdr);
504
505 reg = IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW |
506 IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW |
507 IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG |
508 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT |
509 IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG |
510 IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
511 IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 |
512 IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED;
513 writel(reg, &iomux->gpr[2]);
514
515 reg = readl(&iomux->gpr[3]);
516 reg &= ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK |
517 IOMUXC_GPR3_HDMI_MUX_CTL_MASK);
518 reg |= (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
519 IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET) |
520 (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 <<
521 IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET);
522 writel(reg, &iomux->gpr[3]);
523 }
524 #endif /* CONFIG_VIDEO_IPUV3 */
525
526 /*
527 * Do not overwrite the console
528 * Use always serial for U-Boot console
529 */
overwrite_console(void)530 int overwrite_console(void)
531 {
532 return 1;
533 }
534
board_early_init_f(void)535 int board_early_init_f(void)
536 {
537 setup_iomux_uart();
538
539 #ifdef CONFIG_NAND_MXS
540 setup_gpmi_nand();
541 #endif
542
543 #ifdef CONFIG_MTD_NOR_FLASH
544 eim_clk_setup();
545 #endif
546 return 0;
547 }
548
board_init(void)549 int board_init(void)
550 {
551 /* address of boot parameters */
552 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
553
554 /* I2C 2 and 3 setup - I2C 3 hw mux with EIM */
555 if (is_mx6dq() || is_mx6dqp())
556 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
557 else
558 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
559 /* I2C 3 Steer */
560 gpio_request(IMX_GPIO_NR(5, 4), "steer logic");
561 gpio_direction_output(IMX_GPIO_NR(5, 4), 1);
562 SETUP_IOMUX_PADS(i2c3_pads);
563 #ifndef CONFIG_SYS_FLASH_CFI
564 if (is_mx6dq() || is_mx6dqp())
565 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
566 else
567 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
568 #endif
569 gpio_request(IMX_GPIO_NR(1, 15), "expander en");
570 gpio_direction_output(IMX_GPIO_NR(1, 15), 1);
571 SETUP_IOMUX_PADS(port_exp);
572
573 #ifdef CONFIG_VIDEO_IPUV3
574 setup_display();
575 #endif
576
577 #ifdef CONFIG_MTD_NOR_FLASH
578 setup_iomux_eimnor();
579 #endif
580 return 0;
581 }
582
583 #ifdef CONFIG_MXC_SPI
board_spi_cs_gpio(unsigned bus,unsigned cs)584 int board_spi_cs_gpio(unsigned bus, unsigned cs)
585 {
586 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 9)) : -1;
587 }
588 #endif
589
power_init_board(void)590 int power_init_board(void)
591 {
592 struct pmic *p;
593 unsigned int value;
594
595 p = pfuze_common_init(I2C_PMIC);
596 if (!p)
597 return -ENODEV;
598
599 if (is_mx6dqp()) {
600 /* set SW2 staby volatage 0.975V*/
601 pmic_reg_read(p, PFUZE100_SW2STBY, &value);
602 value &= ~0x3f;
603 value |= 0x17;
604 pmic_reg_write(p, PFUZE100_SW2STBY, value);
605 }
606
607 return pfuze_mode_init(p, APS_PFM);
608 }
609
610 #ifdef CONFIG_CMD_BMODE
611 static const struct boot_mode board_boot_modes[] = {
612 /* 4 bit bus width */
613 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
614 {NULL, 0},
615 };
616 #endif
617
board_late_init(void)618 int board_late_init(void)
619 {
620 #ifdef CONFIG_CMD_BMODE
621 add_board_boot_modes(board_boot_modes);
622 #endif
623
624 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
625 env_set("board_name", "SABREAUTO");
626
627 if (is_mx6dqp())
628 env_set("board_rev", "MX6QP");
629 else if (is_mx6dq())
630 env_set("board_rev", "MX6Q");
631 else if (is_mx6sdl())
632 env_set("board_rev", "MX6DL");
633 #endif
634
635 return 0;
636 }
637
checkboard(void)638 int checkboard(void)
639 {
640 printf("Board: MX6Q-Sabreauto rev%c\n", nxp_board_rev_string());
641
642 return 0;
643 }
644
645 #ifdef CONFIG_USB_EHCI_MX6
board_ehci_hcd_init(int port)646 int board_ehci_hcd_init(int port)
647 {
648 switch (port) {
649 case 0:
650 /*
651 * Set daisy chain for otg_pin_id on 6q.
652 * For 6dl, this bit is reserved.
653 */
654 imx_iomux_set_gpr_register(1, 13, 1, 0);
655 break;
656 case 1:
657 break;
658 default:
659 printf("MXC USB port %d not yet supported\n", port);
660 return -EINVAL;
661 }
662 return 0;
663 }
664 #endif
665
666 #ifdef CONFIG_SPL_BUILD
667 #include <asm/arch/mx6-ddr.h>
668 #include <spl.h>
669 #include <linux/libfdt.h>
670
671 #ifdef CONFIG_SPL_OS_BOOT
spl_start_uboot(void)672 int spl_start_uboot(void)
673 {
674 return 0;
675 }
676 #endif
677
ccgr_init(void)678 static void ccgr_init(void)
679 {
680 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
681
682 writel(0x00C03F3F, &ccm->CCGR0);
683 writel(0x0030FC03, &ccm->CCGR1);
684 writel(0x0FFFC000, &ccm->CCGR2);
685 writel(0x3FF00000, &ccm->CCGR3);
686 writel(0x00FFF300, &ccm->CCGR4);
687 writel(0x0F0000C3, &ccm->CCGR5);
688 writel(0x000003FF, &ccm->CCGR6);
689 }
690
691 static int mx6q_dcd_table[] = {
692 0x020e0798, 0x000C0000,
693 0x020e0758, 0x00000000,
694 0x020e0588, 0x00000030,
695 0x020e0594, 0x00000030,
696 0x020e056c, 0x00000030,
697 0x020e0578, 0x00000030,
698 0x020e074c, 0x00000030,
699 0x020e057c, 0x00000030,
700 0x020e058c, 0x00000000,
701 0x020e059c, 0x00000030,
702 0x020e05a0, 0x00000030,
703 0x020e078c, 0x00000030,
704 0x020e0750, 0x00020000,
705 0x020e05a8, 0x00000028,
706 0x020e05b0, 0x00000028,
707 0x020e0524, 0x00000028,
708 0x020e051c, 0x00000028,
709 0x020e0518, 0x00000028,
710 0x020e050c, 0x00000028,
711 0x020e05b8, 0x00000028,
712 0x020e05c0, 0x00000028,
713 0x020e0774, 0x00020000,
714 0x020e0784, 0x00000028,
715 0x020e0788, 0x00000028,
716 0x020e0794, 0x00000028,
717 0x020e079c, 0x00000028,
718 0x020e07a0, 0x00000028,
719 0x020e07a4, 0x00000028,
720 0x020e07a8, 0x00000028,
721 0x020e0748, 0x00000028,
722 0x020e05ac, 0x00000028,
723 0x020e05b4, 0x00000028,
724 0x020e0528, 0x00000028,
725 0x020e0520, 0x00000028,
726 0x020e0514, 0x00000028,
727 0x020e0510, 0x00000028,
728 0x020e05bc, 0x00000028,
729 0x020e05c4, 0x00000028,
730 0x021b0800, 0xa1390003,
731 0x021b080c, 0x001F001F,
732 0x021b0810, 0x001F001F,
733 0x021b480c, 0x001F001F,
734 0x021b4810, 0x001F001F,
735 0x021b083c, 0x43260335,
736 0x021b0840, 0x031A030B,
737 0x021b483c, 0x4323033B,
738 0x021b4840, 0x0323026F,
739 0x021b0848, 0x483D4545,
740 0x021b4848, 0x44433E48,
741 0x021b0850, 0x41444840,
742 0x021b4850, 0x4835483E,
743 0x021b081c, 0x33333333,
744 0x021b0820, 0x33333333,
745 0x021b0824, 0x33333333,
746 0x021b0828, 0x33333333,
747 0x021b481c, 0x33333333,
748 0x021b4820, 0x33333333,
749 0x021b4824, 0x33333333,
750 0x021b4828, 0x33333333,
751 0x021b08b8, 0x00000800,
752 0x021b48b8, 0x00000800,
753 0x021b0004, 0x00020036,
754 0x021b0008, 0x09444040,
755 0x021b000c, 0x8A8F7955,
756 0x021b0010, 0xFF328F64,
757 0x021b0014, 0x01FF00DB,
758 0x021b0018, 0x00001740,
759 0x021b001c, 0x00008000,
760 0x021b002c, 0x000026d2,
761 0x021b0030, 0x008F1023,
762 0x021b0040, 0x00000047,
763 0x021b0000, 0x841A0000,
764 0x021b001c, 0x04088032,
765 0x021b001c, 0x00008033,
766 0x021b001c, 0x00048031,
767 0x021b001c, 0x09408030,
768 0x021b001c, 0x04008040,
769 0x021b0020, 0x00005800,
770 0x021b0818, 0x00011117,
771 0x021b4818, 0x00011117,
772 0x021b0004, 0x00025576,
773 0x021b0404, 0x00011006,
774 0x021b001c, 0x00000000,
775 0x020c4068, 0x00C03F3F,
776 0x020c406c, 0x0030FC03,
777 0x020c4070, 0x0FFFC000,
778 0x020c4074, 0x3FF00000,
779 0x020c4078, 0xFFFFF300,
780 0x020c407c, 0x0F0000F3,
781 0x020c4080, 0x00000FFF,
782 0x020e0010, 0xF00000CF,
783 0x020e0018, 0x007F007F,
784 0x020e001c, 0x007F007F,
785 };
786
787 static int mx6qp_dcd_table[] = {
788 0x020e0798, 0x000C0000,
789 0x020e0758, 0x00000000,
790 0x020e0588, 0x00000030,
791 0x020e0594, 0x00000030,
792 0x020e056c, 0x00000030,
793 0x020e0578, 0x00000030,
794 0x020e074c, 0x00000030,
795 0x020e057c, 0x00000030,
796 0x020e058c, 0x00000000,
797 0x020e059c, 0x00000030,
798 0x020e05a0, 0x00000030,
799 0x020e078c, 0x00000030,
800 0x020e0750, 0x00020000,
801 0x020e05a8, 0x00000030,
802 0x020e05b0, 0x00000030,
803 0x020e0524, 0x00000030,
804 0x020e051c, 0x00000030,
805 0x020e0518, 0x00000030,
806 0x020e050c, 0x00000030,
807 0x020e05b8, 0x00000030,
808 0x020e05c0, 0x00000030,
809 0x020e0774, 0x00020000,
810 0x020e0784, 0x00000030,
811 0x020e0788, 0x00000030,
812 0x020e0794, 0x00000030,
813 0x020e079c, 0x00000030,
814 0x020e07a0, 0x00000030,
815 0x020e07a4, 0x00000030,
816 0x020e07a8, 0x00000030,
817 0x020e0748, 0x00000030,
818 0x020e05ac, 0x00000030,
819 0x020e05b4, 0x00000030,
820 0x020e0528, 0x00000030,
821 0x020e0520, 0x00000030,
822 0x020e0514, 0x00000030,
823 0x020e0510, 0x00000030,
824 0x020e05bc, 0x00000030,
825 0x020e05c4, 0x00000030,
826 0x021b0800, 0xa1390003,
827 0x021b080c, 0x001b001e,
828 0x021b0810, 0x002e0029,
829 0x021b480c, 0x001b002a,
830 0x021b4810, 0x0019002c,
831 0x021b083c, 0x43240334,
832 0x021b0840, 0x0324031a,
833 0x021b483c, 0x43340344,
834 0x021b4840, 0x03280276,
835 0x021b0848, 0x44383A3E,
836 0x021b4848, 0x3C3C3846,
837 0x021b0850, 0x2e303230,
838 0x021b4850, 0x38283E34,
839 0x021b081c, 0x33333333,
840 0x021b0820, 0x33333333,
841 0x021b0824, 0x33333333,
842 0x021b0828, 0x33333333,
843 0x021b481c, 0x33333333,
844 0x021b4820, 0x33333333,
845 0x021b4824, 0x33333333,
846 0x021b4828, 0x33333333,
847 0x021b08c0, 0x24912492,
848 0x021b48c0, 0x24912492,
849 0x021b08b8, 0x00000800,
850 0x021b48b8, 0x00000800,
851 0x021b0004, 0x00020036,
852 0x021b0008, 0x09444040,
853 0x021b000c, 0x898E7955,
854 0x021b0010, 0xFF328F64,
855 0x021b0014, 0x01FF00DB,
856 0x021b0018, 0x00001740,
857 0x021b001c, 0x00008000,
858 0x021b002c, 0x000026d2,
859 0x021b0030, 0x008E1023,
860 0x021b0040, 0x00000047,
861 0x021b0400, 0x14420000,
862 0x021b0000, 0x841A0000,
863 0x00bb0008, 0x00000004,
864 0x00bb000c, 0x2891E41A,
865 0x00bb0038, 0x00000564,
866 0x00bb0014, 0x00000040,
867 0x00bb0028, 0x00000020,
868 0x00bb002c, 0x00000020,
869 0x021b001c, 0x04088032,
870 0x021b001c, 0x00008033,
871 0x021b001c, 0x00048031,
872 0x021b001c, 0x09408030,
873 0x021b001c, 0x04008040,
874 0x021b0020, 0x00005800,
875 0x021b0818, 0x00011117,
876 0x021b4818, 0x00011117,
877 0x021b0004, 0x00025576,
878 0x021b0404, 0x00011006,
879 0x021b001c, 0x00000000,
880 0x020c4068, 0x00C03F3F,
881 0x020c406c, 0x0030FC03,
882 0x020c4070, 0x0FFFC000,
883 0x020c4074, 0x3FF00000,
884 0x020c4078, 0xFFFFF300,
885 0x020c407c, 0x0F0000F3,
886 0x020c4080, 0x00000FFF,
887 0x020e0010, 0xF00000CF,
888 0x020e0018, 0x77177717,
889 0x020e001c, 0x77177717,
890 };
891
892 static int mx6dl_dcd_table[] = {
893 0x020e0774, 0x000C0000,
894 0x020e0754, 0x00000000,
895 0x020e04ac, 0x00000030,
896 0x020e04b0, 0x00000030,
897 0x020e0464, 0x00000030,
898 0x020e0490, 0x00000030,
899 0x020e074c, 0x00000030,
900 0x020e0494, 0x00000030,
901 0x020e04a0, 0x00000000,
902 0x020e04b4, 0x00000030,
903 0x020e04b8, 0x00000030,
904 0x020e076c, 0x00000030,
905 0x020e0750, 0x00020000,
906 0x020e04bc, 0x00000028,
907 0x020e04c0, 0x00000028,
908 0x020e04c4, 0x00000028,
909 0x020e04c8, 0x00000028,
910 0x020e04cc, 0x00000028,
911 0x020e04d0, 0x00000028,
912 0x020e04d4, 0x00000028,
913 0x020e04d8, 0x00000028,
914 0x020e0760, 0x00020000,
915 0x020e0764, 0x00000028,
916 0x020e0770, 0x00000028,
917 0x020e0778, 0x00000028,
918 0x020e077c, 0x00000028,
919 0x020e0780, 0x00000028,
920 0x020e0784, 0x00000028,
921 0x020e078c, 0x00000028,
922 0x020e0748, 0x00000028,
923 0x020e0470, 0x00000028,
924 0x020e0474, 0x00000028,
925 0x020e0478, 0x00000028,
926 0x020e047c, 0x00000028,
927 0x020e0480, 0x00000028,
928 0x020e0484, 0x00000028,
929 0x020e0488, 0x00000028,
930 0x020e048c, 0x00000028,
931 0x021b0800, 0xa1390003,
932 0x021b080c, 0x001F001F,
933 0x021b0810, 0x001F001F,
934 0x021b480c, 0x001F001F,
935 0x021b4810, 0x001F001F,
936 0x021b083c, 0x42190217,
937 0x021b0840, 0x017B017B,
938 0x021b483c, 0x4176017B,
939 0x021b4840, 0x015F016C,
940 0x021b0848, 0x4C4C4D4C,
941 0x021b4848, 0x4A4D4C48,
942 0x021b0850, 0x3F3F3F40,
943 0x021b4850, 0x3538382E,
944 0x021b081c, 0x33333333,
945 0x021b0820, 0x33333333,
946 0x021b0824, 0x33333333,
947 0x021b0828, 0x33333333,
948 0x021b481c, 0x33333333,
949 0x021b4820, 0x33333333,
950 0x021b4824, 0x33333333,
951 0x021b4828, 0x33333333,
952 0x021b08b8, 0x00000800,
953 0x021b48b8, 0x00000800,
954 0x021b0004, 0x00020025,
955 0x021b0008, 0x00333030,
956 0x021b000c, 0x676B5313,
957 0x021b0010, 0xB66E8B63,
958 0x021b0014, 0x01FF00DB,
959 0x021b0018, 0x00001740,
960 0x021b001c, 0x00008000,
961 0x021b002c, 0x000026d2,
962 0x021b0030, 0x006B1023,
963 0x021b0040, 0x00000047,
964 0x021b0000, 0x841A0000,
965 0x021b001c, 0x04008032,
966 0x021b001c, 0x00008033,
967 0x021b001c, 0x00048031,
968 0x021b001c, 0x05208030,
969 0x021b001c, 0x04008040,
970 0x021b0020, 0x00005800,
971 0x021b0818, 0x00011117,
972 0x021b4818, 0x00011117,
973 0x021b0004, 0x00025565,
974 0x021b0404, 0x00011006,
975 0x021b001c, 0x00000000,
976 0x020c4068, 0x00C03F3F,
977 0x020c406c, 0x0030FC03,
978 0x020c4070, 0x0FFFC000,
979 0x020c4074, 0x3FF00000,
980 0x020c4078, 0xFFFFF300,
981 0x020c407c, 0x0F0000C3,
982 0x020c4080, 0x00000FFF,
983 0x020e0010, 0xF00000CF,
984 0x020e0018, 0x007F007F,
985 0x020e001c, 0x007F007F,
986 };
987
ddr_init(int * table,int size)988 static void ddr_init(int *table, int size)
989 {
990 int i;
991
992 for (i = 0; i < size / 2 ; i++)
993 writel(table[2 * i + 1], table[2 * i]);
994 }
995
spl_dram_init(void)996 static void spl_dram_init(void)
997 {
998 if (is_mx6dq())
999 ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
1000 else if (is_mx6dqp())
1001 ddr_init(mx6qp_dcd_table, ARRAY_SIZE(mx6qp_dcd_table));
1002 else if (is_mx6sdl())
1003 ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1004 }
1005
board_init_f(ulong dummy)1006 void board_init_f(ulong dummy)
1007 {
1008 /* DDR initialization */
1009 spl_dram_init();
1010
1011 /* setup AIPS and disable watchdog */
1012 arch_cpu_init();
1013
1014 ccgr_init();
1015 gpr_init();
1016
1017 /* iomux and setup of i2c */
1018 board_early_init_f();
1019
1020 /* setup GP timer */
1021 timer_init();
1022
1023 /* UART clocks enabled and gd valid - init serial console */
1024 preloader_console_init();
1025
1026 /* Clear the BSS. */
1027 memset(__bss_start, 0, __bss_end - __bss_start);
1028
1029 /* load/boot image from boot device */
1030 board_init_r(NULL, 0);
1031 }
1032 #endif
1033
1034 #ifdef CONFIG_SPL_LOAD_FIT
board_fit_config_name_match(const char * name)1035 int board_fit_config_name_match(const char *name)
1036 {
1037 if (is_mx6dq()) {
1038 if (!strcmp(name, "imx6q-sabreauto"))
1039 return 0;
1040 } else if (is_mx6dqp()) {
1041 if (!strcmp(name, "imx6qp-sabreauto"))
1042 return 0;
1043 } else if (is_mx6dl()) {
1044 if (!strcmp(name, "imx6dl-sabreauto"))
1045 return 0;
1046 }
1047
1048 return -1;
1049 }
1050 #endif
1051