1 /* 2 * Copyright (c) 2016 Hisilicon Limited. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _HNS_ROCE_DEVICE_H 34 #define _HNS_ROCE_DEVICE_H 35 36 #include <rdma/ib_verbs.h> 37 #include <rdma/hns-abi.h> 38 39 #define PCI_REVISION_ID_HIP08 0x21 40 #define PCI_REVISION_ID_HIP09 0x30 41 42 #define HNS_ROCE_MAX_MSG_LEN 0x80000000 43 44 #define HNS_ROCE_IB_MIN_SQ_STRIDE 6 45 46 #define BA_BYTE_LEN 8 47 48 #define HNS_ROCE_MIN_CQE_NUM 0x40 49 #define HNS_ROCE_MIN_SRQ_WQE_NUM 1 50 51 #define HNS_ROCE_MAX_IRQ_NUM 128 52 53 #define HNS_ROCE_SGE_IN_WQE 2 54 #define HNS_ROCE_SGE_SHIFT 4 55 56 #define EQ_ENABLE 1 57 #define EQ_DISABLE 0 58 59 #define HNS_ROCE_CEQ 0 60 #define HNS_ROCE_AEQ 1 61 62 #define HNS_ROCE_CEQE_SIZE 0x4 63 #define HNS_ROCE_AEQE_SIZE 0x10 64 65 #define HNS_ROCE_V3_EQE_SIZE 0x40 66 67 #define HNS_ROCE_V2_CQE_SIZE 32 68 #define HNS_ROCE_V3_CQE_SIZE 64 69 70 #define HNS_ROCE_V2_QPC_SZ 256 71 #define HNS_ROCE_V3_QPC_SZ 512 72 73 #define HNS_ROCE_MAX_PORTS 6 74 #define HNS_ROCE_GID_SIZE 16 75 #define HNS_ROCE_SGE_SIZE 16 76 #define HNS_ROCE_DWQE_SIZE 65536 77 78 #define HNS_ROCE_HOP_NUM_0 0xff 79 80 #define MR_TYPE_MR 0x00 81 #define MR_TYPE_FRMR 0x01 82 #define MR_TYPE_DMA 0x03 83 84 #define HNS_ROCE_FRMR_MAX_PA 512 85 #define HNS_ROCE_FRMR_ALIGN_SIZE 128 86 87 #define PKEY_ID 0xffff 88 #define NODE_DESC_SIZE 64 89 #define DB_REG_OFFSET 0x1000 90 91 /* Configure to HW for PAGE_SIZE larger than 4KB */ 92 #define PG_SHIFT_OFFSET (PAGE_SHIFT - 12) 93 94 #define ATOMIC_WR_LEN 8 95 96 #define HNS_ROCE_IDX_QUE_ENTRY_SZ 4 97 #define SRQ_DB_REG 0x230 98 99 #define HNS_ROCE_QP_BANK_NUM 8 100 #define HNS_ROCE_CQ_BANK_NUM 4 101 102 #define CQ_BANKID_SHIFT 2 103 #define CQ_BANKID_MASK GENMASK(1, 0) 104 105 enum { 106 SERV_TYPE_RC, 107 SERV_TYPE_UC, 108 SERV_TYPE_RD, 109 SERV_TYPE_UD, 110 SERV_TYPE_XRC = 5, 111 }; 112 113 enum hns_roce_event { 114 HNS_ROCE_EVENT_TYPE_PATH_MIG = 0x01, 115 HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED = 0x02, 116 HNS_ROCE_EVENT_TYPE_COMM_EST = 0x03, 117 HNS_ROCE_EVENT_TYPE_SQ_DRAINED = 0x04, 118 HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 119 HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR = 0x06, 120 HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR = 0x07, 121 HNS_ROCE_EVENT_TYPE_SRQ_LIMIT_REACH = 0x08, 122 HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH = 0x09, 123 HNS_ROCE_EVENT_TYPE_SRQ_CATAS_ERROR = 0x0a, 124 HNS_ROCE_EVENT_TYPE_CQ_ACCESS_ERROR = 0x0b, 125 HNS_ROCE_EVENT_TYPE_CQ_OVERFLOW = 0x0c, 126 HNS_ROCE_EVENT_TYPE_CQ_ID_INVALID = 0x0d, 127 HNS_ROCE_EVENT_TYPE_PORT_CHANGE = 0x0f, 128 /* 0x10 and 0x11 is unused in currently application case */ 129 HNS_ROCE_EVENT_TYPE_DB_OVERFLOW = 0x12, 130 HNS_ROCE_EVENT_TYPE_MB = 0x13, 131 HNS_ROCE_EVENT_TYPE_FLR = 0x15, 132 HNS_ROCE_EVENT_TYPE_XRCD_VIOLATION = 0x16, 133 HNS_ROCE_EVENT_TYPE_INVALID_XRCETH = 0x17, 134 }; 135 136 enum { 137 HNS_ROCE_CAP_FLAG_REREG_MR = BIT(0), 138 HNS_ROCE_CAP_FLAG_ROCE_V1_V2 = BIT(1), 139 HNS_ROCE_CAP_FLAG_RQ_INLINE = BIT(2), 140 HNS_ROCE_CAP_FLAG_CQ_RECORD_DB = BIT(3), 141 HNS_ROCE_CAP_FLAG_QP_RECORD_DB = BIT(4), 142 HNS_ROCE_CAP_FLAG_SRQ = BIT(5), 143 HNS_ROCE_CAP_FLAG_XRC = BIT(6), 144 HNS_ROCE_CAP_FLAG_MW = BIT(7), 145 HNS_ROCE_CAP_FLAG_FRMR = BIT(8), 146 HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL = BIT(9), 147 HNS_ROCE_CAP_FLAG_ATOMIC = BIT(10), 148 HNS_ROCE_CAP_FLAG_DIRECT_WQE = BIT(12), 149 HNS_ROCE_CAP_FLAG_SDI_MODE = BIT(14), 150 HNS_ROCE_CAP_FLAG_STASH = BIT(17), 151 HNS_ROCE_CAP_FLAG_CQE_INLINE = BIT(19), 152 }; 153 154 #define HNS_ROCE_DB_TYPE_COUNT 2 155 #define HNS_ROCE_DB_UNIT_SIZE 4 156 157 enum { 158 HNS_ROCE_DB_PER_PAGE = PAGE_SIZE / 4 159 }; 160 161 enum hns_roce_reset_stage { 162 HNS_ROCE_STATE_NON_RST, 163 HNS_ROCE_STATE_RST_BEF_DOWN, 164 HNS_ROCE_STATE_RST_DOWN, 165 HNS_ROCE_STATE_RST_UNINIT, 166 HNS_ROCE_STATE_RST_INIT, 167 HNS_ROCE_STATE_RST_INITED, 168 }; 169 170 enum hns_roce_instance_state { 171 HNS_ROCE_STATE_NON_INIT, 172 HNS_ROCE_STATE_INIT, 173 HNS_ROCE_STATE_INITED, 174 HNS_ROCE_STATE_UNINIT, 175 }; 176 177 enum { 178 HNS_ROCE_RST_DIRECT_RETURN = 0, 179 }; 180 181 #define HNS_ROCE_CMD_SUCCESS 1 182 183 /* The minimum page size is 4K for hardware */ 184 #define HNS_HW_PAGE_SHIFT 12 185 #define HNS_HW_PAGE_SIZE (1 << HNS_HW_PAGE_SHIFT) 186 187 #define HNS_HW_MAX_PAGE_SHIFT 27 188 #define HNS_HW_MAX_PAGE_SIZE (1 << HNS_HW_MAX_PAGE_SHIFT) 189 190 struct hns_roce_uar { 191 u64 pfn; 192 unsigned long index; 193 unsigned long logic_idx; 194 }; 195 196 enum hns_roce_mmap_type { 197 HNS_ROCE_MMAP_TYPE_DB = 1, 198 HNS_ROCE_MMAP_TYPE_DWQE, 199 }; 200 201 struct hns_user_mmap_entry { 202 struct rdma_user_mmap_entry rdma_entry; 203 enum hns_roce_mmap_type mmap_type; 204 u64 address; 205 }; 206 207 struct hns_roce_ucontext { 208 struct ib_ucontext ibucontext; 209 struct hns_roce_uar uar; 210 struct list_head page_list; 211 struct mutex page_mutex; 212 struct hns_user_mmap_entry *db_mmap_entry; 213 u32 config; 214 }; 215 216 struct hns_roce_pd { 217 struct ib_pd ibpd; 218 unsigned long pdn; 219 }; 220 221 struct hns_roce_xrcd { 222 struct ib_xrcd ibxrcd; 223 u32 xrcdn; 224 }; 225 226 struct hns_roce_bitmap { 227 /* Bitmap Traversal last a bit which is 1 */ 228 unsigned long last; 229 unsigned long top; 230 unsigned long max; 231 unsigned long reserved_top; 232 unsigned long mask; 233 spinlock_t lock; 234 unsigned long *table; 235 }; 236 237 struct hns_roce_ida { 238 struct ida ida; 239 u32 min; /* Lowest ID to allocate. */ 240 u32 max; /* Highest ID to allocate. */ 241 }; 242 243 /* For Hardware Entry Memory */ 244 struct hns_roce_hem_table { 245 /* HEM type: 0 = qpc, 1 = mtt, 2 = cqc, 3 = srq, 4 = other */ 246 u32 type; 247 /* HEM array elment num */ 248 unsigned long num_hem; 249 /* Single obj size */ 250 unsigned long obj_size; 251 unsigned long table_chunk_size; 252 struct mutex mutex; 253 struct hns_roce_hem **hem; 254 u64 **bt_l1; 255 dma_addr_t *bt_l1_dma_addr; 256 u64 **bt_l0; 257 dma_addr_t *bt_l0_dma_addr; 258 }; 259 260 struct hns_roce_buf_region { 261 u32 offset; /* page offset */ 262 u32 count; /* page count */ 263 int hopnum; /* addressing hop num */ 264 }; 265 266 #define HNS_ROCE_MAX_BT_REGION 3 267 #define HNS_ROCE_MAX_BT_LEVEL 3 268 struct hns_roce_hem_list { 269 struct list_head root_bt; 270 /* link all bt dma mem by hop config */ 271 struct list_head mid_bt[HNS_ROCE_MAX_BT_REGION][HNS_ROCE_MAX_BT_LEVEL]; 272 struct list_head btm_bt; /* link all bottom bt in @mid_bt */ 273 dma_addr_t root_ba; /* pointer to the root ba table */ 274 }; 275 276 struct hns_roce_buf_attr { 277 struct { 278 size_t size; /* region size */ 279 int hopnum; /* multi-hop addressing hop num */ 280 } region[HNS_ROCE_MAX_BT_REGION]; 281 unsigned int region_count; /* valid region count */ 282 unsigned int page_shift; /* buffer page shift */ 283 unsigned int user_access; /* umem access flag */ 284 bool mtt_only; /* only alloc buffer-required MTT memory */ 285 }; 286 287 struct hns_roce_hem_cfg { 288 dma_addr_t root_ba; /* root BA table's address */ 289 bool is_direct; /* addressing without BA table */ 290 unsigned int ba_pg_shift; /* BA table page shift */ 291 unsigned int buf_pg_shift; /* buffer page shift */ 292 unsigned int buf_pg_count; /* buffer page count */ 293 struct hns_roce_buf_region region[HNS_ROCE_MAX_BT_REGION]; 294 unsigned int region_count; 295 }; 296 297 /* memory translate region */ 298 struct hns_roce_mtr { 299 struct hns_roce_hem_list hem_list; /* multi-hop addressing resource */ 300 struct ib_umem *umem; /* user space buffer */ 301 struct hns_roce_buf *kmem; /* kernel space buffer */ 302 struct hns_roce_hem_cfg hem_cfg; /* config for hardware addressing */ 303 }; 304 305 struct hns_roce_mw { 306 struct ib_mw ibmw; 307 u32 pdn; 308 u32 rkey; 309 int enabled; /* MW's active status */ 310 u32 pbl_hop_num; 311 u32 pbl_ba_pg_sz; 312 u32 pbl_buf_pg_sz; 313 }; 314 315 struct hns_roce_mr { 316 struct ib_mr ibmr; 317 u64 iova; /* MR's virtual original addr */ 318 u64 size; /* Address range of MR */ 319 u32 key; /* Key of MR */ 320 u32 pd; /* PD num of MR */ 321 u32 access; /* Access permission of MR */ 322 int enabled; /* MR's active status */ 323 int type; /* MR's register type */ 324 u32 pbl_hop_num; /* multi-hop number */ 325 struct hns_roce_mtr pbl_mtr; 326 u32 npages; 327 dma_addr_t *page_list; 328 }; 329 330 struct hns_roce_mr_table { 331 struct hns_roce_ida mtpt_ida; 332 struct hns_roce_hem_table mtpt_table; 333 }; 334 335 struct hns_roce_wq { 336 u64 *wrid; /* Work request ID */ 337 spinlock_t lock; 338 u32 wqe_cnt; /* WQE num */ 339 u32 max_gs; 340 u32 rsv_sge; 341 u32 offset; 342 u32 wqe_shift; /* WQE size */ 343 u32 head; 344 u32 tail; 345 void __iomem *db_reg; 346 u32 ext_sge_cnt; 347 }; 348 349 struct hns_roce_sge { 350 unsigned int sge_cnt; /* SGE num */ 351 u32 offset; 352 u32 sge_shift; /* SGE size */ 353 }; 354 355 struct hns_roce_buf_list { 356 void *buf; 357 dma_addr_t map; 358 }; 359 360 /* 361 * %HNS_ROCE_BUF_DIRECT indicates that the all memory must be in a continuous 362 * dma address range. 363 * 364 * %HNS_ROCE_BUF_NOSLEEP indicates that the caller cannot sleep. 365 * 366 * %HNS_ROCE_BUF_NOFAIL allocation only failed when allocated size is zero, even 367 * the allocated size is smaller than the required size. 368 */ 369 enum { 370 HNS_ROCE_BUF_DIRECT = BIT(0), 371 HNS_ROCE_BUF_NOSLEEP = BIT(1), 372 HNS_ROCE_BUF_NOFAIL = BIT(2), 373 }; 374 375 struct hns_roce_buf { 376 struct hns_roce_buf_list *trunk_list; 377 u32 ntrunks; 378 u32 npages; 379 unsigned int trunk_shift; 380 unsigned int page_shift; 381 }; 382 383 struct hns_roce_db_pgdir { 384 struct list_head list; 385 DECLARE_BITMAP(order0, HNS_ROCE_DB_PER_PAGE); 386 DECLARE_BITMAP(order1, HNS_ROCE_DB_PER_PAGE / HNS_ROCE_DB_TYPE_COUNT); 387 unsigned long *bits[HNS_ROCE_DB_TYPE_COUNT]; 388 u32 *page; 389 dma_addr_t db_dma; 390 }; 391 392 struct hns_roce_user_db_page { 393 struct list_head list; 394 struct ib_umem *umem; 395 unsigned long user_virt; 396 refcount_t refcount; 397 }; 398 399 struct hns_roce_db { 400 u32 *db_record; 401 union { 402 struct hns_roce_db_pgdir *pgdir; 403 struct hns_roce_user_db_page *user_page; 404 } u; 405 dma_addr_t dma; 406 void *virt_addr; 407 unsigned long index; 408 unsigned long order; 409 }; 410 411 struct hns_roce_cq { 412 struct ib_cq ib_cq; 413 struct hns_roce_mtr mtr; 414 struct hns_roce_db db; 415 u32 flags; 416 spinlock_t lock; 417 u32 cq_depth; 418 u32 cons_index; 419 u32 *set_ci_db; 420 void __iomem *db_reg; 421 int arm_sn; 422 int cqe_size; 423 unsigned long cqn; 424 u32 vector; 425 refcount_t refcount; 426 struct completion free; 427 struct list_head sq_list; /* all qps on this send cq */ 428 struct list_head rq_list; /* all qps on this recv cq */ 429 int is_armed; /* cq is armed */ 430 struct list_head node; /* all armed cqs are on a list */ 431 }; 432 433 struct hns_roce_idx_que { 434 struct hns_roce_mtr mtr; 435 u32 entry_shift; 436 unsigned long *bitmap; 437 u32 head; 438 u32 tail; 439 }; 440 441 struct hns_roce_srq { 442 struct ib_srq ibsrq; 443 unsigned long srqn; 444 u32 wqe_cnt; 445 int max_gs; 446 u32 rsv_sge; 447 u32 wqe_shift; 448 u32 cqn; 449 u32 xrcdn; 450 void __iomem *db_reg; 451 452 refcount_t refcount; 453 struct completion free; 454 455 struct hns_roce_mtr buf_mtr; 456 457 u64 *wrid; 458 struct hns_roce_idx_que idx_que; 459 spinlock_t lock; 460 struct mutex mutex; 461 void (*event)(struct hns_roce_srq *srq, enum hns_roce_event event); 462 }; 463 464 struct hns_roce_uar_table { 465 struct hns_roce_bitmap bitmap; 466 }; 467 468 struct hns_roce_bank { 469 struct ida ida; 470 u32 inuse; /* Number of IDs allocated */ 471 u32 min; /* Lowest ID to allocate. */ 472 u32 max; /* Highest ID to allocate. */ 473 u32 next; /* Next ID to allocate. */ 474 }; 475 476 struct hns_roce_idx_table { 477 u32 *spare_idx; 478 u32 head; 479 u32 tail; 480 }; 481 482 struct hns_roce_qp_table { 483 struct hns_roce_hem_table qp_table; 484 struct hns_roce_hem_table irrl_table; 485 struct hns_roce_hem_table trrl_table; 486 struct hns_roce_hem_table sccc_table; 487 struct mutex scc_mutex; 488 struct hns_roce_bank bank[HNS_ROCE_QP_BANK_NUM]; 489 struct mutex bank_mutex; 490 struct hns_roce_idx_table idx_table; 491 }; 492 493 struct hns_roce_cq_table { 494 struct xarray array; 495 struct hns_roce_hem_table table; 496 struct hns_roce_bank bank[HNS_ROCE_CQ_BANK_NUM]; 497 struct mutex bank_mutex; 498 }; 499 500 struct hns_roce_srq_table { 501 struct hns_roce_ida srq_ida; 502 struct xarray xa; 503 struct hns_roce_hem_table table; 504 }; 505 506 struct hns_roce_av { 507 u8 port; 508 u8 gid_index; 509 u8 stat_rate; 510 u8 hop_limit; 511 u32 flowlabel; 512 u16 udp_sport; 513 u8 sl; 514 u8 tclass; 515 u8 dgid[HNS_ROCE_GID_SIZE]; 516 u8 mac[ETH_ALEN]; 517 u16 vlan_id; 518 u8 vlan_en; 519 }; 520 521 struct hns_roce_ah { 522 struct ib_ah ibah; 523 struct hns_roce_av av; 524 }; 525 526 struct hns_roce_cmd_context { 527 struct completion done; 528 int result; 529 int next; 530 u64 out_param; 531 u16 token; 532 u16 busy; 533 }; 534 535 enum hns_roce_cmdq_state { 536 HNS_ROCE_CMDQ_STATE_NORMAL, 537 HNS_ROCE_CMDQ_STATE_FATAL_ERR, 538 }; 539 540 struct hns_roce_cmdq { 541 struct dma_pool *pool; 542 struct semaphore poll_sem; 543 /* 544 * Event mode: cmd register mutex protection, 545 * ensure to not exceed max_cmds and user use limit region 546 */ 547 struct semaphore event_sem; 548 int max_cmds; 549 spinlock_t context_lock; 550 int free_head; 551 struct hns_roce_cmd_context *context; 552 /* 553 * Process whether use event mode, init default non-zero 554 * After the event queue of cmd event ready, 555 * can switch into event mode 556 * close device, switch into poll mode(non event mode) 557 */ 558 u8 use_events; 559 enum hns_roce_cmdq_state state; 560 }; 561 562 struct hns_roce_cmd_mailbox { 563 void *buf; 564 dma_addr_t dma; 565 }; 566 567 struct hns_roce_mbox_msg { 568 u64 in_param; 569 u64 out_param; 570 u8 cmd; 571 u32 tag; 572 u16 token; 573 u8 event_en; 574 }; 575 576 struct hns_roce_dev; 577 578 enum { 579 HNS_ROCE_FLUSH_FLAG = 0, 580 }; 581 582 struct hns_roce_work { 583 struct hns_roce_dev *hr_dev; 584 struct work_struct work; 585 int event_type; 586 int sub_type; 587 u32 queue_num; 588 }; 589 590 enum hns_roce_cong_type { 591 CONG_TYPE_DCQCN, 592 CONG_TYPE_LDCP, 593 CONG_TYPE_HC3, 594 CONG_TYPE_DIP, 595 }; 596 597 struct hns_roce_qp { 598 struct ib_qp ibqp; 599 struct hns_roce_wq rq; 600 struct hns_roce_db rdb; 601 struct hns_roce_db sdb; 602 unsigned long en_flags; 603 enum ib_sig_type sq_signal_bits; 604 struct hns_roce_wq sq; 605 606 struct hns_roce_mtr mtr; 607 608 u32 buff_size; 609 struct mutex mutex; 610 u8 port; 611 u8 phy_port; 612 u8 sl; 613 u8 resp_depth; 614 u8 state; 615 u32 atomic_rd_en; 616 u32 qkey; 617 void (*event)(struct hns_roce_qp *qp, 618 enum hns_roce_event event_type); 619 unsigned long qpn; 620 621 u32 xrcdn; 622 623 refcount_t refcount; 624 struct completion free; 625 626 struct hns_roce_sge sge; 627 u32 next_sge; 628 enum ib_mtu path_mtu; 629 u32 max_inline_data; 630 u8 free_mr_en; 631 632 /* 0: flush needed, 1: unneeded */ 633 unsigned long flush_flag; 634 struct hns_roce_work flush_work; 635 struct list_head node; /* all qps are on a list */ 636 struct list_head rq_node; /* all recv qps are on a list */ 637 struct list_head sq_node; /* all send qps are on a list */ 638 struct hns_user_mmap_entry *dwqe_mmap_entry; 639 u32 config; 640 enum hns_roce_cong_type cong_type; 641 }; 642 643 struct hns_roce_ib_iboe { 644 spinlock_t lock; 645 struct net_device *netdevs[HNS_ROCE_MAX_PORTS]; 646 struct notifier_block nb; 647 u8 phy_port[HNS_ROCE_MAX_PORTS]; 648 }; 649 650 struct hns_roce_ceqe { 651 __le32 comp; 652 __le32 rsv[15]; 653 }; 654 655 #define CEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_ceqe, h, l) 656 657 #define CEQE_CQN CEQE_FIELD_LOC(23, 0) 658 #define CEQE_OWNER CEQE_FIELD_LOC(31, 31) 659 660 struct hns_roce_aeqe { 661 __le32 asyn; 662 union { 663 struct { 664 __le32 num; 665 u32 rsv0; 666 u32 rsv1; 667 } queue_event; 668 669 struct { 670 __le64 out_param; 671 __le16 token; 672 u8 status; 673 u8 rsv0; 674 } __packed cmd; 675 } event; 676 __le32 rsv[12]; 677 }; 678 679 #define AEQE_FIELD_LOC(h, l) FIELD_LOC(struct hns_roce_aeqe, h, l) 680 681 #define AEQE_EVENT_TYPE AEQE_FIELD_LOC(7, 0) 682 #define AEQE_SUB_TYPE AEQE_FIELD_LOC(15, 8) 683 #define AEQE_OWNER AEQE_FIELD_LOC(31, 31) 684 #define AEQE_EVENT_QUEUE_NUM AEQE_FIELD_LOC(55, 32) 685 686 struct hns_roce_eq { 687 struct hns_roce_dev *hr_dev; 688 void __iomem *db_reg; 689 690 int type_flag; /* Aeq:1 ceq:0 */ 691 int eqn; 692 u32 entries; 693 int eqe_size; 694 int irq; 695 u32 cons_index; 696 int over_ignore; 697 int coalesce; 698 int arm_st; 699 int hop_num; 700 struct hns_roce_mtr mtr; 701 u16 eq_max_cnt; 702 u32 eq_period; 703 int shift; 704 int event_type; 705 int sub_type; 706 }; 707 708 struct hns_roce_eq_table { 709 struct hns_roce_eq *eq; 710 }; 711 712 struct hns_roce_caps { 713 u64 fw_ver; 714 u8 num_ports; 715 int gid_table_len[HNS_ROCE_MAX_PORTS]; 716 int pkey_table_len[HNS_ROCE_MAX_PORTS]; 717 int local_ca_ack_delay; 718 int num_uars; 719 u32 phy_num_uars; 720 u32 max_sq_sg; 721 u32 max_sq_inline; 722 u32 max_rq_sg; 723 u32 rsv0; 724 u32 num_qps; 725 u32 reserved_qps; 726 u32 num_srqs; 727 u32 max_wqes; 728 u32 max_srq_wrs; 729 u32 max_srq_sges; 730 u32 max_sq_desc_sz; 731 u32 max_rq_desc_sz; 732 u32 rsv2; 733 int max_qp_init_rdma; 734 int max_qp_dest_rdma; 735 u32 num_cqs; 736 u32 max_cqes; 737 u32 min_cqes; 738 u32 min_wqes; 739 u32 reserved_cqs; 740 u32 reserved_srqs; 741 int num_aeq_vectors; 742 int num_comp_vectors; 743 int num_other_vectors; 744 u32 num_mtpts; 745 u32 rsv1; 746 u32 num_srqwqe_segs; 747 u32 num_idx_segs; 748 int reserved_mrws; 749 int reserved_uars; 750 int num_pds; 751 int reserved_pds; 752 u32 num_xrcds; 753 u32 reserved_xrcds; 754 u32 mtt_entry_sz; 755 u32 cqe_sz; 756 u32 page_size_cap; 757 u32 reserved_lkey; 758 int mtpt_entry_sz; 759 int qpc_sz; 760 int irrl_entry_sz; 761 int trrl_entry_sz; 762 int cqc_entry_sz; 763 int sccc_sz; 764 int qpc_timer_entry_sz; 765 int cqc_timer_entry_sz; 766 int srqc_entry_sz; 767 int idx_entry_sz; 768 u32 pbl_ba_pg_sz; 769 u32 pbl_buf_pg_sz; 770 u32 pbl_hop_num; 771 int aeqe_depth; 772 int ceqe_depth; 773 u32 aeqe_size; 774 u32 ceqe_size; 775 enum ib_mtu max_mtu; 776 u32 qpc_bt_num; 777 u32 qpc_timer_bt_num; 778 u32 srqc_bt_num; 779 u32 cqc_bt_num; 780 u32 cqc_timer_bt_num; 781 u32 mpt_bt_num; 782 u32 eqc_bt_num; 783 u32 smac_bt_num; 784 u32 sgid_bt_num; 785 u32 sccc_bt_num; 786 u32 gmv_bt_num; 787 u32 qpc_ba_pg_sz; 788 u32 qpc_buf_pg_sz; 789 u32 qpc_hop_num; 790 u32 srqc_ba_pg_sz; 791 u32 srqc_buf_pg_sz; 792 u32 srqc_hop_num; 793 u32 cqc_ba_pg_sz; 794 u32 cqc_buf_pg_sz; 795 u32 cqc_hop_num; 796 u32 mpt_ba_pg_sz; 797 u32 mpt_buf_pg_sz; 798 u32 mpt_hop_num; 799 u32 mtt_ba_pg_sz; 800 u32 mtt_buf_pg_sz; 801 u32 mtt_hop_num; 802 u32 wqe_sq_hop_num; 803 u32 wqe_sge_hop_num; 804 u32 wqe_rq_hop_num; 805 u32 sccc_ba_pg_sz; 806 u32 sccc_buf_pg_sz; 807 u32 sccc_hop_num; 808 u32 qpc_timer_ba_pg_sz; 809 u32 qpc_timer_buf_pg_sz; 810 u32 qpc_timer_hop_num; 811 u32 cqc_timer_ba_pg_sz; 812 u32 cqc_timer_buf_pg_sz; 813 u32 cqc_timer_hop_num; 814 u32 cqe_ba_pg_sz; /* page_size = 4K*(2^cqe_ba_pg_sz) */ 815 u32 cqe_buf_pg_sz; 816 u32 cqe_hop_num; 817 u32 srqwqe_ba_pg_sz; 818 u32 srqwqe_buf_pg_sz; 819 u32 srqwqe_hop_num; 820 u32 idx_ba_pg_sz; 821 u32 idx_buf_pg_sz; 822 u32 idx_hop_num; 823 u32 eqe_ba_pg_sz; 824 u32 eqe_buf_pg_sz; 825 u32 eqe_hop_num; 826 u32 gmv_entry_num; 827 u32 gmv_entry_sz; 828 u32 gmv_ba_pg_sz; 829 u32 gmv_buf_pg_sz; 830 u32 gmv_hop_num; 831 u32 sl_num; 832 u32 llm_buf_pg_sz; 833 u32 chunk_sz; /* chunk size in non multihop mode */ 834 u64 flags; 835 u16 default_ceq_max_cnt; 836 u16 default_ceq_period; 837 u16 default_aeq_max_cnt; 838 u16 default_aeq_period; 839 u16 default_aeq_arm_st; 840 u16 default_ceq_arm_st; 841 enum hns_roce_cong_type cong_type; 842 }; 843 844 enum hns_roce_device_state { 845 HNS_ROCE_DEVICE_STATE_INITED, 846 HNS_ROCE_DEVICE_STATE_RST_DOWN, 847 HNS_ROCE_DEVICE_STATE_UNINIT, 848 }; 849 850 enum hns_roce_hw_pkt_stat_index { 851 HNS_ROCE_HW_RX_RC_PKT_CNT, 852 HNS_ROCE_HW_RX_UC_PKT_CNT, 853 HNS_ROCE_HW_RX_UD_PKT_CNT, 854 HNS_ROCE_HW_RX_XRC_PKT_CNT, 855 HNS_ROCE_HW_RX_PKT_CNT, 856 HNS_ROCE_HW_RX_ERR_PKT_CNT, 857 HNS_ROCE_HW_RX_CNP_PKT_CNT, 858 HNS_ROCE_HW_TX_RC_PKT_CNT, 859 HNS_ROCE_HW_TX_UC_PKT_CNT, 860 HNS_ROCE_HW_TX_UD_PKT_CNT, 861 HNS_ROCE_HW_TX_XRC_PKT_CNT, 862 HNS_ROCE_HW_TX_PKT_CNT, 863 HNS_ROCE_HW_TX_ERR_PKT_CNT, 864 HNS_ROCE_HW_TX_CNP_PKT_CNT, 865 HNS_ROCE_HW_TRP_GET_MPT_ERR_PKT_CNT, 866 HNS_ROCE_HW_TRP_GET_IRRL_ERR_PKT_CNT, 867 HNS_ROCE_HW_ECN_DB_CNT, 868 HNS_ROCE_HW_RX_BUF_CNT, 869 HNS_ROCE_HW_TRP_RX_SOF_CNT, 870 HNS_ROCE_HW_CQ_CQE_CNT, 871 HNS_ROCE_HW_CQ_POE_CNT, 872 HNS_ROCE_HW_CQ_NOTIFY_CNT, 873 HNS_ROCE_HW_CNT_TOTAL 874 }; 875 876 struct hns_roce_hw { 877 int (*cmq_init)(struct hns_roce_dev *hr_dev); 878 void (*cmq_exit)(struct hns_roce_dev *hr_dev); 879 int (*hw_profile)(struct hns_roce_dev *hr_dev); 880 int (*hw_init)(struct hns_roce_dev *hr_dev); 881 void (*hw_exit)(struct hns_roce_dev *hr_dev); 882 int (*post_mbox)(struct hns_roce_dev *hr_dev, 883 struct hns_roce_mbox_msg *mbox_msg); 884 int (*poll_mbox_done)(struct hns_roce_dev *hr_dev); 885 bool (*chk_mbox_avail)(struct hns_roce_dev *hr_dev, bool *is_busy); 886 int (*set_gid)(struct hns_roce_dev *hr_dev, int gid_index, 887 const union ib_gid *gid, const struct ib_gid_attr *attr); 888 int (*set_mac)(struct hns_roce_dev *hr_dev, u8 phy_port, 889 const u8 *addr); 890 int (*write_mtpt)(struct hns_roce_dev *hr_dev, void *mb_buf, 891 struct hns_roce_mr *mr); 892 int (*rereg_write_mtpt)(struct hns_roce_dev *hr_dev, 893 struct hns_roce_mr *mr, int flags, 894 void *mb_buf); 895 int (*frmr_write_mtpt)(void *mb_buf, struct hns_roce_mr *mr); 896 int (*mw_write_mtpt)(void *mb_buf, struct hns_roce_mw *mw); 897 void (*write_cqc)(struct hns_roce_dev *hr_dev, 898 struct hns_roce_cq *hr_cq, void *mb_buf, u64 *mtts, 899 dma_addr_t dma_handle); 900 int (*set_hem)(struct hns_roce_dev *hr_dev, 901 struct hns_roce_hem_table *table, int obj, u32 step_idx); 902 int (*clear_hem)(struct hns_roce_dev *hr_dev, 903 struct hns_roce_hem_table *table, int obj, 904 u32 step_idx); 905 int (*modify_qp)(struct ib_qp *ibqp, const struct ib_qp_attr *attr, 906 int attr_mask, enum ib_qp_state cur_state, 907 enum ib_qp_state new_state, struct ib_udata *udata); 908 int (*qp_flow_control_init)(struct hns_roce_dev *hr_dev, 909 struct hns_roce_qp *hr_qp); 910 void (*dereg_mr)(struct hns_roce_dev *hr_dev); 911 int (*init_eq)(struct hns_roce_dev *hr_dev); 912 void (*cleanup_eq)(struct hns_roce_dev *hr_dev); 913 int (*write_srqc)(struct hns_roce_srq *srq, void *mb_buf); 914 int (*query_cqc)(struct hns_roce_dev *hr_dev, u32 cqn, void *buffer); 915 int (*query_qpc)(struct hns_roce_dev *hr_dev, u32 qpn, void *buffer); 916 int (*query_mpt)(struct hns_roce_dev *hr_dev, u32 key, void *buffer); 917 int (*query_hw_counter)(struct hns_roce_dev *hr_dev, 918 u64 *stats, u32 port, int *hw_counters); 919 const struct ib_device_ops *hns_roce_dev_ops; 920 const struct ib_device_ops *hns_roce_dev_srq_ops; 921 }; 922 923 struct hns_roce_dev { 924 struct ib_device ib_dev; 925 struct pci_dev *pci_dev; 926 struct device *dev; 927 struct hns_roce_uar priv_uar; 928 const char *irq_names[HNS_ROCE_MAX_IRQ_NUM]; 929 spinlock_t sm_lock; 930 bool active; 931 bool is_reset; 932 bool dis_db; 933 unsigned long reset_cnt; 934 struct hns_roce_ib_iboe iboe; 935 enum hns_roce_device_state state; 936 struct list_head qp_list; /* list of all qps on this dev */ 937 spinlock_t qp_list_lock; /* protect qp_list */ 938 struct list_head dip_list; /* list of all dest ips on this dev */ 939 spinlock_t dip_list_lock; /* protect dip_list */ 940 941 struct list_head pgdir_list; 942 struct mutex pgdir_mutex; 943 int irq[HNS_ROCE_MAX_IRQ_NUM]; 944 u8 __iomem *reg_base; 945 void __iomem *mem_base; 946 struct hns_roce_caps caps; 947 struct xarray qp_table_xa; 948 949 unsigned char dev_addr[HNS_ROCE_MAX_PORTS][ETH_ALEN]; 950 u64 sys_image_guid; 951 u32 vendor_id; 952 u32 vendor_part_id; 953 u32 hw_rev; 954 void __iomem *priv_addr; 955 956 struct hns_roce_cmdq cmd; 957 struct hns_roce_ida pd_ida; 958 struct hns_roce_ida xrcd_ida; 959 struct hns_roce_ida uar_ida; 960 struct hns_roce_mr_table mr_table; 961 struct hns_roce_cq_table cq_table; 962 struct hns_roce_srq_table srq_table; 963 struct hns_roce_qp_table qp_table; 964 struct hns_roce_eq_table eq_table; 965 struct hns_roce_hem_table qpc_timer_table; 966 struct hns_roce_hem_table cqc_timer_table; 967 /* GMV is the memory area that the driver allocates for the hardware 968 * to store SGID, SMAC and VLAN information. 969 */ 970 struct hns_roce_hem_table gmv_table; 971 972 int cmd_mod; 973 int loop_idc; 974 u32 sdb_offset; 975 u32 odb_offset; 976 const struct hns_roce_hw *hw; 977 void *priv; 978 struct workqueue_struct *irq_workq; 979 struct work_struct ecc_work; 980 u32 func_num; 981 u32 is_vf; 982 u32 cong_algo_tmpl_id; 983 u64 dwqe_page; 984 }; 985 to_hr_dev(struct ib_device * ib_dev)986 static inline struct hns_roce_dev *to_hr_dev(struct ib_device *ib_dev) 987 { 988 return container_of(ib_dev, struct hns_roce_dev, ib_dev); 989 } 990 991 static inline struct hns_roce_ucontext to_hr_ucontext(struct ib_ucontext * ibucontext)992 *to_hr_ucontext(struct ib_ucontext *ibucontext) 993 { 994 return container_of(ibucontext, struct hns_roce_ucontext, ibucontext); 995 } 996 to_hr_pd(struct ib_pd * ibpd)997 static inline struct hns_roce_pd *to_hr_pd(struct ib_pd *ibpd) 998 { 999 return container_of(ibpd, struct hns_roce_pd, ibpd); 1000 } 1001 to_hr_xrcd(struct ib_xrcd * ibxrcd)1002 static inline struct hns_roce_xrcd *to_hr_xrcd(struct ib_xrcd *ibxrcd) 1003 { 1004 return container_of(ibxrcd, struct hns_roce_xrcd, ibxrcd); 1005 } 1006 to_hr_ah(struct ib_ah * ibah)1007 static inline struct hns_roce_ah *to_hr_ah(struct ib_ah *ibah) 1008 { 1009 return container_of(ibah, struct hns_roce_ah, ibah); 1010 } 1011 to_hr_mr(struct ib_mr * ibmr)1012 static inline struct hns_roce_mr *to_hr_mr(struct ib_mr *ibmr) 1013 { 1014 return container_of(ibmr, struct hns_roce_mr, ibmr); 1015 } 1016 to_hr_mw(struct ib_mw * ibmw)1017 static inline struct hns_roce_mw *to_hr_mw(struct ib_mw *ibmw) 1018 { 1019 return container_of(ibmw, struct hns_roce_mw, ibmw); 1020 } 1021 to_hr_qp(struct ib_qp * ibqp)1022 static inline struct hns_roce_qp *to_hr_qp(struct ib_qp *ibqp) 1023 { 1024 return container_of(ibqp, struct hns_roce_qp, ibqp); 1025 } 1026 to_hr_cq(struct ib_cq * ib_cq)1027 static inline struct hns_roce_cq *to_hr_cq(struct ib_cq *ib_cq) 1028 { 1029 return container_of(ib_cq, struct hns_roce_cq, ib_cq); 1030 } 1031 to_hr_srq(struct ib_srq * ibsrq)1032 static inline struct hns_roce_srq *to_hr_srq(struct ib_srq *ibsrq) 1033 { 1034 return container_of(ibsrq, struct hns_roce_srq, ibsrq); 1035 } 1036 1037 static inline struct hns_user_mmap_entry * to_hns_mmap(struct rdma_user_mmap_entry * rdma_entry)1038 to_hns_mmap(struct rdma_user_mmap_entry *rdma_entry) 1039 { 1040 return container_of(rdma_entry, struct hns_user_mmap_entry, rdma_entry); 1041 } 1042 hns_roce_write64_k(__le32 val[2],void __iomem * dest)1043 static inline void hns_roce_write64_k(__le32 val[2], void __iomem *dest) 1044 { 1045 writeq(*(u64 *)val, dest); 1046 } 1047 1048 static inline struct hns_roce_qp __hns_roce_qp_lookup(struct hns_roce_dev * hr_dev,u32 qpn)1049 *__hns_roce_qp_lookup(struct hns_roce_dev *hr_dev, u32 qpn) 1050 { 1051 return xa_load(&hr_dev->qp_table_xa, qpn); 1052 } 1053 hns_roce_buf_offset(struct hns_roce_buf * buf,unsigned int offset)1054 static inline void *hns_roce_buf_offset(struct hns_roce_buf *buf, 1055 unsigned int offset) 1056 { 1057 return (char *)(buf->trunk_list[offset >> buf->trunk_shift].buf) + 1058 (offset & ((1 << buf->trunk_shift) - 1)); 1059 } 1060 hns_roce_buf_dma_addr(struct hns_roce_buf * buf,unsigned int offset)1061 static inline dma_addr_t hns_roce_buf_dma_addr(struct hns_roce_buf *buf, 1062 unsigned int offset) 1063 { 1064 return buf->trunk_list[offset >> buf->trunk_shift].map + 1065 (offset & ((1 << buf->trunk_shift) - 1)); 1066 } 1067 hns_roce_buf_page(struct hns_roce_buf * buf,u32 idx)1068 static inline dma_addr_t hns_roce_buf_page(struct hns_roce_buf *buf, u32 idx) 1069 { 1070 return hns_roce_buf_dma_addr(buf, idx << buf->page_shift); 1071 } 1072 1073 #define hr_hw_page_align(x) ALIGN(x, 1 << HNS_HW_PAGE_SHIFT) 1074 to_hr_hw_page_addr(u64 addr)1075 static inline u64 to_hr_hw_page_addr(u64 addr) 1076 { 1077 return addr >> HNS_HW_PAGE_SHIFT; 1078 } 1079 to_hr_hw_page_shift(u32 page_shift)1080 static inline u32 to_hr_hw_page_shift(u32 page_shift) 1081 { 1082 return page_shift - HNS_HW_PAGE_SHIFT; 1083 } 1084 to_hr_hem_hopnum(u32 hopnum,u32 count)1085 static inline u32 to_hr_hem_hopnum(u32 hopnum, u32 count) 1086 { 1087 if (count > 0) 1088 return hopnum == HNS_ROCE_HOP_NUM_0 ? 0 : hopnum; 1089 1090 return 0; 1091 } 1092 to_hr_hem_entries_size(u32 count,u32 buf_shift)1093 static inline u32 to_hr_hem_entries_size(u32 count, u32 buf_shift) 1094 { 1095 return hr_hw_page_align(count << buf_shift); 1096 } 1097 to_hr_hem_entries_count(u32 count,u32 buf_shift)1098 static inline u32 to_hr_hem_entries_count(u32 count, u32 buf_shift) 1099 { 1100 return hr_hw_page_align(count << buf_shift) >> buf_shift; 1101 } 1102 to_hr_hem_entries_shift(u32 count,u32 buf_shift)1103 static inline u32 to_hr_hem_entries_shift(u32 count, u32 buf_shift) 1104 { 1105 if (!count) 1106 return 0; 1107 1108 return ilog2(to_hr_hem_entries_count(count, buf_shift)); 1109 } 1110 1111 #define DSCP_SHIFT 2 1112 get_tclass(const struct ib_global_route * grh)1113 static inline u8 get_tclass(const struct ib_global_route *grh) 1114 { 1115 return grh->sgid_attr->gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP ? 1116 grh->traffic_class >> DSCP_SHIFT : grh->traffic_class; 1117 } 1118 1119 void hns_roce_init_uar_table(struct hns_roce_dev *dev); 1120 int hns_roce_uar_alloc(struct hns_roce_dev *dev, struct hns_roce_uar *uar); 1121 1122 int hns_roce_cmd_init(struct hns_roce_dev *hr_dev); 1123 void hns_roce_cmd_cleanup(struct hns_roce_dev *hr_dev); 1124 void hns_roce_cmd_event(struct hns_roce_dev *hr_dev, u16 token, u8 status, 1125 u64 out_param); 1126 int hns_roce_cmd_use_events(struct hns_roce_dev *hr_dev); 1127 void hns_roce_cmd_use_polling(struct hns_roce_dev *hr_dev); 1128 1129 /* hns roce hw need current block and next block addr from mtt */ 1130 #define MTT_MIN_COUNT 2 hns_roce_get_mtr_ba(struct hns_roce_mtr * mtr)1131 static inline dma_addr_t hns_roce_get_mtr_ba(struct hns_roce_mtr *mtr) 1132 { 1133 return mtr->hem_cfg.root_ba; 1134 } 1135 1136 int hns_roce_mtr_find(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1137 u32 offset, u64 *mtt_buf, int mtt_max); 1138 int hns_roce_mtr_create(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1139 struct hns_roce_buf_attr *buf_attr, 1140 unsigned int page_shift, struct ib_udata *udata, 1141 unsigned long user_addr); 1142 void hns_roce_mtr_destroy(struct hns_roce_dev *hr_dev, 1143 struct hns_roce_mtr *mtr); 1144 int hns_roce_mtr_map(struct hns_roce_dev *hr_dev, struct hns_roce_mtr *mtr, 1145 dma_addr_t *pages, unsigned int page_cnt); 1146 1147 void hns_roce_init_pd_table(struct hns_roce_dev *hr_dev); 1148 void hns_roce_init_mr_table(struct hns_roce_dev *hr_dev); 1149 void hns_roce_init_cq_table(struct hns_roce_dev *hr_dev); 1150 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev); 1151 void hns_roce_init_srq_table(struct hns_roce_dev *hr_dev); 1152 void hns_roce_init_xrcd_table(struct hns_roce_dev *hr_dev); 1153 1154 void hns_roce_cleanup_cq_table(struct hns_roce_dev *hr_dev); 1155 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev); 1156 1157 void hns_roce_cleanup_bitmap(struct hns_roce_dev *hr_dev); 1158 1159 int hns_roce_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1160 struct ib_udata *udata); 1161 int hns_roce_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); hns_roce_destroy_ah(struct ib_ah * ah,u32 flags)1162 static inline int hns_roce_destroy_ah(struct ib_ah *ah, u32 flags) 1163 { 1164 return 0; 1165 } 1166 1167 int hns_roce_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1168 int hns_roce_dealloc_pd(struct ib_pd *pd, struct ib_udata *udata); 1169 1170 struct ib_mr *hns_roce_get_dma_mr(struct ib_pd *pd, int acc); 1171 struct ib_mr *hns_roce_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1172 u64 virt_addr, int access_flags, 1173 struct ib_udata *udata); 1174 struct ib_mr *hns_roce_rereg_user_mr(struct ib_mr *mr, int flags, u64 start, 1175 u64 length, u64 virt_addr, 1176 int mr_access_flags, struct ib_pd *pd, 1177 struct ib_udata *udata); 1178 struct ib_mr *hns_roce_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1179 u32 max_num_sg); 1180 int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1181 unsigned int *sg_offset); 1182 int hns_roce_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1183 unsigned long key_to_hw_index(u32 key); 1184 1185 int hns_roce_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1186 int hns_roce_dealloc_mw(struct ib_mw *ibmw); 1187 1188 void hns_roce_buf_free(struct hns_roce_dev *hr_dev, struct hns_roce_buf *buf); 1189 struct hns_roce_buf *hns_roce_buf_alloc(struct hns_roce_dev *hr_dev, u32 size, 1190 u32 page_shift, u32 flags); 1191 1192 int hns_roce_get_kmem_bufs(struct hns_roce_dev *hr_dev, dma_addr_t *bufs, 1193 int buf_cnt, struct hns_roce_buf *buf, 1194 unsigned int page_shift); 1195 int hns_roce_get_umem_bufs(dma_addr_t *bufs, 1196 int buf_cnt, struct ib_umem *umem, 1197 unsigned int page_shift); 1198 1199 int hns_roce_create_srq(struct ib_srq *srq, 1200 struct ib_srq_init_attr *srq_init_attr, 1201 struct ib_udata *udata); 1202 int hns_roce_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); 1203 1204 int hns_roce_alloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1205 int hns_roce_dealloc_xrcd(struct ib_xrcd *ib_xrcd, struct ib_udata *udata); 1206 1207 int hns_roce_create_qp(struct ib_qp *ib_qp, struct ib_qp_init_attr *init_attr, 1208 struct ib_udata *udata); 1209 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1210 int attr_mask, struct ib_udata *udata); 1211 void init_flush_work(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1212 void *hns_roce_get_recv_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1213 void *hns_roce_get_send_wqe(struct hns_roce_qp *hr_qp, unsigned int n); 1214 void *hns_roce_get_extend_sge(struct hns_roce_qp *hr_qp, unsigned int n); 1215 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, u32 nreq, 1216 struct ib_cq *ib_cq); 1217 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, 1218 struct hns_roce_cq *recv_cq); 1219 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq, 1220 struct hns_roce_cq *recv_cq); 1221 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp); 1222 void hns_roce_qp_destroy(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp, 1223 struct ib_udata *udata); 1224 __be32 send_ieth(const struct ib_send_wr *wr); 1225 int to_hr_qp_type(int qp_type); 1226 1227 int hns_roce_create_cq(struct ib_cq *ib_cq, const struct ib_cq_init_attr *attr, 1228 struct ib_udata *udata); 1229 1230 int hns_roce_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); 1231 int hns_roce_db_map_user(struct hns_roce_ucontext *context, unsigned long virt, 1232 struct hns_roce_db *db); 1233 void hns_roce_db_unmap_user(struct hns_roce_ucontext *context, 1234 struct hns_roce_db *db); 1235 int hns_roce_alloc_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db, 1236 int order); 1237 void hns_roce_free_db(struct hns_roce_dev *hr_dev, struct hns_roce_db *db); 1238 1239 void hns_roce_cq_completion(struct hns_roce_dev *hr_dev, u32 cqn); 1240 void hns_roce_cq_event(struct hns_roce_dev *hr_dev, u32 cqn, int event_type); 1241 void flush_cqe(struct hns_roce_dev *dev, struct hns_roce_qp *qp); 1242 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type); 1243 void hns_roce_flush_cqe(struct hns_roce_dev *hr_dev, u32 qpn); 1244 void hns_roce_srq_event(struct hns_roce_dev *hr_dev, u32 srqn, int event_type); 1245 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev); 1246 int hns_roce_init(struct hns_roce_dev *hr_dev); 1247 void hns_roce_exit(struct hns_roce_dev *hr_dev); 1248 int hns_roce_fill_res_cq_entry(struct sk_buff *msg, struct ib_cq *ib_cq); 1249 int hns_roce_fill_res_cq_entry_raw(struct sk_buff *msg, struct ib_cq *ib_cq); 1250 int hns_roce_fill_res_qp_entry(struct sk_buff *msg, struct ib_qp *ib_qp); 1251 int hns_roce_fill_res_qp_entry_raw(struct sk_buff *msg, struct ib_qp *ib_qp); 1252 int hns_roce_fill_res_mr_entry(struct sk_buff *msg, struct ib_mr *ib_mr); 1253 int hns_roce_fill_res_mr_entry_raw(struct sk_buff *msg, struct ib_mr *ib_mr); 1254 struct hns_user_mmap_entry * 1255 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address, 1256 size_t length, 1257 enum hns_roce_mmap_type mmap_type); 1258 #endif /* _HNS_ROCE_DEVICE_H */ 1259