1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DAL_DCCG_H__ 27 #define __DAL_DCCG_H__ 28 29 #include "dc_types.h" 30 #include "hw_shared.h" 31 32 enum phyd32clk_clock_source { 33 PHYD32CLKA, 34 PHYD32CLKB, 35 PHYD32CLKC, 36 PHYD32CLKD, 37 PHYD32CLKE, 38 PHYD32CLKF, 39 PHYD32CLKG, 40 }; 41 42 enum physymclk_clock_source { 43 PHYSYMCLK_FORCE_SRC_SYMCLK, // Select symclk as source of clock which is output to PHY through DCIO. 44 PHYSYMCLK_FORCE_SRC_PHYD18CLK, // Select phyd18clk as the source of clock which is output to PHY through DCIO. 45 PHYSYMCLK_FORCE_SRC_PHYD32CLK, // Select phyd32clk as the source of clock which is output to PHY through DCIO. 46 }; 47 48 enum streamclk_source { 49 REFCLK, // Selects REFCLK as source for hdmistreamclk. 50 DTBCLK0, // Selects DTBCLK0 as source for hdmistreamclk. 51 DPREFCLK, // Selects DPREFCLK as source for hdmistreamclk 52 }; 53 54 enum dentist_dispclk_change_mode { 55 DISPCLK_CHANGE_MODE_IMMEDIATE, 56 DISPCLK_CHANGE_MODE_RAMPING, 57 }; 58 59 enum pixel_rate_div { 60 PIXEL_RATE_DIV_BY_1 = 0, 61 PIXEL_RATE_DIV_BY_2 = 1, 62 PIXEL_RATE_DIV_BY_4 = 3, 63 PIXEL_RATE_DIV_NA = 0xF 64 }; 65 66 struct dccg { 67 struct dc_context *ctx; 68 const struct dccg_funcs *funcs; 69 int pipe_dppclk_khz[MAX_PIPES]; 70 int ref_dppclk; 71 bool dpp_clock_gated[MAX_PIPES]; 72 //int dtbclk_khz[MAX_PIPES];/* TODO needs to be removed */ 73 //int audio_dtbclk_khz;/* TODO needs to be removed */ 74 //int ref_dtbclk_khz;/* TODO needs to be removed */ 75 }; 76 77 struct dtbclk_dto_params { 78 const struct dc_crtc_timing *timing; 79 int otg_inst; 80 int pixclk_khz; 81 int req_audio_dtbclk_khz; 82 int num_odm_segments; 83 int ref_dtbclk_khz; 84 bool is_hdmi; 85 }; 86 87 struct dccg_funcs { 88 void (*update_dpp_dto)(struct dccg *dccg, 89 int dpp_inst, 90 int req_dppclk); 91 void (*get_dccg_ref_freq)(struct dccg *dccg, 92 unsigned int xtalin_freq_inKhz, 93 unsigned int *dccg_ref_freq_inKhz); 94 void (*set_fifo_errdet_ovr_en)(struct dccg *dccg, 95 bool en); 96 void (*otg_add_pixel)(struct dccg *dccg, 97 uint32_t otg_inst); 98 void (*otg_drop_pixel)(struct dccg *dccg, 99 uint32_t otg_inst); 100 void (*dccg_init)(struct dccg *dccg); 101 102 void (*set_dpstreamclk)( 103 struct dccg *dccg, 104 enum streamclk_source src, 105 int otg_inst, 106 int dp_hpo_inst); 107 108 void (*enable_symclk32_se)( 109 struct dccg *dccg, 110 int hpo_se_inst, 111 enum phyd32clk_clock_source phyd32clk); 112 113 void (*disable_symclk32_se)( 114 struct dccg *dccg, 115 int hpo_se_inst); 116 117 void (*enable_symclk32_le)( 118 struct dccg *dccg, 119 int hpo_le_inst, 120 enum phyd32clk_clock_source phyd32clk); 121 122 void (*disable_symclk32_le)( 123 struct dccg *dccg, 124 int hpo_le_inst); 125 126 void (*set_symclk32_le_root_clock_gating)( 127 struct dccg *dccg, 128 int hpo_le_inst, 129 bool enable); 130 131 void (*set_physymclk)( 132 struct dccg *dccg, 133 int phy_inst, 134 enum physymclk_clock_source clk_src, 135 bool force_enable); 136 137 void (*set_dtbclk_dto)( 138 struct dccg *dccg, 139 const struct dtbclk_dto_params *params); 140 141 void (*set_audio_dtbclk_dto)( 142 struct dccg *dccg, 143 const struct dtbclk_dto_params *params); 144 145 void (*set_dispclk_change_mode)( 146 struct dccg *dccg, 147 enum dentist_dispclk_change_mode change_mode); 148 149 void (*disable_dsc)( 150 struct dccg *dccg, 151 int inst); 152 153 void (*enable_dsc)( 154 struct dccg *dccg, 155 int inst); 156 157 void (*set_pixel_rate_div)(struct dccg *dccg, 158 uint32_t otg_inst, 159 enum pixel_rate_div k1, 160 enum pixel_rate_div k2); 161 162 void (*set_valid_pixel_rate)( 163 struct dccg *dccg, 164 int ref_dtbclk_khz, 165 int otg_inst, 166 int pixclk_khz); 167 168 void (*trigger_dio_fifo_resync)( 169 struct dccg *dccg); 170 171 void (*dpp_root_clock_control)( 172 struct dccg *dccg, 173 unsigned int dpp_inst, 174 bool clock_on); 175 176 void (*enable_symclk_se)( 177 struct dccg *dccg, 178 uint32_t stream_enc_inst, 179 uint32_t link_enc_inst); 180 181 void (*disable_symclk_se)( 182 struct dccg *dccg, 183 uint32_t stream_enc_inst, 184 uint32_t link_enc_inst); 185 }; 186 187 #endif //__DAL_DCCG_H__ 188