1 /*
2 * QEMU PCI VGA Emulator.
3 *
4 * see docs/specs/standard-vga.rst for virtual hardware specs.
5 *
6 * Copyright (c) 2003 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #include "qemu/osdep.h"
28 #include "hw/pci/pci_device.h"
29 #include "hw/qdev-properties.h"
30 #include "migration/vmstate.h"
31 #include "vga_int.h"
32 #include "ui/pixel_ops.h"
33 #include "ui/console.h"
34 #include "qemu/module.h"
35 #include "qemu/timer.h"
36 #include "hw/loader.h"
37 #include "hw/display/edid.h"
38 #include "qom/object.h"
39 #include "hw/acpi/acpi_aml_interface.h"
40
41 enum vga_pci_flags {
42 PCI_VGA_FLAG_ENABLE_MMIO = 1,
43 PCI_VGA_FLAG_ENABLE_QEXT = 2,
44 PCI_VGA_FLAG_ENABLE_EDID = 3,
45 };
46
47 struct PCIVGAState {
48 PCIDevice dev;
49 VGACommonState vga;
50 uint32_t flags;
51 qemu_edid_info edid_info;
52 MemoryRegion mmio;
53 MemoryRegion mrs[4];
54 uint8_t edid[384];
55 };
56
57 #define TYPE_PCI_VGA "pci-vga"
58 OBJECT_DECLARE_SIMPLE_TYPE(PCIVGAState, PCI_VGA)
59
60 static const VMStateDescription vmstate_vga_pci = {
61 .name = "vga",
62 .version_id = 2,
63 .minimum_version_id = 2,
64 .fields = (const VMStateField[]) {
65 VMSTATE_PCI_DEVICE(dev, PCIVGAState),
66 VMSTATE_STRUCT(vga, PCIVGAState, 0, vmstate_vga_common, VGACommonState),
67 VMSTATE_END_OF_LIST()
68 }
69 };
70
pci_vga_ioport_read(void * ptr,hwaddr addr,unsigned size)71 static uint64_t pci_vga_ioport_read(void *ptr, hwaddr addr,
72 unsigned size)
73 {
74 VGACommonState *s = ptr;
75 uint64_t ret = 0;
76
77 switch (size) {
78 case 1:
79 ret = vga_ioport_read(s, addr + 0x3c0);
80 break;
81 case 2:
82 ret = vga_ioport_read(s, addr + 0x3c0);
83 ret |= vga_ioport_read(s, addr + 0x3c1) << 8;
84 break;
85 }
86 return ret;
87 }
88
pci_vga_ioport_write(void * ptr,hwaddr addr,uint64_t val,unsigned size)89 static void pci_vga_ioport_write(void *ptr, hwaddr addr,
90 uint64_t val, unsigned size)
91 {
92 VGACommonState *s = ptr;
93
94 switch (size) {
95 case 1:
96 vga_ioport_write(s, addr + 0x3c0, val);
97 break;
98 case 2:
99 /*
100 * Update bytes in little endian order. Allows to update
101 * indexed registers with a single word write because the
102 * index byte is updated first.
103 */
104 vga_ioport_write(s, addr + 0x3c0, val & 0xff);
105 vga_ioport_write(s, addr + 0x3c1, (val >> 8) & 0xff);
106 break;
107 }
108 }
109
110 static const MemoryRegionOps pci_vga_ioport_ops = {
111 .read = pci_vga_ioport_read,
112 .write = pci_vga_ioport_write,
113 .valid.min_access_size = 1,
114 .valid.max_access_size = 4,
115 .impl.min_access_size = 1,
116 .impl.max_access_size = 2,
117 .endianness = DEVICE_LITTLE_ENDIAN,
118 };
119
pci_vga_bochs_read(void * ptr,hwaddr addr,unsigned size)120 static uint64_t pci_vga_bochs_read(void *ptr, hwaddr addr,
121 unsigned size)
122 {
123 VGACommonState *s = ptr;
124 int index = addr >> 1;
125
126 vbe_ioport_write_index(s, 0, index);
127 return vbe_ioport_read_data(s, 0);
128 }
129
pci_vga_bochs_write(void * ptr,hwaddr addr,uint64_t val,unsigned size)130 static void pci_vga_bochs_write(void *ptr, hwaddr addr,
131 uint64_t val, unsigned size)
132 {
133 VGACommonState *s = ptr;
134 int index = addr >> 1;
135
136 vbe_ioport_write_index(s, 0, index);
137 vbe_ioport_write_data(s, 0, val);
138 }
139
140 static const MemoryRegionOps pci_vga_bochs_ops = {
141 .read = pci_vga_bochs_read,
142 .write = pci_vga_bochs_write,
143 .valid.min_access_size = 1,
144 .valid.max_access_size = 4,
145 .impl.min_access_size = 2,
146 .impl.max_access_size = 2,
147 .endianness = DEVICE_LITTLE_ENDIAN,
148 };
149
pci_vga_qext_read(void * ptr,hwaddr addr,unsigned size)150 static uint64_t pci_vga_qext_read(void *ptr, hwaddr addr, unsigned size)
151 {
152 VGACommonState *s = ptr;
153
154 switch (addr) {
155 case PCI_VGA_QEXT_REG_SIZE:
156 return PCI_VGA_QEXT_SIZE;
157 case PCI_VGA_QEXT_REG_BYTEORDER:
158 return s->big_endian_fb ?
159 PCI_VGA_QEXT_BIG_ENDIAN : PCI_VGA_QEXT_LITTLE_ENDIAN;
160 default:
161 return 0;
162 }
163 }
164
pci_vga_qext_write(void * ptr,hwaddr addr,uint64_t val,unsigned size)165 static void pci_vga_qext_write(void *ptr, hwaddr addr,
166 uint64_t val, unsigned size)
167 {
168 VGACommonState *s = ptr;
169
170 switch (addr) {
171 case PCI_VGA_QEXT_REG_BYTEORDER:
172 if (val == PCI_VGA_QEXT_BIG_ENDIAN) {
173 s->big_endian_fb = true;
174 }
175 if (val == PCI_VGA_QEXT_LITTLE_ENDIAN) {
176 s->big_endian_fb = false;
177 }
178 break;
179 }
180 }
181
vga_get_big_endian_fb(Object * obj,Error ** errp)182 static bool vga_get_big_endian_fb(Object *obj, Error **errp)
183 {
184 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
185
186 return d->vga.big_endian_fb;
187 }
188
vga_set_big_endian_fb(Object * obj,bool value,Error ** errp)189 static void vga_set_big_endian_fb(Object *obj, bool value, Error **errp)
190 {
191 PCIVGAState *d = PCI_VGA(PCI_DEVICE(obj));
192
193 d->vga.big_endian_fb = value;
194 }
195
196 static const MemoryRegionOps pci_vga_qext_ops = {
197 .read = pci_vga_qext_read,
198 .write = pci_vga_qext_write,
199 .valid.min_access_size = 4,
200 .valid.max_access_size = 4,
201 .endianness = DEVICE_LITTLE_ENDIAN,
202 };
203
pci_std_vga_mmio_region_init(VGACommonState * s,Object * owner,MemoryRegion * parent,MemoryRegion * subs,bool qext,bool edid)204 void pci_std_vga_mmio_region_init(VGACommonState *s,
205 Object *owner,
206 MemoryRegion *parent,
207 MemoryRegion *subs,
208 bool qext, bool edid)
209 {
210 PCIVGAState *d = container_of(s, PCIVGAState, vga);
211
212 memory_region_init_io(&subs[0], owner, &pci_vga_ioport_ops, s,
213 "vga ioports remapped", PCI_VGA_IOPORT_SIZE);
214 memory_region_add_subregion(parent, PCI_VGA_IOPORT_OFFSET,
215 &subs[0]);
216
217 memory_region_init_io(&subs[1], owner, &pci_vga_bochs_ops, s,
218 "bochs dispi interface", PCI_VGA_BOCHS_SIZE);
219 memory_region_add_subregion(parent, PCI_VGA_BOCHS_OFFSET,
220 &subs[1]);
221
222 if (qext) {
223 memory_region_init_io(&subs[2], owner, &pci_vga_qext_ops, s,
224 "qemu extended regs", PCI_VGA_QEXT_SIZE);
225 memory_region_add_subregion(parent, PCI_VGA_QEXT_OFFSET,
226 &subs[2]);
227 }
228
229 if (edid) {
230 qemu_edid_generate(d->edid, sizeof(d->edid), &d->edid_info);
231 qemu_edid_region_io(&subs[3], owner, d->edid, sizeof(d->edid));
232 memory_region_add_subregion(parent, 0, &subs[3]);
233 }
234 }
235
pci_std_vga_realize(PCIDevice * dev,Error ** errp)236 static void pci_std_vga_realize(PCIDevice *dev, Error **errp)
237 {
238 PCIVGAState *d = PCI_VGA(dev);
239 VGACommonState *s = &d->vga;
240 bool qext = false;
241 bool edid = false;
242
243 /* vga + console init */
244 if (!vga_common_init(s, OBJECT(dev), errp)) {
245 return;
246 }
247 vga_init(s, OBJECT(dev), pci_address_space(dev), pci_address_space_io(dev),
248 true);
249
250 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
251
252 /* XXX: VGA_RAM_SIZE must be a power of two */
253 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
254
255 /* mmio bar for vga register access */
256 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_MMIO)) {
257 memory_region_init_io(&d->mmio, OBJECT(dev), &unassigned_io_ops, NULL,
258 "vga.mmio", PCI_VGA_MMIO_SIZE);
259
260 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
261 qext = true;
262 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
263 }
264 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
265 edid = true;
266 }
267 pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs,
268 qext, edid);
269
270 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
271 }
272 }
273
pci_secondary_vga_realize(PCIDevice * dev,Error ** errp)274 static void pci_secondary_vga_realize(PCIDevice *dev, Error **errp)
275 {
276 PCIVGAState *d = PCI_VGA(dev);
277 VGACommonState *s = &d->vga;
278 bool qext = false;
279 bool edid = false;
280
281 /* vga + console init */
282 if (!vga_common_init(s, OBJECT(dev), errp)) {
283 return;
284 }
285 s->con = graphic_console_init(DEVICE(dev), 0, s->hw_ops, s);
286
287 /* mmio bar */
288 memory_region_init_io(&d->mmio, OBJECT(dev), &unassigned_io_ops, NULL,
289 "vga.mmio", PCI_VGA_MMIO_SIZE);
290
291 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
292 qext = true;
293 pci_set_byte(&d->dev.config[PCI_REVISION_ID], 2);
294 }
295 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
296 edid = true;
297 }
298 pci_std_vga_mmio_region_init(s, OBJECT(dev), &d->mmio, d->mrs, qext, edid);
299
300 pci_register_bar(&d->dev, 0, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->vram);
301 pci_register_bar(&d->dev, 2, PCI_BASE_ADDRESS_SPACE_MEMORY, &d->mmio);
302 }
303
pci_secondary_vga_exit(PCIDevice * dev)304 static void pci_secondary_vga_exit(PCIDevice *dev)
305 {
306 PCIVGAState *d = PCI_VGA(dev);
307 VGACommonState *s = &d->vga;
308
309 graphic_console_close(s->con);
310 memory_region_del_subregion(&d->mmio, &d->mrs[0]);
311 memory_region_del_subregion(&d->mmio, &d->mrs[1]);
312 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_QEXT)) {
313 memory_region_del_subregion(&d->mmio, &d->mrs[2]);
314 }
315 if (d->flags & (1 << PCI_VGA_FLAG_ENABLE_EDID)) {
316 memory_region_del_subregion(&d->mmio, &d->mrs[3]);
317 }
318 }
319
pci_secondary_vga_init(Object * obj)320 static void pci_secondary_vga_init(Object *obj)
321 {
322 /* Expose framebuffer byteorder via QOM */
323 object_property_add_bool(obj, "big-endian-framebuffer",
324 vga_get_big_endian_fb, vga_set_big_endian_fb);
325 }
326
pci_secondary_vga_reset(DeviceState * dev)327 static void pci_secondary_vga_reset(DeviceState *dev)
328 {
329 PCIVGAState *d = PCI_VGA(PCI_DEVICE(dev));
330 vga_common_reset(&d->vga);
331 }
332
333 static Property vga_pci_properties[] = {
334 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
335 DEFINE_PROP_BIT("mmio", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_MMIO, true),
336 DEFINE_PROP_BIT("qemu-extended-regs",
337 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
338 DEFINE_PROP_BIT("edid",
339 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true),
340 DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
341 DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false),
342 DEFINE_PROP_END_OF_LIST(),
343 };
344
345 static Property secondary_pci_properties[] = {
346 DEFINE_PROP_UINT32("vgamem_mb", PCIVGAState, vga.vram_size_mb, 16),
347 DEFINE_PROP_BIT("qemu-extended-regs",
348 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_QEXT, true),
349 DEFINE_PROP_BIT("edid",
350 PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true),
351 DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info),
352 DEFINE_PROP_END_OF_LIST(),
353 };
354
vga_pci_class_init(ObjectClass * klass,void * data)355 static void vga_pci_class_init(ObjectClass *klass, void *data)
356 {
357 DeviceClass *dc = DEVICE_CLASS(klass);
358 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
359 AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
360
361 k->vendor_id = PCI_VENDOR_ID_QEMU;
362 k->device_id = PCI_DEVICE_ID_QEMU_VGA;
363 dc->vmsd = &vmstate_vga_pci;
364 set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
365 adevc->build_dev_aml = build_vga_aml;
366 }
367
368 static const TypeInfo vga_pci_type_info = {
369 .name = TYPE_PCI_VGA,
370 .parent = TYPE_PCI_DEVICE,
371 .instance_size = sizeof(PCIVGAState),
372 .abstract = true,
373 .class_init = vga_pci_class_init,
374 .interfaces = (InterfaceInfo[]) {
375 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
376 { TYPE_ACPI_DEV_AML_IF },
377 { },
378 },
379 };
380
vga_class_init(ObjectClass * klass,void * data)381 static void vga_class_init(ObjectClass *klass, void *data)
382 {
383 DeviceClass *dc = DEVICE_CLASS(klass);
384 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
385
386 k->realize = pci_std_vga_realize;
387 k->romfile = "vgabios-stdvga.bin";
388 k->class_id = PCI_CLASS_DISPLAY_VGA;
389 device_class_set_props(dc, vga_pci_properties);
390 dc->hotpluggable = false;
391
392 /* Expose framebuffer byteorder via QOM */
393 object_class_property_add_bool(klass, "big-endian-framebuffer",
394 vga_get_big_endian_fb, vga_set_big_endian_fb);
395 }
396
secondary_class_init(ObjectClass * klass,void * data)397 static void secondary_class_init(ObjectClass *klass, void *data)
398 {
399 DeviceClass *dc = DEVICE_CLASS(klass);
400 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
401
402 k->realize = pci_secondary_vga_realize;
403 k->exit = pci_secondary_vga_exit;
404 k->class_id = PCI_CLASS_DISPLAY_OTHER;
405 device_class_set_props(dc, secondary_pci_properties);
406 dc->reset = pci_secondary_vga_reset;
407 }
408
409 static const TypeInfo vga_info = {
410 .name = "VGA",
411 .parent = TYPE_PCI_VGA,
412 .class_init = vga_class_init,
413 };
414
415 static const TypeInfo secondary_info = {
416 .name = "secondary-vga",
417 .parent = TYPE_PCI_VGA,
418 .instance_init = pci_secondary_vga_init,
419 .class_init = secondary_class_init,
420 };
421
vga_register_types(void)422 static void vga_register_types(void)
423 {
424 type_register_static(&vga_pci_type_info);
425 type_register_static(&vga_info);
426 type_register_static(&secondary_info);
427 }
428
429 type_init(vga_register_types)
430