xref: /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c (revision fd5e9fccbd504c5179ab57ff695c610bca8809d6)
1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3  * Copyright 2019 Raptor Engineering, LLC
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: AMD
24  *
25  */
26 
27 #include <linux/slab.h>
28 
29 #include "dm_services.h"
30 #include "dc.h"
31 
32 #include "dcn20_init.h"
33 
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
37 
38 #include "dml/dcn20/dcn20_fpu.h"
39 
40 #include "dcn10/dcn10_hubp.h"
41 #include "dcn10/dcn10_ipp.h"
42 #include "dcn20_hubbub.h"
43 #include "dcn20_mpc.h"
44 #include "dcn20_hubp.h"
45 #include "irq/dcn20/irq_service_dcn20.h"
46 #include "dcn20_dpp.h"
47 #include "dcn20_optc.h"
48 #include "dcn20_hwseq.h"
49 #include "dce110/dce110_hw_sequencer.h"
50 #include "dcn10/dcn10_resource.h"
51 #include "dcn20_opp.h"
52 
53 #include "dcn20_dsc.h"
54 
55 #include "dcn20_link_encoder.h"
56 #include "dcn20_stream_encoder.h"
57 #include "dce/dce_clock_source.h"
58 #include "dce/dce_audio.h"
59 #include "dce/dce_hwseq.h"
60 #include "virtual/virtual_stream_encoder.h"
61 #include "dce110/dce110_resource.h"
62 #include "dml/display_mode_vba.h"
63 #include "dcn20_dccg.h"
64 #include "dcn20_vmid.h"
65 #include "dce/dce_panel_cntl.h"
66 
67 #include "navi10_ip_offset.h"
68 
69 #include "dcn/dcn_2_0_0_offset.h"
70 #include "dcn/dcn_2_0_0_sh_mask.h"
71 #include "dpcs/dpcs_2_0_0_offset.h"
72 #include "dpcs/dpcs_2_0_0_sh_mask.h"
73 
74 #include "nbio/nbio_2_3_offset.h"
75 
76 #include "dcn20/dcn20_dwb.h"
77 #include "dcn20/dcn20_mmhubbub.h"
78 
79 #include "mmhub/mmhub_2_0_0_offset.h"
80 #include "mmhub/mmhub_2_0_0_sh_mask.h"
81 
82 #include "reg_helper.h"
83 #include "dce/dce_abm.h"
84 #include "dce/dce_dmcu.h"
85 #include "dce/dce_aux.h"
86 #include "dce/dce_i2c.h"
87 #include "vm_helper.h"
88 #include "link_enc_cfg.h"
89 
90 #include "amdgpu_socbb.h"
91 
92 #include "link.h"
93 #define DC_LOGGER_INIT(logger)
94 
95 #ifndef mmDP0_DP_DPHY_INTERNAL_CTRL
96 	#define mmDP0_DP_DPHY_INTERNAL_CTRL		0x210f
97 	#define mmDP0_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
98 	#define mmDP1_DP_DPHY_INTERNAL_CTRL		0x220f
99 	#define mmDP1_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
100 	#define mmDP2_DP_DPHY_INTERNAL_CTRL		0x230f
101 	#define mmDP2_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
102 	#define mmDP3_DP_DPHY_INTERNAL_CTRL		0x240f
103 	#define mmDP3_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
104 	#define mmDP4_DP_DPHY_INTERNAL_CTRL		0x250f
105 	#define mmDP4_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
106 	#define mmDP5_DP_DPHY_INTERNAL_CTRL		0x260f
107 	#define mmDP5_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
108 	#define mmDP6_DP_DPHY_INTERNAL_CTRL		0x270f
109 	#define mmDP6_DP_DPHY_INTERNAL_CTRL_BASE_IDX	2
110 #endif
111 
112 
113 enum dcn20_clk_src_array_id {
114 	DCN20_CLK_SRC_PLL0,
115 	DCN20_CLK_SRC_PLL1,
116 	DCN20_CLK_SRC_PLL2,
117 	DCN20_CLK_SRC_PLL3,
118 	DCN20_CLK_SRC_PLL4,
119 	DCN20_CLK_SRC_PLL5,
120 	DCN20_CLK_SRC_TOTAL
121 };
122 
123 /* begin *********************
124  * macros to expend register list macro defined in HW object header file */
125 
126 /* DCN */
127 #define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
128 
129 #define BASE(seg) BASE_INNER(seg)
130 
131 #define SR(reg_name)\
132 		.reg_name = BASE(mm ## reg_name ## _BASE_IDX) +  \
133 					mm ## reg_name
134 
135 #define SRI(reg_name, block, id)\
136 	.reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
137 					mm ## block ## id ## _ ## reg_name
138 
139 #define SRI2_DWB(reg_name, block, id)\
140 	.reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
141 					mm ## reg_name
142 #define SF_DWB(reg_name, field_name, post_fix)\
143 	.field_name = reg_name ## __ ## field_name ## post_fix
144 
145 #define SF_DWB2(reg_name, block, id, field_name, post_fix)	\
146 	.field_name = reg_name ## __ ## field_name ## post_fix
147 
148 #define SRIR(var_name, reg_name, block, id)\
149 	.var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
150 					mm ## block ## id ## _ ## reg_name
151 
152 #define SRII(reg_name, block, id)\
153 	.reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
154 					mm ## block ## id ## _ ## reg_name
155 
156 #define DCCG_SRII(reg_name, block, id)\
157 	.block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
158 					mm ## block ## id ## _ ## reg_name
159 
160 #define VUPDATE_SRII(reg_name, block, id)\
161 	.reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
162 					mm ## reg_name ## _ ## block ## id
163 
164 /* NBIO */
165 #define NBIO_BASE_INNER(seg) \
166 	NBIO_BASE__INST0_SEG ## seg
167 
168 #define NBIO_BASE(seg) \
169 	NBIO_BASE_INNER(seg)
170 
171 #define NBIO_SR(reg_name)\
172 		.reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
173 					mm ## reg_name
174 
175 /* MMHUB */
176 #define MMHUB_BASE_INNER(seg) \
177 	MMHUB_BASE__INST0_SEG ## seg
178 
179 #define MMHUB_BASE(seg) \
180 	MMHUB_BASE_INNER(seg)
181 
182 #define MMHUB_SR(reg_name)\
183 		.reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
184 					mmMM ## reg_name
185 
186 static const struct bios_registers bios_regs = {
187 		NBIO_SR(BIOS_SCRATCH_3),
188 		NBIO_SR(BIOS_SCRATCH_6)
189 };
190 
191 #define clk_src_regs(index, pllid)\
192 [index] = {\
193 	CS_COMMON_REG_LIST_DCN2_0(index, pllid),\
194 }
195 
196 static const struct dce110_clk_src_regs clk_src_regs[] = {
197 	clk_src_regs(0, A),
198 	clk_src_regs(1, B),
199 	clk_src_regs(2, C),
200 	clk_src_regs(3, D),
201 	clk_src_regs(4, E),
202 	clk_src_regs(5, F)
203 };
204 
205 static const struct dce110_clk_src_shift cs_shift = {
206 		CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
207 };
208 
209 static const struct dce110_clk_src_mask cs_mask = {
210 		CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
211 };
212 
213 static const struct dce_dmcu_registers dmcu_regs = {
214 		DMCU_DCN10_REG_LIST()
215 };
216 
217 static const struct dce_dmcu_shift dmcu_shift = {
218 		DMCU_MASK_SH_LIST_DCN10(__SHIFT)
219 };
220 
221 static const struct dce_dmcu_mask dmcu_mask = {
222 		DMCU_MASK_SH_LIST_DCN10(_MASK)
223 };
224 
225 static const struct dce_abm_registers abm_regs = {
226 		ABM_DCN20_REG_LIST()
227 };
228 
229 static const struct dce_abm_shift abm_shift = {
230 		ABM_MASK_SH_LIST_DCN20(__SHIFT)
231 };
232 
233 static const struct dce_abm_mask abm_mask = {
234 		ABM_MASK_SH_LIST_DCN20(_MASK)
235 };
236 
237 #define audio_regs(id)\
238 [id] = {\
239 		AUD_COMMON_REG_LIST(id)\
240 }
241 
242 static const struct dce_audio_registers audio_regs[] = {
243 	audio_regs(0),
244 	audio_regs(1),
245 	audio_regs(2),
246 	audio_regs(3),
247 	audio_regs(4),
248 	audio_regs(5),
249 	audio_regs(6),
250 };
251 
252 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
253 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
254 		SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
255 		AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
256 
257 static const struct dce_audio_shift audio_shift = {
258 		DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
259 };
260 
261 static const struct dce_audio_mask audio_mask = {
262 		DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
263 };
264 
265 #define stream_enc_regs(id)\
266 [id] = {\
267 	SE_DCN2_REG_LIST(id)\
268 }
269 
270 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
271 	stream_enc_regs(0),
272 	stream_enc_regs(1),
273 	stream_enc_regs(2),
274 	stream_enc_regs(3),
275 	stream_enc_regs(4),
276 	stream_enc_regs(5),
277 };
278 
279 static const struct dcn10_stream_encoder_shift se_shift = {
280 		SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
281 };
282 
283 static const struct dcn10_stream_encoder_mask se_mask = {
284 		SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
285 };
286 
287 
288 #define aux_regs(id)\
289 [id] = {\
290 	DCN2_AUX_REG_LIST(id)\
291 }
292 
293 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
294 		aux_regs(0),
295 		aux_regs(1),
296 		aux_regs(2),
297 		aux_regs(3),
298 		aux_regs(4),
299 		aux_regs(5)
300 };
301 
302 #define hpd_regs(id)\
303 [id] = {\
304 	HPD_REG_LIST(id)\
305 }
306 
307 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
308 		hpd_regs(0),
309 		hpd_regs(1),
310 		hpd_regs(2),
311 		hpd_regs(3),
312 		hpd_regs(4),
313 		hpd_regs(5)
314 };
315 
316 #define link_regs(id, phyid)\
317 [id] = {\
318 	LE_DCN10_REG_LIST(id), \
319 	UNIPHY_DCN2_REG_LIST(phyid), \
320 	DPCS_DCN2_REG_LIST(id), \
321 	SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
322 }
323 
324 static const struct dcn10_link_enc_registers link_enc_regs[] = {
325 	link_regs(0, A),
326 	link_regs(1, B),
327 	link_regs(2, C),
328 	link_regs(3, D),
329 	link_regs(4, E),
330 	link_regs(5, F)
331 };
332 
333 static const struct dcn10_link_enc_shift le_shift = {
334 	LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
335 	DPCS_DCN2_MASK_SH_LIST(__SHIFT)
336 };
337 
338 static const struct dcn10_link_enc_mask le_mask = {
339 	LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
340 	DPCS_DCN2_MASK_SH_LIST(_MASK)
341 };
342 
343 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
344 	{ DCN_PANEL_CNTL_REG_LIST() }
345 };
346 
347 static const struct dce_panel_cntl_shift panel_cntl_shift = {
348 	DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
349 };
350 
351 static const struct dce_panel_cntl_mask panel_cntl_mask = {
352 	DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
353 };
354 
355 #define ipp_regs(id)\
356 [id] = {\
357 	IPP_REG_LIST_DCN20(id),\
358 }
359 
360 static const struct dcn10_ipp_registers ipp_regs[] = {
361 	ipp_regs(0),
362 	ipp_regs(1),
363 	ipp_regs(2),
364 	ipp_regs(3),
365 	ipp_regs(4),
366 	ipp_regs(5),
367 };
368 
369 static const struct dcn10_ipp_shift ipp_shift = {
370 		IPP_MASK_SH_LIST_DCN20(__SHIFT)
371 };
372 
373 static const struct dcn10_ipp_mask ipp_mask = {
374 		IPP_MASK_SH_LIST_DCN20(_MASK),
375 };
376 
377 #define opp_regs(id)\
378 [id] = {\
379 	OPP_REG_LIST_DCN20(id),\
380 }
381 
382 static const struct dcn20_opp_registers opp_regs[] = {
383 	opp_regs(0),
384 	opp_regs(1),
385 	opp_regs(2),
386 	opp_regs(3),
387 	opp_regs(4),
388 	opp_regs(5),
389 };
390 
391 static const struct dcn20_opp_shift opp_shift = {
392 		OPP_MASK_SH_LIST_DCN20(__SHIFT)
393 };
394 
395 static const struct dcn20_opp_mask opp_mask = {
396 		OPP_MASK_SH_LIST_DCN20(_MASK)
397 };
398 
399 #define aux_engine_regs(id)\
400 [id] = {\
401 	AUX_COMMON_REG_LIST0(id), \
402 	.AUXN_IMPCAL = 0, \
403 	.AUXP_IMPCAL = 0, \
404 	.AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
405 }
406 
407 static const struct dce110_aux_registers aux_engine_regs[] = {
408 		aux_engine_regs(0),
409 		aux_engine_regs(1),
410 		aux_engine_regs(2),
411 		aux_engine_regs(3),
412 		aux_engine_regs(4),
413 		aux_engine_regs(5)
414 };
415 
416 #define tf_regs(id)\
417 [id] = {\
418 	TF_REG_LIST_DCN20(id),\
419 	TF_REG_LIST_DCN20_COMMON_APPEND(id),\
420 }
421 
422 static const struct dcn2_dpp_registers tf_regs[] = {
423 	tf_regs(0),
424 	tf_regs(1),
425 	tf_regs(2),
426 	tf_regs(3),
427 	tf_regs(4),
428 	tf_regs(5),
429 };
430 
431 static const struct dcn2_dpp_shift tf_shift = {
432 		TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
433 		TF_DEBUG_REG_LIST_SH_DCN20
434 };
435 
436 static const struct dcn2_dpp_mask tf_mask = {
437 		TF_REG_LIST_SH_MASK_DCN20(_MASK),
438 		TF_DEBUG_REG_LIST_MASK_DCN20
439 };
440 
441 #define dwbc_regs_dcn2(id)\
442 [id] = {\
443 	DWBC_COMMON_REG_LIST_DCN2_0(id),\
444 		}
445 
446 static const struct dcn20_dwbc_registers dwbc20_regs[] = {
447 	dwbc_regs_dcn2(0),
448 };
449 
450 static const struct dcn20_dwbc_shift dwbc20_shift = {
451 	DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
452 };
453 
454 static const struct dcn20_dwbc_mask dwbc20_mask = {
455 	DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
456 };
457 
458 #define mcif_wb_regs_dcn2(id)\
459 [id] = {\
460 	MCIF_WB_COMMON_REG_LIST_DCN2_0(id),\
461 		}
462 
463 static const struct dcn20_mmhubbub_registers mcif_wb20_regs[] = {
464 	mcif_wb_regs_dcn2(0),
465 };
466 
467 static const struct dcn20_mmhubbub_shift mcif_wb20_shift = {
468 	MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
469 };
470 
471 static const struct dcn20_mmhubbub_mask mcif_wb20_mask = {
472 	MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
473 };
474 
475 static const struct dcn20_mpc_registers mpc_regs = {
476 		MPC_REG_LIST_DCN2_0(0),
477 		MPC_REG_LIST_DCN2_0(1),
478 		MPC_REG_LIST_DCN2_0(2),
479 		MPC_REG_LIST_DCN2_0(3),
480 		MPC_REG_LIST_DCN2_0(4),
481 		MPC_REG_LIST_DCN2_0(5),
482 		MPC_OUT_MUX_REG_LIST_DCN2_0(0),
483 		MPC_OUT_MUX_REG_LIST_DCN2_0(1),
484 		MPC_OUT_MUX_REG_LIST_DCN2_0(2),
485 		MPC_OUT_MUX_REG_LIST_DCN2_0(3),
486 		MPC_OUT_MUX_REG_LIST_DCN2_0(4),
487 		MPC_OUT_MUX_REG_LIST_DCN2_0(5),
488 		MPC_DBG_REG_LIST_DCN2_0()
489 };
490 
491 static const struct dcn20_mpc_shift mpc_shift = {
492 	MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
493 	MPC_DEBUG_REG_LIST_SH_DCN20
494 };
495 
496 static const struct dcn20_mpc_mask mpc_mask = {
497 	MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
498 	MPC_DEBUG_REG_LIST_MASK_DCN20
499 };
500 
501 #define tg_regs(id)\
502 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
503 
504 
505 static const struct dcn_optc_registers tg_regs[] = {
506 	tg_regs(0),
507 	tg_regs(1),
508 	tg_regs(2),
509 	tg_regs(3),
510 	tg_regs(4),
511 	tg_regs(5)
512 };
513 
514 static const struct dcn_optc_shift tg_shift = {
515 	TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
516 };
517 
518 static const struct dcn_optc_mask tg_mask = {
519 	TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
520 };
521 
522 #define hubp_regs(id)\
523 [id] = {\
524 	HUBP_REG_LIST_DCN20(id)\
525 }
526 
527 static const struct dcn_hubp2_registers hubp_regs[] = {
528 		hubp_regs(0),
529 		hubp_regs(1),
530 		hubp_regs(2),
531 		hubp_regs(3),
532 		hubp_regs(4),
533 		hubp_regs(5)
534 };
535 
536 static const struct dcn_hubp2_shift hubp_shift = {
537 		HUBP_MASK_SH_LIST_DCN20(__SHIFT)
538 };
539 
540 static const struct dcn_hubp2_mask hubp_mask = {
541 		HUBP_MASK_SH_LIST_DCN20(_MASK)
542 };
543 
544 static const struct dcn_hubbub_registers hubbub_reg = {
545 		HUBBUB_REG_LIST_DCN20(0)
546 };
547 
548 static const struct dcn_hubbub_shift hubbub_shift = {
549 		HUBBUB_MASK_SH_LIST_DCN20(__SHIFT)
550 };
551 
552 static const struct dcn_hubbub_mask hubbub_mask = {
553 		HUBBUB_MASK_SH_LIST_DCN20(_MASK)
554 };
555 
556 #define vmid_regs(id)\
557 [id] = {\
558 		DCN20_VMID_REG_LIST(id)\
559 }
560 
561 static const struct dcn_vmid_registers vmid_regs[] = {
562 	vmid_regs(0),
563 	vmid_regs(1),
564 	vmid_regs(2),
565 	vmid_regs(3),
566 	vmid_regs(4),
567 	vmid_regs(5),
568 	vmid_regs(6),
569 	vmid_regs(7),
570 	vmid_regs(8),
571 	vmid_regs(9),
572 	vmid_regs(10),
573 	vmid_regs(11),
574 	vmid_regs(12),
575 	vmid_regs(13),
576 	vmid_regs(14),
577 	vmid_regs(15)
578 };
579 
580 static const struct dcn20_vmid_shift vmid_shifts = {
581 		DCN20_VMID_MASK_SH_LIST(__SHIFT)
582 };
583 
584 static const struct dcn20_vmid_mask vmid_masks = {
585 		DCN20_VMID_MASK_SH_LIST(_MASK)
586 };
587 
588 static const struct dce110_aux_registers_shift aux_shift = {
589 		DCN_AUX_MASK_SH_LIST(__SHIFT)
590 };
591 
592 static const struct dce110_aux_registers_mask aux_mask = {
593 		DCN_AUX_MASK_SH_LIST(_MASK)
594 };
595 
map_transmitter_id_to_phy_instance(enum transmitter transmitter)596 static int map_transmitter_id_to_phy_instance(
597 	enum transmitter transmitter)
598 {
599 	switch (transmitter) {
600 	case TRANSMITTER_UNIPHY_A:
601 		return 0;
602 	break;
603 	case TRANSMITTER_UNIPHY_B:
604 		return 1;
605 	break;
606 	case TRANSMITTER_UNIPHY_C:
607 		return 2;
608 	break;
609 	case TRANSMITTER_UNIPHY_D:
610 		return 3;
611 	break;
612 	case TRANSMITTER_UNIPHY_E:
613 		return 4;
614 	break;
615 	case TRANSMITTER_UNIPHY_F:
616 		return 5;
617 	break;
618 	default:
619 		ASSERT(0);
620 		return 0;
621 	}
622 }
623 
624 #define dsc_regsDCN20(id)\
625 [id] = {\
626 	DSC_REG_LIST_DCN20(id)\
627 }
628 
629 static const struct dcn20_dsc_registers dsc_regs[] = {
630 	dsc_regsDCN20(0),
631 	dsc_regsDCN20(1),
632 	dsc_regsDCN20(2),
633 	dsc_regsDCN20(3),
634 	dsc_regsDCN20(4),
635 	dsc_regsDCN20(5)
636 };
637 
638 static const struct dcn20_dsc_shift dsc_shift = {
639 	DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
640 };
641 
642 static const struct dcn20_dsc_mask dsc_mask = {
643 	DSC_REG_LIST_SH_MASK_DCN20(_MASK)
644 };
645 
646 static const struct dccg_registers dccg_regs = {
647 		DCCG_REG_LIST_DCN2()
648 };
649 
650 static const struct dccg_shift dccg_shift = {
651 		DCCG_MASK_SH_LIST_DCN2(__SHIFT)
652 };
653 
654 static const struct dccg_mask dccg_mask = {
655 		DCCG_MASK_SH_LIST_DCN2(_MASK)
656 };
657 
658 static const struct resource_caps res_cap_nv10 = {
659 		.num_timing_generator = 6,
660 		.num_opp = 6,
661 		.num_video_plane = 6,
662 		.num_audio = 7,
663 		.num_stream_encoder = 6,
664 		.num_pll = 6,
665 		.num_dwb = 1,
666 		.num_ddc = 6,
667 		.num_vmid = 16,
668 		.num_dsc = 6,
669 };
670 
671 static const struct dc_plane_cap plane_cap = {
672 	.type = DC_PLANE_TYPE_DCN_UNIVERSAL,
673 	.per_pixel_alpha = true,
674 
675 	.pixel_format_support = {
676 			.argb8888 = true,
677 			.nv12 = true,
678 			.fp16 = true,
679 			.p010 = true
680 	},
681 
682 	.max_upscale_factor = {
683 			.argb8888 = 16000,
684 			.nv12 = 16000,
685 			.fp16 = 1
686 	},
687 
688 	.max_downscale_factor = {
689 			.argb8888 = 250,
690 			.nv12 = 250,
691 			.fp16 = 1
692 	},
693 	16,
694 	16
695 };
696 static const struct resource_caps res_cap_nv14 = {
697 		.num_timing_generator = 5,
698 		.num_opp = 5,
699 		.num_video_plane = 5,
700 		.num_audio = 6,
701 		.num_stream_encoder = 5,
702 		.num_pll = 5,
703 		.num_dwb = 1,
704 		.num_ddc = 5,
705 		.num_vmid = 16,
706 		.num_dsc = 5,
707 };
708 
709 static const struct dc_debug_options debug_defaults_drv = {
710 		.disable_dmcu = false,
711 		.force_abm_enable = false,
712 		.timing_trace = false,
713 		.clock_trace = true,
714 		.disable_pplib_clock_request = true,
715 		.pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
716 		.force_single_disp_pipe_split = false,
717 		.disable_dcc = DCC_ENABLE,
718 		.vsr_support = true,
719 		.performance_trace = false,
720 		.max_downscale_src_width = 5120,/*upto 5K*/
721 		.disable_pplib_wm_range = false,
722 		.scl_reset_length10 = true,
723 		.sanity_checks = false,
724 		.underflow_assert_delay_us = 0xFFFFFFFF,
725 		.enable_legacy_fast_update = true,
726 };
727 
dcn20_dpp_destroy(struct dpp ** dpp)728 void dcn20_dpp_destroy(struct dpp **dpp)
729 {
730 	kfree(TO_DCN20_DPP(*dpp));
731 	*dpp = NULL;
732 }
733 
dcn20_dpp_create(struct dc_context * ctx,uint32_t inst)734 struct dpp *dcn20_dpp_create(
735 	struct dc_context *ctx,
736 	uint32_t inst)
737 {
738 	struct dcn20_dpp *dpp =
739 		kzalloc(sizeof(struct dcn20_dpp), GFP_ATOMIC);
740 
741 	if (!dpp)
742 		return NULL;
743 
744 	if (dpp2_construct(dpp, ctx, inst,
745 			&tf_regs[inst], &tf_shift, &tf_mask))
746 		return &dpp->base;
747 
748 	BREAK_TO_DEBUGGER();
749 	kfree(dpp);
750 	return NULL;
751 }
752 
dcn20_ipp_create(struct dc_context * ctx,uint32_t inst)753 struct input_pixel_processor *dcn20_ipp_create(
754 	struct dc_context *ctx, uint32_t inst)
755 {
756 	struct dcn10_ipp *ipp =
757 		kzalloc(sizeof(struct dcn10_ipp), GFP_ATOMIC);
758 
759 	if (!ipp) {
760 		BREAK_TO_DEBUGGER();
761 		return NULL;
762 	}
763 
764 	dcn20_ipp_construct(ipp, ctx, inst,
765 			&ipp_regs[inst], &ipp_shift, &ipp_mask);
766 	return &ipp->base;
767 }
768 
769 
dcn20_opp_create(struct dc_context * ctx,uint32_t inst)770 struct output_pixel_processor *dcn20_opp_create(
771 	struct dc_context *ctx, uint32_t inst)
772 {
773 	struct dcn20_opp *opp =
774 		kzalloc(sizeof(struct dcn20_opp), GFP_ATOMIC);
775 
776 	if (!opp) {
777 		BREAK_TO_DEBUGGER();
778 		return NULL;
779 	}
780 
781 	dcn20_opp_construct(opp, ctx, inst,
782 			&opp_regs[inst], &opp_shift, &opp_mask);
783 	return &opp->base;
784 }
785 
dcn20_aux_engine_create(struct dc_context * ctx,uint32_t inst)786 struct dce_aux *dcn20_aux_engine_create(
787 	struct dc_context *ctx,
788 	uint32_t inst)
789 {
790 	struct aux_engine_dce110 *aux_engine =
791 		kzalloc(sizeof(struct aux_engine_dce110), GFP_ATOMIC);
792 
793 	if (!aux_engine)
794 		return NULL;
795 
796 	dce110_aux_engine_construct(aux_engine, ctx, inst,
797 				    SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
798 				    &aux_engine_regs[inst],
799 					&aux_mask,
800 					&aux_shift,
801 					ctx->dc->caps.extended_aux_timeout_support);
802 
803 	return &aux_engine->base;
804 }
805 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
806 
807 static const struct dce_i2c_registers i2c_hw_regs[] = {
808 		i2c_inst_regs(1),
809 		i2c_inst_regs(2),
810 		i2c_inst_regs(3),
811 		i2c_inst_regs(4),
812 		i2c_inst_regs(5),
813 		i2c_inst_regs(6),
814 };
815 
816 static const struct dce_i2c_shift i2c_shifts = {
817 		I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
818 };
819 
820 static const struct dce_i2c_mask i2c_masks = {
821 		I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
822 };
823 
dcn20_i2c_hw_create(struct dc_context * ctx,uint32_t inst)824 struct dce_i2c_hw *dcn20_i2c_hw_create(
825 	struct dc_context *ctx,
826 	uint32_t inst)
827 {
828 	struct dce_i2c_hw *dce_i2c_hw =
829 		kzalloc(sizeof(struct dce_i2c_hw), GFP_ATOMIC);
830 
831 	if (!dce_i2c_hw)
832 		return NULL;
833 
834 	dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
835 				    &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
836 
837 	return dce_i2c_hw;
838 }
dcn20_mpc_create(struct dc_context * ctx)839 struct mpc *dcn20_mpc_create(struct dc_context *ctx)
840 {
841 	struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
842 					  GFP_ATOMIC);
843 
844 	if (!mpc20)
845 		return NULL;
846 
847 	dcn20_mpc_construct(mpc20, ctx,
848 			&mpc_regs,
849 			&mpc_shift,
850 			&mpc_mask,
851 			6);
852 
853 	return &mpc20->base;
854 }
855 
dcn20_hubbub_create(struct dc_context * ctx)856 struct hubbub *dcn20_hubbub_create(struct dc_context *ctx)
857 {
858 	int i;
859 	struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
860 					  GFP_ATOMIC);
861 
862 	if (!hubbub)
863 		return NULL;
864 
865 	hubbub2_construct(hubbub, ctx,
866 			&hubbub_reg,
867 			&hubbub_shift,
868 			&hubbub_mask);
869 
870 	for (i = 0; i < res_cap_nv10.num_vmid; i++) {
871 		struct dcn20_vmid *vmid = &hubbub->vmid[i];
872 
873 		vmid->ctx = ctx;
874 
875 		vmid->regs = &vmid_regs[i];
876 		vmid->shifts = &vmid_shifts;
877 		vmid->masks = &vmid_masks;
878 	}
879 
880 	return &hubbub->base;
881 }
882 
dcn20_timing_generator_create(struct dc_context * ctx,uint32_t instance)883 struct timing_generator *dcn20_timing_generator_create(
884 		struct dc_context *ctx,
885 		uint32_t instance)
886 {
887 	struct optc *tgn10 =
888 		kzalloc(sizeof(struct optc), GFP_ATOMIC);
889 
890 	if (!tgn10)
891 		return NULL;
892 
893 	tgn10->base.inst = instance;
894 	tgn10->base.ctx = ctx;
895 
896 	tgn10->tg_regs = &tg_regs[instance];
897 	tgn10->tg_shift = &tg_shift;
898 	tgn10->tg_mask = &tg_mask;
899 
900 	dcn20_timing_generator_init(tgn10);
901 
902 	return &tgn10->base;
903 }
904 
905 static const struct encoder_feature_support link_enc_feature = {
906 		.max_hdmi_deep_color = COLOR_DEPTH_121212,
907 		.max_hdmi_pixel_clock = 600000,
908 		.hdmi_ycbcr420_supported = true,
909 		.dp_ycbcr420_supported = true,
910 		.fec_supported = true,
911 		.flags.bits.IS_HBR2_CAPABLE = true,
912 		.flags.bits.IS_HBR3_CAPABLE = true,
913 		.flags.bits.IS_TPS3_CAPABLE = true,
914 		.flags.bits.IS_TPS4_CAPABLE = true
915 };
916 
dcn20_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)917 struct link_encoder *dcn20_link_encoder_create(
918 	struct dc_context *ctx,
919 	const struct encoder_init_data *enc_init_data)
920 {
921 	struct dcn20_link_encoder *enc20 =
922 		kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
923 	int link_regs_id;
924 
925 	if (!enc20)
926 		return NULL;
927 
928 	link_regs_id =
929 		map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
930 
931 	dcn20_link_encoder_construct(enc20,
932 				      enc_init_data,
933 				      &link_enc_feature,
934 				      &link_enc_regs[link_regs_id],
935 				      &link_enc_aux_regs[enc_init_data->channel - 1],
936 				      &link_enc_hpd_regs[enc_init_data->hpd_source],
937 				      &le_shift,
938 				      &le_mask);
939 
940 	return &enc20->enc10.base;
941 }
942 
dcn20_panel_cntl_create(const struct panel_cntl_init_data * init_data)943 static struct panel_cntl *dcn20_panel_cntl_create(const struct panel_cntl_init_data *init_data)
944 {
945 	struct dce_panel_cntl *panel_cntl =
946 		kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
947 
948 	if (!panel_cntl)
949 		return NULL;
950 
951 	dce_panel_cntl_construct(panel_cntl,
952 			init_data,
953 			&panel_cntl_regs[init_data->inst],
954 			&panel_cntl_shift,
955 			&panel_cntl_mask);
956 
957 	return &panel_cntl->base;
958 }
959 
dcn20_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)960 static struct clock_source *dcn20_clock_source_create(
961 	struct dc_context *ctx,
962 	struct dc_bios *bios,
963 	enum clock_source_id id,
964 	const struct dce110_clk_src_regs *regs,
965 	bool dp_clk_src)
966 {
967 	struct dce110_clk_src *clk_src =
968 		kzalloc(sizeof(struct dce110_clk_src), GFP_ATOMIC);
969 
970 	if (!clk_src)
971 		return NULL;
972 
973 	if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
974 			regs, &cs_shift, &cs_mask)) {
975 		clk_src->base.dp_clk_src = dp_clk_src;
976 		return &clk_src->base;
977 	}
978 
979 	kfree(clk_src);
980 	BREAK_TO_DEBUGGER();
981 	return NULL;
982 }
983 
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)984 static void read_dce_straps(
985 	struct dc_context *ctx,
986 	struct resource_straps *straps)
987 {
988 	generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
989 		FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
990 }
991 
dcn20_create_audio(struct dc_context * ctx,unsigned int inst)992 static struct audio *dcn20_create_audio(
993 		struct dc_context *ctx, unsigned int inst)
994 {
995 	return dce_audio_create(ctx, inst,
996 			&audio_regs[inst], &audio_shift, &audio_mask);
997 }
998 
dcn20_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)999 struct stream_encoder *dcn20_stream_encoder_create(
1000 	enum engine_id eng_id,
1001 	struct dc_context *ctx)
1002 {
1003 	struct dcn10_stream_encoder *enc1 =
1004 		kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1005 
1006 	if (!enc1)
1007 		return NULL;
1008 
1009 	if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
1010 		if (eng_id >= ENGINE_ID_DIGD)
1011 			eng_id++;
1012 	}
1013 
1014 	dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1015 					&stream_enc_regs[eng_id],
1016 					&se_shift, &se_mask);
1017 
1018 	return &enc1->base;
1019 }
1020 
1021 static const struct dce_hwseq_registers hwseq_reg = {
1022 		HWSEQ_DCN2_REG_LIST()
1023 };
1024 
1025 static const struct dce_hwseq_shift hwseq_shift = {
1026 		HWSEQ_DCN2_MASK_SH_LIST(__SHIFT)
1027 };
1028 
1029 static const struct dce_hwseq_mask hwseq_mask = {
1030 		HWSEQ_DCN2_MASK_SH_LIST(_MASK)
1031 };
1032 
dcn20_hwseq_create(struct dc_context * ctx)1033 struct dce_hwseq *dcn20_hwseq_create(
1034 	struct dc_context *ctx)
1035 {
1036 	struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1037 
1038 	if (hws) {
1039 		hws->ctx = ctx;
1040 		hws->regs = &hwseq_reg;
1041 		hws->shifts = &hwseq_shift;
1042 		hws->masks = &hwseq_mask;
1043 	}
1044 	return hws;
1045 }
1046 
1047 static const struct resource_create_funcs res_create_funcs = {
1048 	.read_dce_straps = read_dce_straps,
1049 	.create_audio = dcn20_create_audio,
1050 	.create_stream_encoder = dcn20_stream_encoder_create,
1051 	.create_hwseq = dcn20_hwseq_create,
1052 };
1053 
1054 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1055 
dcn20_clock_source_destroy(struct clock_source ** clk_src)1056 void dcn20_clock_source_destroy(struct clock_source **clk_src)
1057 {
1058 	kfree(TO_DCE110_CLK_SRC(*clk_src));
1059 	*clk_src = NULL;
1060 }
1061 
1062 
dcn20_dsc_create(struct dc_context * ctx,uint32_t inst)1063 struct display_stream_compressor *dcn20_dsc_create(
1064 	struct dc_context *ctx, uint32_t inst)
1065 {
1066 	struct dcn20_dsc *dsc =
1067 		kzalloc(sizeof(struct dcn20_dsc), GFP_ATOMIC);
1068 
1069 	if (!dsc) {
1070 		BREAK_TO_DEBUGGER();
1071 		return NULL;
1072 	}
1073 
1074 	dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1075 	return &dsc->base;
1076 }
1077 
dcn20_dsc_destroy(struct display_stream_compressor ** dsc)1078 void dcn20_dsc_destroy(struct display_stream_compressor **dsc)
1079 {
1080 	kfree(container_of(*dsc, struct dcn20_dsc, base));
1081 	*dsc = NULL;
1082 }
1083 
1084 
dcn20_resource_destruct(struct dcn20_resource_pool * pool)1085 static void dcn20_resource_destruct(struct dcn20_resource_pool *pool)
1086 {
1087 	unsigned int i;
1088 
1089 	for (i = 0; i < pool->base.stream_enc_count; i++) {
1090 		if (pool->base.stream_enc[i] != NULL) {
1091 			kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1092 			pool->base.stream_enc[i] = NULL;
1093 		}
1094 	}
1095 
1096 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1097 		if (pool->base.dscs[i] != NULL)
1098 			dcn20_dsc_destroy(&pool->base.dscs[i]);
1099 	}
1100 
1101 	if (pool->base.mpc != NULL) {
1102 		kfree(TO_DCN20_MPC(pool->base.mpc));
1103 		pool->base.mpc = NULL;
1104 	}
1105 	if (pool->base.hubbub != NULL) {
1106 		kfree(pool->base.hubbub);
1107 		pool->base.hubbub = NULL;
1108 	}
1109 	for (i = 0; i < pool->base.pipe_count; i++) {
1110 		if (pool->base.dpps[i] != NULL)
1111 			dcn20_dpp_destroy(&pool->base.dpps[i]);
1112 
1113 		if (pool->base.ipps[i] != NULL)
1114 			pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1115 
1116 		if (pool->base.hubps[i] != NULL) {
1117 			kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1118 			pool->base.hubps[i] = NULL;
1119 		}
1120 
1121 		if (pool->base.irqs != NULL) {
1122 			dal_irq_service_destroy(&pool->base.irqs);
1123 		}
1124 	}
1125 
1126 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1127 		if (pool->base.engines[i] != NULL)
1128 			dce110_engine_destroy(&pool->base.engines[i]);
1129 		if (pool->base.hw_i2cs[i] != NULL) {
1130 			kfree(pool->base.hw_i2cs[i]);
1131 			pool->base.hw_i2cs[i] = NULL;
1132 		}
1133 		if (pool->base.sw_i2cs[i] != NULL) {
1134 			kfree(pool->base.sw_i2cs[i]);
1135 			pool->base.sw_i2cs[i] = NULL;
1136 		}
1137 	}
1138 
1139 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1140 		if (pool->base.opps[i] != NULL)
1141 			pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1142 	}
1143 
1144 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1145 		if (pool->base.timing_generators[i] != NULL)	{
1146 			kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1147 			pool->base.timing_generators[i] = NULL;
1148 		}
1149 	}
1150 
1151 	for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1152 		if (pool->base.dwbc[i] != NULL) {
1153 			kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
1154 			pool->base.dwbc[i] = NULL;
1155 		}
1156 		if (pool->base.mcif_wb[i] != NULL) {
1157 			kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
1158 			pool->base.mcif_wb[i] = NULL;
1159 		}
1160 	}
1161 
1162 	for (i = 0; i < pool->base.audio_count; i++) {
1163 		if (pool->base.audios[i])
1164 			dce_aud_destroy(&pool->base.audios[i]);
1165 	}
1166 
1167 	for (i = 0; i < pool->base.clk_src_count; i++) {
1168 		if (pool->base.clock_sources[i] != NULL) {
1169 			dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1170 			pool->base.clock_sources[i] = NULL;
1171 		}
1172 	}
1173 
1174 	if (pool->base.dp_clock_source != NULL) {
1175 		dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1176 		pool->base.dp_clock_source = NULL;
1177 	}
1178 
1179 
1180 	if (pool->base.abm != NULL)
1181 		dce_abm_destroy(&pool->base.abm);
1182 
1183 	if (pool->base.dmcu != NULL)
1184 		dce_dmcu_destroy(&pool->base.dmcu);
1185 
1186 	if (pool->base.dccg != NULL)
1187 		dcn_dccg_destroy(&pool->base.dccg);
1188 
1189 	if (pool->base.pp_smu != NULL)
1190 		dcn20_pp_smu_destroy(&pool->base.pp_smu);
1191 
1192 	if (pool->base.oem_device != NULL) {
1193 		struct dc *dc = pool->base.oem_device->ctx->dc;
1194 
1195 		dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1196 	}
1197 }
1198 
dcn20_hubp_create(struct dc_context * ctx,uint32_t inst)1199 struct hubp *dcn20_hubp_create(
1200 	struct dc_context *ctx,
1201 	uint32_t inst)
1202 {
1203 	struct dcn20_hubp *hubp2 =
1204 		kzalloc(sizeof(struct dcn20_hubp), GFP_ATOMIC);
1205 
1206 	if (!hubp2)
1207 		return NULL;
1208 
1209 	if (hubp2_construct(hubp2, ctx, inst,
1210 			&hubp_regs[inst], &hubp_shift, &hubp_mask))
1211 		return &hubp2->base;
1212 
1213 	BREAK_TO_DEBUGGER();
1214 	kfree(hubp2);
1215 	return NULL;
1216 }
1217 
get_pixel_clock_parameters(struct pipe_ctx * pipe_ctx,struct pixel_clk_params * pixel_clk_params)1218 static void get_pixel_clock_parameters(
1219 	struct pipe_ctx *pipe_ctx,
1220 	struct pixel_clk_params *pixel_clk_params)
1221 {
1222 	const struct dc_stream_state *stream = pipe_ctx->stream;
1223 	struct pipe_ctx *odm_pipe;
1224 	int opp_cnt = 1;
1225 	struct dc_link *link = stream->link;
1226 	struct link_encoder *link_enc = NULL;
1227 	struct dc *dc = pipe_ctx->stream->ctx->dc;
1228 	struct dce_hwseq *hws = dc->hwseq;
1229 
1230 	for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1231 		opp_cnt++;
1232 
1233 	pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1234 
1235 	link_enc = link_enc_cfg_get_link_enc(link);
1236 	if (link_enc)
1237 		pixel_clk_params->encoder_object_id = link_enc->id;
1238 
1239 	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1240 	pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1241 	/* TODO: un-hardcode*/
1242 	/* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1243 	pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1244 		LINK_RATE_REF_FREQ_IN_KHZ;
1245 	pixel_clk_params->flags.ENABLE_SS = 0;
1246 	pixel_clk_params->color_depth =
1247 		stream->timing.display_color_depth;
1248 	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1249 	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1250 
1251 	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1252 		pixel_clk_params->color_depth = COLOR_DEPTH_888;
1253 
1254 	if (opp_cnt == 4)
1255 		pixel_clk_params->requested_pix_clk_100hz /= 4;
1256 	else if (optc2_is_two_pixels_per_containter(&stream->timing) || opp_cnt == 2)
1257 		pixel_clk_params->requested_pix_clk_100hz /= 2;
1258 	else if (hws->funcs.is_dp_dig_pixel_rate_div_policy) {
1259 		if (hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx))
1260 			pixel_clk_params->requested_pix_clk_100hz /= 2;
1261 	}
1262 
1263 	if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1264 		pixel_clk_params->requested_pix_clk_100hz *= 2;
1265 
1266 }
1267 
build_clamping_params(struct dc_stream_state * stream)1268 static void build_clamping_params(struct dc_stream_state *stream)
1269 {
1270 	stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
1271 	stream->clamping.c_depth = stream->timing.display_color_depth;
1272 	stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
1273 }
1274 
build_pipe_hw_param(struct pipe_ctx * pipe_ctx)1275 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
1276 {
1277 
1278 	get_pixel_clock_parameters(pipe_ctx, &pipe_ctx->stream_res.pix_clk_params);
1279 
1280 	pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1281 		pipe_ctx->clock_source,
1282 		&pipe_ctx->stream_res.pix_clk_params,
1283 		&pipe_ctx->pll_settings);
1284 
1285 	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
1286 
1287 	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
1288 					&pipe_ctx->stream->bit_depth_params);
1289 	build_clamping_params(pipe_ctx->stream);
1290 
1291 	return DC_OK;
1292 }
1293 
dcn20_build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)1294 enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state *context, struct dc_stream_state *stream)
1295 {
1296 	enum dc_status status = DC_OK;
1297 	struct pipe_ctx *pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, stream);
1298 
1299 	if (!pipe_ctx)
1300 		return DC_ERROR_UNEXPECTED;
1301 
1302 
1303 	status = build_pipe_hw_param(pipe_ctx);
1304 
1305 	return status;
1306 }
1307 
1308 
dcn20_acquire_dsc(const struct dc * dc,struct resource_context * res_ctx,struct display_stream_compressor ** dsc,int pipe_idx)1309 void dcn20_acquire_dsc(const struct dc *dc,
1310 			struct resource_context *res_ctx,
1311 			struct display_stream_compressor **dsc,
1312 			int pipe_idx)
1313 {
1314 	int i;
1315 	const struct resource_pool *pool = dc->res_pool;
1316 	struct display_stream_compressor *dsc_old = dc->current_state->res_ctx.pipe_ctx[pipe_idx].stream_res.dsc;
1317 
1318 	ASSERT(*dsc == NULL); /* If this ASSERT fails, dsc was not released properly */
1319 	*dsc = NULL;
1320 
1321 	/* Always do 1-to-1 mapping when number of DSCs is same as number of pipes */
1322 	if (pool->res_cap->num_dsc == pool->res_cap->num_opp) {
1323 		*dsc = pool->dscs[pipe_idx];
1324 		res_ctx->is_dsc_acquired[pipe_idx] = true;
1325 		return;
1326 	}
1327 
1328 	/* Return old DSC to avoid the need for re-programming */
1329 	if (dsc_old && !res_ctx->is_dsc_acquired[dsc_old->inst]) {
1330 		*dsc = dsc_old;
1331 		res_ctx->is_dsc_acquired[dsc_old->inst] = true;
1332 		return ;
1333 	}
1334 
1335 	/* Find first free DSC */
1336 	for (i = 0; i < pool->res_cap->num_dsc; i++)
1337 		if (!res_ctx->is_dsc_acquired[i]) {
1338 			*dsc = pool->dscs[i];
1339 			res_ctx->is_dsc_acquired[i] = true;
1340 			break;
1341 		}
1342 }
1343 
dcn20_release_dsc(struct resource_context * res_ctx,const struct resource_pool * pool,struct display_stream_compressor ** dsc)1344 void dcn20_release_dsc(struct resource_context *res_ctx,
1345 			const struct resource_pool *pool,
1346 			struct display_stream_compressor **dsc)
1347 {
1348 	int i;
1349 
1350 	for (i = 0; i < pool->res_cap->num_dsc; i++)
1351 		if (pool->dscs[i] == *dsc) {
1352 			res_ctx->is_dsc_acquired[i] = false;
1353 			*dsc = NULL;
1354 			break;
1355 		}
1356 }
1357 
1358 
1359 
dcn20_add_dsc_to_stream_resource(struct dc * dc,struct dc_state * dc_ctx,struct dc_stream_state * dc_stream)1360 enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc,
1361 		struct dc_state *dc_ctx,
1362 		struct dc_stream_state *dc_stream)
1363 {
1364 	enum dc_status result = DC_OK;
1365 	int i;
1366 
1367 	/* Get a DSC if required and available */
1368 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1369 		struct pipe_ctx *pipe_ctx = &dc_ctx->res_ctx.pipe_ctx[i];
1370 
1371 		if (pipe_ctx->top_pipe)
1372 			continue;
1373 
1374 		if (pipe_ctx->stream != dc_stream)
1375 			continue;
1376 
1377 		if (pipe_ctx->stream_res.dsc)
1378 			continue;
1379 
1380 		dcn20_acquire_dsc(dc, &dc_ctx->res_ctx, &pipe_ctx->stream_res.dsc, i);
1381 
1382 		/* The number of DSCs can be less than the number of pipes */
1383 		if (!pipe_ctx->stream_res.dsc) {
1384 			result = DC_NO_DSC_RESOURCE;
1385 		}
1386 
1387 		break;
1388 	}
1389 
1390 	return result;
1391 }
1392 
1393 
remove_dsc_from_stream_resource(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1394 static enum dc_status remove_dsc_from_stream_resource(struct dc *dc,
1395 		struct dc_state *new_ctx,
1396 		struct dc_stream_state *dc_stream)
1397 {
1398 	struct pipe_ctx *pipe_ctx = NULL;
1399 	int i;
1400 
1401 	for (i = 0; i < MAX_PIPES; i++) {
1402 		if (new_ctx->res_ctx.pipe_ctx[i].stream == dc_stream && !new_ctx->res_ctx.pipe_ctx[i].top_pipe) {
1403 			pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1404 
1405 			if (pipe_ctx->stream_res.dsc)
1406 				dcn20_release_dsc(&new_ctx->res_ctx, dc->res_pool, &pipe_ctx->stream_res.dsc);
1407 		}
1408 	}
1409 
1410 	if (!pipe_ctx)
1411 		return DC_ERROR_UNEXPECTED;
1412 	else
1413 		return DC_OK;
1414 }
1415 
1416 
dcn20_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1417 enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1418 {
1419 	enum dc_status result = DC_ERROR_UNEXPECTED;
1420 
1421 	result = resource_map_pool_resources(dc, new_ctx, dc_stream);
1422 
1423 	if (result == DC_OK)
1424 		result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream);
1425 
1426 	/* Get a DSC if required and available */
1427 	if (result == DC_OK && dc_stream->timing.flags.DSC)
1428 		result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream);
1429 
1430 	if (result == DC_OK)
1431 		result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream);
1432 
1433 	return result;
1434 }
1435 
1436 
dcn20_remove_stream_from_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)1437 enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream)
1438 {
1439 	enum dc_status result = DC_OK;
1440 
1441 	result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream);
1442 
1443 	return result;
1444 }
1445 
1446 /**
1447  * dcn20_split_stream_for_odm - Check if stream can be splited for ODM
1448  *
1449  * @dc: DC object with resource pool info required for pipe split
1450  * @res_ctx: Persistent state of resources
1451  * @prev_odm_pipe: Reference to the previous ODM pipe
1452  * @next_odm_pipe: Reference to the next ODM pipe
1453  *
1454  * This function takes a logically active pipe and a logically free pipe and
1455  * halves all the scaling parameters that need to be halved while populating
1456  * the free pipe with the required resources and configuring the next/previous
1457  * ODM pipe pointers.
1458  *
1459  * Return:
1460  * Return true if split stream for ODM is possible, otherwise, return false.
1461  */
dcn20_split_stream_for_odm(const struct dc * dc,struct resource_context * res_ctx,struct pipe_ctx * prev_odm_pipe,struct pipe_ctx * next_odm_pipe)1462 bool dcn20_split_stream_for_odm(
1463 		const struct dc *dc,
1464 		struct resource_context *res_ctx,
1465 		struct pipe_ctx *prev_odm_pipe,
1466 		struct pipe_ctx *next_odm_pipe)
1467 {
1468 	int pipe_idx = next_odm_pipe->pipe_idx;
1469 	const struct resource_pool *pool = dc->res_pool;
1470 
1471 	*next_odm_pipe = *prev_odm_pipe;
1472 
1473 	next_odm_pipe->pipe_idx = pipe_idx;
1474 	next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
1475 	next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
1476 	next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
1477 	next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
1478 	next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
1479 	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
1480 	next_odm_pipe->stream_res.dsc = NULL;
1481 	if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
1482 		next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
1483 		next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe;
1484 	}
1485 	if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) {
1486 		prev_odm_pipe->top_pipe->next_odm_pipe->bottom_pipe = next_odm_pipe;
1487 		next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe;
1488 	}
1489 	if (prev_odm_pipe->bottom_pipe && prev_odm_pipe->bottom_pipe->next_odm_pipe) {
1490 		prev_odm_pipe->bottom_pipe->next_odm_pipe->top_pipe = next_odm_pipe;
1491 		next_odm_pipe->bottom_pipe = prev_odm_pipe->bottom_pipe->next_odm_pipe;
1492 	}
1493 	prev_odm_pipe->next_odm_pipe = next_odm_pipe;
1494 	next_odm_pipe->prev_odm_pipe = prev_odm_pipe;
1495 
1496 	if (prev_odm_pipe->plane_state) {
1497 		struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data;
1498 		int new_width;
1499 
1500 		/* HACTIVE halved for odm combine */
1501 		sd->h_active /= 2;
1502 		/* Calculate new vp and recout for left pipe */
1503 		/* Need at least 16 pixels width per side */
1504 		if (sd->recout.x + 16 >= sd->h_active)
1505 			return false;
1506 		new_width = sd->h_active - sd->recout.x;
1507 		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1508 				sd->ratios.horz, sd->recout.width - new_width));
1509 		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1510 				sd->ratios.horz_c, sd->recout.width - new_width));
1511 		sd->recout.width = new_width;
1512 
1513 		/* Calculate new vp and recout for right pipe */
1514 		sd = &next_odm_pipe->plane_res.scl_data;
1515 		/* HACTIVE halved for odm combine */
1516 		sd->h_active /= 2;
1517 		/* Need at least 16 pixels width per side */
1518 		if (new_width <= 16)
1519 			return false;
1520 		new_width = sd->recout.width + sd->recout.x - sd->h_active;
1521 		sd->viewport.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1522 				sd->ratios.horz, sd->recout.width - new_width));
1523 		sd->viewport_c.width -= dc_fixpt_floor(dc_fixpt_mul_int(
1524 				sd->ratios.horz_c, sd->recout.width - new_width));
1525 		sd->recout.width = new_width;
1526 		sd->viewport.x += dc_fixpt_floor(dc_fixpt_mul_int(
1527 				sd->ratios.horz, sd->h_active - sd->recout.x));
1528 		sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int(
1529 				sd->ratios.horz_c, sd->h_active - sd->recout.x));
1530 		sd->recout.x = 0;
1531 	}
1532 	if (!next_odm_pipe->top_pipe)
1533 		next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx];
1534 	else
1535 		next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp;
1536 	if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) {
1537 		dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx);
1538 		ASSERT(next_odm_pipe->stream_res.dsc);
1539 		if (next_odm_pipe->stream_res.dsc == NULL)
1540 			return false;
1541 	}
1542 
1543 	return true;
1544 }
1545 
dcn20_split_stream_for_mpc(struct resource_context * res_ctx,const struct resource_pool * pool,struct pipe_ctx * primary_pipe,struct pipe_ctx * secondary_pipe)1546 void dcn20_split_stream_for_mpc(
1547 		struct resource_context *res_ctx,
1548 		const struct resource_pool *pool,
1549 		struct pipe_ctx *primary_pipe,
1550 		struct pipe_ctx *secondary_pipe)
1551 {
1552 	int pipe_idx = secondary_pipe->pipe_idx;
1553 	struct pipe_ctx *sec_bot_pipe = secondary_pipe->bottom_pipe;
1554 
1555 	*secondary_pipe = *primary_pipe;
1556 	secondary_pipe->bottom_pipe = sec_bot_pipe;
1557 
1558 	secondary_pipe->pipe_idx = pipe_idx;
1559 	secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
1560 	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
1561 	secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
1562 	secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
1563 	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
1564 	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
1565 	secondary_pipe->stream_res.dsc = NULL;
1566 	if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
1567 		ASSERT(!secondary_pipe->bottom_pipe);
1568 		secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
1569 		secondary_pipe->bottom_pipe->top_pipe = secondary_pipe;
1570 	}
1571 	primary_pipe->bottom_pipe = secondary_pipe;
1572 	secondary_pipe->top_pipe = primary_pipe;
1573 
1574 	ASSERT(primary_pipe->plane_state);
1575 }
1576 
dcn20_calc_max_scaled_time(unsigned int time_per_pixel,enum mmhubbub_wbif_mode mode,unsigned int urgent_watermark)1577 unsigned int dcn20_calc_max_scaled_time(
1578 		unsigned int time_per_pixel,
1579 		enum mmhubbub_wbif_mode mode,
1580 		unsigned int urgent_watermark)
1581 {
1582 	unsigned int time_per_byte = 0;
1583 	unsigned int total_y_free_entry = 0x200; /* two memory piece for luma */
1584 	unsigned int total_c_free_entry = 0x140; /* two memory piece for chroma */
1585 	unsigned int small_free_entry, max_free_entry;
1586 	unsigned int buf_lh_capability;
1587 	unsigned int max_scaled_time;
1588 
1589 	if (mode == PACKED_444) /* packed mode */
1590 		time_per_byte = time_per_pixel/4;
1591 	else if (mode == PLANAR_420_8BPC)
1592 		time_per_byte  = time_per_pixel;
1593 	else if (mode == PLANAR_420_10BPC) /* p010 */
1594 		time_per_byte  = time_per_pixel * 819/1024;
1595 
1596 	if (time_per_byte == 0)
1597 		time_per_byte = 1;
1598 
1599 	small_free_entry  = (total_y_free_entry > total_c_free_entry) ? total_c_free_entry : total_y_free_entry;
1600 	max_free_entry    = (mode == PACKED_444) ? total_y_free_entry + total_c_free_entry : small_free_entry;
1601 	buf_lh_capability = max_free_entry*time_per_byte*32/16; /* there is 4bit fraction */
1602 	max_scaled_time   = buf_lh_capability - urgent_watermark;
1603 	return max_scaled_time;
1604 }
1605 
dcn20_set_mcif_arb_params(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int pipe_cnt)1606 void dcn20_set_mcif_arb_params(
1607 		struct dc *dc,
1608 		struct dc_state *context,
1609 		display_e2e_pipe_params_st *pipes,
1610 		int pipe_cnt)
1611 {
1612 	enum mmhubbub_wbif_mode wbif_mode;
1613 	struct mcif_arb_params *wb_arb_params;
1614 	int i, j, dwb_pipe;
1615 
1616 	/* Writeback MCIF_WB arbitration parameters */
1617 	dwb_pipe = 0;
1618 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1619 
1620 		if (!context->res_ctx.pipe_ctx[i].stream)
1621 			continue;
1622 
1623 		for (j = 0; j < MAX_DWB_PIPES; j++) {
1624 			if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].wb_enabled == false)
1625 				continue;
1626 
1627 			//wb_arb_params = &context->res_ctx.pipe_ctx[i].stream->writeback_info[j].mcif_arb_params;
1628 			wb_arb_params = &context->bw_ctx.bw.dcn.bw_writeback.mcif_wb_arb[dwb_pipe];
1629 
1630 			if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.out_format == dwb_scaler_mode_yuv420) {
1631 				if (context->res_ctx.pipe_ctx[i].stream->writeback_info[j].dwb_params.output_depth == DWB_OUTPUT_PIXEL_DEPTH_8BPC)
1632 					wbif_mode = PLANAR_420_8BPC;
1633 				else
1634 					wbif_mode = PLANAR_420_10BPC;
1635 			} else
1636 				wbif_mode = PACKED_444;
1637 
1638 			DC_FP_START();
1639 			dcn20_fpu_set_wb_arb_params(wb_arb_params, context, pipes, pipe_cnt, i);
1640 			DC_FP_END();
1641 
1642 			wb_arb_params->slice_lines = 32;
1643 			wb_arb_params->arbitration_slice = 2;
1644 			wb_arb_params->max_scaled_time = dcn20_calc_max_scaled_time(wb_arb_params->time_per_pixel,
1645 				wbif_mode,
1646 				wb_arb_params->cli_watermark[0]); /* assume 4 watermark sets have the same value */
1647 
1648 			dwb_pipe++;
1649 
1650 			if (dwb_pipe >= MAX_DWB_PIPES)
1651 				return;
1652 		}
1653 		if (dwb_pipe >= MAX_DWB_PIPES)
1654 			return;
1655 	}
1656 }
1657 
dcn20_validate_dsc(struct dc * dc,struct dc_state * new_ctx)1658 bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx)
1659 {
1660 	int i;
1661 
1662 	/* Validate DSC config, dsc count validation is already done */
1663 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1664 		struct pipe_ctx *pipe_ctx = &new_ctx->res_ctx.pipe_ctx[i];
1665 		struct dc_stream_state *stream = pipe_ctx->stream;
1666 		struct dsc_config dsc_cfg;
1667 		struct pipe_ctx *odm_pipe;
1668 		int opp_cnt = 1;
1669 
1670 		for (odm_pipe = pipe_ctx->next_odm_pipe; odm_pipe; odm_pipe = odm_pipe->next_odm_pipe)
1671 			opp_cnt++;
1672 
1673 		/* Only need to validate top pipe */
1674 		if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe || !stream || !stream->timing.flags.DSC)
1675 			continue;
1676 
1677 		dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left
1678 				+ stream->timing.h_border_right) / opp_cnt;
1679 		dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top
1680 				+ stream->timing.v_border_bottom;
1681 		dsc_cfg.pixel_encoding = stream->timing.pixel_encoding;
1682 		dsc_cfg.color_depth = stream->timing.display_color_depth;
1683 		dsc_cfg.is_odm = pipe_ctx->next_odm_pipe ? true : false;
1684 		dsc_cfg.dc_dsc_cfg = stream->timing.dsc_cfg;
1685 		dsc_cfg.dc_dsc_cfg.num_slices_h /= opp_cnt;
1686 
1687 		if (!pipe_ctx->stream_res.dsc->funcs->dsc_validate_stream(pipe_ctx->stream_res.dsc, &dsc_cfg))
1688 			return false;
1689 	}
1690 	return true;
1691 }
1692 
dcn20_find_secondary_pipe(struct dc * dc,struct resource_context * res_ctx,const struct resource_pool * pool,const struct pipe_ctx * primary_pipe)1693 struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
1694 		struct resource_context *res_ctx,
1695 		const struct resource_pool *pool,
1696 		const struct pipe_ctx *primary_pipe)
1697 {
1698 	struct pipe_ctx *secondary_pipe = NULL;
1699 
1700 	if (dc && primary_pipe) {
1701 		int j;
1702 		int preferred_pipe_idx = 0;
1703 
1704 		/* first check the prev dc state:
1705 		 * if this primary pipe has a bottom pipe in prev. state
1706 		 * and if the bottom pipe is still available (which it should be),
1707 		 * pick that pipe as secondary
1708 		 * Same logic applies for ODM pipes
1709 		 */
1710 		if (dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe) {
1711 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
1712 			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1713 				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1714 				secondary_pipe->pipe_idx = preferred_pipe_idx;
1715 			}
1716 		}
1717 		if (secondary_pipe == NULL &&
1718 				dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe) {
1719 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
1720 			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1721 				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1722 				secondary_pipe->pipe_idx = preferred_pipe_idx;
1723 			}
1724 		}
1725 
1726 		/*
1727 		 * if this primary pipe does not have a bottom pipe in prev. state
1728 		 * start backward and find a pipe that did not used to be a bottom pipe in
1729 		 * prev. dc state. This way we make sure we keep the same assignment as
1730 		 * last state and will not have to reprogram every pipe
1731 		 */
1732 		if (secondary_pipe == NULL) {
1733 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
1734 				if (dc->current_state->res_ctx.pipe_ctx[j].top_pipe == NULL
1735 						&& dc->current_state->res_ctx.pipe_ctx[j].prev_odm_pipe == NULL) {
1736 					preferred_pipe_idx = j;
1737 
1738 					if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1739 						secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1740 						secondary_pipe->pipe_idx = preferred_pipe_idx;
1741 						break;
1742 					}
1743 				}
1744 			}
1745 		}
1746 		/*
1747 		 * We should never hit this assert unless assignments are shuffled around
1748 		 * if this happens we will prob. hit a vsync tdr
1749 		 */
1750 		ASSERT(secondary_pipe);
1751 		/*
1752 		 * search backwards for the second pipe to keep pipe
1753 		 * assignment more consistent
1754 		 */
1755 		if (secondary_pipe == NULL) {
1756 			for (j = dc->res_pool->pipe_count - 1; j >= 0; j--) {
1757 				preferred_pipe_idx = j;
1758 
1759 				if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
1760 					secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
1761 					secondary_pipe->pipe_idx = preferred_pipe_idx;
1762 					break;
1763 				}
1764 			}
1765 		}
1766 	}
1767 
1768 	return secondary_pipe;
1769 }
1770 
dcn20_merge_pipes_for_validate(struct dc * dc,struct dc_state * context)1771 void dcn20_merge_pipes_for_validate(
1772 		struct dc *dc,
1773 		struct dc_state *context)
1774 {
1775 	int i;
1776 
1777 	/* merge previously split odm pipes since mode support needs to make the decision */
1778 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1779 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1780 		struct pipe_ctx *odm_pipe = pipe->next_odm_pipe;
1781 
1782 		if (pipe->prev_odm_pipe)
1783 			continue;
1784 
1785 		pipe->next_odm_pipe = NULL;
1786 		while (odm_pipe) {
1787 			struct pipe_ctx *next_odm_pipe = odm_pipe->next_odm_pipe;
1788 
1789 			odm_pipe->plane_state = NULL;
1790 			odm_pipe->stream = NULL;
1791 			odm_pipe->top_pipe = NULL;
1792 			odm_pipe->bottom_pipe = NULL;
1793 			odm_pipe->prev_odm_pipe = NULL;
1794 			odm_pipe->next_odm_pipe = NULL;
1795 			if (odm_pipe->stream_res.dsc)
1796 				dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc);
1797 			/* Clear plane_res and stream_res */
1798 			memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res));
1799 			memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res));
1800 			odm_pipe = next_odm_pipe;
1801 		}
1802 		if (pipe->plane_state)
1803 			resource_build_scaling_params(pipe);
1804 	}
1805 
1806 	/* merge previously mpc split pipes since mode support needs to make the decision */
1807 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1808 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1809 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1810 
1811 		if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state)
1812 			continue;
1813 
1814 		pipe->bottom_pipe = hsplit_pipe->bottom_pipe;
1815 		if (hsplit_pipe->bottom_pipe)
1816 			hsplit_pipe->bottom_pipe->top_pipe = pipe;
1817 		hsplit_pipe->plane_state = NULL;
1818 		hsplit_pipe->stream = NULL;
1819 		hsplit_pipe->top_pipe = NULL;
1820 		hsplit_pipe->bottom_pipe = NULL;
1821 
1822 		/* Clear plane_res and stream_res */
1823 		memset(&hsplit_pipe->plane_res, 0, sizeof(hsplit_pipe->plane_res));
1824 		memset(&hsplit_pipe->stream_res, 0, sizeof(hsplit_pipe->stream_res));
1825 		if (pipe->plane_state)
1826 			resource_build_scaling_params(pipe);
1827 	}
1828 }
1829 
dcn20_validate_apply_pipe_split_flags(struct dc * dc,struct dc_state * context,int vlevel,int * split,bool * merge)1830 int dcn20_validate_apply_pipe_split_flags(
1831 		struct dc *dc,
1832 		struct dc_state *context,
1833 		int vlevel,
1834 		int *split,
1835 		bool *merge)
1836 {
1837 	int i, pipe_idx, vlevel_split;
1838 	int plane_count = 0;
1839 	bool force_split = false;
1840 	bool avoid_split = dc->debug.pipe_split_policy == MPC_SPLIT_AVOID;
1841 	struct vba_vars_st *v = &context->bw_ctx.dml.vba;
1842 	int max_mpc_comb = v->maxMpcComb;
1843 
1844 	if (context->stream_count > 1) {
1845 		if (dc->debug.pipe_split_policy == MPC_SPLIT_AVOID_MULT_DISP)
1846 			avoid_split = true;
1847 	} else if (dc->debug.force_single_disp_pipe_split)
1848 			force_split = true;
1849 
1850 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1851 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1852 
1853 		/**
1854 		 * Workaround for avoiding pipe-split in cases where we'd split
1855 		 * planes that are too small, resulting in splits that aren't
1856 		 * valid for the scaler.
1857 		 */
1858 		if (pipe->plane_state &&
1859 		    (pipe->plane_state->dst_rect.width <= 16 ||
1860 		     pipe->plane_state->dst_rect.height <= 16 ||
1861 		     pipe->plane_state->src_rect.width <= 16 ||
1862 		     pipe->plane_state->src_rect.height <= 16))
1863 			avoid_split = true;
1864 
1865 		/* TODO: fix dc bugs and remove this split threshold thing */
1866 		if (pipe->stream && !pipe->prev_odm_pipe &&
1867 				(!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state))
1868 			++plane_count;
1869 	}
1870 	if (plane_count > dc->res_pool->pipe_count / 2)
1871 		avoid_split = true;
1872 
1873 	/* W/A: Mode timing with borders may not work well with pipe split, avoid for this corner case */
1874 	for (i = 0; i < dc->res_pool->pipe_count; i++) {
1875 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1876 		struct dc_crtc_timing timing;
1877 
1878 		if (!pipe->stream)
1879 			continue;
1880 		else {
1881 			timing = pipe->stream->timing;
1882 			if (timing.h_border_left + timing.h_border_right
1883 					+ timing.v_border_top + timing.v_border_bottom > 0) {
1884 				avoid_split = true;
1885 				break;
1886 			}
1887 		}
1888 	}
1889 
1890 	/* Avoid split loop looks for lowest voltage level that allows most unsplit pipes possible */
1891 	if (avoid_split) {
1892 		for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1893 			if (!context->res_ctx.pipe_ctx[i].stream)
1894 				continue;
1895 
1896 			for (vlevel_split = vlevel; vlevel <= context->bw_ctx.dml.soc.num_states; vlevel++)
1897 				if (v->NoOfDPP[vlevel][0][pipe_idx] == 1 &&
1898 						v->ModeSupport[vlevel][0])
1899 					break;
1900 			/* Impossible to not split this pipe */
1901 			if (vlevel > context->bw_ctx.dml.soc.num_states)
1902 				vlevel = vlevel_split;
1903 			else
1904 				max_mpc_comb = 0;
1905 			pipe_idx++;
1906 		}
1907 		v->maxMpcComb = max_mpc_comb;
1908 	}
1909 
1910 	/* Split loop sets which pipe should be split based on dml outputs and dc flags */
1911 	for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1912 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1913 		int pipe_plane = v->pipe_plane[pipe_idx];
1914 		bool split4mpc = context->stream_count == 1 && plane_count == 1
1915 				&& dc->config.enable_4to1MPC && dc->res_pool->pipe_count >= 4;
1916 
1917 		if (!context->res_ctx.pipe_ctx[i].stream)
1918 			continue;
1919 
1920 		if (split4mpc || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 4)
1921 			split[i] = 4;
1922 		else if (force_split || v->NoOfDPP[vlevel][max_mpc_comb][pipe_plane] == 2)
1923 				split[i] = 2;
1924 
1925 		if ((pipe->stream->view_format ==
1926 				VIEW_3D_FORMAT_SIDE_BY_SIDE ||
1927 				pipe->stream->view_format ==
1928 				VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
1929 				(pipe->stream->timing.timing_3d_format ==
1930 				TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
1931 				 pipe->stream->timing.timing_3d_format ==
1932 				TIMING_3D_FORMAT_SIDE_BY_SIDE))
1933 			split[i] = 2;
1934 		if (dc->debug.force_odm_combine & (1 << pipe->stream_res.tg->inst)) {
1935 			split[i] = 2;
1936 			v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_2to1;
1937 		}
1938 		if (dc->debug.force_odm_combine_4to1 & (1 << pipe->stream_res.tg->inst)) {
1939 			split[i] = 4;
1940 			v->ODMCombineEnablePerState[vlevel][pipe_plane] = dm_odm_combine_mode_4to1;
1941 		}
1942 		/*420 format workaround*/
1943 		if (pipe->stream->timing.h_addressable > 7680 &&
1944 				pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1945 			split[i] = 4;
1946 		}
1947 		v->ODMCombineEnabled[pipe_plane] =
1948 			v->ODMCombineEnablePerState[vlevel][pipe_plane];
1949 
1950 		if (v->ODMCombineEnabled[pipe_plane] == dm_odm_combine_mode_disabled) {
1951 			if (resource_get_num_mpc_splits(pipe) == 1) {
1952 				/*If need split for mpc but 2 way split already*/
1953 				if (split[i] == 4)
1954 					split[i] = 2; /* 2 -> 4 MPC */
1955 				else if (split[i] == 2)
1956 					split[i] = 0; /* 2 -> 2 MPC */
1957 				else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state)
1958 					merge[i] = true; /* 2 -> 1 MPC */
1959 			} else if (resource_get_num_mpc_splits(pipe) == 3) {
1960 				/*If need split for mpc but 4 way split already*/
1961 				if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe)
1962 						|| !pipe->bottom_pipe)) {
1963 					merge[i] = true; /* 4 -> 2 MPC */
1964 				} else if (split[i] == 0 && pipe->top_pipe &&
1965 						pipe->top_pipe->plane_state == pipe->plane_state)
1966 					merge[i] = true; /* 4 -> 1 MPC */
1967 				split[i] = 0;
1968 			} else if (resource_get_num_odm_splits(pipe)) {
1969 				/* ODM -> MPC transition */
1970 				if (pipe->prev_odm_pipe) {
1971 					split[i] = 0;
1972 					merge[i] = true;
1973 				}
1974 			}
1975 		} else {
1976 			if (resource_get_num_odm_splits(pipe) == 1) {
1977 				/*If need split for odm but 2 way split already*/
1978 				if (split[i] == 4)
1979 					split[i] = 2; /* 2 -> 4 ODM */
1980 				else if (split[i] == 2)
1981 					split[i] = 0; /* 2 -> 2 ODM */
1982 				else if (pipe->prev_odm_pipe) {
1983 					ASSERT(0); /* NOT expected yet */
1984 					merge[i] = true; /* exit ODM */
1985 				}
1986 			} else if (resource_get_num_odm_splits(pipe) == 3) {
1987 				/*If need split for odm but 4 way split already*/
1988 				if (split[i] == 2 && ((pipe->prev_odm_pipe && !pipe->prev_odm_pipe->prev_odm_pipe)
1989 						|| !pipe->next_odm_pipe)) {
1990 					merge[i] = true; /* 4 -> 2 ODM */
1991 				} else if (split[i] == 0 && pipe->prev_odm_pipe) {
1992 					ASSERT(0); /* NOT expected yet */
1993 					merge[i] = true; /* exit ODM */
1994 				}
1995 				split[i] = 0;
1996 			} else if (resource_get_num_mpc_splits(pipe)) {
1997 				/* MPC -> ODM transition */
1998 				ASSERT(0); /* NOT expected yet */
1999 				if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) {
2000 					split[i] = 0;
2001 					merge[i] = true;
2002 				}
2003 			}
2004 		}
2005 
2006 		/* Adjust dppclk when split is forced, do not bother with dispclk */
2007 		if (split[i] != 0 && v->NoOfDPP[vlevel][max_mpc_comb][pipe_idx] == 1) {
2008 			DC_FP_START();
2009 			dcn20_fpu_adjust_dppclk(v, vlevel, max_mpc_comb, pipe_idx, false);
2010 			DC_FP_END();
2011 		}
2012 		pipe_idx++;
2013 	}
2014 
2015 	return vlevel;
2016 }
2017 
dcn20_fast_validate_bw(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * pipe_cnt_out,int * pipe_split_from,int * vlevel_out,bool fast_validate)2018 bool dcn20_fast_validate_bw(
2019 		struct dc *dc,
2020 		struct dc_state *context,
2021 		display_e2e_pipe_params_st *pipes,
2022 		int *pipe_cnt_out,
2023 		int *pipe_split_from,
2024 		int *vlevel_out,
2025 		bool fast_validate)
2026 {
2027 	bool out = false;
2028 	int split[MAX_PIPES] = { 0 };
2029 	bool merge[MAX_PIPES] = { false };
2030 	int pipe_cnt, i, pipe_idx, vlevel;
2031 
2032 	ASSERT(pipes);
2033 	if (!pipes)
2034 		return false;
2035 
2036 	dcn20_merge_pipes_for_validate(dc, context);
2037 
2038 	DC_FP_START();
2039 	pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
2040 	DC_FP_END();
2041 
2042 	*pipe_cnt_out = pipe_cnt;
2043 
2044 	if (!pipe_cnt) {
2045 		out = true;
2046 		goto validate_out;
2047 	}
2048 
2049 	vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
2050 
2051 	if (vlevel > context->bw_ctx.dml.soc.num_states)
2052 		goto validate_fail;
2053 
2054 	vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, merge);
2055 
2056 	/*initialize pipe_just_split_from to invalid idx*/
2057 	for (i = 0; i < MAX_PIPES; i++)
2058 		pipe_split_from[i] = -1;
2059 
2060 	for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
2061 		struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
2062 		struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
2063 
2064 		if (!pipe->stream || pipe_split_from[i] >= 0)
2065 			continue;
2066 
2067 		pipe_idx++;
2068 
2069 		if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2070 			hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2071 			ASSERT(hsplit_pipe);
2072 			if (!dcn20_split_stream_for_odm(
2073 					dc, &context->res_ctx,
2074 					pipe, hsplit_pipe))
2075 				goto validate_fail;
2076 			pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2077 			dcn20_build_mapped_resource(dc, context, pipe->stream);
2078 		}
2079 
2080 		if (!pipe->plane_state)
2081 			continue;
2082 		/* Skip 2nd half of already split pipe */
2083 		if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
2084 			continue;
2085 
2086 		/* We do not support mpo + odm at the moment */
2087 		if (hsplit_pipe && hsplit_pipe->plane_state != pipe->plane_state
2088 				&& context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx])
2089 			goto validate_fail;
2090 
2091 		if (split[i] == 2) {
2092 			if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
2093 				/* pipe not split previously needs split */
2094 				hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
2095 				ASSERT(hsplit_pipe);
2096 				if (!hsplit_pipe) {
2097 					DC_FP_START();
2098 					dcn20_fpu_adjust_dppclk(&context->bw_ctx.dml.vba, vlevel, context->bw_ctx.dml.vba.maxMpcComb, pipe_idx, true);
2099 					DC_FP_END();
2100 					continue;
2101 				}
2102 				if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
2103 					if (!dcn20_split_stream_for_odm(
2104 							dc, &context->res_ctx,
2105 							pipe, hsplit_pipe))
2106 						goto validate_fail;
2107 					dcn20_build_mapped_resource(dc, context, pipe->stream);
2108 				} else {
2109 					dcn20_split_stream_for_mpc(
2110 							&context->res_ctx, dc->res_pool,
2111 							pipe, hsplit_pipe);
2112 					resource_build_scaling_params(pipe);
2113 					resource_build_scaling_params(hsplit_pipe);
2114 				}
2115 				pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
2116 			}
2117 		} else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
2118 			/* merge should already have been done */
2119 			ASSERT(0);
2120 		}
2121 	}
2122 	/* Actual dsc count per stream dsc validation*/
2123 	if (!dcn20_validate_dsc(dc, context)) {
2124 		context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
2125 				DML_FAIL_DSC_VALIDATION_FAILURE;
2126 		goto validate_fail;
2127 	}
2128 
2129 	*vlevel_out = vlevel;
2130 
2131 	out = true;
2132 	goto validate_out;
2133 
2134 validate_fail:
2135 	out = false;
2136 
2137 validate_out:
2138 	return out;
2139 }
2140 
dcn20_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)2141 bool dcn20_validate_bandwidth(struct dc *dc, struct dc_state *context,
2142 		bool fast_validate)
2143 {
2144 	bool voltage_supported;
2145 	DC_FP_START();
2146 	voltage_supported = dcn20_validate_bandwidth_fp(dc, context, fast_validate);
2147 	DC_FP_END();
2148 	return voltage_supported;
2149 }
2150 
dcn20_acquire_free_pipe_for_layer(const struct dc_state * cur_ctx,struct dc_state * new_ctx,const struct resource_pool * pool,const struct pipe_ctx * opp_head)2151 struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(
2152 		const struct dc_state *cur_ctx,
2153 		struct dc_state *new_ctx,
2154 		const struct resource_pool *pool,
2155 		const struct pipe_ctx *opp_head)
2156 {
2157 	struct resource_context *res_ctx = &new_ctx->res_ctx;
2158 	struct pipe_ctx *otg_master = resource_get_otg_master_for_stream(res_ctx, opp_head->stream);
2159 	struct pipe_ctx *sec_dpp_pipe = resource_find_free_secondary_pipe_legacy(res_ctx, pool, otg_master);
2160 
2161 	ASSERT(otg_master);
2162 
2163 	if (!sec_dpp_pipe)
2164 		return NULL;
2165 
2166 	sec_dpp_pipe->stream = opp_head->stream;
2167 	sec_dpp_pipe->stream_res.tg = opp_head->stream_res.tg;
2168 	sec_dpp_pipe->stream_res.opp = opp_head->stream_res.opp;
2169 
2170 	sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx];
2171 	sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx];
2172 	sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx];
2173 	sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst;
2174 
2175 	return sec_dpp_pipe;
2176 }
2177 
dcn20_get_dcc_compression_cap(const struct dc * dc,const struct dc_dcc_surface_param * input,struct dc_surface_dcc_cap * output)2178 bool dcn20_get_dcc_compression_cap(const struct dc *dc,
2179 		const struct dc_dcc_surface_param *input,
2180 		struct dc_surface_dcc_cap *output)
2181 {
2182 	return dc->res_pool->hubbub->funcs->get_dcc_compression_cap(
2183 			dc->res_pool->hubbub,
2184 			input,
2185 			output);
2186 }
2187 
dcn20_destroy_resource_pool(struct resource_pool ** pool)2188 static void dcn20_destroy_resource_pool(struct resource_pool **pool)
2189 {
2190 	struct dcn20_resource_pool *dcn20_pool = TO_DCN20_RES_POOL(*pool);
2191 
2192 	dcn20_resource_destruct(dcn20_pool);
2193 	kfree(dcn20_pool);
2194 	*pool = NULL;
2195 }
2196 
2197 
2198 static struct dc_cap_funcs cap_funcs = {
2199 	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
2200 };
2201 
2202 
dcn20_patch_unknown_plane_state(struct dc_plane_state * plane_state)2203 enum dc_status dcn20_patch_unknown_plane_state(struct dc_plane_state *plane_state)
2204 {
2205 	enum surface_pixel_format surf_pix_format = plane_state->format;
2206 	unsigned int bpp = resource_pixel_format_to_bpp(surf_pix_format);
2207 
2208 	plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_S;
2209 	if (bpp == 64)
2210 		plane_state->tiling_info.gfx9.swizzle = DC_SW_64KB_D;
2211 
2212 	return DC_OK;
2213 }
2214 
2215 static const struct resource_funcs dcn20_res_pool_funcs = {
2216 	.destroy = dcn20_destroy_resource_pool,
2217 	.link_enc_create = dcn20_link_encoder_create,
2218 	.panel_cntl_create = dcn20_panel_cntl_create,
2219 	.validate_bandwidth = dcn20_validate_bandwidth,
2220 	.acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer,
2221 	.add_stream_to_ctx = dcn20_add_stream_to_ctx,
2222 	.add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
2223 	.remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
2224 	.populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
2225 	.patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
2226 	.set_mcif_arb_params = dcn20_set_mcif_arb_params,
2227 	.populate_dml_pipes = dcn20_populate_dml_pipes_from_context,
2228 	.find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link
2229 };
2230 
dcn20_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)2231 bool dcn20_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
2232 {
2233 	int i;
2234 	uint32_t pipe_count = pool->res_cap->num_dwb;
2235 
2236 	for (i = 0; i < pipe_count; i++) {
2237 		struct dcn20_dwbc *dwbc20 = kzalloc(sizeof(struct dcn20_dwbc),
2238 						    GFP_KERNEL);
2239 
2240 		if (!dwbc20) {
2241 			dm_error("DC: failed to create dwbc20!\n");
2242 			return false;
2243 		}
2244 		dcn20_dwbc_construct(dwbc20, ctx,
2245 				&dwbc20_regs[i],
2246 				&dwbc20_shift,
2247 				&dwbc20_mask,
2248 				i);
2249 		pool->dwbc[i] = &dwbc20->base;
2250 	}
2251 	return true;
2252 }
2253 
dcn20_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)2254 bool dcn20_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
2255 {
2256 	int i;
2257 	uint32_t pipe_count = pool->res_cap->num_dwb;
2258 
2259 	ASSERT(pipe_count > 0);
2260 
2261 	for (i = 0; i < pipe_count; i++) {
2262 		struct dcn20_mmhubbub *mcif_wb20 = kzalloc(sizeof(struct dcn20_mmhubbub),
2263 						    GFP_KERNEL);
2264 
2265 		if (!mcif_wb20) {
2266 			dm_error("DC: failed to create mcif_wb20!\n");
2267 			return false;
2268 		}
2269 
2270 		dcn20_mmhubbub_construct(mcif_wb20, ctx,
2271 				&mcif_wb20_regs[i],
2272 				&mcif_wb20_shift,
2273 				&mcif_wb20_mask,
2274 				i);
2275 
2276 		pool->mcif_wb[i] = &mcif_wb20->base;
2277 	}
2278 	return true;
2279 }
2280 
dcn20_pp_smu_create(struct dc_context * ctx)2281 static struct pp_smu_funcs *dcn20_pp_smu_create(struct dc_context *ctx)
2282 {
2283 	struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_ATOMIC);
2284 
2285 	if (!pp_smu)
2286 		return pp_smu;
2287 
2288 	dm_pp_get_funcs(ctx, pp_smu);
2289 
2290 	if (pp_smu->ctx.ver != PP_SMU_VER_NV)
2291 		pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
2292 
2293 	return pp_smu;
2294 }
2295 
dcn20_pp_smu_destroy(struct pp_smu_funcs ** pp_smu)2296 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
2297 {
2298 	if (pp_smu && *pp_smu) {
2299 		kfree(*pp_smu);
2300 		*pp_smu = NULL;
2301 	}
2302 }
2303 
get_asic_rev_soc_bb(uint32_t hw_internal_rev)2304 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(
2305 	uint32_t hw_internal_rev)
2306 {
2307 	if (ASICREV_IS_NAVI14_M(hw_internal_rev))
2308 		return &dcn2_0_nv14_soc;
2309 
2310 	if (ASICREV_IS_NAVI12_P(hw_internal_rev))
2311 		return &dcn2_0_nv12_soc;
2312 
2313 	return &dcn2_0_soc;
2314 }
2315 
get_asic_rev_ip_params(uint32_t hw_internal_rev)2316 static struct _vcs_dpi_ip_params_st *get_asic_rev_ip_params(
2317 	uint32_t hw_internal_rev)
2318 {
2319 	/* NV14 */
2320 	if (ASICREV_IS_NAVI14_M(hw_internal_rev))
2321 		return &dcn2_0_nv14_ip;
2322 
2323 	/* NV12 and NV10 */
2324 	return &dcn2_0_ip;
2325 }
2326 
get_dml_project_version(uint32_t hw_internal_rev)2327 static enum dml_project get_dml_project_version(uint32_t hw_internal_rev)
2328 {
2329 	return DML_PROJECT_NAVI10v2;
2330 }
2331 
init_soc_bounding_box(struct dc * dc,struct dcn20_resource_pool * pool)2332 static bool init_soc_bounding_box(struct dc *dc,
2333 				  struct dcn20_resource_pool *pool)
2334 {
2335 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
2336 			get_asic_rev_soc_bb(dc->ctx->asic_id.hw_internal_rev);
2337 	struct _vcs_dpi_ip_params_st *loaded_ip =
2338 			get_asic_rev_ip_params(dc->ctx->asic_id.hw_internal_rev);
2339 
2340 	DC_LOGGER_INIT(dc->ctx->logger);
2341 
2342 	if (pool->base.pp_smu) {
2343 		struct pp_smu_nv_clock_table max_clocks = {0};
2344 		unsigned int uclk_states[8] = {0};
2345 		unsigned int num_states = 0;
2346 		enum pp_smu_status status;
2347 		bool clock_limits_available = false;
2348 		bool uclk_states_available = false;
2349 
2350 		if (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states) {
2351 			status = (pool->base.pp_smu->nv_funcs.get_uclk_dpm_states)
2352 				(&pool->base.pp_smu->nv_funcs.pp_smu, uclk_states, &num_states);
2353 
2354 			uclk_states_available = (status == PP_SMU_RESULT_OK);
2355 		}
2356 
2357 		if (pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks) {
2358 			status = (*pool->base.pp_smu->nv_funcs.get_maximum_sustainable_clocks)
2359 					(&pool->base.pp_smu->nv_funcs.pp_smu, &max_clocks);
2360 			/* SMU cannot set DCF clock to anything equal to or higher than SOC clock
2361 			 */
2362 			if (max_clocks.dcfClockInKhz >= max_clocks.socClockInKhz)
2363 				max_clocks.dcfClockInKhz = max_clocks.socClockInKhz - 1000;
2364 			clock_limits_available = (status == PP_SMU_RESULT_OK);
2365 		}
2366 
2367 		if (clock_limits_available && uclk_states_available && num_states) {
2368 			DC_FP_START();
2369 			dcn20_update_bounding_box(dc, loaded_bb, &max_clocks, uclk_states, num_states);
2370 			DC_FP_END();
2371 		} else if (clock_limits_available) {
2372 			DC_FP_START();
2373 			dcn20_cap_soc_clocks(loaded_bb, max_clocks);
2374 			DC_FP_END();
2375 		}
2376 	}
2377 
2378 	loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
2379 	loaded_ip->max_num_dpp = pool->base.pipe_count;
2380 	DC_FP_START();
2381 	dcn20_patch_bounding_box(dc, loaded_bb);
2382 	DC_FP_END();
2383 	return true;
2384 }
2385 
dcn20_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn20_resource_pool * pool)2386 static bool dcn20_resource_construct(
2387 	uint8_t num_virtual_links,
2388 	struct dc *dc,
2389 	struct dcn20_resource_pool *pool)
2390 {
2391 	int i;
2392 	struct dc_context *ctx = dc->ctx;
2393 	struct irq_service_init_data init_data;
2394 	struct ddc_service_init_data ddc_init_data = {0};
2395 	struct _vcs_dpi_soc_bounding_box_st *loaded_bb =
2396 			get_asic_rev_soc_bb(ctx->asic_id.hw_internal_rev);
2397 	struct _vcs_dpi_ip_params_st *loaded_ip =
2398 			get_asic_rev_ip_params(ctx->asic_id.hw_internal_rev);
2399 	enum dml_project dml_project_version =
2400 			get_dml_project_version(ctx->asic_id.hw_internal_rev);
2401 
2402 	ctx->dc_bios->regs = &bios_regs;
2403 	pool->base.funcs = &dcn20_res_pool_funcs;
2404 
2405 	if (ASICREV_IS_NAVI14_M(ctx->asic_id.hw_internal_rev)) {
2406 		pool->base.res_cap = &res_cap_nv14;
2407 		pool->base.pipe_count = 5;
2408 		pool->base.mpcc_count = 5;
2409 	} else {
2410 		pool->base.res_cap = &res_cap_nv10;
2411 		pool->base.pipe_count = 6;
2412 		pool->base.mpcc_count = 6;
2413 	}
2414 	/*************************************************
2415 	 *  Resource + asic cap harcoding                *
2416 	 *************************************************/
2417 	pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
2418 
2419 	dc->caps.max_downscale_ratio = 200;
2420 	dc->caps.i2c_speed_in_khz = 100;
2421 	dc->caps.i2c_speed_in_khz_hdcp = 100; /*1.4 w/a not applied by default*/
2422 	dc->caps.max_cursor_size = 256;
2423 	dc->caps.min_horizontal_blanking_period = 80;
2424 	dc->caps.dmdata_alloc_size = 2048;
2425 
2426 	dc->caps.max_slave_planes = 1;
2427 	dc->caps.max_slave_yuv_planes = 1;
2428 	dc->caps.max_slave_rgb_planes = 1;
2429 	dc->caps.post_blend_color_processing = true;
2430 	dc->caps.force_dp_tps4_for_cp2520 = true;
2431 	dc->caps.extended_aux_timeout_support = true;
2432 
2433 	/* Color pipeline capabilities */
2434 	dc->caps.color.dpp.dcn_arch = 1;
2435 	dc->caps.color.dpp.input_lut_shared = 0;
2436 	dc->caps.color.dpp.icsc = 1;
2437 	dc->caps.color.dpp.dgam_ram = 1;
2438 	dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2439 	dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2440 	dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
2441 	dc->caps.color.dpp.dgam_rom_caps.pq = 0;
2442 	dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
2443 	dc->caps.color.dpp.post_csc = 0;
2444 	dc->caps.color.dpp.gamma_corr = 0;
2445 	dc->caps.color.dpp.dgam_rom_for_yuv = 1;
2446 
2447 	dc->caps.color.dpp.hw_3d_lut = 1;
2448 	dc->caps.color.dpp.ogam_ram = 1;
2449 	// no OGAM ROM on DCN2, only MPC ROM
2450 	dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2451 	dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2452 	dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2453 	dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2454 	dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2455 	dc->caps.color.dpp.ocsc = 0;
2456 
2457 	dc->caps.color.mpc.gamut_remap = 0;
2458 	dc->caps.color.mpc.num_3dluts = 0;
2459 	dc->caps.color.mpc.shared_3d_lut = 0;
2460 	dc->caps.color.mpc.ogam_ram = 1;
2461 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2462 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2463 	dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2464 	dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2465 	dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2466 	dc->caps.color.mpc.ocsc = 1;
2467 
2468 	dc->caps.dp_hdmi21_pcon_support = true;
2469 
2470 	if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2471 		dc->debug = debug_defaults_drv;
2472 
2473 	//dcn2.0x
2474 	dc->work_arounds.dedcn20_305_wa = true;
2475 
2476 	// Init the vm_helper
2477 	if (dc->vm_helper)
2478 		vm_helper_init(dc->vm_helper, 16);
2479 
2480 	/*************************************************
2481 	 *  Create resources                             *
2482 	 *************************************************/
2483 
2484 	pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
2485 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2486 				CLOCK_SOURCE_COMBO_PHY_PLL0,
2487 				&clk_src_regs[0], false);
2488 	pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
2489 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2490 				CLOCK_SOURCE_COMBO_PHY_PLL1,
2491 				&clk_src_regs[1], false);
2492 	pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
2493 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2494 				CLOCK_SOURCE_COMBO_PHY_PLL2,
2495 				&clk_src_regs[2], false);
2496 	pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
2497 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2498 				CLOCK_SOURCE_COMBO_PHY_PLL3,
2499 				&clk_src_regs[3], false);
2500 	pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
2501 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2502 				CLOCK_SOURCE_COMBO_PHY_PLL4,
2503 				&clk_src_regs[4], false);
2504 	pool->base.clock_sources[DCN20_CLK_SRC_PLL5] =
2505 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2506 				CLOCK_SOURCE_COMBO_PHY_PLL5,
2507 				&clk_src_regs[5], false);
2508 	pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL;
2509 	/* todo: not reuse phy_pll registers */
2510 	pool->base.dp_clock_source =
2511 			dcn20_clock_source_create(ctx, ctx->dc_bios,
2512 				CLOCK_SOURCE_ID_DP_DTO,
2513 				&clk_src_regs[0], true);
2514 
2515 	for (i = 0; i < pool->base.clk_src_count; i++) {
2516 		if (pool->base.clock_sources[i] == NULL) {
2517 			dm_error("DC: failed to create clock sources!\n");
2518 			BREAK_TO_DEBUGGER();
2519 			goto create_fail;
2520 		}
2521 	}
2522 
2523 	pool->base.dccg = dccg2_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2524 	if (pool->base.dccg == NULL) {
2525 		dm_error("DC: failed to create dccg!\n");
2526 		BREAK_TO_DEBUGGER();
2527 		goto create_fail;
2528 	}
2529 
2530 	pool->base.dmcu = dcn20_dmcu_create(ctx,
2531 			&dmcu_regs,
2532 			&dmcu_shift,
2533 			&dmcu_mask);
2534 	if (pool->base.dmcu == NULL) {
2535 		dm_error("DC: failed to create dmcu!\n");
2536 		BREAK_TO_DEBUGGER();
2537 		goto create_fail;
2538 	}
2539 
2540 	pool->base.abm = dce_abm_create(ctx,
2541 			&abm_regs,
2542 			&abm_shift,
2543 			&abm_mask);
2544 	if (pool->base.abm == NULL) {
2545 		dm_error("DC: failed to create abm!\n");
2546 		BREAK_TO_DEBUGGER();
2547 		goto create_fail;
2548 	}
2549 
2550 	pool->base.pp_smu = dcn20_pp_smu_create(ctx);
2551 
2552 
2553 	if (!init_soc_bounding_box(dc, pool)) {
2554 		dm_error("DC: failed to initialize soc bounding box!\n");
2555 		BREAK_TO_DEBUGGER();
2556 		goto create_fail;
2557 	}
2558 
2559 	dml_init_instance(&dc->dml, loaded_bb, loaded_ip, dml_project_version);
2560 
2561 	if (!dc->debug.disable_pplib_wm_range) {
2562 		struct pp_smu_wm_range_sets ranges = {0};
2563 		int i = 0;
2564 
2565 		ranges.num_reader_wm_sets = 0;
2566 
2567 		if (loaded_bb->num_states == 1) {
2568 			ranges.reader_wm_sets[0].wm_inst = i;
2569 			ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2570 			ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2571 			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2572 			ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2573 
2574 			ranges.num_reader_wm_sets = 1;
2575 		} else if (loaded_bb->num_states > 1) {
2576 			for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
2577 				ranges.reader_wm_sets[i].wm_inst = i;
2578 				ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2579 				ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2580 				DC_FP_START();
2581 				dcn20_fpu_set_wm_ranges(i, &ranges, loaded_bb);
2582 				DC_FP_END();
2583 
2584 				ranges.num_reader_wm_sets = i + 1;
2585 			}
2586 
2587 			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2588 			ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2589 		}
2590 
2591 		ranges.num_writer_wm_sets = 1;
2592 
2593 		ranges.writer_wm_sets[0].wm_inst = 0;
2594 		ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2595 		ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2596 		ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
2597 		ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
2598 
2599 		/* Notify PP Lib/SMU which Watermarks to use for which clock ranges */
2600 		if (pool->base.pp_smu->nv_funcs.set_wm_ranges)
2601 			pool->base.pp_smu->nv_funcs.set_wm_ranges(&pool->base.pp_smu->nv_funcs.pp_smu, &ranges);
2602 	}
2603 
2604 	init_data.ctx = dc->ctx;
2605 	pool->base.irqs = dal_irq_service_dcn20_create(&init_data);
2606 	if (!pool->base.irqs)
2607 		goto create_fail;
2608 
2609 	/* mem input -> ipp -> dpp -> opp -> TG */
2610 	for (i = 0; i < pool->base.pipe_count; i++) {
2611 		pool->base.hubps[i] = dcn20_hubp_create(ctx, i);
2612 		if (pool->base.hubps[i] == NULL) {
2613 			BREAK_TO_DEBUGGER();
2614 			dm_error(
2615 				"DC: failed to create memory input!\n");
2616 			goto create_fail;
2617 		}
2618 
2619 		pool->base.ipps[i] = dcn20_ipp_create(ctx, i);
2620 		if (pool->base.ipps[i] == NULL) {
2621 			BREAK_TO_DEBUGGER();
2622 			dm_error(
2623 				"DC: failed to create input pixel processor!\n");
2624 			goto create_fail;
2625 		}
2626 
2627 		pool->base.dpps[i] = dcn20_dpp_create(ctx, i);
2628 		if (pool->base.dpps[i] == NULL) {
2629 			BREAK_TO_DEBUGGER();
2630 			dm_error(
2631 				"DC: failed to create dpps!\n");
2632 			goto create_fail;
2633 		}
2634 	}
2635 	for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2636 		pool->base.engines[i] = dcn20_aux_engine_create(ctx, i);
2637 		if (pool->base.engines[i] == NULL) {
2638 			BREAK_TO_DEBUGGER();
2639 			dm_error(
2640 				"DC:failed to create aux engine!!\n");
2641 			goto create_fail;
2642 		}
2643 		pool->base.hw_i2cs[i] = dcn20_i2c_hw_create(ctx, i);
2644 		if (pool->base.hw_i2cs[i] == NULL) {
2645 			BREAK_TO_DEBUGGER();
2646 			dm_error(
2647 				"DC:failed to create hw i2c!!\n");
2648 			goto create_fail;
2649 		}
2650 		pool->base.sw_i2cs[i] = NULL;
2651 	}
2652 
2653 	for (i = 0; i < pool->base.res_cap->num_opp; i++) {
2654 		pool->base.opps[i] = dcn20_opp_create(ctx, i);
2655 		if (pool->base.opps[i] == NULL) {
2656 			BREAK_TO_DEBUGGER();
2657 			dm_error(
2658 				"DC: failed to create output pixel processor!\n");
2659 			goto create_fail;
2660 		}
2661 	}
2662 
2663 	for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
2664 		pool->base.timing_generators[i] = dcn20_timing_generator_create(
2665 				ctx, i);
2666 		if (pool->base.timing_generators[i] == NULL) {
2667 			BREAK_TO_DEBUGGER();
2668 			dm_error("DC: failed to create tg!\n");
2669 			goto create_fail;
2670 		}
2671 	}
2672 
2673 	pool->base.timing_generator_count = i;
2674 
2675 	pool->base.mpc = dcn20_mpc_create(ctx);
2676 	if (pool->base.mpc == NULL) {
2677 		BREAK_TO_DEBUGGER();
2678 		dm_error("DC: failed to create mpc!\n");
2679 		goto create_fail;
2680 	}
2681 
2682 	pool->base.hubbub = dcn20_hubbub_create(ctx);
2683 	if (pool->base.hubbub == NULL) {
2684 		BREAK_TO_DEBUGGER();
2685 		dm_error("DC: failed to create hubbub!\n");
2686 		goto create_fail;
2687 	}
2688 
2689 	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2690 		pool->base.dscs[i] = dcn20_dsc_create(ctx, i);
2691 		if (pool->base.dscs[i] == NULL) {
2692 			BREAK_TO_DEBUGGER();
2693 			dm_error("DC: failed to create display stream compressor %d!\n", i);
2694 			goto create_fail;
2695 		}
2696 	}
2697 
2698 	if (!dcn20_dwbc_create(ctx, &pool->base)) {
2699 		BREAK_TO_DEBUGGER();
2700 		dm_error("DC: failed to create dwbc!\n");
2701 		goto create_fail;
2702 	}
2703 	if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
2704 		BREAK_TO_DEBUGGER();
2705 		dm_error("DC: failed to create mcif_wb!\n");
2706 		goto create_fail;
2707 	}
2708 
2709 	if (!resource_construct(num_virtual_links, dc, &pool->base,
2710 			&res_create_funcs))
2711 		goto create_fail;
2712 
2713 	dcn20_hw_sequencer_construct(dc);
2714 
2715 	// IF NV12, set PG function pointer to NULL. It's not that
2716 	// PG isn't supported for NV12, it's that we don't want to
2717 	// program the registers because that will cause more power
2718 	// to be consumed. We could have created dcn20_init_hw to get
2719 	// the same effect by checking ASIC rev, but there was a
2720 	// request at some point to not check ASIC rev on hw sequencer.
2721 	if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev)) {
2722 		dc->hwseq->funcs.enable_power_gating_plane = NULL;
2723 		dc->debug.disable_dpp_power_gate = true;
2724 		dc->debug.disable_hubp_power_gate = true;
2725 	}
2726 
2727 
2728 	dc->caps.max_planes =  pool->base.pipe_count;
2729 
2730 	for (i = 0; i < dc->caps.max_planes; ++i)
2731 		dc->caps.planes[i] = plane_cap;
2732 
2733 	dc->cap_funcs = cap_funcs;
2734 
2735 	if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2736 		ddc_init_data.ctx = dc->ctx;
2737 		ddc_init_data.link = NULL;
2738 		ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2739 		ddc_init_data.id.enum_id = 0;
2740 		ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2741 		pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2742 	} else {
2743 		pool->base.oem_device = NULL;
2744 	}
2745 
2746 	return true;
2747 
2748 create_fail:
2749 
2750 	dcn20_resource_destruct(pool);
2751 
2752 	return false;
2753 }
2754 
dcn20_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2755 struct resource_pool *dcn20_create_resource_pool(
2756 		const struct dc_init_data *init_data,
2757 		struct dc *dc)
2758 {
2759 	struct dcn20_resource_pool *pool =
2760 		kzalloc(sizeof(struct dcn20_resource_pool), GFP_ATOMIC);
2761 
2762 	if (!pool)
2763 		return NULL;
2764 
2765 	if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
2766 		return &pool->base;
2767 
2768 	BREAK_TO_DEBUGGER();
2769 	kfree(pool);
2770 	return NULL;
2771 }
2772