1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4 * Author: Ludovic.barre@st.com for STMicroelectronics.
5 */
6 #include <linux/bitfield.h>
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
9 #include <linux/iopoll.h>
10 #include <linux/mmc/host.h>
11 #include <linux/mmc/card.h>
12 #include <linux/of_address.h>
13 #include <linux/reset.h>
14 #include <linux/scatterlist.h>
15 #include "mmci.h"
16
17 #define SDMMC_LLI_BUF_LEN PAGE_SIZE
18
19 #define DLYB_CR 0x0
20 #define DLYB_CR_DEN BIT(0)
21 #define DLYB_CR_SEN BIT(1)
22
23 #define DLYB_CFGR 0x4
24 #define DLYB_CFGR_SEL_MASK GENMASK(3, 0)
25 #define DLYB_CFGR_UNIT_MASK GENMASK(14, 8)
26 #define DLYB_CFGR_LNG_MASK GENMASK(27, 16)
27 #define DLYB_CFGR_LNGF BIT(31)
28
29 #define DLYB_NB_DELAY 11
30 #define DLYB_CFGR_SEL_MAX (DLYB_NB_DELAY + 1)
31 #define DLYB_CFGR_UNIT_MAX 127
32
33 #define DLYB_LNG_TIMEOUT_US 1000
34 #define SDMMC_VSWEND_TIMEOUT_US 10000
35
36 #define SYSCFG_DLYBSD_CR 0x0
37 #define DLYBSD_CR_EN BIT(0)
38 #define DLYBSD_CR_RXTAPSEL_MASK GENMASK(6, 1)
39 #define DLYBSD_TAPSEL_NB 32
40 #define DLYBSD_BYP_EN BIT(16)
41 #define DLYBSD_BYP_CMD GENMASK(21, 17)
42 #define DLYBSD_ANTIGLITCH_EN BIT(22)
43
44 #define SYSCFG_DLYBSD_SR 0x4
45 #define DLYBSD_SR_LOCK BIT(0)
46 #define DLYBSD_SR_RXTAPSEL_ACK BIT(1)
47
48 #define DLYBSD_TIMEOUT_1S_IN_US 1000000
49
50 struct sdmmc_lli_desc {
51 u32 idmalar;
52 u32 idmabase;
53 u32 idmasize;
54 };
55
56 struct sdmmc_idma {
57 dma_addr_t sg_dma;
58 void *sg_cpu;
59 dma_addr_t bounce_dma_addr;
60 void *bounce_buf;
61 bool use_bounce_buffer;
62 };
63
64 struct sdmmc_dlyb;
65
66 struct sdmmc_tuning_ops {
67 int (*dlyb_enable)(struct sdmmc_dlyb *dlyb);
68 void (*set_input_ck)(struct sdmmc_dlyb *dlyb);
69 int (*tuning_prepare)(struct mmci_host *host);
70 int (*set_cfg)(struct sdmmc_dlyb *dlyb, int unit __maybe_unused,
71 int phase, bool sampler __maybe_unused);
72 };
73
74 struct sdmmc_dlyb {
75 void __iomem *base;
76 u32 unit;
77 u32 max;
78 struct sdmmc_tuning_ops *ops;
79 };
80
sdmmc_idma_validate_data(struct mmci_host * host,struct mmc_data * data)81 static int sdmmc_idma_validate_data(struct mmci_host *host,
82 struct mmc_data *data)
83 {
84 struct sdmmc_idma *idma = host->dma_priv;
85 struct device *dev = mmc_dev(host->mmc);
86 struct scatterlist *sg;
87 int i;
88
89 /*
90 * idma has constraints on idmabase & idmasize for each element
91 * excepted the last element which has no constraint on idmasize
92 */
93 idma->use_bounce_buffer = false;
94 for_each_sg(data->sg, sg, data->sg_len - 1, i) {
95 if (!IS_ALIGNED(sg->offset, sizeof(u32)) ||
96 !IS_ALIGNED(sg->length,
97 host->variant->stm32_idmabsize_align)) {
98 dev_dbg(mmc_dev(host->mmc),
99 "unaligned scatterlist: ofst:%x length:%d\n",
100 data->sg->offset, data->sg->length);
101 goto use_bounce_buffer;
102 }
103 }
104
105 if (!IS_ALIGNED(sg->offset, sizeof(u32))) {
106 dev_dbg(mmc_dev(host->mmc),
107 "unaligned last scatterlist: ofst:%x length:%d\n",
108 data->sg->offset, data->sg->length);
109 goto use_bounce_buffer;
110 }
111
112 return 0;
113
114 use_bounce_buffer:
115 if (!idma->bounce_buf) {
116 idma->bounce_buf = dmam_alloc_coherent(dev,
117 host->mmc->max_req_size,
118 &idma->bounce_dma_addr,
119 GFP_KERNEL);
120 if (!idma->bounce_buf) {
121 dev_err(dev, "Unable to map allocate DMA bounce buffer.\n");
122 return -ENOMEM;
123 }
124 }
125
126 idma->use_bounce_buffer = true;
127
128 return 0;
129 }
130
_sdmmc_idma_prep_data(struct mmci_host * host,struct mmc_data * data)131 static int _sdmmc_idma_prep_data(struct mmci_host *host,
132 struct mmc_data *data)
133 {
134 struct sdmmc_idma *idma = host->dma_priv;
135
136 if (idma->use_bounce_buffer) {
137 if (data->flags & MMC_DATA_WRITE) {
138 unsigned int xfer_bytes = data->blksz * data->blocks;
139
140 sg_copy_to_buffer(data->sg, data->sg_len,
141 idma->bounce_buf, xfer_bytes);
142 dma_wmb();
143 }
144 } else {
145 int n_elem;
146
147 n_elem = dma_map_sg(mmc_dev(host->mmc),
148 data->sg,
149 data->sg_len,
150 mmc_get_dma_dir(data));
151
152 if (!n_elem) {
153 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n");
154 return -EINVAL;
155 }
156 }
157 return 0;
158 }
159
sdmmc_idma_prep_data(struct mmci_host * host,struct mmc_data * data,bool next)160 static int sdmmc_idma_prep_data(struct mmci_host *host,
161 struct mmc_data *data, bool next)
162 {
163 /* Check if job is already prepared. */
164 if (!next && data->host_cookie == host->next_cookie)
165 return 0;
166
167 return _sdmmc_idma_prep_data(host, data);
168 }
169
sdmmc_idma_unprep_data(struct mmci_host * host,struct mmc_data * data,int err)170 static void sdmmc_idma_unprep_data(struct mmci_host *host,
171 struct mmc_data *data, int err)
172 {
173 struct sdmmc_idma *idma = host->dma_priv;
174
175 if (idma->use_bounce_buffer) {
176 if (data->flags & MMC_DATA_READ) {
177 unsigned int xfer_bytes = data->blksz * data->blocks;
178
179 sg_copy_from_buffer(data->sg, data->sg_len,
180 idma->bounce_buf, xfer_bytes);
181 }
182 } else {
183 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
184 mmc_get_dma_dir(data));
185 }
186 }
187
sdmmc_idma_setup(struct mmci_host * host)188 static int sdmmc_idma_setup(struct mmci_host *host)
189 {
190 struct sdmmc_idma *idma;
191 struct device *dev = mmc_dev(host->mmc);
192
193 idma = devm_kzalloc(dev, sizeof(*idma), GFP_KERNEL);
194 if (!idma)
195 return -ENOMEM;
196
197 host->dma_priv = idma;
198
199 if (host->variant->dma_lli) {
200 idma->sg_cpu = dmam_alloc_coherent(dev, SDMMC_LLI_BUF_LEN,
201 &idma->sg_dma, GFP_KERNEL);
202 if (!idma->sg_cpu) {
203 dev_err(dev, "Failed to alloc IDMA descriptor\n");
204 return -ENOMEM;
205 }
206 host->mmc->max_segs = SDMMC_LLI_BUF_LEN /
207 sizeof(struct sdmmc_lli_desc);
208 host->mmc->max_seg_size = host->variant->stm32_idmabsize_mask;
209
210 host->mmc->max_req_size = SZ_1M;
211 } else {
212 host->mmc->max_segs = 1;
213 host->mmc->max_seg_size = host->mmc->max_req_size;
214 }
215
216 return dma_set_max_seg_size(dev, host->mmc->max_seg_size);
217 }
218
sdmmc_idma_start(struct mmci_host * host,unsigned int * datactrl)219 static int sdmmc_idma_start(struct mmci_host *host, unsigned int *datactrl)
220
221 {
222 struct sdmmc_idma *idma = host->dma_priv;
223 struct sdmmc_lli_desc *desc = (struct sdmmc_lli_desc *)idma->sg_cpu;
224 struct mmc_data *data = host->data;
225 struct scatterlist *sg;
226 int i;
227
228 host->dma_in_progress = true;
229
230 if (!host->variant->dma_lli || data->sg_len == 1 ||
231 idma->use_bounce_buffer) {
232 u32 dma_addr;
233
234 if (idma->use_bounce_buffer)
235 dma_addr = idma->bounce_dma_addr;
236 else
237 dma_addr = sg_dma_address(data->sg);
238
239 writel_relaxed(dma_addr,
240 host->base + MMCI_STM32_IDMABASE0R);
241 writel_relaxed(MMCI_STM32_IDMAEN,
242 host->base + MMCI_STM32_IDMACTRLR);
243 return 0;
244 }
245
246 for_each_sg(data->sg, sg, data->sg_len, i) {
247 desc[i].idmalar = (i + 1) * sizeof(struct sdmmc_lli_desc);
248 desc[i].idmalar |= MMCI_STM32_ULA | MMCI_STM32_ULS
249 | MMCI_STM32_ABR;
250 desc[i].idmabase = sg_dma_address(sg);
251 desc[i].idmasize = sg_dma_len(sg);
252 }
253
254 /* notice the end of link list */
255 desc[data->sg_len - 1].idmalar &= ~MMCI_STM32_ULA;
256
257 dma_wmb();
258 writel_relaxed(idma->sg_dma, host->base + MMCI_STM32_IDMABAR);
259 writel_relaxed(desc[0].idmalar, host->base + MMCI_STM32_IDMALAR);
260 writel_relaxed(desc[0].idmabase, host->base + MMCI_STM32_IDMABASE0R);
261 writel_relaxed(desc[0].idmasize, host->base + MMCI_STM32_IDMABSIZER);
262 writel_relaxed(MMCI_STM32_IDMAEN | MMCI_STM32_IDMALLIEN,
263 host->base + MMCI_STM32_IDMACTRLR);
264
265 return 0;
266 }
267
sdmmc_idma_error(struct mmci_host * host)268 static void sdmmc_idma_error(struct mmci_host *host)
269 {
270 struct mmc_data *data = host->data;
271 struct sdmmc_idma *idma = host->dma_priv;
272
273 if (!dma_inprogress(host))
274 return;
275
276 writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
277 host->dma_in_progress = false;
278 data->host_cookie = 0;
279
280 if (!idma->use_bounce_buffer)
281 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
282 mmc_get_dma_dir(data));
283 }
284
sdmmc_idma_finalize(struct mmci_host * host,struct mmc_data * data)285 static void sdmmc_idma_finalize(struct mmci_host *host, struct mmc_data *data)
286 {
287 if (!dma_inprogress(host))
288 return;
289
290 writel_relaxed(0, host->base + MMCI_STM32_IDMACTRLR);
291 host->dma_in_progress = false;
292
293 if (!data->host_cookie)
294 sdmmc_idma_unprep_data(host, data, 0);
295 }
296
mmci_sdmmc_set_clkreg(struct mmci_host * host,unsigned int desired)297 static void mmci_sdmmc_set_clkreg(struct mmci_host *host, unsigned int desired)
298 {
299 unsigned int clk = 0, ddr = 0;
300
301 if (host->mmc->ios.timing == MMC_TIMING_MMC_DDR52 ||
302 host->mmc->ios.timing == MMC_TIMING_UHS_DDR50)
303 ddr = MCI_STM32_CLK_DDR;
304
305 /*
306 * cclk = mclk / (2 * clkdiv)
307 * clkdiv 0 => bypass
308 * in ddr mode bypass is not possible
309 */
310 if (desired) {
311 if (desired >= host->mclk && !ddr) {
312 host->cclk = host->mclk;
313 } else {
314 clk = DIV_ROUND_UP(host->mclk, 2 * desired);
315 if (clk > MCI_STM32_CLK_CLKDIV_MSK)
316 clk = MCI_STM32_CLK_CLKDIV_MSK;
317 host->cclk = host->mclk / (2 * clk);
318 }
319 } else {
320 /*
321 * while power-on phase the clock can't be define to 0,
322 * Only power-off and power-cyc deactivate the clock.
323 * if desired clock is 0, set max divider
324 */
325 clk = MCI_STM32_CLK_CLKDIV_MSK;
326 host->cclk = host->mclk / (2 * clk);
327 }
328
329 /* Set actual clock for debug */
330 if (host->mmc->ios.power_mode == MMC_POWER_ON)
331 host->mmc->actual_clock = host->cclk;
332 else
333 host->mmc->actual_clock = 0;
334
335 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
336 clk |= MCI_STM32_CLK_WIDEBUS_4;
337 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
338 clk |= MCI_STM32_CLK_WIDEBUS_8;
339
340 clk |= MCI_STM32_CLK_HWFCEN;
341 clk |= host->clk_reg_add;
342 clk |= ddr;
343
344 if (host->mmc->ios.timing >= MMC_TIMING_UHS_SDR50)
345 clk |= MCI_STM32_CLK_BUSSPEED;
346
347 mmci_write_clkreg(host, clk);
348 }
349
sdmmc_dlyb_mp15_input_ck(struct sdmmc_dlyb * dlyb)350 static void sdmmc_dlyb_mp15_input_ck(struct sdmmc_dlyb *dlyb)
351 {
352 if (!dlyb || !dlyb->base)
353 return;
354
355 /* Output clock = Input clock */
356 writel_relaxed(0, dlyb->base + DLYB_CR);
357 }
358
mmci_sdmmc_set_pwrreg(struct mmci_host * host,unsigned int pwr)359 static void mmci_sdmmc_set_pwrreg(struct mmci_host *host, unsigned int pwr)
360 {
361 struct mmc_ios ios = host->mmc->ios;
362 struct sdmmc_dlyb *dlyb = host->variant_priv;
363
364 /* adds OF options */
365 pwr = host->pwr_reg_add;
366
367 if (dlyb && dlyb->ops->set_input_ck)
368 dlyb->ops->set_input_ck(dlyb);
369
370 if (ios.power_mode == MMC_POWER_OFF) {
371 /* Only a reset could power-off sdmmc */
372 reset_control_assert(host->rst);
373 udelay(2);
374 reset_control_deassert(host->rst);
375
376 /*
377 * Set the SDMMC in Power-cycle state.
378 * This will make that the SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK
379 * are driven low, to prevent the Card from being supplied
380 * through the signal lines.
381 */
382 mmci_write_pwrreg(host, MCI_STM32_PWR_CYC | pwr);
383 } else if (ios.power_mode == MMC_POWER_ON) {
384 /*
385 * After power-off (reset): the irq mask defined in probe
386 * functionis lost
387 * ault irq mask (probe) must be activated
388 */
389 writel(MCI_IRQENABLE | host->variant->start_err,
390 host->base + MMCIMASK0);
391
392 /* preserves voltage switch bits */
393 pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN |
394 MCI_STM32_VSWITCH);
395
396 /*
397 * After a power-cycle state, we must set the SDMMC in
398 * Power-off. The SDMMC_D[7:0], SDMMC_CMD and SDMMC_CK are
399 * driven high. Then we can set the SDMMC to Power-on state
400 */
401 mmci_write_pwrreg(host, MCI_PWR_OFF | pwr);
402 mdelay(1);
403 mmci_write_pwrreg(host, MCI_PWR_ON | pwr);
404 }
405 }
406
sdmmc_get_dctrl_cfg(struct mmci_host * host)407 static u32 sdmmc_get_dctrl_cfg(struct mmci_host *host)
408 {
409 u32 datactrl;
410
411 datactrl = mmci_dctrl_blksz(host);
412
413 if (host->hw_revision >= 3) {
414 u32 thr = 0;
415
416 if (host->mmc->ios.timing == MMC_TIMING_UHS_SDR104 ||
417 host->mmc->ios.timing == MMC_TIMING_MMC_HS200) {
418 thr = ffs(min_t(unsigned int, host->data->blksz,
419 host->variant->fifosize));
420 thr = min_t(u32, thr, MMCI_STM32_THR_MASK);
421 }
422
423 writel_relaxed(thr, host->base + MMCI_STM32_FIFOTHRR);
424 }
425
426 if (host->mmc->card && mmc_card_sdio(host->mmc->card) &&
427 host->data->blocks == 1)
428 datactrl |= MCI_DPSM_STM32_MODE_SDIO;
429 else if (host->data->stop && !host->mrq->sbc)
430 datactrl |= MCI_DPSM_STM32_MODE_BLOCK_STOP;
431 else
432 datactrl |= MCI_DPSM_STM32_MODE_BLOCK;
433
434 return datactrl;
435 }
436
sdmmc_busy_complete(struct mmci_host * host,struct mmc_command * cmd,u32 status,u32 err_msk)437 static bool sdmmc_busy_complete(struct mmci_host *host, struct mmc_command *cmd,
438 u32 status, u32 err_msk)
439 {
440 void __iomem *base = host->base;
441 u32 busy_d0, busy_d0end, mask, sdmmc_status;
442
443 mask = readl_relaxed(base + MMCIMASK0);
444 sdmmc_status = readl_relaxed(base + MMCISTATUS);
445 busy_d0end = sdmmc_status & MCI_STM32_BUSYD0END;
446 busy_d0 = sdmmc_status & MCI_STM32_BUSYD0;
447
448 /* complete if there is an error or busy_d0end */
449 if ((status & err_msk) || busy_d0end)
450 goto complete;
451
452 /*
453 * On response the busy signaling is reflected in the BUSYD0 flag.
454 * if busy_d0 is in-progress we must activate busyd0end interrupt
455 * to wait this completion. Else this request has no busy step.
456 */
457 if (busy_d0) {
458 if (!host->busy_status) {
459 writel_relaxed(mask | host->variant->busy_detect_mask,
460 base + MMCIMASK0);
461 host->busy_status = status &
462 (MCI_CMDSENT | MCI_CMDRESPEND);
463 }
464 return false;
465 }
466
467 complete:
468 if (host->busy_status) {
469 writel_relaxed(mask & ~host->variant->busy_detect_mask,
470 base + MMCIMASK0);
471 host->busy_status = 0;
472 }
473
474 writel_relaxed(host->variant->busy_detect_mask, base + MMCICLEAR);
475
476 return true;
477 }
478
sdmmc_dlyb_mp15_enable(struct sdmmc_dlyb * dlyb)479 static int sdmmc_dlyb_mp15_enable(struct sdmmc_dlyb *dlyb)
480 {
481 writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
482
483 return 0;
484 }
485
sdmmc_dlyb_mp15_set_cfg(struct sdmmc_dlyb * dlyb,int unit,int phase,bool sampler)486 static int sdmmc_dlyb_mp15_set_cfg(struct sdmmc_dlyb *dlyb,
487 int unit, int phase, bool sampler)
488 {
489 u32 cfgr;
490
491 writel_relaxed(DLYB_CR_SEN | DLYB_CR_DEN, dlyb->base + DLYB_CR);
492
493 cfgr = FIELD_PREP(DLYB_CFGR_UNIT_MASK, unit) |
494 FIELD_PREP(DLYB_CFGR_SEL_MASK, phase);
495 writel_relaxed(cfgr, dlyb->base + DLYB_CFGR);
496
497 if (!sampler)
498 writel_relaxed(DLYB_CR_DEN, dlyb->base + DLYB_CR);
499
500 return 0;
501 }
502
sdmmc_dlyb_mp15_prepare(struct mmci_host * host)503 static int sdmmc_dlyb_mp15_prepare(struct mmci_host *host)
504 {
505 struct sdmmc_dlyb *dlyb = host->variant_priv;
506 u32 cfgr;
507 int i, lng, ret;
508
509 for (i = 0; i <= DLYB_CFGR_UNIT_MAX; i++) {
510 dlyb->ops->set_cfg(dlyb, i, DLYB_CFGR_SEL_MAX, true);
511
512 ret = readl_relaxed_poll_timeout(dlyb->base + DLYB_CFGR, cfgr,
513 (cfgr & DLYB_CFGR_LNGF),
514 1, DLYB_LNG_TIMEOUT_US);
515 if (ret) {
516 dev_warn(mmc_dev(host->mmc),
517 "delay line cfg timeout unit:%d cfgr:%d\n",
518 i, cfgr);
519 continue;
520 }
521
522 lng = FIELD_GET(DLYB_CFGR_LNG_MASK, cfgr);
523 if (lng < BIT(DLYB_NB_DELAY) && lng > 0)
524 break;
525 }
526
527 if (i > DLYB_CFGR_UNIT_MAX)
528 return -EINVAL;
529
530 dlyb->unit = i;
531 dlyb->max = __fls(lng);
532
533 return 0;
534 }
535
sdmmc_dlyb_mp25_enable(struct sdmmc_dlyb * dlyb)536 static int sdmmc_dlyb_mp25_enable(struct sdmmc_dlyb *dlyb)
537 {
538 u32 cr, sr;
539
540 cr = readl_relaxed(dlyb->base + SYSCFG_DLYBSD_CR);
541 cr |= DLYBSD_CR_EN;
542
543 writel_relaxed(cr, dlyb->base + SYSCFG_DLYBSD_CR);
544
545 return readl_relaxed_poll_timeout(dlyb->base + SYSCFG_DLYBSD_SR,
546 sr, sr & DLYBSD_SR_LOCK, 1,
547 DLYBSD_TIMEOUT_1S_IN_US);
548 }
549
sdmmc_dlyb_mp25_set_cfg(struct sdmmc_dlyb * dlyb,int unit __maybe_unused,int phase,bool sampler __maybe_unused)550 static int sdmmc_dlyb_mp25_set_cfg(struct sdmmc_dlyb *dlyb,
551 int unit __maybe_unused, int phase,
552 bool sampler __maybe_unused)
553 {
554 u32 cr, sr;
555
556 cr = readl_relaxed(dlyb->base + SYSCFG_DLYBSD_CR);
557 cr &= ~DLYBSD_CR_RXTAPSEL_MASK;
558 cr |= FIELD_PREP(DLYBSD_CR_RXTAPSEL_MASK, phase);
559
560 writel_relaxed(cr, dlyb->base + SYSCFG_DLYBSD_CR);
561
562 return readl_relaxed_poll_timeout(dlyb->base + SYSCFG_DLYBSD_SR,
563 sr, sr & DLYBSD_SR_RXTAPSEL_ACK, 1,
564 DLYBSD_TIMEOUT_1S_IN_US);
565 }
566
sdmmc_dlyb_mp25_prepare(struct mmci_host * host)567 static int sdmmc_dlyb_mp25_prepare(struct mmci_host *host)
568 {
569 struct sdmmc_dlyb *dlyb = host->variant_priv;
570
571 dlyb->max = DLYBSD_TAPSEL_NB;
572
573 return 0;
574 }
575
sdmmc_dlyb_phase_tuning(struct mmci_host * host,u32 opcode)576 static int sdmmc_dlyb_phase_tuning(struct mmci_host *host, u32 opcode)
577 {
578 struct sdmmc_dlyb *dlyb = host->variant_priv;
579 int cur_len = 0, max_len = 0, end_of_len = 0;
580 int phase, ret;
581
582 for (phase = 0; phase <= dlyb->max; phase++) {
583 ret = dlyb->ops->set_cfg(dlyb, dlyb->unit, phase, false);
584 if (ret) {
585 dev_err(mmc_dev(host->mmc), "tuning config failed\n");
586 return ret;
587 }
588
589 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
590 cur_len = 0;
591 } else {
592 cur_len++;
593 if (cur_len > max_len) {
594 max_len = cur_len;
595 end_of_len = phase;
596 }
597 }
598 }
599
600 if (!max_len) {
601 dev_err(mmc_dev(host->mmc), "no tuning point found\n");
602 return -EINVAL;
603 }
604
605 if (dlyb->ops->set_input_ck)
606 dlyb->ops->set_input_ck(dlyb);
607
608 phase = end_of_len - max_len / 2;
609 ret = dlyb->ops->set_cfg(dlyb, dlyb->unit, phase, false);
610 if (ret) {
611 dev_err(mmc_dev(host->mmc), "tuning reconfig failed\n");
612 return ret;
613 }
614
615 dev_dbg(mmc_dev(host->mmc), "unit:%d max_dly:%d phase:%d\n",
616 dlyb->unit, dlyb->max, phase);
617
618 return 0;
619 }
620
sdmmc_execute_tuning(struct mmc_host * mmc,u32 opcode)621 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
622 {
623 struct mmci_host *host = mmc_priv(mmc);
624 struct sdmmc_dlyb *dlyb = host->variant_priv;
625 u32 clk;
626 int ret;
627
628 if ((host->mmc->ios.timing != MMC_TIMING_UHS_SDR104 &&
629 host->mmc->ios.timing != MMC_TIMING_MMC_HS200) ||
630 host->mmc->actual_clock <= 50000000)
631 return 0;
632
633 if (!dlyb || !dlyb->base)
634 return -EINVAL;
635
636 ret = dlyb->ops->dlyb_enable(dlyb);
637 if (ret)
638 return ret;
639
640 /*
641 * SDMMC_FBCK is selected when an external Delay Block is needed
642 * with SDR104 or HS200.
643 */
644 clk = host->clk_reg;
645 clk &= ~MCI_STM32_CLK_SEL_MSK;
646 clk |= MCI_STM32_CLK_SELFBCK;
647 mmci_write_clkreg(host, clk);
648
649 ret = dlyb->ops->tuning_prepare(host);
650 if (ret)
651 return ret;
652
653 return sdmmc_dlyb_phase_tuning(host, opcode);
654 }
655
sdmmc_pre_sig_volt_vswitch(struct mmci_host * host)656 static void sdmmc_pre_sig_volt_vswitch(struct mmci_host *host)
657 {
658 /* clear the voltage switch completion flag */
659 writel_relaxed(MCI_STM32_VSWENDC, host->base + MMCICLEAR);
660 /* enable Voltage switch procedure */
661 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN);
662 }
663
sdmmc_post_sig_volt_switch(struct mmci_host * host,struct mmc_ios * ios)664 static int sdmmc_post_sig_volt_switch(struct mmci_host *host,
665 struct mmc_ios *ios)
666 {
667 unsigned long flags;
668 u32 status;
669 int ret = 0;
670
671 spin_lock_irqsave(&host->lock, flags);
672 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 &&
673 host->pwr_reg & MCI_STM32_VSWITCHEN) {
674 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH);
675 spin_unlock_irqrestore(&host->lock, flags);
676
677 /* wait voltage switch completion while 10ms */
678 ret = readl_relaxed_poll_timeout(host->base + MMCISTATUS,
679 status,
680 (status & MCI_STM32_VSWEND),
681 10, SDMMC_VSWEND_TIMEOUT_US);
682
683 writel_relaxed(MCI_STM32_VSWENDC | MCI_STM32_CKSTOPC,
684 host->base + MMCICLEAR);
685 spin_lock_irqsave(&host->lock, flags);
686 mmci_write_pwrreg(host, host->pwr_reg &
687 ~(MCI_STM32_VSWITCHEN | MCI_STM32_VSWITCH));
688 }
689 spin_unlock_irqrestore(&host->lock, flags);
690
691 return ret;
692 }
693
694 static struct mmci_host_ops sdmmc_variant_ops = {
695 .validate_data = sdmmc_idma_validate_data,
696 .prep_data = sdmmc_idma_prep_data,
697 .unprep_data = sdmmc_idma_unprep_data,
698 .get_datactrl_cfg = sdmmc_get_dctrl_cfg,
699 .dma_setup = sdmmc_idma_setup,
700 .dma_start = sdmmc_idma_start,
701 .dma_finalize = sdmmc_idma_finalize,
702 .dma_error = sdmmc_idma_error,
703 .set_clkreg = mmci_sdmmc_set_clkreg,
704 .set_pwrreg = mmci_sdmmc_set_pwrreg,
705 .busy_complete = sdmmc_busy_complete,
706 .pre_sig_volt_switch = sdmmc_pre_sig_volt_vswitch,
707 .post_sig_volt_switch = sdmmc_post_sig_volt_switch,
708 };
709
710 static struct sdmmc_tuning_ops dlyb_tuning_mp15_ops = {
711 .dlyb_enable = sdmmc_dlyb_mp15_enable,
712 .set_input_ck = sdmmc_dlyb_mp15_input_ck,
713 .tuning_prepare = sdmmc_dlyb_mp15_prepare,
714 .set_cfg = sdmmc_dlyb_mp15_set_cfg,
715 };
716
717 static struct sdmmc_tuning_ops dlyb_tuning_mp25_ops = {
718 .dlyb_enable = sdmmc_dlyb_mp25_enable,
719 .tuning_prepare = sdmmc_dlyb_mp25_prepare,
720 .set_cfg = sdmmc_dlyb_mp25_set_cfg,
721 };
722
sdmmc_variant_init(struct mmci_host * host)723 void sdmmc_variant_init(struct mmci_host *host)
724 {
725 struct device_node *np = host->mmc->parent->of_node;
726 void __iomem *base_dlyb;
727 struct sdmmc_dlyb *dlyb;
728
729 host->ops = &sdmmc_variant_ops;
730 host->pwr_reg = readl_relaxed(host->base + MMCIPOWER);
731
732 base_dlyb = devm_of_iomap(mmc_dev(host->mmc), np, 1, NULL);
733 if (IS_ERR(base_dlyb))
734 return;
735
736 dlyb = devm_kzalloc(mmc_dev(host->mmc), sizeof(*dlyb), GFP_KERNEL);
737 if (!dlyb)
738 return;
739
740 dlyb->base = base_dlyb;
741 if (of_device_is_compatible(np, "st,stm32mp25-sdmmc2"))
742 dlyb->ops = &dlyb_tuning_mp25_ops;
743 else
744 dlyb->ops = &dlyb_tuning_mp15_ops;
745
746 host->variant_priv = dlyb;
747 host->mmc_ops->execute_tuning = sdmmc_execute_tuning;
748 }
749