1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/firmware.h>
26 #include <linux/module.h>
27 #include <linux/pci.h>
28
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32
33 #include "gc/gc_10_3_0_offset.h"
34 #include "gc/gc_10_3_0_sh_mask.h"
35 #include "ivsrcid/sdma0/irqsrcs_sdma0_5_0.h"
36 #include "ivsrcid/sdma1/irqsrcs_sdma1_5_0.h"
37 #include "ivsrcid/sdma2/irqsrcs_sdma2_5_0.h"
38 #include "ivsrcid/sdma3/irqsrcs_sdma3_5_0.h"
39
40 #include "soc15_common.h"
41 #include "soc15.h"
42 #include "navi10_sdma_pkt_open.h"
43 #include "nbio_v2_3.h"
44 #include "sdma_common.h"
45 #include "sdma_v5_2.h"
46
47 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sdma.bin");
48 MODULE_FIRMWARE("amdgpu/navy_flounder_sdma.bin");
49 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sdma.bin");
50 MODULE_FIRMWARE("amdgpu/beige_goby_sdma.bin");
51
52 MODULE_FIRMWARE("amdgpu/vangogh_sdma.bin");
53 MODULE_FIRMWARE("amdgpu/yellow_carp_sdma.bin");
54 MODULE_FIRMWARE("amdgpu/sdma_5_2_6.bin");
55 MODULE_FIRMWARE("amdgpu/sdma_5_2_7.bin");
56
57 #define SDMA1_REG_OFFSET 0x600
58 #define SDMA3_REG_OFFSET 0x400
59 #define SDMA0_HYP_DEC_REG_START 0x5880
60 #define SDMA0_HYP_DEC_REG_END 0x5893
61 #define SDMA1_HYP_DEC_REG_OFFSET 0x20
62
63 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev);
64 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev);
65 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev);
66 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev);
67
sdma_v5_2_get_reg_offset(struct amdgpu_device * adev,u32 instance,u32 internal_offset)68 static u32 sdma_v5_2_get_reg_offset(struct amdgpu_device *adev, u32 instance, u32 internal_offset)
69 {
70 u32 base;
71
72 if (internal_offset >= SDMA0_HYP_DEC_REG_START &&
73 internal_offset <= SDMA0_HYP_DEC_REG_END) {
74 base = adev->reg_offset[GC_HWIP][0][1];
75 if (instance != 0)
76 internal_offset += SDMA1_HYP_DEC_REG_OFFSET * instance;
77 } else {
78 if (instance < 2) {
79 base = adev->reg_offset[GC_HWIP][0][0];
80 if (instance == 1)
81 internal_offset += SDMA1_REG_OFFSET;
82 } else {
83 base = adev->reg_offset[GC_HWIP][0][2];
84 if (instance == 3)
85 internal_offset += SDMA3_REG_OFFSET;
86 }
87 }
88
89 return base + internal_offset;
90 }
91
sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring * ring)92 static unsigned sdma_v5_2_ring_init_cond_exec(struct amdgpu_ring *ring)
93 {
94 unsigned ret;
95
96 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_COND_EXE));
97 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
98 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
99 amdgpu_ring_write(ring, 1);
100 ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */
101 amdgpu_ring_write(ring, 0x55aa55aa);/* insert dummy here and patch it later */
102
103 return ret;
104 }
105
sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring * ring,unsigned offset)106 static void sdma_v5_2_ring_patch_cond_exec(struct amdgpu_ring *ring,
107 unsigned offset)
108 {
109 unsigned cur;
110
111 BUG_ON(offset > ring->buf_mask);
112 BUG_ON(ring->ring[offset] != 0x55aa55aa);
113
114 cur = (ring->wptr - 1) & ring->buf_mask;
115 if (cur > offset)
116 ring->ring[offset] = cur - offset;
117 else
118 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
119 }
120
121 /**
122 * sdma_v5_2_ring_get_rptr - get the current read pointer
123 *
124 * @ring: amdgpu ring pointer
125 *
126 * Get the current rptr from the hardware (NAVI10+).
127 */
sdma_v5_2_ring_get_rptr(struct amdgpu_ring * ring)128 static uint64_t sdma_v5_2_ring_get_rptr(struct amdgpu_ring *ring)
129 {
130 u64 *rptr;
131
132 /* XXX check if swapping is necessary on BE */
133 rptr = (u64 *)ring->rptr_cpu_addr;
134
135 DRM_DEBUG("rptr before shift == 0x%016llx\n", *rptr);
136 return ((*rptr) >> 2);
137 }
138
139 /**
140 * sdma_v5_2_ring_get_wptr - get the current write pointer
141 *
142 * @ring: amdgpu ring pointer
143 *
144 * Get the current wptr from the hardware (NAVI10+).
145 */
sdma_v5_2_ring_get_wptr(struct amdgpu_ring * ring)146 static uint64_t sdma_v5_2_ring_get_wptr(struct amdgpu_ring *ring)
147 {
148 struct amdgpu_device *adev = ring->adev;
149 u64 wptr;
150
151 if (ring->use_doorbell) {
152 /* XXX check if swapping is necessary on BE */
153 wptr = READ_ONCE(*((u64 *)ring->wptr_cpu_addr));
154 DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr);
155 } else {
156 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI));
157 wptr = wptr << 32;
158 wptr |= RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR));
159 DRM_DEBUG("wptr before shift [%i] wptr == 0x%016llx\n", ring->me, wptr);
160 }
161
162 return wptr >> 2;
163 }
164
165 /**
166 * sdma_v5_2_ring_set_wptr - commit the write pointer
167 *
168 * @ring: amdgpu ring pointer
169 *
170 * Write the wptr back to the hardware (NAVI10+).
171 */
sdma_v5_2_ring_set_wptr(struct amdgpu_ring * ring)172 static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring)
173 {
174 struct amdgpu_device *adev = ring->adev;
175
176 DRM_DEBUG("Setting write pointer\n");
177 if (ring->use_doorbell) {
178 DRM_DEBUG("Using doorbell -- "
179 "wptr_offs == 0x%08x "
180 "lower_32_bits(ring->wptr << 2) == 0x%08x "
181 "upper_32_bits(ring->wptr << 2) == 0x%08x\n",
182 ring->wptr_offs,
183 lower_32_bits(ring->wptr << 2),
184 upper_32_bits(ring->wptr << 2));
185 /* XXX check if swapping is necessary on BE */
186 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
187 ring->wptr << 2);
188 DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n",
189 ring->doorbell_index, ring->wptr << 2);
190 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
191 /* SDMA seems to miss doorbells sometimes when powergating kicks in.
192 * Updating the wptr directly will wake it. This is only safe because
193 * we disallow gfxoff in begin_use() and then allow it again in end_use().
194 */
195 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
196 lower_32_bits(ring->wptr << 2));
197 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
198 upper_32_bits(ring->wptr << 2));
199 } else {
200 DRM_DEBUG("Not using doorbell -- "
201 "mmSDMA%i_GFX_RB_WPTR == 0x%08x "
202 "mmSDMA%i_GFX_RB_WPTR_HI == 0x%08x\n",
203 ring->me,
204 lower_32_bits(ring->wptr << 2),
205 ring->me,
206 upper_32_bits(ring->wptr << 2));
207 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR),
208 lower_32_bits(ring->wptr << 2));
209 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI),
210 upper_32_bits(ring->wptr << 2));
211 }
212 }
213
sdma_v5_2_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)214 static void sdma_v5_2_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
215 {
216 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
217 int i;
218
219 for (i = 0; i < count; i++)
220 if (sdma && sdma->burst_nop && (i == 0))
221 amdgpu_ring_write(ring, ring->funcs->nop |
222 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
223 else
224 amdgpu_ring_write(ring, ring->funcs->nop);
225 }
226
227 /**
228 * sdma_v5_2_ring_emit_ib - Schedule an IB on the DMA engine
229 *
230 * @ring: amdgpu ring pointer
231 * @job: job to retrieve vmid from
232 * @ib: IB object to schedule
233 * @flags: unused
234 *
235 * Schedule an IB in the DMA ring.
236 */
sdma_v5_2_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)237 static void sdma_v5_2_ring_emit_ib(struct amdgpu_ring *ring,
238 struct amdgpu_job *job,
239 struct amdgpu_ib *ib,
240 uint32_t flags)
241 {
242 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
243 uint64_t csa_mc_addr = amdgpu_sdma_get_csa_mc_addr(ring, vmid);
244
245 /* An IB packet must end on a 8 DW boundary--the next dword
246 * must be on a 8-dword boundary. Our IB packet below is 6
247 * dwords long, thus add x number of NOPs, such that, in
248 * modular arithmetic,
249 * wptr + 6 + x = 8k, k >= 0, which in C is,
250 * (wptr + 6 + x) % 8 = 0.
251 * The expression below, is a solution of x.
252 */
253 sdma_v5_2_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
254
255 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
256 SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
257 /* base must be 32 byte aligned */
258 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
259 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
260 amdgpu_ring_write(ring, ib->length_dw);
261 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
262 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
263 }
264
265 /**
266 * sdma_v5_2_ring_emit_mem_sync - flush the IB by graphics cache rinse
267 *
268 * @ring: amdgpu ring pointer
269 *
270 * flush the IB by graphics cache rinse.
271 */
sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring * ring)272 static void sdma_v5_2_ring_emit_mem_sync(struct amdgpu_ring *ring)
273 {
274 uint32_t gcr_cntl = SDMA_GCR_GL2_INV | SDMA_GCR_GL2_WB |
275 SDMA_GCR_GLM_INV | SDMA_GCR_GL1_INV |
276 SDMA_GCR_GLV_INV | SDMA_GCR_GLK_INV |
277 SDMA_GCR_GLI_INV(1);
278
279 /* flush entire cache L0/L1/L2, this can be optimized by performance requirement */
280 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_GCR_REQ));
281 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD1_BASE_VA_31_7(0));
282 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD2_GCR_CONTROL_15_0(gcr_cntl) |
283 SDMA_PKT_GCR_REQ_PAYLOAD2_BASE_VA_47_32(0));
284 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD3_LIMIT_VA_31_7(0) |
285 SDMA_PKT_GCR_REQ_PAYLOAD3_GCR_CONTROL_18_16(gcr_cntl >> 16));
286 amdgpu_ring_write(ring, SDMA_PKT_GCR_REQ_PAYLOAD4_LIMIT_VA_47_32(0) |
287 SDMA_PKT_GCR_REQ_PAYLOAD4_VMID(0));
288 }
289
290 /**
291 * sdma_v5_2_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
292 *
293 * @ring: amdgpu ring pointer
294 *
295 * Emit an hdp flush packet on the requested DMA ring.
296 */
sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring * ring)297 static void sdma_v5_2_ring_emit_hdp_flush(struct amdgpu_ring *ring)
298 {
299 struct amdgpu_device *adev = ring->adev;
300 u32 ref_and_mask = 0;
301 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
302
303 if (ring->me > 1) {
304 amdgpu_asic_flush_hdp(adev, ring);
305 } else {
306 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
307
308 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
309 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
310 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
311 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_done_offset(adev)) << 2);
312 amdgpu_ring_write(ring, (adev->nbio.funcs->get_hdp_flush_req_offset(adev)) << 2);
313 amdgpu_ring_write(ring, ref_and_mask); /* reference */
314 amdgpu_ring_write(ring, ref_and_mask); /* mask */
315 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
316 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
317 }
318 }
319
320 /**
321 * sdma_v5_2_ring_emit_fence - emit a fence on the DMA ring
322 *
323 * @ring: amdgpu ring pointer
324 * @addr: address
325 * @seq: sequence number
326 * @flags: fence related flags
327 *
328 * Add a DMA fence packet to the ring to write
329 * the fence seq number and DMA trap packet to generate
330 * an interrupt if needed.
331 */
sdma_v5_2_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)332 static void sdma_v5_2_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
333 unsigned flags)
334 {
335 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
336 /* write the fence */
337 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
338 SDMA_PKT_FENCE_HEADER_MTYPE(0x3)); /* Ucached(UC) */
339 /* zero in first two bits */
340 BUG_ON(addr & 0x3);
341 amdgpu_ring_write(ring, lower_32_bits(addr));
342 amdgpu_ring_write(ring, upper_32_bits(addr));
343 amdgpu_ring_write(ring, lower_32_bits(seq));
344
345 /* optionally write high bits as well */
346 if (write64bit) {
347 addr += 4;
348 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE) |
349 SDMA_PKT_FENCE_HEADER_MTYPE(0x3));
350 /* zero in first two bits */
351 BUG_ON(addr & 0x3);
352 amdgpu_ring_write(ring, lower_32_bits(addr));
353 amdgpu_ring_write(ring, upper_32_bits(addr));
354 amdgpu_ring_write(ring, upper_32_bits(seq));
355 }
356
357 if ((flags & AMDGPU_FENCE_FLAG_INT)) {
358 uint32_t ctx = ring->is_mes_queue ?
359 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0;
360 /* generate an interrupt */
361 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
362 amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(ctx));
363 }
364 }
365
366
367 /**
368 * sdma_v5_2_gfx_stop - stop the gfx async dma engines
369 *
370 * @adev: amdgpu_device pointer
371 *
372 * Stop the gfx async dma ring buffers.
373 */
sdma_v5_2_gfx_stop(struct amdgpu_device * adev)374 static void sdma_v5_2_gfx_stop(struct amdgpu_device *adev)
375 {
376 u32 rb_cntl, ib_cntl;
377 int i;
378
379 amdgpu_sdma_unset_buffer_funcs_helper(adev);
380
381 for (i = 0; i < adev->sdma.num_instances; i++) {
382 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
383 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
384 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
385 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
386 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
387 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
388 }
389 }
390
391 /**
392 * sdma_v5_2_rlc_stop - stop the compute async dma engines
393 *
394 * @adev: amdgpu_device pointer
395 *
396 * Stop the compute async dma queues.
397 */
sdma_v5_2_rlc_stop(struct amdgpu_device * adev)398 static void sdma_v5_2_rlc_stop(struct amdgpu_device *adev)
399 {
400 /* XXX todo */
401 }
402
403 /**
404 * sdma_v5_2_ctx_switch_enable - stop the async dma engines context switch
405 *
406 * @adev: amdgpu_device pointer
407 * @enable: enable/disable the DMA MEs context switch.
408 *
409 * Halt or unhalt the async dma engines context switch.
410 */
sdma_v5_2_ctx_switch_enable(struct amdgpu_device * adev,bool enable)411 static void sdma_v5_2_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
412 {
413 u32 f32_cntl, phase_quantum = 0;
414 int i;
415
416 if (amdgpu_sdma_phase_quantum) {
417 unsigned value = amdgpu_sdma_phase_quantum;
418 unsigned unit = 0;
419
420 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
421 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
422 value = (value + 1) >> 1;
423 unit++;
424 }
425 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
426 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
427 value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
428 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
429 unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
430 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
431 WARN_ONCE(1,
432 "clamping sdma_phase_quantum to %uK clock cycles\n",
433 value << unit);
434 }
435 phase_quantum =
436 value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
437 unit << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
438 }
439
440 for (i = 0; i < adev->sdma.num_instances; i++) {
441 if (enable && amdgpu_sdma_phase_quantum) {
442 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE0_QUANTUM),
443 phase_quantum);
444 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE1_QUANTUM),
445 phase_quantum);
446 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_PHASE2_QUANTUM),
447 phase_quantum);
448 }
449
450 if (!amdgpu_sriov_vf(adev)) {
451 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
452 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
453 AUTO_CTXSW_ENABLE, enable ? 1 : 0);
454 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), f32_cntl);
455 }
456 }
457
458 }
459
460 /**
461 * sdma_v5_2_enable - stop the async dma engines
462 *
463 * @adev: amdgpu_device pointer
464 * @enable: enable/disable the DMA MEs.
465 *
466 * Halt or unhalt the async dma engines.
467 */
sdma_v5_2_enable(struct amdgpu_device * adev,bool enable)468 static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable)
469 {
470 u32 f32_cntl;
471 int i;
472
473 if (!enable) {
474 sdma_v5_2_gfx_stop(adev);
475 sdma_v5_2_rlc_stop(adev);
476 }
477
478 if (!amdgpu_sriov_vf(adev)) {
479 for (i = 0; i < adev->sdma.num_instances; i++) {
480 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
481 f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, enable ? 0 : 1);
482 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
483 }
484 }
485 }
486
487 /**
488 * sdma_v5_2_gfx_resume - setup and start the async dma engines
489 *
490 * @adev: amdgpu_device pointer
491 *
492 * Set up the gfx DMA ring buffers and enable them.
493 * Returns 0 for success, error for failure.
494 */
sdma_v5_2_gfx_resume(struct amdgpu_device * adev)495 static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev)
496 {
497 struct amdgpu_ring *ring;
498 u32 rb_cntl, ib_cntl;
499 u32 rb_bufsz;
500 u32 doorbell;
501 u32 doorbell_offset;
502 u32 temp;
503 u32 wptr_poll_cntl;
504 u64 wptr_gpu_addr;
505 int i, r;
506
507 for (i = 0; i < adev->sdma.num_instances; i++) {
508 ring = &adev->sdma.instance[i].ring;
509
510 if (!amdgpu_sriov_vf(adev))
511 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0);
512
513 /* Set ring buffer size in dwords */
514 rb_bufsz = order_base_2(ring->ring_size / 4);
515 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL));
516 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
517 #ifdef __BIG_ENDIAN
518 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
519 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
520 RPTR_WRITEBACK_SWAP_ENABLE, 1);
521 #endif
522 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
523
524 /* Initialize the ring buffer's read and write pointers */
525 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
526 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0);
527 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0);
528 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0);
529
530 /* setup the wptr shadow polling */
531 wptr_gpu_addr = ring->wptr_gpu_addr;
532 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO),
533 lower_32_bits(wptr_gpu_addr));
534 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI),
535 upper_32_bits(wptr_gpu_addr));
536 wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i,
537 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
538 wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
539 SDMA0_GFX_RB_WPTR_POLL_CNTL,
540 F32_POLL_ENABLE, 1);
541 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL),
542 wptr_poll_cntl);
543
544 /* set the wb address whether it's enabled or not */
545 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI),
546 upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
547 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO),
548 lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
549
550 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
551
552 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8);
553 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
554
555 ring->wptr = 0;
556
557 /* before programing wptr to a less value, need set minor_ptr_update first */
558 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1);
559
560 if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */
561 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2));
562 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
563 }
564
565 doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL));
566 doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET));
567
568 if (ring->use_doorbell) {
569 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
570 doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET,
571 OFFSET, ring->doorbell_index);
572 } else {
573 doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
574 }
575 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell);
576 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset);
577
578 adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell,
579 ring->doorbell_index,
580 adev->doorbell_index.sdma_doorbell_range);
581
582 if (amdgpu_sriov_vf(adev))
583 sdma_v5_2_ring_set_wptr(ring);
584
585 /* set minor_ptr_update to 0 after wptr programed */
586
587 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0);
588
589 /* SRIOV VF has no control of any of registers below */
590 if (!amdgpu_sriov_vf(adev)) {
591 /* set utc l1 enable flag always to 1 */
592 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL));
593 temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1);
594
595 /* enable MCBP */
596 temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1);
597 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp);
598
599 /* Set up RESP_MODE to non-copy addresses */
600 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
601 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3);
602 temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9);
603 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
604
605 /* program default cache read and write policy */
606 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE));
607 /* clean read policy and write policy bits */
608 temp &= 0xFF0FFF;
609 temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) |
610 (CACHE_WRITE_POLICY_L2__DEFAULT << 14) |
611 SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK);
612 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp);
613
614 /* unhalt engine */
615 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
616 temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0);
617 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
618 }
619
620 /* enable DMA RB */
621 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
622 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl);
623
624 ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL));
625 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
626 #ifdef __BIG_ENDIAN
627 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
628 #endif
629 /* enable DMA IBs */
630 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl);
631
632 if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */
633 sdma_v5_2_ctx_switch_enable(adev, true);
634 sdma_v5_2_enable(adev, true);
635 }
636
637 r = amdgpu_ring_test_helper(ring);
638 if (r)
639 return r;
640
641 if (adev->mman.buffer_funcs_ring == ring)
642 amdgpu_ttm_set_buffer_funcs_status(adev, true);
643 }
644
645 return 0;
646 }
647
648 /**
649 * sdma_v5_2_rlc_resume - setup and start the async dma engines
650 *
651 * @adev: amdgpu_device pointer
652 *
653 * Set up the compute DMA queues and enable them.
654 * Returns 0 for success, error for failure.
655 */
sdma_v5_2_rlc_resume(struct amdgpu_device * adev)656 static int sdma_v5_2_rlc_resume(struct amdgpu_device *adev)
657 {
658 return 0;
659 }
660
661 /**
662 * sdma_v5_2_load_microcode - load the sDMA ME ucode
663 *
664 * @adev: amdgpu_device pointer
665 *
666 * Loads the sDMA0/1/2/3 ucode.
667 * Returns 0 for success, -EINVAL if the ucode is not available.
668 */
sdma_v5_2_load_microcode(struct amdgpu_device * adev)669 static int sdma_v5_2_load_microcode(struct amdgpu_device *adev)
670 {
671 const struct sdma_firmware_header_v1_0 *hdr;
672 const __le32 *fw_data;
673 u32 fw_size;
674 int i, j;
675
676 /* halt the MEs */
677 sdma_v5_2_enable(adev, false);
678
679 for (i = 0; i < adev->sdma.num_instances; i++) {
680 if (!adev->sdma.instance[i].fw)
681 return -EINVAL;
682
683 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
684 amdgpu_ucode_print_sdma_hdr(&hdr->header);
685 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
686
687 fw_data = (const __le32 *)
688 (adev->sdma.instance[i].fw->data +
689 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
690
691 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), 0);
692
693 for (j = 0; j < fw_size; j++) {
694 if (amdgpu_emu_mode == 1 && j % 500 == 0)
695 msleep(1);
696 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_DATA), le32_to_cpup(fw_data++));
697 }
698
699 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UCODE_ADDR), adev->sdma.instance[i].fw_version);
700 }
701
702 return 0;
703 }
704
sdma_v5_2_soft_reset(void * handle)705 static int sdma_v5_2_soft_reset(void *handle)
706 {
707 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
708 u32 grbm_soft_reset;
709 u32 tmp;
710 int i;
711
712 for (i = 0; i < adev->sdma.num_instances; i++) {
713 grbm_soft_reset = REG_SET_FIELD(0,
714 GRBM_SOFT_RESET, SOFT_RESET_SDMA0,
715 1);
716 grbm_soft_reset <<= i;
717
718 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
719 tmp |= grbm_soft_reset;
720 DRM_DEBUG("GRBM_SOFT_RESET=0x%08X\n", tmp);
721 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
722 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
723
724 udelay(50);
725
726 tmp &= ~grbm_soft_reset;
727 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
728 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
729
730 udelay(50);
731 }
732
733 return 0;
734 }
735
736 /**
737 * sdma_v5_2_start - setup and start the async dma engines
738 *
739 * @adev: amdgpu_device pointer
740 *
741 * Set up the DMA engines and enable them.
742 * Returns 0 for success, error for failure.
743 */
sdma_v5_2_start(struct amdgpu_device * adev)744 static int sdma_v5_2_start(struct amdgpu_device *adev)
745 {
746 int r = 0;
747
748 if (amdgpu_sriov_vf(adev)) {
749 sdma_v5_2_ctx_switch_enable(adev, false);
750 sdma_v5_2_enable(adev, false);
751
752 /* set RB registers */
753 r = sdma_v5_2_gfx_resume(adev);
754 return r;
755 }
756
757 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
758 r = sdma_v5_2_load_microcode(adev);
759 if (r)
760 return r;
761
762 /* The value of mmSDMA_F32_CNTL is invalid the moment after loading fw */
763 if (amdgpu_emu_mode == 1)
764 msleep(1000);
765 }
766
767 sdma_v5_2_soft_reset(adev);
768 /* unhalt the MEs */
769 sdma_v5_2_enable(adev, true);
770 /* enable sdma ring preemption */
771 sdma_v5_2_ctx_switch_enable(adev, true);
772
773 /* start the gfx rings and rlc compute queues */
774 r = sdma_v5_2_gfx_resume(adev);
775 if (r)
776 return r;
777 r = sdma_v5_2_rlc_resume(adev);
778
779 return r;
780 }
781
sdma_v5_2_mqd_init(struct amdgpu_device * adev,void * mqd,struct amdgpu_mqd_prop * prop)782 static int sdma_v5_2_mqd_init(struct amdgpu_device *adev, void *mqd,
783 struct amdgpu_mqd_prop *prop)
784 {
785 struct v10_sdma_mqd *m = mqd;
786 uint64_t wb_gpu_addr;
787
788 m->sdmax_rlcx_rb_cntl =
789 order_base_2(prop->queue_size / 4) << SDMA0_RLC0_RB_CNTL__RB_SIZE__SHIFT |
790 1 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_ENABLE__SHIFT |
791 6 << SDMA0_RLC0_RB_CNTL__RPTR_WRITEBACK_TIMER__SHIFT |
792 1 << SDMA0_RLC0_RB_CNTL__RB_PRIV__SHIFT;
793
794 m->sdmax_rlcx_rb_base = lower_32_bits(prop->hqd_base_gpu_addr >> 8);
795 m->sdmax_rlcx_rb_base_hi = upper_32_bits(prop->hqd_base_gpu_addr >> 8);
796
797 m->sdmax_rlcx_rb_wptr_poll_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
798 mmSDMA0_GFX_RB_WPTR_POLL_CNTL));
799
800 wb_gpu_addr = prop->wptr_gpu_addr;
801 m->sdmax_rlcx_rb_wptr_poll_addr_lo = lower_32_bits(wb_gpu_addr);
802 m->sdmax_rlcx_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr);
803
804 wb_gpu_addr = prop->rptr_gpu_addr;
805 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits(wb_gpu_addr);
806 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits(wb_gpu_addr);
807
808 m->sdmax_rlcx_ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, 0,
809 mmSDMA0_GFX_IB_CNTL));
810
811 m->sdmax_rlcx_doorbell_offset =
812 prop->doorbell_index << SDMA0_RLC0_DOORBELL_OFFSET__OFFSET__SHIFT;
813
814 m->sdmax_rlcx_doorbell = REG_SET_FIELD(0, SDMA0_RLC0_DOORBELL, ENABLE, 1);
815
816 return 0;
817 }
818
sdma_v5_2_set_mqd_funcs(struct amdgpu_device * adev)819 static void sdma_v5_2_set_mqd_funcs(struct amdgpu_device *adev)
820 {
821 adev->mqds[AMDGPU_HW_IP_DMA].mqd_size = sizeof(struct v10_sdma_mqd);
822 adev->mqds[AMDGPU_HW_IP_DMA].init_mqd = sdma_v5_2_mqd_init;
823 }
824
825 /**
826 * sdma_v5_2_ring_test_ring - simple async dma engine test
827 *
828 * @ring: amdgpu_ring structure holding ring information
829 *
830 * Test the DMA engine by writing using it to write an
831 * value to memory.
832 * Returns 0 for success, error for failure.
833 */
sdma_v5_2_ring_test_ring(struct amdgpu_ring * ring)834 static int sdma_v5_2_ring_test_ring(struct amdgpu_ring *ring)
835 {
836 struct amdgpu_device *adev = ring->adev;
837 unsigned i;
838 unsigned index;
839 int r;
840 u32 tmp;
841 u64 gpu_addr;
842 volatile uint32_t *cpu_ptr = NULL;
843
844 tmp = 0xCAFEDEAD;
845
846 if (ring->is_mes_queue) {
847 uint32_t offset = 0;
848 offset = amdgpu_mes_ctx_get_offs(ring,
849 AMDGPU_MES_CTX_PADDING_OFFS);
850 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
851 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
852 *cpu_ptr = tmp;
853 } else {
854 r = amdgpu_device_wb_get(adev, &index);
855 if (r) {
856 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
857 return r;
858 }
859
860 gpu_addr = adev->wb.gpu_addr + (index * 4);
861 adev->wb.wb[index] = cpu_to_le32(tmp);
862 }
863
864 r = amdgpu_ring_alloc(ring, 20);
865 if (r) {
866 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
867 amdgpu_device_wb_free(adev, index);
868 return r;
869 }
870
871 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
872 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
873 amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
874 amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
875 amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0));
876 amdgpu_ring_write(ring, 0xDEADBEEF);
877 amdgpu_ring_commit(ring);
878
879 for (i = 0; i < adev->usec_timeout; i++) {
880 if (ring->is_mes_queue)
881 tmp = le32_to_cpu(*cpu_ptr);
882 else
883 tmp = le32_to_cpu(adev->wb.wb[index]);
884 if (tmp == 0xDEADBEEF)
885 break;
886 if (amdgpu_emu_mode == 1)
887 msleep(1);
888 else
889 udelay(1);
890 }
891
892 if (i >= adev->usec_timeout)
893 r = -ETIMEDOUT;
894
895 if (!ring->is_mes_queue)
896 amdgpu_device_wb_free(adev, index);
897
898 return r;
899 }
900
901 /**
902 * sdma_v5_2_ring_test_ib - test an IB on the DMA engine
903 *
904 * @ring: amdgpu_ring structure holding ring information
905 * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
906 *
907 * Test a simple IB in the DMA ring.
908 * Returns 0 on success, error on failure.
909 */
sdma_v5_2_ring_test_ib(struct amdgpu_ring * ring,long timeout)910 static int sdma_v5_2_ring_test_ib(struct amdgpu_ring *ring, long timeout)
911 {
912 struct amdgpu_device *adev = ring->adev;
913 struct amdgpu_ib ib;
914 struct dma_fence *f = NULL;
915 unsigned index;
916 long r;
917 u32 tmp = 0;
918 u64 gpu_addr;
919 volatile uint32_t *cpu_ptr = NULL;
920
921 tmp = 0xCAFEDEAD;
922 memset(&ib, 0, sizeof(ib));
923
924 if (ring->is_mes_queue) {
925 uint32_t offset = 0;
926 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
927 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
928 ib.ptr = (void *)amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
929
930 offset = amdgpu_mes_ctx_get_offs(ring,
931 AMDGPU_MES_CTX_PADDING_OFFS);
932 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
933 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
934 *cpu_ptr = tmp;
935 } else {
936 r = amdgpu_device_wb_get(adev, &index);
937 if (r) {
938 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
939 return r;
940 }
941
942 gpu_addr = adev->wb.gpu_addr + (index * 4);
943 adev->wb.wb[index] = cpu_to_le32(tmp);
944
945 r = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
946 if (r) {
947 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
948 goto err0;
949 }
950 }
951
952 ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
953 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
954 ib.ptr[1] = lower_32_bits(gpu_addr);
955 ib.ptr[2] = upper_32_bits(gpu_addr);
956 ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(0);
957 ib.ptr[4] = 0xDEADBEEF;
958 ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
959 ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
960 ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
961 ib.length_dw = 8;
962
963 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
964 if (r)
965 goto err1;
966
967 r = dma_fence_wait_timeout(f, false, timeout);
968 if (r == 0) {
969 DRM_ERROR("amdgpu: IB test timed out\n");
970 r = -ETIMEDOUT;
971 goto err1;
972 } else if (r < 0) {
973 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
974 goto err1;
975 }
976
977 if (ring->is_mes_queue)
978 tmp = le32_to_cpu(*cpu_ptr);
979 else
980 tmp = le32_to_cpu(adev->wb.wb[index]);
981
982 if (tmp == 0xDEADBEEF)
983 r = 0;
984 else
985 r = -EINVAL;
986
987 err1:
988 amdgpu_ib_free(adev, &ib, NULL);
989 dma_fence_put(f);
990 err0:
991 if (!ring->is_mes_queue)
992 amdgpu_device_wb_free(adev, index);
993 return r;
994 }
995
996
997 /**
998 * sdma_v5_2_vm_copy_pte - update PTEs by copying them from the GART
999 *
1000 * @ib: indirect buffer to fill with commands
1001 * @pe: addr of the page entry
1002 * @src: src addr to copy from
1003 * @count: number of page entries to update
1004 *
1005 * Update PTEs by copying them from the GART using sDMA.
1006 */
sdma_v5_2_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)1007 static void sdma_v5_2_vm_copy_pte(struct amdgpu_ib *ib,
1008 uint64_t pe, uint64_t src,
1009 unsigned count)
1010 {
1011 unsigned bytes = count * 8;
1012
1013 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1014 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1015 ib->ptr[ib->length_dw++] = bytes - 1;
1016 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1017 ib->ptr[ib->length_dw++] = lower_32_bits(src);
1018 ib->ptr[ib->length_dw++] = upper_32_bits(src);
1019 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1020 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1021
1022 }
1023
1024 /**
1025 * sdma_v5_2_vm_write_pte - update PTEs by writing them manually
1026 *
1027 * @ib: indirect buffer to fill with commands
1028 * @pe: addr of the page entry
1029 * @value: dst addr to write into pe
1030 * @count: number of page entries to update
1031 * @incr: increase next addr by incr bytes
1032 *
1033 * Update PTEs by writing them manually using sDMA.
1034 */
sdma_v5_2_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)1035 static void sdma_v5_2_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
1036 uint64_t value, unsigned count,
1037 uint32_t incr)
1038 {
1039 unsigned ndw = count * 2;
1040
1041 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
1042 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
1043 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
1044 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1045 ib->ptr[ib->length_dw++] = ndw - 1;
1046 for (; ndw > 0; ndw -= 2) {
1047 ib->ptr[ib->length_dw++] = lower_32_bits(value);
1048 ib->ptr[ib->length_dw++] = upper_32_bits(value);
1049 value += incr;
1050 }
1051 }
1052
1053 /**
1054 * sdma_v5_2_vm_set_pte_pde - update the page tables using sDMA
1055 *
1056 * @ib: indirect buffer to fill with commands
1057 * @pe: addr of the page entry
1058 * @addr: dst addr to write into pe
1059 * @count: number of page entries to update
1060 * @incr: increase next addr by incr bytes
1061 * @flags: access flags
1062 *
1063 * Update the page tables using sDMA.
1064 */
sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)1065 static void sdma_v5_2_vm_set_pte_pde(struct amdgpu_ib *ib,
1066 uint64_t pe,
1067 uint64_t addr, unsigned count,
1068 uint32_t incr, uint64_t flags)
1069 {
1070 /* for physically contiguous pages (vram) */
1071 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_PTEPDE);
1072 ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
1073 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
1074 ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
1075 ib->ptr[ib->length_dw++] = upper_32_bits(flags);
1076 ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
1077 ib->ptr[ib->length_dw++] = upper_32_bits(addr);
1078 ib->ptr[ib->length_dw++] = incr; /* increment size */
1079 ib->ptr[ib->length_dw++] = 0;
1080 ib->ptr[ib->length_dw++] = count - 1; /* number of entries */
1081 }
1082
1083 /**
1084 * sdma_v5_2_ring_pad_ib - pad the IB
1085 *
1086 * @ib: indirect buffer to fill with padding
1087 * @ring: amdgpu_ring structure holding ring information
1088 *
1089 * Pad the IB with NOPs to a boundary multiple of 8.
1090 */
sdma_v5_2_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)1091 static void sdma_v5_2_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1092 {
1093 struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1094 u32 pad_count;
1095 int i;
1096
1097 pad_count = (-ib->length_dw) & 0x7;
1098 for (i = 0; i < pad_count; i++)
1099 if (sdma && sdma->burst_nop && (i == 0))
1100 ib->ptr[ib->length_dw++] =
1101 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1102 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1103 else
1104 ib->ptr[ib->length_dw++] =
1105 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1106 }
1107
1108
1109 /**
1110 * sdma_v5_2_ring_emit_pipeline_sync - sync the pipeline
1111 *
1112 * @ring: amdgpu_ring pointer
1113 *
1114 * Make sure all previous operations are completed (CIK).
1115 */
sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring * ring)1116 static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1117 {
1118 uint32_t seq = ring->fence_drv.sync_seq;
1119 uint64_t addr = ring->fence_drv.gpu_addr;
1120
1121 /* wait for idle */
1122 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1123 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1124 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1125 SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1126 amdgpu_ring_write(ring, addr & 0xfffffffc);
1127 amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1128 amdgpu_ring_write(ring, seq); /* reference */
1129 amdgpu_ring_write(ring, 0xffffffff); /* mask */
1130 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1131 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1132 }
1133
1134
1135 /**
1136 * sdma_v5_2_ring_emit_vm_flush - vm flush using sDMA
1137 *
1138 * @ring: amdgpu_ring pointer
1139 * @vmid: vmid number to use
1140 * @pd_addr: address
1141 *
1142 * Update the page table base and flush the VM TLB
1143 * using sDMA.
1144 */
sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)1145 static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring,
1146 unsigned vmid, uint64_t pd_addr)
1147 {
1148 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1149 }
1150
sdma_v5_2_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)1151 static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring,
1152 uint32_t reg, uint32_t val)
1153 {
1154 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1155 SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1156 amdgpu_ring_write(ring, reg);
1157 amdgpu_ring_write(ring, val);
1158 }
1159
sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)1160 static void sdma_v5_2_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1161 uint32_t val, uint32_t mask)
1162 {
1163 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1164 SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1165 SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
1166 amdgpu_ring_write(ring, reg << 2);
1167 amdgpu_ring_write(ring, 0);
1168 amdgpu_ring_write(ring, val); /* reference */
1169 amdgpu_ring_write(ring, mask); /* mask */
1170 amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1171 SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
1172 }
1173
sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)1174 static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
1175 uint32_t reg0, uint32_t reg1,
1176 uint32_t ref, uint32_t mask)
1177 {
1178 amdgpu_ring_emit_wreg(ring, reg0, ref);
1179 /* wait for a cycle to reset vm_inv_eng*_ack */
1180 amdgpu_ring_emit_reg_wait(ring, reg0, 0, 0);
1181 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
1182 }
1183
sdma_v5_2_early_init(void * handle)1184 static int sdma_v5_2_early_init(void *handle)
1185 {
1186 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1187
1188 sdma_v5_2_set_ring_funcs(adev);
1189 sdma_v5_2_set_buffer_funcs(adev);
1190 sdma_v5_2_set_vm_pte_funcs(adev);
1191 sdma_v5_2_set_irq_funcs(adev);
1192 sdma_v5_2_set_mqd_funcs(adev);
1193
1194 return 0;
1195 }
1196
sdma_v5_2_seq_to_irq_id(int seq_num)1197 static unsigned sdma_v5_2_seq_to_irq_id(int seq_num)
1198 {
1199 switch (seq_num) {
1200 case 0:
1201 return SOC15_IH_CLIENTID_SDMA0;
1202 case 1:
1203 return SOC15_IH_CLIENTID_SDMA1;
1204 case 2:
1205 return SOC15_IH_CLIENTID_SDMA2;
1206 case 3:
1207 return SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid;
1208 default:
1209 break;
1210 }
1211 return -EINVAL;
1212 }
1213
sdma_v5_2_seq_to_trap_id(int seq_num)1214 static unsigned sdma_v5_2_seq_to_trap_id(int seq_num)
1215 {
1216 switch (seq_num) {
1217 case 0:
1218 return SDMA0_5_0__SRCID__SDMA_TRAP;
1219 case 1:
1220 return SDMA1_5_0__SRCID__SDMA_TRAP;
1221 case 2:
1222 return SDMA2_5_0__SRCID__SDMA_TRAP;
1223 case 3:
1224 return SDMA3_5_0__SRCID__SDMA_TRAP;
1225 default:
1226 break;
1227 }
1228 return -EINVAL;
1229 }
1230
sdma_v5_2_sw_init(void * handle)1231 static int sdma_v5_2_sw_init(void *handle)
1232 {
1233 struct amdgpu_ring *ring;
1234 int r, i;
1235 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1236
1237 /* SDMA trap event */
1238 for (i = 0; i < adev->sdma.num_instances; i++) {
1239 r = amdgpu_irq_add_id(adev, sdma_v5_2_seq_to_irq_id(i),
1240 sdma_v5_2_seq_to_trap_id(i),
1241 &adev->sdma.trap_irq);
1242 if (r)
1243 return r;
1244 }
1245
1246 r = amdgpu_sdma_init_microcode(adev, 0, true);
1247 if (r) {
1248 DRM_ERROR("Failed to load sdma firmware!\n");
1249 return r;
1250 }
1251
1252 for (i = 0; i < adev->sdma.num_instances; i++) {
1253 ring = &adev->sdma.instance[i].ring;
1254 ring->ring_obj = NULL;
1255 ring->use_doorbell = true;
1256 ring->me = i;
1257
1258 DRM_INFO("use_doorbell being set to: [%s]\n",
1259 ring->use_doorbell?"true":"false");
1260
1261 ring->doorbell_index =
1262 (adev->doorbell_index.sdma_engine[i] << 1); //get DWORD offset
1263
1264 ring->vm_hub = AMDGPU_GFXHUB(0);
1265 sprintf(ring->name, "sdma%d", i);
1266 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1267 AMDGPU_SDMA_IRQ_INSTANCE0 + i,
1268 AMDGPU_RING_PRIO_DEFAULT, NULL);
1269 if (r)
1270 return r;
1271 }
1272
1273 return r;
1274 }
1275
sdma_v5_2_sw_fini(void * handle)1276 static int sdma_v5_2_sw_fini(void *handle)
1277 {
1278 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1279 int i;
1280
1281 for (i = 0; i < adev->sdma.num_instances; i++)
1282 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1283
1284 amdgpu_sdma_destroy_inst_ctx(adev, true);
1285
1286 return 0;
1287 }
1288
sdma_v5_2_hw_init(void * handle)1289 static int sdma_v5_2_hw_init(void *handle)
1290 {
1291 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1292
1293 return sdma_v5_2_start(adev);
1294 }
1295
sdma_v5_2_hw_fini(void * handle)1296 static int sdma_v5_2_hw_fini(void *handle)
1297 {
1298 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1299
1300 if (amdgpu_sriov_vf(adev)) {
1301 /* disable the scheduler for SDMA */
1302 amdgpu_sdma_unset_buffer_funcs_helper(adev);
1303 return 0;
1304 }
1305
1306 sdma_v5_2_ctx_switch_enable(adev, false);
1307 sdma_v5_2_enable(adev, false);
1308
1309 return 0;
1310 }
1311
sdma_v5_2_suspend(void * handle)1312 static int sdma_v5_2_suspend(void *handle)
1313 {
1314 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1315
1316 return sdma_v5_2_hw_fini(adev);
1317 }
1318
sdma_v5_2_resume(void * handle)1319 static int sdma_v5_2_resume(void *handle)
1320 {
1321 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1322
1323 return sdma_v5_2_hw_init(adev);
1324 }
1325
sdma_v5_2_is_idle(void * handle)1326 static bool sdma_v5_2_is_idle(void *handle)
1327 {
1328 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1329 u32 i;
1330
1331 for (i = 0; i < adev->sdma.num_instances; i++) {
1332 u32 tmp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS_REG));
1333
1334 if (!(tmp & SDMA0_STATUS_REG__IDLE_MASK))
1335 return false;
1336 }
1337
1338 return true;
1339 }
1340
sdma_v5_2_wait_for_idle(void * handle)1341 static int sdma_v5_2_wait_for_idle(void *handle)
1342 {
1343 unsigned i;
1344 u32 sdma0, sdma1, sdma2, sdma3;
1345 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1346
1347 for (i = 0; i < adev->usec_timeout; i++) {
1348 sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG));
1349 sdma1 = RREG32(sdma_v5_2_get_reg_offset(adev, 1, mmSDMA0_STATUS_REG));
1350 sdma2 = RREG32(sdma_v5_2_get_reg_offset(adev, 2, mmSDMA0_STATUS_REG));
1351 sdma3 = RREG32(sdma_v5_2_get_reg_offset(adev, 3, mmSDMA0_STATUS_REG));
1352
1353 if (sdma0 & sdma1 & sdma2 & sdma3 & SDMA0_STATUS_REG__IDLE_MASK)
1354 return 0;
1355 udelay(1);
1356 }
1357 return -ETIMEDOUT;
1358 }
1359
sdma_v5_2_ring_preempt_ib(struct amdgpu_ring * ring)1360 static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring)
1361 {
1362 int i, r = 0;
1363 struct amdgpu_device *adev = ring->adev;
1364 u32 index = 0;
1365 u64 sdma_gfx_preempt;
1366
1367 amdgpu_sdma_get_index_from_ring(ring, &index);
1368 sdma_gfx_preempt =
1369 sdma_v5_2_get_reg_offset(adev, index, mmSDMA0_GFX_PREEMPT);
1370
1371 /* assert preemption condition */
1372 amdgpu_ring_set_preempt_cond_exec(ring, false);
1373
1374 /* emit the trailing fence */
1375 ring->trail_seq += 1;
1376 amdgpu_ring_alloc(ring, 10);
1377 sdma_v5_2_ring_emit_fence(ring, ring->trail_fence_gpu_addr,
1378 ring->trail_seq, 0);
1379 amdgpu_ring_commit(ring);
1380
1381 /* assert IB preemption */
1382 WREG32(sdma_gfx_preempt, 1);
1383
1384 /* poll the trailing fence */
1385 for (i = 0; i < adev->usec_timeout; i++) {
1386 if (ring->trail_seq ==
1387 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
1388 break;
1389 udelay(1);
1390 }
1391
1392 if (i >= adev->usec_timeout) {
1393 r = -EINVAL;
1394 DRM_ERROR("ring %d failed to be preempted\n", ring->idx);
1395 }
1396
1397 /* deassert IB preemption */
1398 WREG32(sdma_gfx_preempt, 0);
1399
1400 /* deassert the preemption condition */
1401 amdgpu_ring_set_preempt_cond_exec(ring, true);
1402 return r;
1403 }
1404
sdma_v5_2_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)1405 static int sdma_v5_2_set_trap_irq_state(struct amdgpu_device *adev,
1406 struct amdgpu_irq_src *source,
1407 unsigned type,
1408 enum amdgpu_interrupt_state state)
1409 {
1410 u32 sdma_cntl;
1411 u32 reg_offset = sdma_v5_2_get_reg_offset(adev, type, mmSDMA0_CNTL);
1412
1413 if (!amdgpu_sriov_vf(adev)) {
1414 sdma_cntl = RREG32(reg_offset);
1415 sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE,
1416 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
1417 WREG32(reg_offset, sdma_cntl);
1418 }
1419
1420 return 0;
1421 }
1422
sdma_v5_2_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1423 static int sdma_v5_2_process_trap_irq(struct amdgpu_device *adev,
1424 struct amdgpu_irq_src *source,
1425 struct amdgpu_iv_entry *entry)
1426 {
1427 uint32_t mes_queue_id = entry->src_data[0];
1428
1429 DRM_DEBUG("IH: SDMA trap\n");
1430
1431 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
1432 struct amdgpu_mes_queue *queue;
1433
1434 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
1435
1436 spin_lock(&adev->mes.queue_id_lock);
1437 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
1438 if (queue) {
1439 DRM_DEBUG("process smda queue id = %d\n", mes_queue_id);
1440 amdgpu_fence_process(queue->ring);
1441 }
1442 spin_unlock(&adev->mes.queue_id_lock);
1443 return 0;
1444 }
1445
1446 switch (entry->client_id) {
1447 case SOC15_IH_CLIENTID_SDMA0:
1448 switch (entry->ring_id) {
1449 case 0:
1450 amdgpu_fence_process(&adev->sdma.instance[0].ring);
1451 break;
1452 case 1:
1453 /* XXX compute */
1454 break;
1455 case 2:
1456 /* XXX compute */
1457 break;
1458 case 3:
1459 /* XXX page queue*/
1460 break;
1461 }
1462 break;
1463 case SOC15_IH_CLIENTID_SDMA1:
1464 switch (entry->ring_id) {
1465 case 0:
1466 amdgpu_fence_process(&adev->sdma.instance[1].ring);
1467 break;
1468 case 1:
1469 /* XXX compute */
1470 break;
1471 case 2:
1472 /* XXX compute */
1473 break;
1474 case 3:
1475 /* XXX page queue*/
1476 break;
1477 }
1478 break;
1479 case SOC15_IH_CLIENTID_SDMA2:
1480 switch (entry->ring_id) {
1481 case 0:
1482 amdgpu_fence_process(&adev->sdma.instance[2].ring);
1483 break;
1484 case 1:
1485 /* XXX compute */
1486 break;
1487 case 2:
1488 /* XXX compute */
1489 break;
1490 case 3:
1491 /* XXX page queue*/
1492 break;
1493 }
1494 break;
1495 case SOC15_IH_CLIENTID_SDMA3_Sienna_Cichlid:
1496 switch (entry->ring_id) {
1497 case 0:
1498 amdgpu_fence_process(&adev->sdma.instance[3].ring);
1499 break;
1500 case 1:
1501 /* XXX compute */
1502 break;
1503 case 2:
1504 /* XXX compute */
1505 break;
1506 case 3:
1507 /* XXX page queue*/
1508 break;
1509 }
1510 break;
1511 }
1512 return 0;
1513 }
1514
sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1515 static int sdma_v5_2_process_illegal_inst_irq(struct amdgpu_device *adev,
1516 struct amdgpu_irq_src *source,
1517 struct amdgpu_iv_entry *entry)
1518 {
1519 return 0;
1520 }
1521
sdma_v5_2_firmware_mgcg_support(struct amdgpu_device * adev,int i)1522 static bool sdma_v5_2_firmware_mgcg_support(struct amdgpu_device *adev,
1523 int i)
1524 {
1525 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1526 case IP_VERSION(5, 2, 1):
1527 if (adev->sdma.instance[i].fw_version < 70)
1528 return false;
1529 break;
1530 case IP_VERSION(5, 2, 3):
1531 if (adev->sdma.instance[i].fw_version < 47)
1532 return false;
1533 break;
1534 case IP_VERSION(5, 2, 7):
1535 if (adev->sdma.instance[i].fw_version < 9)
1536 return false;
1537 break;
1538 default:
1539 return true;
1540 }
1541
1542 return true;
1543
1544 }
1545
sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)1546 static void sdma_v5_2_update_medium_grain_clock_gating(struct amdgpu_device *adev,
1547 bool enable)
1548 {
1549 uint32_t data, def;
1550 int i;
1551
1552 for (i = 0; i < adev->sdma.num_instances; i++) {
1553
1554 if (!sdma_v5_2_firmware_mgcg_support(adev, i))
1555 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_MGCG;
1556
1557 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1558 /* Enable sdma clock gating */
1559 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1560 data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1561 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1562 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1563 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1564 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1565 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1566 if (def != data)
1567 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1568 } else {
1569 /* Disable sdma clock gating */
1570 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL));
1571 data |= (SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1572 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1573 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1574 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1575 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK |
1576 SDMA0_CLK_CTRL__SOFT_OVERRIDER_REG_MASK);
1577 if (def != data)
1578 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CLK_CTRL), data);
1579 }
1580 }
1581 }
1582
sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device * adev,bool enable)1583 static void sdma_v5_2_update_medium_grain_light_sleep(struct amdgpu_device *adev,
1584 bool enable)
1585 {
1586 uint32_t data, def;
1587 int i;
1588
1589 for (i = 0; i < adev->sdma.num_instances; i++) {
1590
1591 if (adev->sdma.instance[i].fw_version < 70 && adev->ip_versions[SDMA0_HWIP][0] == IP_VERSION(5, 2, 1))
1592 adev->cg_flags &= ~AMD_CG_SUPPORT_SDMA_LS;
1593
1594 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1595 /* Enable sdma mem light sleep */
1596 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1597 data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1598 if (def != data)
1599 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1600
1601 } else {
1602 /* Disable sdma mem light sleep */
1603 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL));
1604 data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1605 if (def != data)
1606 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data);
1607
1608 }
1609 }
1610 }
1611
sdma_v5_2_set_clockgating_state(void * handle,enum amd_clockgating_state state)1612 static int sdma_v5_2_set_clockgating_state(void *handle,
1613 enum amd_clockgating_state state)
1614 {
1615 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1616
1617 if (amdgpu_sriov_vf(adev))
1618 return 0;
1619
1620 switch (adev->ip_versions[SDMA0_HWIP][0]) {
1621 case IP_VERSION(5, 2, 0):
1622 case IP_VERSION(5, 2, 2):
1623 case IP_VERSION(5, 2, 1):
1624 case IP_VERSION(5, 2, 4):
1625 case IP_VERSION(5, 2, 5):
1626 case IP_VERSION(5, 2, 6):
1627 case IP_VERSION(5, 2, 3):
1628 case IP_VERSION(5, 2, 7):
1629 sdma_v5_2_update_medium_grain_clock_gating(adev,
1630 state == AMD_CG_STATE_GATE);
1631 sdma_v5_2_update_medium_grain_light_sleep(adev,
1632 state == AMD_CG_STATE_GATE);
1633 break;
1634 default:
1635 break;
1636 }
1637
1638 return 0;
1639 }
1640
sdma_v5_2_set_powergating_state(void * handle,enum amd_powergating_state state)1641 static int sdma_v5_2_set_powergating_state(void *handle,
1642 enum amd_powergating_state state)
1643 {
1644 return 0;
1645 }
1646
sdma_v5_2_get_clockgating_state(void * handle,u64 * flags)1647 static void sdma_v5_2_get_clockgating_state(void *handle, u64 *flags)
1648 {
1649 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1650 int data;
1651
1652 if (amdgpu_sriov_vf(adev))
1653 *flags = 0;
1654
1655 /* AMD_CG_SUPPORT_SDMA_MGCG */
1656 data = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_CLK_CTRL));
1657 if (!(data & SDMA0_CLK_CTRL__CGCG_EN_OVERRIDE_MASK))
1658 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1659
1660 /* AMD_CG_SUPPORT_SDMA_LS */
1661 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
1662 if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1663 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1664 }
1665
sdma_v5_2_ring_begin_use(struct amdgpu_ring * ring)1666 static void sdma_v5_2_ring_begin_use(struct amdgpu_ring *ring)
1667 {
1668 struct amdgpu_device *adev = ring->adev;
1669
1670 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly
1671 * disallow GFXOFF in some cases leading to
1672 * hangs in SDMA. Disallow GFXOFF while SDMA is active.
1673 * We can probably just limit this to 5.2.3,
1674 * but it shouldn't hurt for other parts since
1675 * this GFXOFF will be disallowed anyway when SDMA is
1676 * active, this just makes it explicit.
1677 * sdma_v5_2_ring_set_wptr() takes advantage of this
1678 * to update the wptr because sometimes SDMA seems to miss
1679 * doorbells when entering PG. If you remove this, update
1680 * sdma_v5_2_ring_set_wptr() as well!
1681 */
1682 amdgpu_gfx_off_ctrl(adev, false);
1683 }
1684
sdma_v5_2_ring_end_use(struct amdgpu_ring * ring)1685 static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring)
1686 {
1687 struct amdgpu_device *adev = ring->adev;
1688
1689 /* SDMA 5.2.3 (RMB) FW doesn't seem to properly
1690 * disallow GFXOFF in some cases leading to
1691 * hangs in SDMA. Allow GFXOFF when SDMA is complete.
1692 */
1693 amdgpu_gfx_off_ctrl(adev, true);
1694 }
1695
1696 const struct amd_ip_funcs sdma_v5_2_ip_funcs = {
1697 .name = "sdma_v5_2",
1698 .early_init = sdma_v5_2_early_init,
1699 .late_init = NULL,
1700 .sw_init = sdma_v5_2_sw_init,
1701 .sw_fini = sdma_v5_2_sw_fini,
1702 .hw_init = sdma_v5_2_hw_init,
1703 .hw_fini = sdma_v5_2_hw_fini,
1704 .suspend = sdma_v5_2_suspend,
1705 .resume = sdma_v5_2_resume,
1706 .is_idle = sdma_v5_2_is_idle,
1707 .wait_for_idle = sdma_v5_2_wait_for_idle,
1708 .soft_reset = sdma_v5_2_soft_reset,
1709 .set_clockgating_state = sdma_v5_2_set_clockgating_state,
1710 .set_powergating_state = sdma_v5_2_set_powergating_state,
1711 .get_clockgating_state = sdma_v5_2_get_clockgating_state,
1712 };
1713
1714 static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = {
1715 .type = AMDGPU_RING_TYPE_SDMA,
1716 .align_mask = 0xf,
1717 .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1718 .support_64bit_ptrs = true,
1719 .secure_submission_supported = true,
1720 .get_rptr = sdma_v5_2_ring_get_rptr,
1721 .get_wptr = sdma_v5_2_ring_get_wptr,
1722 .set_wptr = sdma_v5_2_ring_set_wptr,
1723 .emit_frame_size =
1724 5 + /* sdma_v5_2_ring_init_cond_exec */
1725 6 + /* sdma_v5_2_ring_emit_hdp_flush */
1726 3 + /* hdp_invalidate */
1727 6 + /* sdma_v5_2_ring_emit_pipeline_sync */
1728 /* sdma_v5_2_ring_emit_vm_flush */
1729 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1730 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6 +
1731 10 + 10 + 10, /* sdma_v5_2_ring_emit_fence x3 for user fence, vm fence */
1732 .emit_ib_size = 7 + 6, /* sdma_v5_2_ring_emit_ib */
1733 .emit_ib = sdma_v5_2_ring_emit_ib,
1734 .emit_mem_sync = sdma_v5_2_ring_emit_mem_sync,
1735 .emit_fence = sdma_v5_2_ring_emit_fence,
1736 .emit_pipeline_sync = sdma_v5_2_ring_emit_pipeline_sync,
1737 .emit_vm_flush = sdma_v5_2_ring_emit_vm_flush,
1738 .emit_hdp_flush = sdma_v5_2_ring_emit_hdp_flush,
1739 .test_ring = sdma_v5_2_ring_test_ring,
1740 .test_ib = sdma_v5_2_ring_test_ib,
1741 .insert_nop = sdma_v5_2_ring_insert_nop,
1742 .pad_ib = sdma_v5_2_ring_pad_ib,
1743 .begin_use = sdma_v5_2_ring_begin_use,
1744 .end_use = sdma_v5_2_ring_end_use,
1745 .emit_wreg = sdma_v5_2_ring_emit_wreg,
1746 .emit_reg_wait = sdma_v5_2_ring_emit_reg_wait,
1747 .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait,
1748 .init_cond_exec = sdma_v5_2_ring_init_cond_exec,
1749 .patch_cond_exec = sdma_v5_2_ring_patch_cond_exec,
1750 .preempt_ib = sdma_v5_2_ring_preempt_ib,
1751 };
1752
sdma_v5_2_set_ring_funcs(struct amdgpu_device * adev)1753 static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev)
1754 {
1755 int i;
1756
1757 for (i = 0; i < adev->sdma.num_instances; i++) {
1758 adev->sdma.instance[i].ring.funcs = &sdma_v5_2_ring_funcs;
1759 adev->sdma.instance[i].ring.me = i;
1760 }
1761 }
1762
1763 static const struct amdgpu_irq_src_funcs sdma_v5_2_trap_irq_funcs = {
1764 .set = sdma_v5_2_set_trap_irq_state,
1765 .process = sdma_v5_2_process_trap_irq,
1766 };
1767
1768 static const struct amdgpu_irq_src_funcs sdma_v5_2_illegal_inst_irq_funcs = {
1769 .process = sdma_v5_2_process_illegal_inst_irq,
1770 };
1771
sdma_v5_2_set_irq_funcs(struct amdgpu_device * adev)1772 static void sdma_v5_2_set_irq_funcs(struct amdgpu_device *adev)
1773 {
1774 adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_INSTANCE0 +
1775 adev->sdma.num_instances;
1776 adev->sdma.trap_irq.funcs = &sdma_v5_2_trap_irq_funcs;
1777 adev->sdma.illegal_inst_irq.funcs = &sdma_v5_2_illegal_inst_irq_funcs;
1778 }
1779
1780 /**
1781 * sdma_v5_2_emit_copy_buffer - copy buffer using the sDMA engine
1782 *
1783 * @ib: indirect buffer to copy to
1784 * @src_offset: src GPU address
1785 * @dst_offset: dst GPU address
1786 * @byte_count: number of bytes to xfer
1787 * @tmz: if a secure copy should be used
1788 *
1789 * Copy GPU buffers using the DMA engine.
1790 * Used by the amdgpu ttm implementation to move pages if
1791 * registered as the asic copy callback.
1792 */
sdma_v5_2_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,bool tmz)1793 static void sdma_v5_2_emit_copy_buffer(struct amdgpu_ib *ib,
1794 uint64_t src_offset,
1795 uint64_t dst_offset,
1796 uint32_t byte_count,
1797 bool tmz)
1798 {
1799 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1800 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) |
1801 SDMA_PKT_COPY_LINEAR_HEADER_TMZ(tmz ? 1 : 0);
1802 ib->ptr[ib->length_dw++] = byte_count - 1;
1803 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1804 ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1805 ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1806 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1807 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1808 }
1809
1810 /**
1811 * sdma_v5_2_emit_fill_buffer - fill buffer using the sDMA engine
1812 *
1813 * @ib: indirect buffer to fill
1814 * @src_data: value to write to buffer
1815 * @dst_offset: dst GPU address
1816 * @byte_count: number of bytes to xfer
1817 *
1818 * Fill GPU buffers using the DMA engine.
1819 */
sdma_v5_2_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)1820 static void sdma_v5_2_emit_fill_buffer(struct amdgpu_ib *ib,
1821 uint32_t src_data,
1822 uint64_t dst_offset,
1823 uint32_t byte_count)
1824 {
1825 ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1826 ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1827 ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1828 ib->ptr[ib->length_dw++] = src_data;
1829 ib->ptr[ib->length_dw++] = byte_count - 1;
1830 }
1831
1832 static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
1833 .copy_max_bytes = 0x400000,
1834 .copy_num_dw = 7,
1835 .emit_copy_buffer = sdma_v5_2_emit_copy_buffer,
1836
1837 .fill_max_bytes = 0x400000,
1838 .fill_num_dw = 5,
1839 .emit_fill_buffer = sdma_v5_2_emit_fill_buffer,
1840 };
1841
sdma_v5_2_set_buffer_funcs(struct amdgpu_device * adev)1842 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
1843 {
1844 if (adev->mman.buffer_funcs == NULL) {
1845 adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
1846 adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1847 }
1848 }
1849
1850 static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
1851 .copy_pte_num_dw = 7,
1852 .copy_pte = sdma_v5_2_vm_copy_pte,
1853 .write_pte = sdma_v5_2_vm_write_pte,
1854 .set_pte_pde = sdma_v5_2_vm_set_pte_pde,
1855 };
1856
sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device * adev)1857 static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
1858 {
1859 unsigned i;
1860
1861 if (adev->vm_manager.vm_pte_funcs == NULL) {
1862 adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
1863 for (i = 0; i < adev->sdma.num_instances; i++) {
1864 adev->vm_manager.vm_pte_scheds[i] =
1865 &adev->sdma.instance[i].ring.sched;
1866 }
1867 adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1868 }
1869 }
1870
1871 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
1872 .type = AMD_IP_BLOCK_TYPE_SDMA,
1873 .major = 5,
1874 .minor = 2,
1875 .rev = 0,
1876 .funcs = &sdma_v5_2_ip_funcs,
1877 };
1878