1 /*
2  * Copyright 2014 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 
25 #include <linux/delay.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 
29 #include "amdgpu.h"
30 #include "amdgpu_ucode.h"
31 #include "amdgpu_trace.h"
32 #include "vi.h"
33 #include "vid.h"
34 
35 #include "oss/oss_2_4_d.h"
36 #include "oss/oss_2_4_sh_mask.h"
37 
38 #include "gmc/gmc_7_1_d.h"
39 #include "gmc/gmc_7_1_sh_mask.h"
40 
41 #include "gca/gfx_8_0_d.h"
42 #include "gca/gfx_8_0_enum.h"
43 #include "gca/gfx_8_0_sh_mask.h"
44 
45 #include "bif/bif_5_0_d.h"
46 #include "bif/bif_5_0_sh_mask.h"
47 
48 #include "iceland_sdma_pkt_open.h"
49 
50 #include "ivsrcid/ivsrcid_vislands30.h"
51 
52 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
53 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
54 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
55 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
56 
57 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
58 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
59 
60 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
61 {
62 	SDMA0_REGISTER_OFFSET,
63 	SDMA1_REGISTER_OFFSET
64 };
65 
66 static const u32 golden_settings_iceland_a11[] =
67 {
68 	mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
69 	mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
70 	mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
71 	mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
72 };
73 
74 static const u32 iceland_mgcg_cgcg_init[] =
75 {
76 	mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
77 	mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
78 };
79 
80 /*
81  * sDMA - System DMA
82  * Starting with CIK, the GPU has new asynchronous
83  * DMA engines.  These engines are used for compute
84  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
85  * and each one supports 1 ring buffer used for gfx
86  * and 2 queues used for compute.
87  *
88  * The programming model is very similar to the CP
89  * (ring buffer, IBs, etc.), but sDMA has it's own
90  * packet format that is different from the PM4 format
91  * used by the CP. sDMA supports copying data, writing
92  * embedded data, solid fills, and a number of other
93  * things.  It also has support for tiling/detiling of
94  * buffers.
95  */
96 
sdma_v2_4_init_golden_registers(struct amdgpu_device * adev)97 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
98 {
99 	switch (adev->asic_type) {
100 	case CHIP_TOPAZ:
101 		amdgpu_device_program_register_sequence(adev,
102 							iceland_mgcg_cgcg_init,
103 							ARRAY_SIZE(iceland_mgcg_cgcg_init));
104 		amdgpu_device_program_register_sequence(adev,
105 							golden_settings_iceland_a11,
106 							ARRAY_SIZE(golden_settings_iceland_a11));
107 		break;
108 	default:
109 		break;
110 	}
111 }
112 
sdma_v2_4_free_microcode(struct amdgpu_device * adev)113 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
114 {
115 	int i;
116 
117 	for (i = 0; i < adev->sdma.num_instances; i++)
118 		amdgpu_ucode_release(&adev->sdma.instance[i].fw);
119 }
120 
121 /**
122  * sdma_v2_4_init_microcode - load ucode images from disk
123  *
124  * @adev: amdgpu_device pointer
125  *
126  * Use the firmware interface to load the ucode images into
127  * the driver (not loaded into hw).
128  * Returns 0 on success, error on failure.
129  */
sdma_v2_4_init_microcode(struct amdgpu_device * adev)130 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
131 {
132 	const char *chip_name;
133 	char fw_name[30];
134 	int err = 0, i;
135 	struct amdgpu_firmware_info *info = NULL;
136 	const struct common_firmware_header *header = NULL;
137 	const struct sdma_firmware_header_v1_0 *hdr;
138 
139 	DRM_DEBUG("\n");
140 
141 	switch (adev->asic_type) {
142 	case CHIP_TOPAZ:
143 		chip_name = "topaz";
144 		break;
145 	default: BUG();
146 	}
147 
148 	for (i = 0; i < adev->sdma.num_instances; i++) {
149 		if (i == 0)
150 			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
151 		else
152 			snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
153 		err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name);
154 		if (err)
155 			goto out;
156 		hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
157 		adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
158 		adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
159 		if (adev->sdma.instance[i].feature_version >= 20)
160 			adev->sdma.instance[i].burst_nop = true;
161 
162 		if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
163 			info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
164 			info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
165 			info->fw = adev->sdma.instance[i].fw;
166 			header = (const struct common_firmware_header *)info->fw->data;
167 			adev->firmware.fw_size +=
168 				ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
169 		}
170 	}
171 
172 out:
173 	if (err) {
174 		pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name);
175 		for (i = 0; i < adev->sdma.num_instances; i++)
176 			amdgpu_ucode_release(&adev->sdma.instance[i].fw);
177 	}
178 	return err;
179 }
180 
181 /**
182  * sdma_v2_4_ring_get_rptr - get the current read pointer
183  *
184  * @ring: amdgpu ring pointer
185  *
186  * Get the current rptr from the hardware (VI+).
187  */
sdma_v2_4_ring_get_rptr(struct amdgpu_ring * ring)188 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
189 {
190 	/* XXX check if swapping is necessary on BE */
191 	return *ring->rptr_cpu_addr >> 2;
192 }
193 
194 /**
195  * sdma_v2_4_ring_get_wptr - get the current write pointer
196  *
197  * @ring: amdgpu ring pointer
198  *
199  * Get the current wptr from the hardware (VI+).
200  */
sdma_v2_4_ring_get_wptr(struct amdgpu_ring * ring)201 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
202 {
203 	struct amdgpu_device *adev = ring->adev;
204 	u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
205 
206 	return wptr;
207 }
208 
209 /**
210  * sdma_v2_4_ring_set_wptr - commit the write pointer
211  *
212  * @ring: amdgpu ring pointer
213  *
214  * Write the wptr back to the hardware (VI+).
215  */
sdma_v2_4_ring_set_wptr(struct amdgpu_ring * ring)216 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
217 {
218 	struct amdgpu_device *adev = ring->adev;
219 
220 	WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);
221 }
222 
sdma_v2_4_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)223 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
224 {
225 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
226 	int i;
227 
228 	for (i = 0; i < count; i++)
229 		if (sdma && sdma->burst_nop && (i == 0))
230 			amdgpu_ring_write(ring, ring->funcs->nop |
231 				SDMA_PKT_NOP_HEADER_COUNT(count - 1));
232 		else
233 			amdgpu_ring_write(ring, ring->funcs->nop);
234 }
235 
236 /**
237  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
238  *
239  * @ring: amdgpu ring pointer
240  * @job: job to retrieve vmid from
241  * @ib: IB object to schedule
242  * @flags: unused
243  *
244  * Schedule an IB in the DMA ring (VI).
245  */
sdma_v2_4_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)246 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
247 				   struct amdgpu_job *job,
248 				   struct amdgpu_ib *ib,
249 				   uint32_t flags)
250 {
251 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
252 
253 	/* IB packet must end on a 8 DW boundary */
254 	sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
255 
256 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
257 			  SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
258 	/* base must be 32 byte aligned */
259 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
260 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
261 	amdgpu_ring_write(ring, ib->length_dw);
262 	amdgpu_ring_write(ring, 0);
263 	amdgpu_ring_write(ring, 0);
264 
265 }
266 
267 /**
268  * sdma_v2_4_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
269  *
270  * @ring: amdgpu ring pointer
271  *
272  * Emit an hdp flush packet on the requested DMA ring.
273  */
sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring * ring)274 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
275 {
276 	u32 ref_and_mask = 0;
277 
278 	if (ring->me == 0)
279 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
280 	else
281 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
282 
283 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
284 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
285 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
286 	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
287 	amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
288 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
289 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
290 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
291 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
292 }
293 
294 /**
295  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
296  *
297  * @ring: amdgpu ring pointer
298  * @addr: address
299  * @seq: sequence number
300  * @flags: fence related flags
301  *
302  * Add a DMA fence packet to the ring to write
303  * the fence seq number and DMA trap packet to generate
304  * an interrupt if needed (VI).
305  */
sdma_v2_4_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)306 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
307 				      unsigned flags)
308 {
309 	bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
310 	/* write the fence */
311 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
312 	amdgpu_ring_write(ring, lower_32_bits(addr));
313 	amdgpu_ring_write(ring, upper_32_bits(addr));
314 	amdgpu_ring_write(ring, lower_32_bits(seq));
315 
316 	/* optionally write high bits as well */
317 	if (write64bit) {
318 		addr += 4;
319 		amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
320 		amdgpu_ring_write(ring, lower_32_bits(addr));
321 		amdgpu_ring_write(ring, upper_32_bits(addr));
322 		amdgpu_ring_write(ring, upper_32_bits(seq));
323 	}
324 
325 	/* generate an interrupt */
326 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
327 	amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
328 }
329 
330 /**
331  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
332  *
333  * @adev: amdgpu_device pointer
334  *
335  * Stop the gfx async dma ring buffers (VI).
336  */
sdma_v2_4_gfx_stop(struct amdgpu_device * adev)337 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
338 {
339 	u32 rb_cntl, ib_cntl;
340 	int i;
341 
342 	amdgpu_sdma_unset_buffer_funcs_helper(adev);
343 
344 	for (i = 0; i < adev->sdma.num_instances; i++) {
345 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
346 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
347 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
348 		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
349 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
350 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
351 	}
352 }
353 
354 /**
355  * sdma_v2_4_rlc_stop - stop the compute async dma engines
356  *
357  * @adev: amdgpu_device pointer
358  *
359  * Stop the compute async dma queues (VI).
360  */
sdma_v2_4_rlc_stop(struct amdgpu_device * adev)361 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
362 {
363 	/* XXX todo */
364 }
365 
366 /**
367  * sdma_v2_4_enable - stop the async dma engines
368  *
369  * @adev: amdgpu_device pointer
370  * @enable: enable/disable the DMA MEs.
371  *
372  * Halt or unhalt the async dma engines (VI).
373  */
sdma_v2_4_enable(struct amdgpu_device * adev,bool enable)374 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
375 {
376 	u32 f32_cntl;
377 	int i;
378 
379 	if (!enable) {
380 		sdma_v2_4_gfx_stop(adev);
381 		sdma_v2_4_rlc_stop(adev);
382 	}
383 
384 	for (i = 0; i < adev->sdma.num_instances; i++) {
385 		f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
386 		if (enable)
387 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
388 		else
389 			f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
390 		WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
391 	}
392 }
393 
394 /**
395  * sdma_v2_4_gfx_resume - setup and start the async dma engines
396  *
397  * @adev: amdgpu_device pointer
398  *
399  * Set up the gfx DMA ring buffers and enable them (VI).
400  * Returns 0 for success, error for failure.
401  */
sdma_v2_4_gfx_resume(struct amdgpu_device * adev)402 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
403 {
404 	struct amdgpu_ring *ring;
405 	u32 rb_cntl, ib_cntl;
406 	u32 rb_bufsz;
407 	int i, j, r;
408 
409 	for (i = 0; i < adev->sdma.num_instances; i++) {
410 		ring = &adev->sdma.instance[i].ring;
411 
412 		mutex_lock(&adev->srbm_mutex);
413 		for (j = 0; j < 16; j++) {
414 			vi_srbm_select(adev, 0, 0, 0, j);
415 			/* SDMA GFX */
416 			WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
417 			WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
418 		}
419 		vi_srbm_select(adev, 0, 0, 0, 0);
420 		mutex_unlock(&adev->srbm_mutex);
421 
422 		WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
423 		       adev->gfx.config.gb_addr_config & 0x70);
424 
425 		WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
426 
427 		/* Set ring buffer size in dwords */
428 		rb_bufsz = order_base_2(ring->ring_size / 4);
429 		rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
430 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
431 #ifdef __BIG_ENDIAN
432 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
433 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
434 					RPTR_WRITEBACK_SWAP_ENABLE, 1);
435 #endif
436 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
437 
438 		/* Initialize the ring buffer's read and write pointers */
439 		WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
440 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
441 		WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
442 		WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
443 
444 		/* set the wb address whether it's enabled or not */
445 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
446 		       upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
447 		WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
448 		       lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
449 
450 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
451 
452 		WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
453 		WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
454 
455 		ring->wptr = 0;
456 		WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], ring->wptr << 2);
457 
458 		/* enable DMA RB */
459 		rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
460 		WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
461 
462 		ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
463 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
464 #ifdef __BIG_ENDIAN
465 		ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
466 #endif
467 		/* enable DMA IBs */
468 		WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
469 	}
470 
471 	sdma_v2_4_enable(adev, true);
472 	for (i = 0; i < adev->sdma.num_instances; i++) {
473 		ring = &adev->sdma.instance[i].ring;
474 		r = amdgpu_ring_test_helper(ring);
475 		if (r)
476 			return r;
477 
478 		if (adev->mman.buffer_funcs_ring == ring)
479 			amdgpu_ttm_set_buffer_funcs_status(adev, true);
480 	}
481 
482 	return 0;
483 }
484 
485 /**
486  * sdma_v2_4_rlc_resume - setup and start the async dma engines
487  *
488  * @adev: amdgpu_device pointer
489  *
490  * Set up the compute DMA queues and enable them (VI).
491  * Returns 0 for success, error for failure.
492  */
sdma_v2_4_rlc_resume(struct amdgpu_device * adev)493 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
494 {
495 	/* XXX todo */
496 	return 0;
497 }
498 
499 
500 /**
501  * sdma_v2_4_start - setup and start the async dma engines
502  *
503  * @adev: amdgpu_device pointer
504  *
505  * Set up the DMA engines and enable them (VI).
506  * Returns 0 for success, error for failure.
507  */
sdma_v2_4_start(struct amdgpu_device * adev)508 static int sdma_v2_4_start(struct amdgpu_device *adev)
509 {
510 	int r;
511 
512 	/* halt the engine before programing */
513 	sdma_v2_4_enable(adev, false);
514 
515 	/* start the gfx rings and rlc compute queues */
516 	r = sdma_v2_4_gfx_resume(adev);
517 	if (r)
518 		return r;
519 	r = sdma_v2_4_rlc_resume(adev);
520 	if (r)
521 		return r;
522 
523 	return 0;
524 }
525 
526 /**
527  * sdma_v2_4_ring_test_ring - simple async dma engine test
528  *
529  * @ring: amdgpu_ring structure holding ring information
530  *
531  * Test the DMA engine by writing using it to write an
532  * value to memory. (VI).
533  * Returns 0 for success, error for failure.
534  */
sdma_v2_4_ring_test_ring(struct amdgpu_ring * ring)535 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
536 {
537 	struct amdgpu_device *adev = ring->adev;
538 	unsigned i;
539 	unsigned index;
540 	int r;
541 	u32 tmp;
542 	u64 gpu_addr;
543 
544 	r = amdgpu_device_wb_get(adev, &index);
545 	if (r)
546 		return r;
547 
548 	gpu_addr = adev->wb.gpu_addr + (index * 4);
549 	tmp = 0xCAFEDEAD;
550 	adev->wb.wb[index] = cpu_to_le32(tmp);
551 
552 	r = amdgpu_ring_alloc(ring, 5);
553 	if (r)
554 		goto error_free_wb;
555 
556 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
557 			  SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
558 	amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
559 	amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
560 	amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
561 	amdgpu_ring_write(ring, 0xDEADBEEF);
562 	amdgpu_ring_commit(ring);
563 
564 	for (i = 0; i < adev->usec_timeout; i++) {
565 		tmp = le32_to_cpu(adev->wb.wb[index]);
566 		if (tmp == 0xDEADBEEF)
567 			break;
568 		udelay(1);
569 	}
570 
571 	if (i >= adev->usec_timeout)
572 		r = -ETIMEDOUT;
573 
574 error_free_wb:
575 	amdgpu_device_wb_free(adev, index);
576 	return r;
577 }
578 
579 /**
580  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
581  *
582  * @ring: amdgpu_ring structure holding ring information
583  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
584  *
585  * Test a simple IB in the DMA ring (VI).
586  * Returns 0 on success, error on failure.
587  */
sdma_v2_4_ring_test_ib(struct amdgpu_ring * ring,long timeout)588 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
589 {
590 	struct amdgpu_device *adev = ring->adev;
591 	struct amdgpu_ib ib;
592 	struct dma_fence *f = NULL;
593 	unsigned index;
594 	u32 tmp = 0;
595 	u64 gpu_addr;
596 	long r;
597 
598 	r = amdgpu_device_wb_get(adev, &index);
599 	if (r)
600 		return r;
601 
602 	gpu_addr = adev->wb.gpu_addr + (index * 4);
603 	tmp = 0xCAFEDEAD;
604 	adev->wb.wb[index] = cpu_to_le32(tmp);
605 	memset(&ib, 0, sizeof(ib));
606 	r = amdgpu_ib_get(adev, NULL, 256,
607 					AMDGPU_IB_POOL_DIRECT, &ib);
608 	if (r)
609 		goto err0;
610 
611 	ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
612 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
613 	ib.ptr[1] = lower_32_bits(gpu_addr);
614 	ib.ptr[2] = upper_32_bits(gpu_addr);
615 	ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
616 	ib.ptr[4] = 0xDEADBEEF;
617 	ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
618 	ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
619 	ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
620 	ib.length_dw = 8;
621 
622 	r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
623 	if (r)
624 		goto err1;
625 
626 	r = dma_fence_wait_timeout(f, false, timeout);
627 	if (r == 0) {
628 		r = -ETIMEDOUT;
629 		goto err1;
630 	} else if (r < 0) {
631 		goto err1;
632 	}
633 	tmp = le32_to_cpu(adev->wb.wb[index]);
634 	if (tmp == 0xDEADBEEF)
635 		r = 0;
636 	else
637 		r = -EINVAL;
638 
639 err1:
640 	amdgpu_ib_free(adev, &ib, NULL);
641 	dma_fence_put(f);
642 err0:
643 	amdgpu_device_wb_free(adev, index);
644 	return r;
645 }
646 
647 /**
648  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
649  *
650  * @ib: indirect buffer to fill with commands
651  * @pe: addr of the page entry
652  * @src: src addr to copy from
653  * @count: number of page entries to update
654  *
655  * Update PTEs by copying them from the GART using sDMA (CIK).
656  */
sdma_v2_4_vm_copy_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t src,unsigned count)657 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
658 				  uint64_t pe, uint64_t src,
659 				  unsigned count)
660 {
661 	unsigned bytes = count * 8;
662 
663 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
664 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
665 	ib->ptr[ib->length_dw++] = bytes;
666 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
667 	ib->ptr[ib->length_dw++] = lower_32_bits(src);
668 	ib->ptr[ib->length_dw++] = upper_32_bits(src);
669 	ib->ptr[ib->length_dw++] = lower_32_bits(pe);
670 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
671 }
672 
673 /**
674  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
675  *
676  * @ib: indirect buffer to fill with commands
677  * @pe: addr of the page entry
678  * @value: dst addr to write into pe
679  * @count: number of page entries to update
680  * @incr: increase next addr by incr bytes
681  *
682  * Update PTEs by writing them manually using sDMA (CIK).
683  */
sdma_v2_4_vm_write_pte(struct amdgpu_ib * ib,uint64_t pe,uint64_t value,unsigned count,uint32_t incr)684 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
685 				   uint64_t value, unsigned count,
686 				   uint32_t incr)
687 {
688 	unsigned ndw = count * 2;
689 
690 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
691 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
692 	ib->ptr[ib->length_dw++] = pe;
693 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
694 	ib->ptr[ib->length_dw++] = ndw;
695 	for (; ndw > 0; ndw -= 2) {
696 		ib->ptr[ib->length_dw++] = lower_32_bits(value);
697 		ib->ptr[ib->length_dw++] = upper_32_bits(value);
698 		value += incr;
699 	}
700 }
701 
702 /**
703  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
704  *
705  * @ib: indirect buffer to fill with commands
706  * @pe: addr of the page entry
707  * @addr: dst addr to write into pe
708  * @count: number of page entries to update
709  * @incr: increase next addr by incr bytes
710  * @flags: access flags
711  *
712  * Update the page tables using sDMA (CIK).
713  */
sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib * ib,uint64_t pe,uint64_t addr,unsigned count,uint32_t incr,uint64_t flags)714 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
715 				     uint64_t addr, unsigned count,
716 				     uint32_t incr, uint64_t flags)
717 {
718 	/* for physically contiguous pages (vram) */
719 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
720 	ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
721 	ib->ptr[ib->length_dw++] = upper_32_bits(pe);
722 	ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
723 	ib->ptr[ib->length_dw++] = upper_32_bits(flags);
724 	ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
725 	ib->ptr[ib->length_dw++] = upper_32_bits(addr);
726 	ib->ptr[ib->length_dw++] = incr; /* increment size */
727 	ib->ptr[ib->length_dw++] = 0;
728 	ib->ptr[ib->length_dw++] = count; /* number of entries */
729 }
730 
731 /**
732  * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
733  *
734  * @ring: amdgpu_ring structure holding ring information
735  * @ib: indirect buffer to fill with padding
736  *
737  */
sdma_v2_4_ring_pad_ib(struct amdgpu_ring * ring,struct amdgpu_ib * ib)738 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
739 {
740 	struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
741 	u32 pad_count;
742 	int i;
743 
744 	pad_count = (-ib->length_dw) & 7;
745 	for (i = 0; i < pad_count; i++)
746 		if (sdma && sdma->burst_nop && (i == 0))
747 			ib->ptr[ib->length_dw++] =
748 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
749 				SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
750 		else
751 			ib->ptr[ib->length_dw++] =
752 				SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
753 }
754 
755 /**
756  * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
757  *
758  * @ring: amdgpu_ring pointer
759  *
760  * Make sure all previous operations are completed (CIK).
761  */
sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring * ring)762 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
763 {
764 	uint32_t seq = ring->fence_drv.sync_seq;
765 	uint64_t addr = ring->fence_drv.gpu_addr;
766 
767 	/* wait for idle */
768 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
769 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
770 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
771 			  SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
772 	amdgpu_ring_write(ring, addr & 0xfffffffc);
773 	amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
774 	amdgpu_ring_write(ring, seq); /* reference */
775 	amdgpu_ring_write(ring, 0xffffffff); /* mask */
776 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
777 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
778 }
779 
780 /**
781  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
782  *
783  * @ring: amdgpu_ring pointer
784  * @vmid: vmid number to use
785  * @pd_addr: address
786  *
787  * Update the page table base and flush the VM TLB
788  * using sDMA (VI).
789  */
sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)790 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
791 					 unsigned vmid, uint64_t pd_addr)
792 {
793 	amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
794 
795 	/* wait for flush */
796 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
797 			  SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
798 			  SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
799 	amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
800 	amdgpu_ring_write(ring, 0);
801 	amdgpu_ring_write(ring, 0); /* reference */
802 	amdgpu_ring_write(ring, 0); /* mask */
803 	amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
804 			  SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
805 }
806 
sdma_v2_4_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)807 static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,
808 				     uint32_t reg, uint32_t val)
809 {
810 	amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
811 			  SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
812 	amdgpu_ring_write(ring, reg);
813 	amdgpu_ring_write(ring, val);
814 }
815 
sdma_v2_4_early_init(void * handle)816 static int sdma_v2_4_early_init(void *handle)
817 {
818 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
819 
820 	adev->sdma.num_instances = SDMA_MAX_INSTANCE;
821 
822 	sdma_v2_4_set_ring_funcs(adev);
823 	sdma_v2_4_set_buffer_funcs(adev);
824 	sdma_v2_4_set_vm_pte_funcs(adev);
825 	sdma_v2_4_set_irq_funcs(adev);
826 
827 	return 0;
828 }
829 
sdma_v2_4_sw_init(void * handle)830 static int sdma_v2_4_sw_init(void *handle)
831 {
832 	struct amdgpu_ring *ring;
833 	int r, i;
834 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
835 
836 	/* SDMA trap event */
837 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
838 			      &adev->sdma.trap_irq);
839 	if (r)
840 		return r;
841 
842 	/* SDMA Privileged inst */
843 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
844 			      &adev->sdma.illegal_inst_irq);
845 	if (r)
846 		return r;
847 
848 	/* SDMA Privileged inst */
849 	r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
850 			      &adev->sdma.illegal_inst_irq);
851 	if (r)
852 		return r;
853 
854 	r = sdma_v2_4_init_microcode(adev);
855 	if (r) {
856 		DRM_ERROR("Failed to load sdma firmware!\n");
857 		return r;
858 	}
859 
860 	for (i = 0; i < adev->sdma.num_instances; i++) {
861 		ring = &adev->sdma.instance[i].ring;
862 		ring->ring_obj = NULL;
863 		ring->use_doorbell = false;
864 		sprintf(ring->name, "sdma%d", i);
865 		r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
866 				     (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
867 				     AMDGPU_SDMA_IRQ_INSTANCE1,
868 				     AMDGPU_RING_PRIO_DEFAULT, NULL);
869 		if (r)
870 			return r;
871 	}
872 
873 	return r;
874 }
875 
sdma_v2_4_sw_fini(void * handle)876 static int sdma_v2_4_sw_fini(void *handle)
877 {
878 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
879 	int i;
880 
881 	for (i = 0; i < adev->sdma.num_instances; i++)
882 		amdgpu_ring_fini(&adev->sdma.instance[i].ring);
883 
884 	sdma_v2_4_free_microcode(adev);
885 	return 0;
886 }
887 
sdma_v2_4_hw_init(void * handle)888 static int sdma_v2_4_hw_init(void *handle)
889 {
890 	int r;
891 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
892 
893 	sdma_v2_4_init_golden_registers(adev);
894 
895 	r = sdma_v2_4_start(adev);
896 	if (r)
897 		return r;
898 
899 	return r;
900 }
901 
sdma_v2_4_hw_fini(void * handle)902 static int sdma_v2_4_hw_fini(void *handle)
903 {
904 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
905 
906 	sdma_v2_4_enable(adev, false);
907 
908 	return 0;
909 }
910 
sdma_v2_4_suspend(void * handle)911 static int sdma_v2_4_suspend(void *handle)
912 {
913 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
914 
915 	return sdma_v2_4_hw_fini(adev);
916 }
917 
sdma_v2_4_resume(void * handle)918 static int sdma_v2_4_resume(void *handle)
919 {
920 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
921 
922 	return sdma_v2_4_hw_init(adev);
923 }
924 
sdma_v2_4_is_idle(void * handle)925 static bool sdma_v2_4_is_idle(void *handle)
926 {
927 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
928 	u32 tmp = RREG32(mmSRBM_STATUS2);
929 
930 	if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
931 		   SRBM_STATUS2__SDMA1_BUSY_MASK))
932 	    return false;
933 
934 	return true;
935 }
936 
sdma_v2_4_wait_for_idle(void * handle)937 static int sdma_v2_4_wait_for_idle(void *handle)
938 {
939 	unsigned i;
940 	u32 tmp;
941 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
942 
943 	for (i = 0; i < adev->usec_timeout; i++) {
944 		tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
945 				SRBM_STATUS2__SDMA1_BUSY_MASK);
946 
947 		if (!tmp)
948 			return 0;
949 		udelay(1);
950 	}
951 	return -ETIMEDOUT;
952 }
953 
sdma_v2_4_soft_reset(void * handle)954 static int sdma_v2_4_soft_reset(void *handle)
955 {
956 	u32 srbm_soft_reset = 0;
957 	struct amdgpu_device *adev = (struct amdgpu_device *)handle;
958 	u32 tmp = RREG32(mmSRBM_STATUS2);
959 
960 	if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
961 		/* sdma0 */
962 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
963 		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
964 		WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
965 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
966 	}
967 	if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
968 		/* sdma1 */
969 		tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
970 		tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
971 		WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
972 		srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
973 	}
974 
975 	if (srbm_soft_reset) {
976 		tmp = RREG32(mmSRBM_SOFT_RESET);
977 		tmp |= srbm_soft_reset;
978 		dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
979 		WREG32(mmSRBM_SOFT_RESET, tmp);
980 		tmp = RREG32(mmSRBM_SOFT_RESET);
981 
982 		udelay(50);
983 
984 		tmp &= ~srbm_soft_reset;
985 		WREG32(mmSRBM_SOFT_RESET, tmp);
986 		tmp = RREG32(mmSRBM_SOFT_RESET);
987 
988 		/* Wait a little for things to settle down */
989 		udelay(50);
990 	}
991 
992 	return 0;
993 }
994 
sdma_v2_4_set_trap_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)995 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
996 					struct amdgpu_irq_src *src,
997 					unsigned type,
998 					enum amdgpu_interrupt_state state)
999 {
1000 	u32 sdma_cntl;
1001 
1002 	switch (type) {
1003 	case AMDGPU_SDMA_IRQ_INSTANCE0:
1004 		switch (state) {
1005 		case AMDGPU_IRQ_STATE_DISABLE:
1006 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1007 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1008 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1009 			break;
1010 		case AMDGPU_IRQ_STATE_ENABLE:
1011 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1012 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1013 			WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1014 			break;
1015 		default:
1016 			break;
1017 		}
1018 		break;
1019 	case AMDGPU_SDMA_IRQ_INSTANCE1:
1020 		switch (state) {
1021 		case AMDGPU_IRQ_STATE_DISABLE:
1022 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1023 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1024 			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1025 			break;
1026 		case AMDGPU_IRQ_STATE_ENABLE:
1027 			sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1028 			sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1029 			WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1030 			break;
1031 		default:
1032 			break;
1033 		}
1034 		break;
1035 	default:
1036 		break;
1037 	}
1038 	return 0;
1039 }
1040 
sdma_v2_4_process_trap_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1041 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1042 				      struct amdgpu_irq_src *source,
1043 				      struct amdgpu_iv_entry *entry)
1044 {
1045 	u8 instance_id, queue_id;
1046 
1047 	instance_id = (entry->ring_id & 0x3) >> 0;
1048 	queue_id = (entry->ring_id & 0xc) >> 2;
1049 	DRM_DEBUG("IH: SDMA trap\n");
1050 	switch (instance_id) {
1051 	case 0:
1052 		switch (queue_id) {
1053 		case 0:
1054 			amdgpu_fence_process(&adev->sdma.instance[0].ring);
1055 			break;
1056 		case 1:
1057 			/* XXX compute */
1058 			break;
1059 		case 2:
1060 			/* XXX compute */
1061 			break;
1062 		}
1063 		break;
1064 	case 1:
1065 		switch (queue_id) {
1066 		case 0:
1067 			amdgpu_fence_process(&adev->sdma.instance[1].ring);
1068 			break;
1069 		case 1:
1070 			/* XXX compute */
1071 			break;
1072 		case 2:
1073 			/* XXX compute */
1074 			break;
1075 		}
1076 		break;
1077 	}
1078 	return 0;
1079 }
1080 
sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1081 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1082 					      struct amdgpu_irq_src *source,
1083 					      struct amdgpu_iv_entry *entry)
1084 {
1085 	u8 instance_id, queue_id;
1086 
1087 	DRM_ERROR("Illegal instruction in SDMA command stream\n");
1088 	instance_id = (entry->ring_id & 0x3) >> 0;
1089 	queue_id = (entry->ring_id & 0xc) >> 2;
1090 
1091 	if (instance_id <= 1 && queue_id == 0)
1092 		drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1093 	return 0;
1094 }
1095 
sdma_v2_4_set_clockgating_state(void * handle,enum amd_clockgating_state state)1096 static int sdma_v2_4_set_clockgating_state(void *handle,
1097 					  enum amd_clockgating_state state)
1098 {
1099 	/* XXX handled via the smc on VI */
1100 	return 0;
1101 }
1102 
sdma_v2_4_set_powergating_state(void * handle,enum amd_powergating_state state)1103 static int sdma_v2_4_set_powergating_state(void *handle,
1104 					  enum amd_powergating_state state)
1105 {
1106 	return 0;
1107 }
1108 
1109 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1110 	.name = "sdma_v2_4",
1111 	.early_init = sdma_v2_4_early_init,
1112 	.late_init = NULL,
1113 	.sw_init = sdma_v2_4_sw_init,
1114 	.sw_fini = sdma_v2_4_sw_fini,
1115 	.hw_init = sdma_v2_4_hw_init,
1116 	.hw_fini = sdma_v2_4_hw_fini,
1117 	.suspend = sdma_v2_4_suspend,
1118 	.resume = sdma_v2_4_resume,
1119 	.is_idle = sdma_v2_4_is_idle,
1120 	.wait_for_idle = sdma_v2_4_wait_for_idle,
1121 	.soft_reset = sdma_v2_4_soft_reset,
1122 	.set_clockgating_state = sdma_v2_4_set_clockgating_state,
1123 	.set_powergating_state = sdma_v2_4_set_powergating_state,
1124 };
1125 
1126 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1127 	.type = AMDGPU_RING_TYPE_SDMA,
1128 	.align_mask = 0xf,
1129 	.nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1130 	.support_64bit_ptrs = false,
1131 	.secure_submission_supported = true,
1132 	.get_rptr = sdma_v2_4_ring_get_rptr,
1133 	.get_wptr = sdma_v2_4_ring_get_wptr,
1134 	.set_wptr = sdma_v2_4_ring_set_wptr,
1135 	.emit_frame_size =
1136 		6 + /* sdma_v2_4_ring_emit_hdp_flush */
1137 		3 + /* hdp invalidate */
1138 		6 + /* sdma_v2_4_ring_emit_pipeline_sync */
1139 		VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */
1140 		10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
1141 	.emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
1142 	.emit_ib = sdma_v2_4_ring_emit_ib,
1143 	.emit_fence = sdma_v2_4_ring_emit_fence,
1144 	.emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1145 	.emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1146 	.emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1147 	.test_ring = sdma_v2_4_ring_test_ring,
1148 	.test_ib = sdma_v2_4_ring_test_ib,
1149 	.insert_nop = sdma_v2_4_ring_insert_nop,
1150 	.pad_ib = sdma_v2_4_ring_pad_ib,
1151 	.emit_wreg = sdma_v2_4_ring_emit_wreg,
1152 };
1153 
sdma_v2_4_set_ring_funcs(struct amdgpu_device * adev)1154 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1155 {
1156 	int i;
1157 
1158 	for (i = 0; i < adev->sdma.num_instances; i++) {
1159 		adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1160 		adev->sdma.instance[i].ring.me = i;
1161 	}
1162 }
1163 
1164 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1165 	.set = sdma_v2_4_set_trap_irq_state,
1166 	.process = sdma_v2_4_process_trap_irq,
1167 };
1168 
1169 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1170 	.process = sdma_v2_4_process_illegal_inst_irq,
1171 };
1172 
sdma_v2_4_set_irq_funcs(struct amdgpu_device * adev)1173 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1174 {
1175 	adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1176 	adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1177 	adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1178 }
1179 
1180 /**
1181  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1182  *
1183  * @ib: indirect buffer to copy to
1184  * @src_offset: src GPU address
1185  * @dst_offset: dst GPU address
1186  * @byte_count: number of bytes to xfer
1187  * @tmz: unused
1188  *
1189  * Copy GPU buffers using the DMA engine (VI).
1190  * Used by the amdgpu ttm implementation to move pages if
1191  * registered as the asic copy callback.
1192  */
sdma_v2_4_emit_copy_buffer(struct amdgpu_ib * ib,uint64_t src_offset,uint64_t dst_offset,uint32_t byte_count,bool tmz)1193 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1194 				       uint64_t src_offset,
1195 				       uint64_t dst_offset,
1196 				       uint32_t byte_count,
1197 				       bool tmz)
1198 {
1199 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1200 		SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1201 	ib->ptr[ib->length_dw++] = byte_count;
1202 	ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1203 	ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1204 	ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1205 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1206 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1207 }
1208 
1209 /**
1210  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1211  *
1212  * @ib: indirect buffer to copy to
1213  * @src_data: value to write to buffer
1214  * @dst_offset: dst GPU address
1215  * @byte_count: number of bytes to xfer
1216  *
1217  * Fill GPU buffers using the DMA engine (VI).
1218  */
sdma_v2_4_emit_fill_buffer(struct amdgpu_ib * ib,uint32_t src_data,uint64_t dst_offset,uint32_t byte_count)1219 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1220 				       uint32_t src_data,
1221 				       uint64_t dst_offset,
1222 				       uint32_t byte_count)
1223 {
1224 	ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1225 	ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1226 	ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1227 	ib->ptr[ib->length_dw++] = src_data;
1228 	ib->ptr[ib->length_dw++] = byte_count;
1229 }
1230 
1231 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1232 	.copy_max_bytes = 0x1fffff,
1233 	.copy_num_dw = 7,
1234 	.emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1235 
1236 	.fill_max_bytes = 0x1fffff,
1237 	.fill_num_dw = 7,
1238 	.emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1239 };
1240 
sdma_v2_4_set_buffer_funcs(struct amdgpu_device * adev)1241 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1242 {
1243 	adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1244 	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1245 }
1246 
1247 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1248 	.copy_pte_num_dw = 7,
1249 	.copy_pte = sdma_v2_4_vm_copy_pte,
1250 
1251 	.write_pte = sdma_v2_4_vm_write_pte,
1252 	.set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1253 };
1254 
sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device * adev)1255 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1256 {
1257 	unsigned i;
1258 
1259 	adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1260 	for (i = 0; i < adev->sdma.num_instances; i++) {
1261 		adev->vm_manager.vm_pte_scheds[i] =
1262 			&adev->sdma.instance[i].ring.sched;
1263 	}
1264 	adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1265 }
1266 
1267 const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
1268 {
1269 	.type = AMD_IP_BLOCK_TYPE_SDMA,
1270 	.major = 2,
1271 	.minor = 4,
1272 	.rev = 0,
1273 	.funcs = &sdma_v2_4_ip_funcs,
1274 };
1275