1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface
3 *
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
5 *
6 * Thanks to the following companies for their support:
7 *
8 * - JMicron (hardware and technical support)
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/string.h>
13 #include <linux/delay.h>
14 #include <linux/highmem.h>
15 #include <linux/module.h>
16 #include <linux/pci.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/slab.h>
19 #include <linux/device.h>
20 #include <linux/scatterlist.h>
21 #include <linux/io.h>
22 #include <linux/iopoll.h>
23 #include <linux/gpio.h>
24 #include <linux/gpio/machine.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/pm_qos.h>
27 #include <linux/debugfs.h>
28 #include <linux/acpi.h>
29 #include <linux/dmi.h>
30
31 #include <linux/mmc/host.h>
32 #include <linux/mmc/mmc.h>
33 #include <linux/mmc/slot-gpio.h>
34
35 #ifdef CONFIG_X86
36 #include <asm/iosf_mbi.h>
37 #endif
38
39 #include "cqhci.h"
40
41 #include "sdhci.h"
42 #include "sdhci-cqhci.h"
43 #include "sdhci-pci.h"
44
45 static void sdhci_pci_hw_reset(struct sdhci_host *host);
46
47 #ifdef CONFIG_PM_SLEEP
sdhci_pci_init_wakeup(struct sdhci_pci_chip * chip)48 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip)
49 {
50 mmc_pm_flag_t pm_flags = 0;
51 bool cap_cd_wake = false;
52 int i;
53
54 for (i = 0; i < chip->num_slots; i++) {
55 struct sdhci_pci_slot *slot = chip->slots[i];
56
57 if (slot) {
58 pm_flags |= slot->host->mmc->pm_flags;
59 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE)
60 cap_cd_wake = true;
61 }
62 }
63
64 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ))
65 return device_wakeup_enable(&chip->pdev->dev);
66 else if (!cap_cd_wake)
67 return device_wakeup_disable(&chip->pdev->dev);
68
69 return 0;
70 }
71
sdhci_pci_suspend_host(struct sdhci_pci_chip * chip)72 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip)
73 {
74 int i, ret;
75
76 sdhci_pci_init_wakeup(chip);
77
78 for (i = 0; i < chip->num_slots; i++) {
79 struct sdhci_pci_slot *slot = chip->slots[i];
80 struct sdhci_host *host;
81
82 if (!slot)
83 continue;
84
85 host = slot->host;
86
87 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3)
88 mmc_retune_needed(host->mmc);
89
90 ret = sdhci_suspend_host(host);
91 if (ret)
92 goto err_pci_suspend;
93
94 if (device_may_wakeup(&chip->pdev->dev))
95 mmc_gpio_set_cd_wake(host->mmc, true);
96 }
97
98 return 0;
99
100 err_pci_suspend:
101 while (--i >= 0)
102 sdhci_resume_host(chip->slots[i]->host);
103 return ret;
104 }
105
sdhci_pci_resume_host(struct sdhci_pci_chip * chip)106 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip)
107 {
108 struct sdhci_pci_slot *slot;
109 int i, ret;
110
111 for (i = 0; i < chip->num_slots; i++) {
112 slot = chip->slots[i];
113 if (!slot)
114 continue;
115
116 ret = sdhci_resume_host(slot->host);
117 if (ret)
118 return ret;
119
120 mmc_gpio_set_cd_wake(slot->host->mmc, false);
121 }
122
123 return 0;
124 }
125
sdhci_cqhci_suspend(struct sdhci_pci_chip * chip)126 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip)
127 {
128 int ret;
129
130 ret = cqhci_suspend(chip->slots[0]->host->mmc);
131 if (ret)
132 return ret;
133
134 return sdhci_pci_suspend_host(chip);
135 }
136
sdhci_cqhci_resume(struct sdhci_pci_chip * chip)137 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip)
138 {
139 int ret;
140
141 ret = sdhci_pci_resume_host(chip);
142 if (ret)
143 return ret;
144
145 return cqhci_resume(chip->slots[0]->host->mmc);
146 }
147 #endif
148
149 #ifdef CONFIG_PM
sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip * chip)150 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip)
151 {
152 struct sdhci_pci_slot *slot;
153 struct sdhci_host *host;
154 int i, ret;
155
156 for (i = 0; i < chip->num_slots; i++) {
157 slot = chip->slots[i];
158 if (!slot)
159 continue;
160
161 host = slot->host;
162
163 ret = sdhci_runtime_suspend_host(host);
164 if (ret)
165 goto err_pci_runtime_suspend;
166
167 if (chip->rpm_retune &&
168 host->tuning_mode != SDHCI_TUNING_MODE_3)
169 mmc_retune_needed(host->mmc);
170 }
171
172 return 0;
173
174 err_pci_runtime_suspend:
175 while (--i >= 0)
176 sdhci_runtime_resume_host(chip->slots[i]->host, 0);
177 return ret;
178 }
179
sdhci_pci_runtime_resume_host(struct sdhci_pci_chip * chip)180 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip)
181 {
182 struct sdhci_pci_slot *slot;
183 int i, ret;
184
185 for (i = 0; i < chip->num_slots; i++) {
186 slot = chip->slots[i];
187 if (!slot)
188 continue;
189
190 ret = sdhci_runtime_resume_host(slot->host, 0);
191 if (ret)
192 return ret;
193 }
194
195 return 0;
196 }
197
sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip * chip)198 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip)
199 {
200 int ret;
201
202 ret = cqhci_suspend(chip->slots[0]->host->mmc);
203 if (ret)
204 return ret;
205
206 return sdhci_pci_runtime_suspend_host(chip);
207 }
208
sdhci_cqhci_runtime_resume(struct sdhci_pci_chip * chip)209 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip)
210 {
211 int ret;
212
213 ret = sdhci_pci_runtime_resume_host(chip);
214 if (ret)
215 return ret;
216
217 return cqhci_resume(chip->slots[0]->host->mmc);
218 }
219 #endif
220
sdhci_cqhci_irq(struct sdhci_host * host,u32 intmask)221 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask)
222 {
223 int cmd_error = 0;
224 int data_error = 0;
225
226 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
227 return intmask;
228
229 cqhci_irq(host->mmc, intmask, cmd_error, data_error);
230
231 return 0;
232 }
233
sdhci_pci_dumpregs(struct mmc_host * mmc)234 static void sdhci_pci_dumpregs(struct mmc_host *mmc)
235 {
236 sdhci_dumpregs(mmc_priv(mmc));
237 }
238
239 /*****************************************************************************\
240 * *
241 * Hardware specific quirk handling *
242 * *
243 \*****************************************************************************/
244
ricoh_probe(struct sdhci_pci_chip * chip)245 static int ricoh_probe(struct sdhci_pci_chip *chip)
246 {
247 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG ||
248 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY)
249 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET;
250 return 0;
251 }
252
ricoh_mmc_probe_slot(struct sdhci_pci_slot * slot)253 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot)
254 {
255 u32 caps =
256 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) |
257 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) |
258 SDHCI_TIMEOUT_CLK_UNIT |
259 SDHCI_CAN_VDD_330 |
260 SDHCI_CAN_DO_HISPD |
261 SDHCI_CAN_DO_SDMA;
262 u32 caps1 = 0;
263
264 __sdhci_read_caps(slot->host, NULL, &caps, &caps1);
265 return 0;
266 }
267
268 #ifdef CONFIG_PM_SLEEP
ricoh_mmc_resume(struct sdhci_pci_chip * chip)269 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip)
270 {
271 /* Apply a delay to allow controller to settle */
272 /* Otherwise it becomes confused if card state changed
273 during suspend */
274 msleep(500);
275 return sdhci_pci_resume_host(chip);
276 }
277 #endif
278
279 static const struct sdhci_pci_fixes sdhci_ricoh = {
280 .probe = ricoh_probe,
281 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
282 SDHCI_QUIRK_FORCE_DMA |
283 SDHCI_QUIRK_CLOCK_BEFORE_RESET,
284 };
285
286 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = {
287 .probe_slot = ricoh_mmc_probe_slot,
288 #ifdef CONFIG_PM_SLEEP
289 .resume = ricoh_mmc_resume,
290 #endif
291 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR |
292 SDHCI_QUIRK_CLOCK_BEFORE_RESET |
293 SDHCI_QUIRK_NO_CARD_NO_RESET,
294 };
295
ene_714_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)296 static void ene_714_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
297 {
298 struct sdhci_host *host = mmc_priv(mmc);
299
300 sdhci_set_ios(mmc, ios);
301
302 /*
303 * Some (ENE) controllers misbehave on some ios operations,
304 * signalling timeout and CRC errors even on CMD0. Resetting
305 * it on each ios seems to solve the problem.
306 */
307 if (!(host->flags & SDHCI_DEVICE_DEAD))
308 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
309 }
310
ene_714_probe_slot(struct sdhci_pci_slot * slot)311 static int ene_714_probe_slot(struct sdhci_pci_slot *slot)
312 {
313 slot->host->mmc_host_ops.set_ios = ene_714_set_ios;
314 return 0;
315 }
316
317 static const struct sdhci_pci_fixes sdhci_ene_712 = {
318 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
319 SDHCI_QUIRK_BROKEN_DMA,
320 };
321
322 static const struct sdhci_pci_fixes sdhci_ene_714 = {
323 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE |
324 SDHCI_QUIRK_BROKEN_DMA,
325 .probe_slot = ene_714_probe_slot,
326 };
327
328 static const struct sdhci_pci_fixes sdhci_cafe = {
329 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER |
330 SDHCI_QUIRK_NO_BUSY_IRQ |
331 SDHCI_QUIRK_BROKEN_CARD_DETECTION |
332 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL,
333 };
334
335 static const struct sdhci_pci_fixes sdhci_intel_qrk = {
336 .quirks = SDHCI_QUIRK_NO_HISPD_BIT,
337 };
338
mrst_hc_probe_slot(struct sdhci_pci_slot * slot)339 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot)
340 {
341 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
342 return 0;
343 }
344
345 /*
346 * ADMA operation is disabled for Moorestown platform due to
347 * hardware bugs.
348 */
mrst_hc_probe(struct sdhci_pci_chip * chip)349 static int mrst_hc_probe(struct sdhci_pci_chip *chip)
350 {
351 /*
352 * slots number is fixed here for MRST as SDIO3/5 are never used and
353 * have hardware bugs.
354 */
355 chip->num_slots = 1;
356 return 0;
357 }
358
pch_hc_probe_slot(struct sdhci_pci_slot * slot)359 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot)
360 {
361 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA;
362 return 0;
363 }
364
mfd_emmc_probe_slot(struct sdhci_pci_slot * slot)365 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot)
366 {
367 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
368 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC;
369 return 0;
370 }
371
mfd_sdio_probe_slot(struct sdhci_pci_slot * slot)372 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot)
373 {
374 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
375 return 0;
376 }
377
378 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = {
379 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
380 .probe_slot = mrst_hc_probe_slot,
381 };
382
383 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = {
384 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT,
385 .probe = mrst_hc_probe,
386 };
387
388 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = {
389 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
390 .allow_runtime_pm = true,
391 .own_cd_for_runtime_pm = true,
392 };
393
394 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = {
395 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
396 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
397 .allow_runtime_pm = true,
398 .probe_slot = mfd_sdio_probe_slot,
399 };
400
401 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = {
402 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
403 .allow_runtime_pm = true,
404 .probe_slot = mfd_emmc_probe_slot,
405 };
406
407 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
408 .quirks = SDHCI_QUIRK_BROKEN_ADMA,
409 .probe_slot = pch_hc_probe_slot,
410 };
411
412 #ifdef CONFIG_X86
413
414 #define BYT_IOSF_SCCEP 0x63
415 #define BYT_IOSF_OCP_NETCTRL0 0x1078
416 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8)
417
byt_ocp_setting(struct pci_dev * pdev)418 static void byt_ocp_setting(struct pci_dev *pdev)
419 {
420 u32 val = 0;
421
422 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC &&
423 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO &&
424 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD &&
425 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2)
426 return;
427
428 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0,
429 &val)) {
430 dev_err(&pdev->dev, "%s read error\n", __func__);
431 return;
432 }
433
434 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE))
435 return;
436
437 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE;
438
439 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0,
440 val)) {
441 dev_err(&pdev->dev, "%s write error\n", __func__);
442 return;
443 }
444
445 dev_dbg(&pdev->dev, "%s completed\n", __func__);
446 }
447
448 #else
449
byt_ocp_setting(struct pci_dev * pdev)450 static inline void byt_ocp_setting(struct pci_dev *pdev)
451 {
452 }
453
454 #endif
455
456 enum {
457 INTEL_DSM_FNS = 0,
458 INTEL_DSM_V18_SWITCH = 3,
459 INTEL_DSM_V33_SWITCH = 4,
460 INTEL_DSM_DRV_STRENGTH = 9,
461 INTEL_DSM_D3_RETUNE = 10,
462 };
463
464 struct intel_host {
465 u32 dsm_fns;
466 int drv_strength;
467 bool d3_retune;
468 bool rpm_retune_ok;
469 bool needs_pwr_off;
470 u32 glk_rx_ctrl1;
471 u32 glk_tun_val;
472 u32 active_ltr;
473 u32 idle_ltr;
474 };
475
476 static const guid_t intel_dsm_guid =
477 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F,
478 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61);
479
__intel_dsm(struct intel_host * intel_host,struct device * dev,unsigned int fn,u32 * result)480 static int __intel_dsm(struct intel_host *intel_host, struct device *dev,
481 unsigned int fn, u32 *result)
482 {
483 union acpi_object *obj;
484 int err = 0;
485 size_t len;
486
487 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL);
488 if (!obj)
489 return -EOPNOTSUPP;
490
491 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) {
492 err = -EINVAL;
493 goto out;
494 }
495
496 len = min_t(size_t, obj->buffer.length, 4);
497
498 *result = 0;
499 memcpy(result, obj->buffer.pointer, len);
500 out:
501 ACPI_FREE(obj);
502
503 return err;
504 }
505
intel_dsm(struct intel_host * intel_host,struct device * dev,unsigned int fn,u32 * result)506 static int intel_dsm(struct intel_host *intel_host, struct device *dev,
507 unsigned int fn, u32 *result)
508 {
509 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn)))
510 return -EOPNOTSUPP;
511
512 return __intel_dsm(intel_host, dev, fn, result);
513 }
514
intel_dsm_init(struct intel_host * intel_host,struct device * dev,struct mmc_host * mmc)515 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev,
516 struct mmc_host *mmc)
517 {
518 int err;
519 u32 val;
520
521 intel_host->d3_retune = true;
522
523 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns);
524 if (err) {
525 pr_debug("%s: DSM not supported, error %d\n",
526 mmc_hostname(mmc), err);
527 return;
528 }
529
530 pr_debug("%s: DSM function mask %#x\n",
531 mmc_hostname(mmc), intel_host->dsm_fns);
532
533 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val);
534 intel_host->drv_strength = err ? 0 : val;
535
536 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val);
537 intel_host->d3_retune = err ? true : !!val;
538 }
539
sdhci_pci_int_hw_reset(struct sdhci_host * host)540 static void sdhci_pci_int_hw_reset(struct sdhci_host *host)
541 {
542 u8 reg;
543
544 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
545 reg |= 0x10;
546 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
547 /* For eMMC, minimum is 1us but give it 9us for good measure */
548 udelay(9);
549 reg &= ~0x10;
550 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
551 /* For eMMC, minimum is 200us but give it 300us for good measure */
552 usleep_range(300, 1000);
553 }
554
intel_select_drive_strength(struct mmc_card * card,unsigned int max_dtr,int host_drv,int card_drv,int * drv_type)555 static int intel_select_drive_strength(struct mmc_card *card,
556 unsigned int max_dtr, int host_drv,
557 int card_drv, int *drv_type)
558 {
559 struct sdhci_host *host = mmc_priv(card->host);
560 struct sdhci_pci_slot *slot = sdhci_priv(host);
561 struct intel_host *intel_host = sdhci_pci_priv(slot);
562
563 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv))
564 return 0;
565
566 return intel_host->drv_strength;
567 }
568
bxt_get_cd(struct mmc_host * mmc)569 static int bxt_get_cd(struct mmc_host *mmc)
570 {
571 int gpio_cd = mmc_gpio_get_cd(mmc);
572
573 if (!gpio_cd)
574 return 0;
575
576 return sdhci_get_cd_nogpio(mmc);
577 }
578
mrfld_get_cd(struct mmc_host * mmc)579 static int mrfld_get_cd(struct mmc_host *mmc)
580 {
581 return sdhci_get_cd_nogpio(mmc);
582 }
583
584 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20
585 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100
586
sdhci_intel_set_power(struct sdhci_host * host,unsigned char mode,unsigned short vdd)587 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode,
588 unsigned short vdd)
589 {
590 struct sdhci_pci_slot *slot = sdhci_priv(host);
591 struct intel_host *intel_host = sdhci_pci_priv(slot);
592 int cntr;
593 u8 reg;
594
595 /*
596 * Bus power may control card power, but a full reset still may not
597 * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can.
598 * That might be needed to initialize correctly, if the card was left
599 * powered on previously.
600 */
601 if (intel_host->needs_pwr_off) {
602 intel_host->needs_pwr_off = false;
603 if (mode != MMC_POWER_OFF) {
604 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
605 usleep_range(10000, 12500);
606 }
607 }
608
609 sdhci_set_power(host, mode, vdd);
610
611 if (mode == MMC_POWER_OFF) {
612 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
613 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BYT_SD)
614 usleep_range(15000, 17500);
615 return;
616 }
617
618 /*
619 * Bus power might not enable after D3 -> D0 transition due to the
620 * present state not yet having propagated. Retry for up to 2ms.
621 */
622 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) {
623 reg = sdhci_readb(host, SDHCI_POWER_CONTROL);
624 if (reg & SDHCI_POWER_ON)
625 break;
626 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY);
627 reg |= SDHCI_POWER_ON;
628 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL);
629 }
630 }
631
sdhci_intel_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)632 static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host,
633 unsigned int timing)
634 {
635 /* Set UHS timing to SDR25 for High Speed mode */
636 if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS)
637 timing = MMC_TIMING_UHS_SDR25;
638 sdhci_set_uhs_signaling(host, timing);
639 }
640
641 #define INTEL_HS400_ES_REG 0x78
642 #define INTEL_HS400_ES_BIT BIT(0)
643
intel_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)644 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc,
645 struct mmc_ios *ios)
646 {
647 struct sdhci_host *host = mmc_priv(mmc);
648 u32 val;
649
650 val = sdhci_readl(host, INTEL_HS400_ES_REG);
651 if (ios->enhanced_strobe)
652 val |= INTEL_HS400_ES_BIT;
653 else
654 val &= ~INTEL_HS400_ES_BIT;
655 sdhci_writel(host, val, INTEL_HS400_ES_REG);
656 }
657
intel_start_signal_voltage_switch(struct mmc_host * mmc,struct mmc_ios * ios)658 static int intel_start_signal_voltage_switch(struct mmc_host *mmc,
659 struct mmc_ios *ios)
660 {
661 struct device *dev = mmc_dev(mmc);
662 struct sdhci_host *host = mmc_priv(mmc);
663 struct sdhci_pci_slot *slot = sdhci_priv(host);
664 struct intel_host *intel_host = sdhci_pci_priv(slot);
665 unsigned int fn;
666 u32 result = 0;
667 int err;
668
669 err = sdhci_start_signal_voltage_switch(mmc, ios);
670 if (err)
671 return err;
672
673 switch (ios->signal_voltage) {
674 case MMC_SIGNAL_VOLTAGE_330:
675 fn = INTEL_DSM_V33_SWITCH;
676 break;
677 case MMC_SIGNAL_VOLTAGE_180:
678 fn = INTEL_DSM_V18_SWITCH;
679 break;
680 default:
681 return 0;
682 }
683
684 err = intel_dsm(intel_host, dev, fn, &result);
685 pr_debug("%s: %s DSM fn %u error %d result %u\n",
686 mmc_hostname(mmc), __func__, fn, err, result);
687
688 return 0;
689 }
690
691 static const struct sdhci_ops sdhci_intel_byt_ops = {
692 .set_clock = sdhci_set_clock,
693 .set_power = sdhci_intel_set_power,
694 .enable_dma = sdhci_pci_enable_dma,
695 .set_bus_width = sdhci_set_bus_width,
696 .reset = sdhci_reset,
697 .set_uhs_signaling = sdhci_intel_set_uhs_signaling,
698 .hw_reset = sdhci_pci_hw_reset,
699 };
700
701 static const struct sdhci_ops sdhci_intel_glk_ops = {
702 .set_clock = sdhci_set_clock,
703 .set_power = sdhci_intel_set_power,
704 .enable_dma = sdhci_pci_enable_dma,
705 .set_bus_width = sdhci_set_bus_width,
706 .reset = sdhci_and_cqhci_reset,
707 .set_uhs_signaling = sdhci_intel_set_uhs_signaling,
708 .hw_reset = sdhci_pci_hw_reset,
709 .irq = sdhci_cqhci_irq,
710 };
711
byt_read_dsm(struct sdhci_pci_slot * slot)712 static void byt_read_dsm(struct sdhci_pci_slot *slot)
713 {
714 struct intel_host *intel_host = sdhci_pci_priv(slot);
715 struct device *dev = &slot->chip->pdev->dev;
716 struct mmc_host *mmc = slot->host->mmc;
717
718 intel_dsm_init(intel_host, dev, mmc);
719 slot->chip->rpm_retune = intel_host->d3_retune;
720 }
721
intel_execute_tuning(struct mmc_host * mmc,u32 opcode)722 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode)
723 {
724 int err = sdhci_execute_tuning(mmc, opcode);
725 struct sdhci_host *host = mmc_priv(mmc);
726
727 if (err)
728 return err;
729
730 /*
731 * Tuning can leave the IP in an active state (Buffer Read Enable bit
732 * set) which prevents the entry to low power states (i.e. S0i3). Data
733 * reset will clear it.
734 */
735 sdhci_reset(host, SDHCI_RESET_DATA);
736
737 return 0;
738 }
739
740 #define INTEL_ACTIVELTR 0x804
741 #define INTEL_IDLELTR 0x808
742
743 #define INTEL_LTR_REQ BIT(15)
744 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10)
745 #define INTEL_LTR_SCALE_1US (2 << 10)
746 #define INTEL_LTR_SCALE_32US (3 << 10)
747 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0)
748
intel_cache_ltr(struct sdhci_pci_slot * slot)749 static void intel_cache_ltr(struct sdhci_pci_slot *slot)
750 {
751 struct intel_host *intel_host = sdhci_pci_priv(slot);
752 struct sdhci_host *host = slot->host;
753
754 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR);
755 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR);
756 }
757
intel_ltr_set(struct device * dev,s32 val)758 static void intel_ltr_set(struct device *dev, s32 val)
759 {
760 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
761 struct sdhci_pci_slot *slot = chip->slots[0];
762 struct intel_host *intel_host = sdhci_pci_priv(slot);
763 struct sdhci_host *host = slot->host;
764 u32 ltr;
765
766 pm_runtime_get_sync(dev);
767
768 /*
769 * Program latency tolerance (LTR) accordingly what has been asked
770 * by the PM QoS layer or disable it in case we were passed
771 * negative value or PM_QOS_LATENCY_ANY.
772 */
773 ltr = readl(host->ioaddr + INTEL_ACTIVELTR);
774
775 if (val == PM_QOS_LATENCY_ANY || val < 0) {
776 ltr &= ~INTEL_LTR_REQ;
777 } else {
778 ltr |= INTEL_LTR_REQ;
779 ltr &= ~INTEL_LTR_SCALE_MASK;
780 ltr &= ~INTEL_LTR_VALUE_MASK;
781
782 if (val > INTEL_LTR_VALUE_MASK) {
783 val >>= 5;
784 if (val > INTEL_LTR_VALUE_MASK)
785 val = INTEL_LTR_VALUE_MASK;
786 ltr |= INTEL_LTR_SCALE_32US | val;
787 } else {
788 ltr |= INTEL_LTR_SCALE_1US | val;
789 }
790 }
791
792 if (ltr == intel_host->active_ltr)
793 goto out;
794
795 writel(ltr, host->ioaddr + INTEL_ACTIVELTR);
796 writel(ltr, host->ioaddr + INTEL_IDLELTR);
797
798 /* Cache the values into lpss structure */
799 intel_cache_ltr(slot);
800 out:
801 pm_runtime_put_autosuspend(dev);
802 }
803
intel_use_ltr(struct sdhci_pci_chip * chip)804 static bool intel_use_ltr(struct sdhci_pci_chip *chip)
805 {
806 switch (chip->pdev->device) {
807 case PCI_DEVICE_ID_INTEL_BYT_EMMC:
808 case PCI_DEVICE_ID_INTEL_BYT_EMMC2:
809 case PCI_DEVICE_ID_INTEL_BYT_SDIO:
810 case PCI_DEVICE_ID_INTEL_BYT_SD:
811 case PCI_DEVICE_ID_INTEL_BSW_EMMC:
812 case PCI_DEVICE_ID_INTEL_BSW_SDIO:
813 case PCI_DEVICE_ID_INTEL_BSW_SD:
814 return false;
815 default:
816 return true;
817 }
818 }
819
intel_ltr_expose(struct sdhci_pci_chip * chip)820 static void intel_ltr_expose(struct sdhci_pci_chip *chip)
821 {
822 struct device *dev = &chip->pdev->dev;
823
824 if (!intel_use_ltr(chip))
825 return;
826
827 dev->power.set_latency_tolerance = intel_ltr_set;
828 dev_pm_qos_expose_latency_tolerance(dev);
829 }
830
intel_ltr_hide(struct sdhci_pci_chip * chip)831 static void intel_ltr_hide(struct sdhci_pci_chip *chip)
832 {
833 struct device *dev = &chip->pdev->dev;
834
835 if (!intel_use_ltr(chip))
836 return;
837
838 dev_pm_qos_hide_latency_tolerance(dev);
839 dev->power.set_latency_tolerance = NULL;
840 }
841
byt_probe_slot(struct sdhci_pci_slot * slot)842 static void byt_probe_slot(struct sdhci_pci_slot *slot)
843 {
844 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
845 struct device *dev = &slot->chip->pdev->dev;
846 struct mmc_host *mmc = slot->host->mmc;
847
848 byt_read_dsm(slot);
849
850 byt_ocp_setting(slot->chip->pdev);
851
852 ops->execute_tuning = intel_execute_tuning;
853 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch;
854
855 device_property_read_u32(dev, "max-frequency", &mmc->f_max);
856
857 if (!mmc->slotno) {
858 slot->chip->slots[mmc->slotno] = slot;
859 intel_ltr_expose(slot->chip);
860 }
861 }
862
byt_add_debugfs(struct sdhci_pci_slot * slot)863 static void byt_add_debugfs(struct sdhci_pci_slot *slot)
864 {
865 struct intel_host *intel_host = sdhci_pci_priv(slot);
866 struct mmc_host *mmc = slot->host->mmc;
867 struct dentry *dir = mmc->debugfs_root;
868
869 if (!intel_use_ltr(slot->chip))
870 return;
871
872 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr);
873 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr);
874
875 intel_cache_ltr(slot);
876 }
877
byt_add_host(struct sdhci_pci_slot * slot)878 static int byt_add_host(struct sdhci_pci_slot *slot)
879 {
880 int ret = sdhci_add_host(slot->host);
881
882 if (!ret)
883 byt_add_debugfs(slot);
884 return ret;
885 }
886
byt_remove_slot(struct sdhci_pci_slot * slot,int dead)887 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead)
888 {
889 struct mmc_host *mmc = slot->host->mmc;
890
891 if (!mmc->slotno)
892 intel_ltr_hide(slot->chip);
893 }
894
byt_emmc_probe_slot(struct sdhci_pci_slot * slot)895 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
896 {
897 byt_probe_slot(slot);
898 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE |
899 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR |
900 MMC_CAP_CMD_DURING_TFR |
901 MMC_CAP_WAIT_WHILE_BUSY;
902 slot->hw_reset = sdhci_pci_int_hw_reset;
903 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC)
904 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */
905 slot->host->mmc_host_ops.select_drive_strength =
906 intel_select_drive_strength;
907 return 0;
908 }
909
glk_broken_cqhci(struct sdhci_pci_slot * slot)910 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot)
911 {
912 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
913 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") ||
914 dmi_match(DMI_SYS_VENDOR, "IRBIS") ||
915 dmi_match(DMI_SYS_VENDOR, "Positivo Tecnologia SA"));
916 }
917
jsl_broken_hs400es(struct sdhci_pci_slot * slot)918 static bool jsl_broken_hs400es(struct sdhci_pci_slot *slot)
919 {
920 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_JSL_EMMC &&
921 dmi_match(DMI_BIOS_VENDOR, "ASUSTeK COMPUTER INC.");
922 }
923
glk_emmc_probe_slot(struct sdhci_pci_slot * slot)924 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot)
925 {
926 int ret = byt_emmc_probe_slot(slot);
927
928 if (!glk_broken_cqhci(slot))
929 slot->host->mmc->caps2 |= MMC_CAP2_CQE;
930
931 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) {
932 if (!jsl_broken_hs400es(slot)) {
933 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES;
934 slot->host->mmc_host_ops.hs400_enhanced_strobe =
935 intel_hs400_enhanced_strobe;
936 }
937 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD;
938 }
939
940 return ret;
941 }
942
943 static const struct cqhci_host_ops glk_cqhci_ops = {
944 .enable = sdhci_cqe_enable,
945 .disable = sdhci_cqe_disable,
946 .dumpregs = sdhci_pci_dumpregs,
947 };
948
glk_emmc_add_host(struct sdhci_pci_slot * slot)949 static int glk_emmc_add_host(struct sdhci_pci_slot *slot)
950 {
951 struct device *dev = &slot->chip->pdev->dev;
952 struct sdhci_host *host = slot->host;
953 struct cqhci_host *cq_host;
954 bool dma64;
955 int ret;
956
957 ret = sdhci_setup_host(host);
958 if (ret)
959 return ret;
960
961 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
962 if (!cq_host) {
963 ret = -ENOMEM;
964 goto cleanup;
965 }
966
967 cq_host->mmio = host->ioaddr + 0x200;
968 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ;
969 cq_host->ops = &glk_cqhci_ops;
970
971 dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
972 if (dma64)
973 cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
974
975 ret = cqhci_init(cq_host, host->mmc, dma64);
976 if (ret)
977 goto cleanup;
978
979 ret = __sdhci_add_host(host);
980 if (ret)
981 goto cleanup;
982
983 byt_add_debugfs(slot);
984
985 return 0;
986
987 cleanup:
988 sdhci_cleanup_host(host);
989 return ret;
990 }
991
992 #ifdef CONFIG_PM
993 #define GLK_RX_CTRL1 0x834
994 #define GLK_TUN_VAL 0x840
995 #define GLK_PATH_PLL GENMASK(13, 8)
996 #define GLK_DLY GENMASK(6, 0)
997 /* Workaround firmware failing to restore the tuning value */
glk_rpm_retune_wa(struct sdhci_pci_chip * chip,bool susp)998 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp)
999 {
1000 struct sdhci_pci_slot *slot = chip->slots[0];
1001 struct intel_host *intel_host = sdhci_pci_priv(slot);
1002 struct sdhci_host *host = slot->host;
1003 u32 glk_rx_ctrl1;
1004 u32 glk_tun_val;
1005 u32 dly;
1006
1007 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc))
1008 return;
1009
1010 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1);
1011 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL);
1012
1013 if (susp) {
1014 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1;
1015 intel_host->glk_tun_val = glk_tun_val;
1016 return;
1017 }
1018
1019 if (!intel_host->glk_tun_val)
1020 return;
1021
1022 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) {
1023 intel_host->rpm_retune_ok = true;
1024 return;
1025 }
1026
1027 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) +
1028 (intel_host->glk_tun_val << 1));
1029 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1))
1030 return;
1031
1032 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly;
1033 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1);
1034
1035 intel_host->rpm_retune_ok = true;
1036 chip->rpm_retune = true;
1037 mmc_retune_needed(host->mmc);
1038 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc));
1039 }
1040
glk_rpm_retune_chk(struct sdhci_pci_chip * chip,bool susp)1041 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp)
1042 {
1043 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC &&
1044 !chip->rpm_retune)
1045 glk_rpm_retune_wa(chip, susp);
1046 }
1047
glk_runtime_suspend(struct sdhci_pci_chip * chip)1048 static int glk_runtime_suspend(struct sdhci_pci_chip *chip)
1049 {
1050 glk_rpm_retune_chk(chip, true);
1051
1052 return sdhci_cqhci_runtime_suspend(chip);
1053 }
1054
glk_runtime_resume(struct sdhci_pci_chip * chip)1055 static int glk_runtime_resume(struct sdhci_pci_chip *chip)
1056 {
1057 glk_rpm_retune_chk(chip, false);
1058
1059 return sdhci_cqhci_runtime_resume(chip);
1060 }
1061 #endif
1062
1063 #ifdef CONFIG_ACPI
ni_set_max_freq(struct sdhci_pci_slot * slot)1064 static int ni_set_max_freq(struct sdhci_pci_slot *slot)
1065 {
1066 acpi_status status;
1067 unsigned long long max_freq;
1068
1069 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev),
1070 "MXFQ", NULL, &max_freq);
1071 if (ACPI_FAILURE(status)) {
1072 dev_err(&slot->chip->pdev->dev,
1073 "MXFQ not found in acpi table\n");
1074 return -EINVAL;
1075 }
1076
1077 slot->host->mmc->f_max = max_freq * 1000000;
1078
1079 return 0;
1080 }
1081 #else
ni_set_max_freq(struct sdhci_pci_slot * slot)1082 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot)
1083 {
1084 return 0;
1085 }
1086 #endif
1087
ni_byt_sdio_probe_slot(struct sdhci_pci_slot * slot)1088 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
1089 {
1090 int err;
1091
1092 byt_probe_slot(slot);
1093
1094 err = ni_set_max_freq(slot);
1095 if (err)
1096 return err;
1097
1098 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
1099 MMC_CAP_WAIT_WHILE_BUSY;
1100 return 0;
1101 }
1102
byt_sdio_probe_slot(struct sdhci_pci_slot * slot)1103 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
1104 {
1105 byt_probe_slot(slot);
1106 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE |
1107 MMC_CAP_WAIT_WHILE_BUSY;
1108 return 0;
1109 }
1110
byt_needs_pwr_off(struct sdhci_pci_slot * slot)1111 static void byt_needs_pwr_off(struct sdhci_pci_slot *slot)
1112 {
1113 struct intel_host *intel_host = sdhci_pci_priv(slot);
1114 u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL);
1115
1116 intel_host->needs_pwr_off = reg & SDHCI_POWER_ON;
1117 }
1118
byt_sd_probe_slot(struct sdhci_pci_slot * slot)1119 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot)
1120 {
1121 byt_probe_slot(slot);
1122 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY |
1123 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE;
1124 slot->cd_idx = 0;
1125 slot->cd_override_level = true;
1126 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD ||
1127 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD ||
1128 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD ||
1129 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD)
1130 slot->host->mmc_host_ops.get_cd = bxt_get_cd;
1131
1132 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI &&
1133 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3)
1134 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V;
1135
1136 byt_needs_pwr_off(slot);
1137
1138 return 0;
1139 }
1140
1141 #ifdef CONFIG_PM_SLEEP
1142
byt_resume(struct sdhci_pci_chip * chip)1143 static int byt_resume(struct sdhci_pci_chip *chip)
1144 {
1145 byt_ocp_setting(chip->pdev);
1146
1147 return sdhci_pci_resume_host(chip);
1148 }
1149
1150 #endif
1151
1152 #ifdef CONFIG_PM
1153
byt_runtime_resume(struct sdhci_pci_chip * chip)1154 static int byt_runtime_resume(struct sdhci_pci_chip *chip)
1155 {
1156 byt_ocp_setting(chip->pdev);
1157
1158 return sdhci_pci_runtime_resume_host(chip);
1159 }
1160
1161 #endif
1162
1163 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
1164 #ifdef CONFIG_PM_SLEEP
1165 .resume = byt_resume,
1166 #endif
1167 #ifdef CONFIG_PM
1168 .runtime_resume = byt_runtime_resume,
1169 #endif
1170 .allow_runtime_pm = true,
1171 .probe_slot = byt_emmc_probe_slot,
1172 .add_host = byt_add_host,
1173 .remove_slot = byt_remove_slot,
1174 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1175 SDHCI_QUIRK_NO_LED,
1176 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1177 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1178 SDHCI_QUIRK2_STOP_WITH_TC,
1179 .ops = &sdhci_intel_byt_ops,
1180 .priv_size = sizeof(struct intel_host),
1181 };
1182
1183 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = {
1184 .allow_runtime_pm = true,
1185 .probe_slot = glk_emmc_probe_slot,
1186 .add_host = glk_emmc_add_host,
1187 .remove_slot = byt_remove_slot,
1188 #ifdef CONFIG_PM_SLEEP
1189 .suspend = sdhci_cqhci_suspend,
1190 .resume = sdhci_cqhci_resume,
1191 #endif
1192 #ifdef CONFIG_PM
1193 .runtime_suspend = glk_runtime_suspend,
1194 .runtime_resume = glk_runtime_resume,
1195 #endif
1196 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1197 SDHCI_QUIRK_NO_LED,
1198 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1199 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 |
1200 SDHCI_QUIRK2_STOP_WITH_TC,
1201 .ops = &sdhci_intel_glk_ops,
1202 .priv_size = sizeof(struct intel_host),
1203 };
1204
1205 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = {
1206 #ifdef CONFIG_PM_SLEEP
1207 .resume = byt_resume,
1208 #endif
1209 #ifdef CONFIG_PM
1210 .runtime_resume = byt_runtime_resume,
1211 #endif
1212 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1213 SDHCI_QUIRK_NO_LED,
1214 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1215 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1216 .allow_runtime_pm = true,
1217 .probe_slot = ni_byt_sdio_probe_slot,
1218 .add_host = byt_add_host,
1219 .remove_slot = byt_remove_slot,
1220 .ops = &sdhci_intel_byt_ops,
1221 .priv_size = sizeof(struct intel_host),
1222 };
1223
1224 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
1225 #ifdef CONFIG_PM_SLEEP
1226 .resume = byt_resume,
1227 #endif
1228 #ifdef CONFIG_PM
1229 .runtime_resume = byt_runtime_resume,
1230 #endif
1231 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1232 SDHCI_QUIRK_NO_LED,
1233 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON |
1234 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1235 .allow_runtime_pm = true,
1236 .probe_slot = byt_sdio_probe_slot,
1237 .add_host = byt_add_host,
1238 .remove_slot = byt_remove_slot,
1239 .ops = &sdhci_intel_byt_ops,
1240 .priv_size = sizeof(struct intel_host),
1241 };
1242
1243 /* DMI quirks for devices with missing or broken CD GPIO info */
1244 static const struct gpiod_lookup_table vexia_edu_atla10_cd_gpios = {
1245 .dev_id = "0000:00:12.0",
1246 .table = {
1247 GPIO_LOOKUP("INT33FC:00", 38, "cd", GPIO_ACTIVE_HIGH),
1248 { }
1249 },
1250 };
1251
1252 static const struct dmi_system_id sdhci_intel_byt_cd_gpio_override[] = {
1253 {
1254 /* Vexia Edu Atla 10 tablet 9V version */
1255 .matches = {
1256 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"),
1257 DMI_MATCH(DMI_BOARD_NAME, "Aptio CRB"),
1258 /* Above strings are too generic, also match on BIOS date */
1259 DMI_MATCH(DMI_BIOS_DATE, "08/25/2014"),
1260 },
1261 .driver_data = (void *)&vexia_edu_atla10_cd_gpios,
1262 },
1263 { }
1264 };
1265
1266 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
1267 #ifdef CONFIG_PM_SLEEP
1268 .resume = byt_resume,
1269 #endif
1270 #ifdef CONFIG_PM
1271 .runtime_resume = byt_runtime_resume,
1272 #endif
1273 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
1274 SDHCI_QUIRK_NO_LED,
1275 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON |
1276 SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1277 SDHCI_QUIRK2_STOP_WITH_TC,
1278 .allow_runtime_pm = true,
1279 .own_cd_for_runtime_pm = true,
1280 .probe_slot = byt_sd_probe_slot,
1281 .add_host = byt_add_host,
1282 .remove_slot = byt_remove_slot,
1283 .ops = &sdhci_intel_byt_ops,
1284 .cd_gpio_override = sdhci_intel_byt_cd_gpio_override,
1285 .priv_size = sizeof(struct intel_host),
1286 };
1287
1288 /* Define Host controllers for Intel Merrifield platform */
1289 #define INTEL_MRFLD_EMMC_0 0
1290 #define INTEL_MRFLD_EMMC_1 1
1291 #define INTEL_MRFLD_SD 2
1292 #define INTEL_MRFLD_SDIO 3
1293
1294 #ifdef CONFIG_ACPI
intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot * slot)1295 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot)
1296 {
1297 struct acpi_device *device;
1298
1299 device = ACPI_COMPANION(&slot->chip->pdev->dev);
1300 if (device)
1301 acpi_device_fix_up_power_extended(device);
1302 }
1303 #else
intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot * slot)1304 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {}
1305 #endif
1306
intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot * slot)1307 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot)
1308 {
1309 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn);
1310
1311 switch (func) {
1312 case INTEL_MRFLD_EMMC_0:
1313 case INTEL_MRFLD_EMMC_1:
1314 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1315 MMC_CAP_8_BIT_DATA |
1316 MMC_CAP_1_8V_DDR;
1317 break;
1318 case INTEL_MRFLD_SD:
1319 slot->cd_idx = 0;
1320 slot->cd_override_level = true;
1321 /*
1322 * There are two PCB designs of SD card slot with the opposite
1323 * card detection sense. Quirk this out by ignoring GPIO state
1324 * completely in the custom ->get_cd() callback.
1325 */
1326 slot->host->mmc_host_ops.get_cd = mrfld_get_cd;
1327 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
1328 break;
1329 case INTEL_MRFLD_SDIO:
1330 /* Advertise 2.0v for compatibility with the SDIO card's OCR */
1331 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195;
1332 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE |
1333 MMC_CAP_POWER_OFF_CARD;
1334 break;
1335 default:
1336 return -ENODEV;
1337 }
1338
1339 intel_mrfld_mmc_fix_up_power_slot(slot);
1340 return 0;
1341 }
1342
1343 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = {
1344 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1345 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 |
1346 SDHCI_QUIRK2_PRESET_VALUE_BROKEN,
1347 .allow_runtime_pm = true,
1348 .probe_slot = intel_mrfld_mmc_probe_slot,
1349 };
1350
jmicron_pmos(struct sdhci_pci_chip * chip,int on)1351 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on)
1352 {
1353 u8 scratch;
1354 int ret;
1355
1356 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch);
1357 if (ret)
1358 goto fail;
1359
1360 /*
1361 * Turn PMOS on [bit 0], set over current detection to 2.4 V
1362 * [bit 1:2] and enable over current debouncing [bit 6].
1363 */
1364 if (on)
1365 scratch |= 0x47;
1366 else
1367 scratch &= ~0x47;
1368
1369 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch);
1370
1371 fail:
1372 return pcibios_err_to_errno(ret);
1373 }
1374
jmicron_probe(struct sdhci_pci_chip * chip)1375 static int jmicron_probe(struct sdhci_pci_chip *chip)
1376 {
1377 int ret;
1378 u16 mmcdev = 0;
1379
1380 if (chip->pdev->revision == 0) {
1381 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR |
1382 SDHCI_QUIRK_32BIT_DMA_SIZE |
1383 SDHCI_QUIRK_32BIT_ADMA_SIZE |
1384 SDHCI_QUIRK_RESET_AFTER_REQUEST |
1385 SDHCI_QUIRK_BROKEN_SMALL_PIO;
1386 }
1387
1388 /*
1389 * JMicron chips can have two interfaces to the same hardware
1390 * in order to work around limitations in Microsoft's driver.
1391 * We need to make sure we only bind to one of them.
1392 *
1393 * This code assumes two things:
1394 *
1395 * 1. The PCI code adds subfunctions in order.
1396 *
1397 * 2. The MMC interface has a lower subfunction number
1398 * than the SD interface.
1399 */
1400 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD)
1401 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC;
1402 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD)
1403 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD;
1404
1405 if (mmcdev) {
1406 struct pci_dev *sd_dev;
1407
1408 sd_dev = NULL;
1409 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON,
1410 mmcdev, sd_dev)) != NULL) {
1411 if ((PCI_SLOT(chip->pdev->devfn) ==
1412 PCI_SLOT(sd_dev->devfn)) &&
1413 (chip->pdev->bus == sd_dev->bus))
1414 break;
1415 }
1416
1417 if (sd_dev) {
1418 pci_dev_put(sd_dev);
1419 dev_info(&chip->pdev->dev, "Refusing to bind to "
1420 "secondary interface.\n");
1421 return -ENODEV;
1422 }
1423 }
1424
1425 /*
1426 * JMicron chips need a bit of a nudge to enable the power
1427 * output pins.
1428 */
1429 ret = jmicron_pmos(chip, 1);
1430 if (ret) {
1431 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1432 return ret;
1433 }
1434
1435 /* quirk for unsable RO-detection on JM388 chips */
1436 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
1437 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1438 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
1439
1440 return 0;
1441 }
1442
jmicron_enable_mmc(struct sdhci_host * host,int on)1443 static void jmicron_enable_mmc(struct sdhci_host *host, int on)
1444 {
1445 u8 scratch;
1446
1447 scratch = readb(host->ioaddr + 0xC0);
1448
1449 if (on)
1450 scratch |= 0x01;
1451 else
1452 scratch &= ~0x01;
1453
1454 writeb(scratch, host->ioaddr + 0xC0);
1455 }
1456
jmicron_probe_slot(struct sdhci_pci_slot * slot)1457 static int jmicron_probe_slot(struct sdhci_pci_slot *slot)
1458 {
1459 if (slot->chip->pdev->revision == 0) {
1460 u16 version;
1461
1462 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION);
1463 version = (version & SDHCI_VENDOR_VER_MASK) >>
1464 SDHCI_VENDOR_VER_SHIFT;
1465
1466 /*
1467 * Older versions of the chip have lots of nasty glitches
1468 * in the ADMA engine. It's best just to avoid it
1469 * completely.
1470 */
1471 if (version < 0xAC)
1472 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
1473 }
1474
1475 /* JM388 MMC doesn't support 1.8V while SD supports it */
1476 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1477 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 |
1478 MMC_VDD_29_30 | MMC_VDD_30_31 |
1479 MMC_VDD_165_195; /* allow 1.8V */
1480 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 |
1481 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */
1482 }
1483
1484 /*
1485 * The secondary interface requires a bit set to get the
1486 * interrupts.
1487 */
1488 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1489 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1490 jmicron_enable_mmc(slot->host, 1);
1491
1492 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST;
1493
1494 return 0;
1495 }
1496
jmicron_remove_slot(struct sdhci_pci_slot * slot,int dead)1497 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead)
1498 {
1499 if (dead)
1500 return;
1501
1502 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1503 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
1504 jmicron_enable_mmc(slot->host, 0);
1505 }
1506
1507 #ifdef CONFIG_PM_SLEEP
jmicron_suspend(struct sdhci_pci_chip * chip)1508 static int jmicron_suspend(struct sdhci_pci_chip *chip)
1509 {
1510 int i, ret;
1511
1512 ret = sdhci_pci_suspend_host(chip);
1513 if (ret)
1514 return ret;
1515
1516 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1517 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1518 for (i = 0; i < chip->num_slots; i++)
1519 jmicron_enable_mmc(chip->slots[i]->host, 0);
1520 }
1521
1522 return 0;
1523 }
1524
jmicron_resume(struct sdhci_pci_chip * chip)1525 static int jmicron_resume(struct sdhci_pci_chip *chip)
1526 {
1527 int ret, i;
1528
1529 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
1530 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
1531 for (i = 0; i < chip->num_slots; i++)
1532 jmicron_enable_mmc(chip->slots[i]->host, 1);
1533 }
1534
1535 ret = jmicron_pmos(chip, 1);
1536 if (ret) {
1537 dev_err(&chip->pdev->dev, "Failure enabling card power\n");
1538 return ret;
1539 }
1540
1541 return sdhci_pci_resume_host(chip);
1542 }
1543 #endif
1544
1545 static const struct sdhci_pci_fixes sdhci_jmicron = {
1546 .probe = jmicron_probe,
1547
1548 .probe_slot = jmicron_probe_slot,
1549 .remove_slot = jmicron_remove_slot,
1550
1551 #ifdef CONFIG_PM_SLEEP
1552 .suspend = jmicron_suspend,
1553 .resume = jmicron_resume,
1554 #endif
1555 };
1556
1557 /* SysKonnect CardBus2SDIO extra registers */
1558 #define SYSKT_CTRL 0x200
1559 #define SYSKT_RDFIFO_STAT 0x204
1560 #define SYSKT_WRFIFO_STAT 0x208
1561 #define SYSKT_POWER_DATA 0x20c
1562 #define SYSKT_POWER_330 0xef
1563 #define SYSKT_POWER_300 0xf8
1564 #define SYSKT_POWER_184 0xcc
1565 #define SYSKT_POWER_CMD 0x20d
1566 #define SYSKT_POWER_START (1 << 7)
1567 #define SYSKT_POWER_STATUS 0x20e
1568 #define SYSKT_POWER_STATUS_OK (1 << 0)
1569 #define SYSKT_BOARD_REV 0x210
1570 #define SYSKT_CHIP_REV 0x211
1571 #define SYSKT_CONF_DATA 0x212
1572 #define SYSKT_CONF_DATA_1V8 (1 << 2)
1573 #define SYSKT_CONF_DATA_2V5 (1 << 1)
1574 #define SYSKT_CONF_DATA_3V3 (1 << 0)
1575
syskt_probe(struct sdhci_pci_chip * chip)1576 static int syskt_probe(struct sdhci_pci_chip *chip)
1577 {
1578 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
1579 chip->pdev->class &= ~0x0000FF;
1580 chip->pdev->class |= PCI_SDHCI_IFDMA;
1581 }
1582 return 0;
1583 }
1584
syskt_probe_slot(struct sdhci_pci_slot * slot)1585 static int syskt_probe_slot(struct sdhci_pci_slot *slot)
1586 {
1587 int tm, ps;
1588
1589 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV);
1590 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV);
1591 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, "
1592 "board rev %d.%d, chip rev %d.%d\n",
1593 board_rev >> 4, board_rev & 0xf,
1594 chip_rev >> 4, chip_rev & 0xf);
1595 if (chip_rev >= 0x20)
1596 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA;
1597
1598 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA);
1599 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD);
1600 udelay(50);
1601 tm = 10; /* Wait max 1 ms */
1602 do {
1603 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS);
1604 if (ps & SYSKT_POWER_STATUS_OK)
1605 break;
1606 udelay(100);
1607 } while (--tm);
1608 if (!tm) {
1609 dev_err(&slot->chip->pdev->dev,
1610 "power regulator never stabilized");
1611 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD);
1612 return -ENODEV;
1613 }
1614
1615 return 0;
1616 }
1617
1618 static const struct sdhci_pci_fixes sdhci_syskt = {
1619 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER,
1620 .probe = syskt_probe,
1621 .probe_slot = syskt_probe_slot,
1622 };
1623
via_probe(struct sdhci_pci_chip * chip)1624 static int via_probe(struct sdhci_pci_chip *chip)
1625 {
1626 if (chip->pdev->revision == 0x10)
1627 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER;
1628
1629 return 0;
1630 }
1631
1632 static const struct sdhci_pci_fixes sdhci_via = {
1633 .probe = via_probe,
1634 };
1635
rtsx_probe_slot(struct sdhci_pci_slot * slot)1636 static int rtsx_probe_slot(struct sdhci_pci_slot *slot)
1637 {
1638 slot->host->mmc->caps2 |= MMC_CAP2_HS200;
1639 return 0;
1640 }
1641
1642 static const struct sdhci_pci_fixes sdhci_rtsx = {
1643 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
1644 SDHCI_QUIRK2_BROKEN_64_BIT_DMA |
1645 SDHCI_QUIRK2_BROKEN_DDR50,
1646 .probe_slot = rtsx_probe_slot,
1647 };
1648
1649 /*AMD chipset generation*/
1650 enum amd_chipset_gen {
1651 AMD_CHIPSET_BEFORE_ML,
1652 AMD_CHIPSET_CZ,
1653 AMD_CHIPSET_NL,
1654 AMD_CHIPSET_UNKNOWN,
1655 };
1656
1657 /* AMD registers */
1658 #define AMD_SD_AUTO_PATTERN 0xB8
1659 #define AMD_MSLEEP_DURATION 4
1660 #define AMD_SD_MISC_CONTROL 0xD0
1661 #define AMD_MAX_TUNE_VALUE 0x0B
1662 #define AMD_AUTO_TUNE_SEL 0x10800
1663 #define AMD_FIFO_PTR 0x30
1664 #define AMD_BIT_MASK 0x1F
1665
amd_tuning_reset(struct sdhci_host * host)1666 static void amd_tuning_reset(struct sdhci_host *host)
1667 {
1668 unsigned int val;
1669
1670 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1671 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING;
1672 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1673
1674 val = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1675 val &= ~SDHCI_CTRL_EXEC_TUNING;
1676 sdhci_writew(host, val, SDHCI_HOST_CONTROL2);
1677 }
1678
amd_config_tuning_phase(struct pci_dev * pdev,u8 phase)1679 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase)
1680 {
1681 unsigned int val;
1682
1683 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val);
1684 val &= ~AMD_BIT_MASK;
1685 val |= (AMD_AUTO_TUNE_SEL | (phase << 1));
1686 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val);
1687 }
1688
amd_enable_manual_tuning(struct pci_dev * pdev)1689 static void amd_enable_manual_tuning(struct pci_dev *pdev)
1690 {
1691 unsigned int val;
1692
1693 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val);
1694 val |= AMD_FIFO_PTR;
1695 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val);
1696 }
1697
amd_execute_tuning_hs200(struct sdhci_host * host,u32 opcode)1698 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode)
1699 {
1700 struct sdhci_pci_slot *slot = sdhci_priv(host);
1701 struct pci_dev *pdev = slot->chip->pdev;
1702 u8 valid_win = 0;
1703 u8 valid_win_max = 0;
1704 u8 valid_win_end = 0;
1705 u8 ctrl, tune_around;
1706
1707 amd_tuning_reset(host);
1708
1709 for (tune_around = 0; tune_around < 12; tune_around++) {
1710 amd_config_tuning_phase(pdev, tune_around);
1711
1712 if (mmc_send_tuning(host->mmc, opcode, NULL)) {
1713 valid_win = 0;
1714 msleep(AMD_MSLEEP_DURATION);
1715 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA;
1716 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET);
1717 } else if (++valid_win > valid_win_max) {
1718 valid_win_max = valid_win;
1719 valid_win_end = tune_around;
1720 }
1721 }
1722
1723 if (!valid_win_max) {
1724 dev_err(&pdev->dev, "no tuning point found\n");
1725 return -EIO;
1726 }
1727
1728 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2);
1729
1730 amd_enable_manual_tuning(pdev);
1731
1732 host->mmc->retune_period = 0;
1733
1734 return 0;
1735 }
1736
amd_execute_tuning(struct mmc_host * mmc,u32 opcode)1737 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode)
1738 {
1739 struct sdhci_host *host = mmc_priv(mmc);
1740
1741 /* AMD requires custom HS200 tuning */
1742 if (host->timing == MMC_TIMING_MMC_HS200)
1743 return amd_execute_tuning_hs200(host, opcode);
1744
1745 /* Otherwise perform standard SDHCI tuning */
1746 return sdhci_execute_tuning(mmc, opcode);
1747 }
1748
amd_probe_slot(struct sdhci_pci_slot * slot)1749 static int amd_probe_slot(struct sdhci_pci_slot *slot)
1750 {
1751 struct mmc_host_ops *ops = &slot->host->mmc_host_ops;
1752
1753 ops->execute_tuning = amd_execute_tuning;
1754
1755 return 0;
1756 }
1757
amd_probe(struct sdhci_pci_chip * chip)1758 static int amd_probe(struct sdhci_pci_chip *chip)
1759 {
1760 struct pci_dev *smbus_dev;
1761 enum amd_chipset_gen gen;
1762
1763 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1764 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
1765 if (smbus_dev) {
1766 gen = AMD_CHIPSET_BEFORE_ML;
1767 } else {
1768 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
1769 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL);
1770 if (smbus_dev) {
1771 if (smbus_dev->revision < 0x51)
1772 gen = AMD_CHIPSET_CZ;
1773 else
1774 gen = AMD_CHIPSET_NL;
1775 } else {
1776 gen = AMD_CHIPSET_UNKNOWN;
1777 }
1778 }
1779
1780 pci_dev_put(smbus_dev);
1781
1782 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ)
1783 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD;
1784
1785 return 0;
1786 }
1787
sdhci_read_present_state(struct sdhci_host * host)1788 static u32 sdhci_read_present_state(struct sdhci_host *host)
1789 {
1790 return sdhci_readl(host, SDHCI_PRESENT_STATE);
1791 }
1792
amd_sdhci_reset(struct sdhci_host * host,u8 mask)1793 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask)
1794 {
1795 struct sdhci_pci_slot *slot = sdhci_priv(host);
1796 struct pci_dev *pdev = slot->chip->pdev;
1797 u32 present_state;
1798
1799 /*
1800 * SDHC 0x7906 requires a hard reset to clear all internal state.
1801 * Otherwise it can get into a bad state where the DATA lines are always
1802 * read as zeros.
1803 */
1804 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) {
1805 pci_clear_master(pdev);
1806
1807 pci_save_state(pdev);
1808
1809 pci_set_power_state(pdev, PCI_D3cold);
1810 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc),
1811 pdev->current_state);
1812 pci_set_power_state(pdev, PCI_D0);
1813
1814 pci_restore_state(pdev);
1815
1816 /*
1817 * SDHCI_RESET_ALL says the card detect logic should not be
1818 * reset, but since we need to reset the entire controller
1819 * we should wait until the card detect logic has stabilized.
1820 *
1821 * This normally takes about 40ms.
1822 */
1823 readx_poll_timeout(
1824 sdhci_read_present_state,
1825 host,
1826 present_state,
1827 present_state & SDHCI_CD_STABLE,
1828 10000,
1829 100000
1830 );
1831 }
1832
1833 return sdhci_reset(host, mask);
1834 }
1835
1836 static const struct sdhci_ops amd_sdhci_pci_ops = {
1837 .set_clock = sdhci_set_clock,
1838 .enable_dma = sdhci_pci_enable_dma,
1839 .set_bus_width = sdhci_set_bus_width,
1840 .reset = amd_sdhci_reset,
1841 .set_uhs_signaling = sdhci_set_uhs_signaling,
1842 };
1843
1844 static const struct sdhci_pci_fixes sdhci_amd = {
1845 .probe = amd_probe,
1846 .ops = &amd_sdhci_pci_ops,
1847 .probe_slot = amd_probe_slot,
1848 };
1849
1850 static const struct pci_device_id pci_ids[] = {
1851 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh),
1852 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc),
1853 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc),
1854 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc),
1855 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712),
1856 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712),
1857 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714),
1858 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714),
1859 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe),
1860 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron),
1861 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron),
1862 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron),
1863 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron),
1864 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt),
1865 SDHCI_PCI_DEVICE(VIA, 95D0, via),
1866 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx),
1867 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk),
1868 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0),
1869 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2),
1870 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2),
1871 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd),
1872 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio),
1873 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio),
1874 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc),
1875 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc),
1876 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio),
1877 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio),
1878 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc),
1879 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio),
1880 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio),
1881 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd),
1882 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc),
1883 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc),
1884 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio),
1885 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd),
1886 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd),
1887 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio),
1888 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio),
1889 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc),
1890 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc),
1891 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc),
1892 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc),
1893 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio),
1894 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd),
1895 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc),
1896 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc),
1897 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc),
1898 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio),
1899 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd),
1900 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc),
1901 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio),
1902 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd),
1903 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc),
1904 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio),
1905 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd),
1906 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc),
1907 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio),
1908 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd),
1909 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc),
1910 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd),
1911 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd),
1912 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc),
1913 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd),
1914 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc),
1915 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd),
1916 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc),
1917 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd),
1918 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd),
1919 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc),
1920 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd),
1921 SDHCI_PCI_DEVICE(INTEL, LKF_EMMC, intel_glk_emmc),
1922 SDHCI_PCI_DEVICE(INTEL, LKF_SD, intel_byt_sd),
1923 SDHCI_PCI_DEVICE(INTEL, ADL_EMMC, intel_glk_emmc),
1924 SDHCI_PCI_DEVICE(O2, 8120, o2),
1925 SDHCI_PCI_DEVICE(O2, 8220, o2),
1926 SDHCI_PCI_DEVICE(O2, 8221, o2),
1927 SDHCI_PCI_DEVICE(O2, 8320, o2),
1928 SDHCI_PCI_DEVICE(O2, 8321, o2),
1929 SDHCI_PCI_DEVICE(O2, FUJIN2, o2),
1930 SDHCI_PCI_DEVICE(O2, SDS0, o2),
1931 SDHCI_PCI_DEVICE(O2, SDS1, o2),
1932 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2),
1933 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2),
1934 SDHCI_PCI_DEVICE(O2, GG8_9860, o2),
1935 SDHCI_PCI_DEVICE(O2, GG8_9861, o2),
1936 SDHCI_PCI_DEVICE(O2, GG8_9862, o2),
1937 SDHCI_PCI_DEVICE(O2, GG8_9863, o2),
1938 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan),
1939 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps),
1940 SDHCI_PCI_DEVICE(GLI, 9750, gl9750),
1941 SDHCI_PCI_DEVICE(GLI, 9755, gl9755),
1942 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e),
1943 SDHCI_PCI_DEVICE(GLI, 9767, gl9767),
1944 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd),
1945 /* Generic SD host controller */
1946 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)},
1947 { /* end: all zeroes */ },
1948 };
1949
1950 MODULE_DEVICE_TABLE(pci, pci_ids);
1951
1952 /*****************************************************************************\
1953 * *
1954 * SDHCI core callbacks *
1955 * *
1956 \*****************************************************************************/
1957
sdhci_pci_enable_dma(struct sdhci_host * host)1958 int sdhci_pci_enable_dma(struct sdhci_host *host)
1959 {
1960 struct sdhci_pci_slot *slot;
1961 struct pci_dev *pdev;
1962
1963 slot = sdhci_priv(host);
1964 pdev = slot->chip->pdev;
1965
1966 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) &&
1967 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) &&
1968 (host->flags & SDHCI_USE_SDMA)) {
1969 dev_warn(&pdev->dev, "Will use DMA mode even though HW "
1970 "doesn't fully claim to support it.\n");
1971 }
1972
1973 pci_set_master(pdev);
1974
1975 return 0;
1976 }
1977
sdhci_pci_hw_reset(struct sdhci_host * host)1978 static void sdhci_pci_hw_reset(struct sdhci_host *host)
1979 {
1980 struct sdhci_pci_slot *slot = sdhci_priv(host);
1981
1982 if (slot->hw_reset)
1983 slot->hw_reset(host);
1984 }
1985
1986 static const struct sdhci_ops sdhci_pci_ops = {
1987 .set_clock = sdhci_set_clock,
1988 .enable_dma = sdhci_pci_enable_dma,
1989 .set_bus_width = sdhci_set_bus_width,
1990 .reset = sdhci_reset,
1991 .set_uhs_signaling = sdhci_set_uhs_signaling,
1992 .hw_reset = sdhci_pci_hw_reset,
1993 };
1994
1995 /*****************************************************************************\
1996 * *
1997 * Suspend/resume *
1998 * *
1999 \*****************************************************************************/
2000
2001 #ifdef CONFIG_PM_SLEEP
sdhci_pci_suspend(struct device * dev)2002 static int sdhci_pci_suspend(struct device *dev)
2003 {
2004 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2005
2006 if (!chip)
2007 return 0;
2008
2009 if (chip->fixes && chip->fixes->suspend)
2010 return chip->fixes->suspend(chip);
2011
2012 return sdhci_pci_suspend_host(chip);
2013 }
2014
sdhci_pci_resume(struct device * dev)2015 static int sdhci_pci_resume(struct device *dev)
2016 {
2017 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2018
2019 if (!chip)
2020 return 0;
2021
2022 if (chip->fixes && chip->fixes->resume)
2023 return chip->fixes->resume(chip);
2024
2025 return sdhci_pci_resume_host(chip);
2026 }
2027 #endif
2028
2029 #ifdef CONFIG_PM
sdhci_pci_runtime_suspend(struct device * dev)2030 static int sdhci_pci_runtime_suspend(struct device *dev)
2031 {
2032 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2033
2034 if (!chip)
2035 return 0;
2036
2037 if (chip->fixes && chip->fixes->runtime_suspend)
2038 return chip->fixes->runtime_suspend(chip);
2039
2040 return sdhci_pci_runtime_suspend_host(chip);
2041 }
2042
sdhci_pci_runtime_resume(struct device * dev)2043 static int sdhci_pci_runtime_resume(struct device *dev)
2044 {
2045 struct sdhci_pci_chip *chip = dev_get_drvdata(dev);
2046
2047 if (!chip)
2048 return 0;
2049
2050 if (chip->fixes && chip->fixes->runtime_resume)
2051 return chip->fixes->runtime_resume(chip);
2052
2053 return sdhci_pci_runtime_resume_host(chip);
2054 }
2055 #endif
2056
2057 static const struct dev_pm_ops sdhci_pci_pm_ops = {
2058 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume)
2059 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend,
2060 sdhci_pci_runtime_resume, NULL)
2061 };
2062
2063 /*****************************************************************************\
2064 * *
2065 * Device probing/removal *
2066 * *
2067 \*****************************************************************************/
2068
sdhci_pci_add_gpio_lookup_table(struct sdhci_pci_chip * chip)2069 static struct gpiod_lookup_table *sdhci_pci_add_gpio_lookup_table(
2070 struct sdhci_pci_chip *chip)
2071 {
2072 struct gpiod_lookup_table *cd_gpio_lookup_table;
2073 const struct dmi_system_id *dmi_id = NULL;
2074 size_t count;
2075
2076 if (chip->fixes && chip->fixes->cd_gpio_override)
2077 dmi_id = dmi_first_match(chip->fixes->cd_gpio_override);
2078
2079 if (!dmi_id)
2080 return NULL;
2081
2082 cd_gpio_lookup_table = dmi_id->driver_data;
2083 for (count = 0; cd_gpio_lookup_table->table[count].key; count++)
2084 ;
2085
2086 cd_gpio_lookup_table = kmemdup(dmi_id->driver_data,
2087 /* count + 1 terminating entry */
2088 struct_size(cd_gpio_lookup_table, table, count + 1),
2089 GFP_KERNEL);
2090 if (!cd_gpio_lookup_table)
2091 return ERR_PTR(-ENOMEM);
2092
2093 gpiod_add_lookup_table(cd_gpio_lookup_table);
2094 return cd_gpio_lookup_table;
2095 }
2096
sdhci_pci_remove_gpio_lookup_table(struct gpiod_lookup_table * lookup_table)2097 static void sdhci_pci_remove_gpio_lookup_table(struct gpiod_lookup_table *lookup_table)
2098 {
2099 if (lookup_table) {
2100 gpiod_remove_lookup_table(lookup_table);
2101 kfree(lookup_table);
2102 }
2103 }
2104
sdhci_pci_probe_slot(struct pci_dev * pdev,struct sdhci_pci_chip * chip,int first_bar,int slotno)2105 static struct sdhci_pci_slot *sdhci_pci_probe_slot(
2106 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar,
2107 int slotno)
2108 {
2109 struct sdhci_pci_slot *slot;
2110 struct sdhci_host *host;
2111 int ret, bar = first_bar + slotno;
2112 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0;
2113
2114 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
2115 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar);
2116 return ERR_PTR(-ENODEV);
2117 }
2118
2119 if (pci_resource_len(pdev, bar) < 0x100) {
2120 dev_err(&pdev->dev, "Invalid iomem size. You may "
2121 "experience problems.\n");
2122 }
2123
2124 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) {
2125 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n");
2126 return ERR_PTR(-ENODEV);
2127 }
2128
2129 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) {
2130 dev_err(&pdev->dev, "Unknown interface. Aborting.\n");
2131 return ERR_PTR(-ENODEV);
2132 }
2133
2134 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size);
2135 if (IS_ERR(host)) {
2136 dev_err(&pdev->dev, "cannot allocate host\n");
2137 return ERR_CAST(host);
2138 }
2139
2140 slot = sdhci_priv(host);
2141
2142 slot->chip = chip;
2143 slot->host = host;
2144 slot->cd_idx = -1;
2145
2146 host->hw_name = "PCI";
2147 host->ops = chip->fixes && chip->fixes->ops ?
2148 chip->fixes->ops :
2149 &sdhci_pci_ops;
2150 host->quirks = chip->quirks;
2151 host->quirks2 = chip->quirks2;
2152
2153 host->irq = pdev->irq;
2154
2155 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc));
2156 if (ret) {
2157 dev_err(&pdev->dev, "cannot request region\n");
2158 goto cleanup;
2159 }
2160
2161 host->ioaddr = pcim_iomap_table(pdev)[bar];
2162
2163 if (chip->fixes && chip->fixes->probe_slot) {
2164 ret = chip->fixes->probe_slot(slot);
2165 if (ret)
2166 goto cleanup;
2167 }
2168
2169 host->mmc->pm_caps = MMC_PM_KEEP_POWER;
2170 host->mmc->slotno = slotno;
2171 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP;
2172
2173 if (device_can_wakeup(&pdev->dev))
2174 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
2175
2176 if (host->mmc->caps & MMC_CAP_CD_WAKE)
2177 device_init_wakeup(&pdev->dev, true);
2178
2179 if (slot->cd_idx >= 0) {
2180 struct gpiod_lookup_table *cd_gpio_lookup_table;
2181
2182 cd_gpio_lookup_table = sdhci_pci_add_gpio_lookup_table(chip);
2183 if (IS_ERR(cd_gpio_lookup_table)) {
2184 ret = PTR_ERR(cd_gpio_lookup_table);
2185 goto remove;
2186 }
2187
2188 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx,
2189 slot->cd_override_level, 0);
2190
2191 sdhci_pci_remove_gpio_lookup_table(cd_gpio_lookup_table);
2192
2193 if (ret && ret != -EPROBE_DEFER)
2194 ret = mmc_gpiod_request_cd(host->mmc, NULL,
2195 slot->cd_idx,
2196 slot->cd_override_level,
2197 0);
2198 if (ret == -EPROBE_DEFER)
2199 goto remove;
2200
2201 if (ret) {
2202 dev_warn(&pdev->dev, "failed to setup card detect gpio\n");
2203 slot->cd_idx = -1;
2204 }
2205 }
2206
2207 if (chip->fixes && chip->fixes->add_host)
2208 ret = chip->fixes->add_host(slot);
2209 else
2210 ret = sdhci_add_host(host);
2211 if (ret)
2212 goto remove;
2213
2214 /*
2215 * Check if the chip needs a separate GPIO for card detect to wake up
2216 * from runtime suspend. If it is not there, don't allow runtime PM.
2217 */
2218 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && slot->cd_idx < 0)
2219 chip->allow_runtime_pm = false;
2220
2221 return slot;
2222
2223 remove:
2224 if (chip->fixes && chip->fixes->remove_slot)
2225 chip->fixes->remove_slot(slot, 0);
2226
2227 cleanup:
2228 sdhci_free_host(host);
2229
2230 return ERR_PTR(ret);
2231 }
2232
sdhci_pci_remove_slot(struct sdhci_pci_slot * slot)2233 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot)
2234 {
2235 int dead;
2236 u32 scratch;
2237
2238 dead = 0;
2239 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS);
2240 if (scratch == (u32)-1)
2241 dead = 1;
2242
2243 sdhci_remove_host(slot->host, dead);
2244
2245 if (slot->chip->fixes && slot->chip->fixes->remove_slot)
2246 slot->chip->fixes->remove_slot(slot, dead);
2247
2248 sdhci_free_host(slot->host);
2249 }
2250
sdhci_pci_runtime_pm_allow(struct device * dev)2251 static void sdhci_pci_runtime_pm_allow(struct device *dev)
2252 {
2253 pm_suspend_ignore_children(dev, 1);
2254 pm_runtime_set_autosuspend_delay(dev, 50);
2255 pm_runtime_use_autosuspend(dev);
2256 pm_runtime_allow(dev);
2257 /* Stay active until mmc core scans for a card */
2258 pm_runtime_put_noidle(dev);
2259 }
2260
sdhci_pci_runtime_pm_forbid(struct device * dev)2261 static void sdhci_pci_runtime_pm_forbid(struct device *dev)
2262 {
2263 pm_runtime_forbid(dev);
2264 pm_runtime_get_noresume(dev);
2265 }
2266
sdhci_pci_probe(struct pci_dev * pdev,const struct pci_device_id * ent)2267 static int sdhci_pci_probe(struct pci_dev *pdev,
2268 const struct pci_device_id *ent)
2269 {
2270 struct sdhci_pci_chip *chip;
2271 struct sdhci_pci_slot *slot;
2272
2273 u8 slots, first_bar;
2274 int ret, i;
2275
2276 BUG_ON(pdev == NULL);
2277 BUG_ON(ent == NULL);
2278
2279 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n",
2280 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision);
2281
2282 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
2283 if (ret)
2284 return pcibios_err_to_errno(ret);
2285
2286 slots = PCI_SLOT_INFO_SLOTS(slots) + 1;
2287 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots);
2288
2289 BUG_ON(slots > MAX_SLOTS);
2290
2291 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar);
2292 if (ret)
2293 return pcibios_err_to_errno(ret);
2294
2295 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK;
2296
2297 if (first_bar > 5) {
2298 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n");
2299 return -ENODEV;
2300 }
2301
2302 ret = pcim_enable_device(pdev);
2303 if (ret)
2304 return ret;
2305
2306 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
2307 if (!chip)
2308 return -ENOMEM;
2309
2310 chip->pdev = pdev;
2311 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
2312 if (chip->fixes) {
2313 chip->quirks = chip->fixes->quirks;
2314 chip->quirks2 = chip->fixes->quirks2;
2315 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm;
2316 }
2317 chip->num_slots = slots;
2318 chip->pm_retune = true;
2319 chip->rpm_retune = true;
2320
2321 pci_set_drvdata(pdev, chip);
2322
2323 if (chip->fixes && chip->fixes->probe) {
2324 ret = chip->fixes->probe(chip);
2325 if (ret)
2326 return ret;
2327 }
2328
2329 slots = chip->num_slots; /* Quirk may have changed this */
2330
2331 for (i = 0; i < slots; i++) {
2332 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i);
2333 if (IS_ERR(slot)) {
2334 for (i--; i >= 0; i--)
2335 sdhci_pci_remove_slot(chip->slots[i]);
2336 return PTR_ERR(slot);
2337 }
2338
2339 chip->slots[i] = slot;
2340 }
2341
2342 if (chip->allow_runtime_pm)
2343 sdhci_pci_runtime_pm_allow(&pdev->dev);
2344
2345 return 0;
2346 }
2347
sdhci_pci_remove(struct pci_dev * pdev)2348 static void sdhci_pci_remove(struct pci_dev *pdev)
2349 {
2350 int i;
2351 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev);
2352
2353 if (chip->allow_runtime_pm)
2354 sdhci_pci_runtime_pm_forbid(&pdev->dev);
2355
2356 for (i = 0; i < chip->num_slots; i++)
2357 sdhci_pci_remove_slot(chip->slots[i]);
2358 }
2359
2360 static struct pci_driver sdhci_driver = {
2361 .name = "sdhci-pci",
2362 .id_table = pci_ids,
2363 .probe = sdhci_pci_probe,
2364 .remove = sdhci_pci_remove,
2365 .driver = {
2366 .pm = &sdhci_pci_pm_ops,
2367 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
2368 },
2369 };
2370
2371 module_pci_driver(sdhci_driver);
2372
2373 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
2374 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver");
2375 MODULE_LICENSE("GPL");
2376