1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MediaTek SD/MMC Card Interface driver 4 * 5 * Copyright (C) 2018 MediaTek Inc. 6 * Author: Weijie Gao <weijie.gao@mediatek.com> 7 */ 8 9 #include <clk.h> 10 #include <common.h> 11 #include <dm.h> 12 #include <mmc.h> 13 #include <errno.h> 14 #include <malloc.h> 15 #include <stdbool.h> 16 #include <asm/gpio.h> 17 #include <dm/pinctrl.h> 18 #include <linux/bitops.h> 19 #include <linux/io.h> 20 #include <linux/iopoll.h> 21 22 /* MSDC_CFG */ 23 #define MSDC_CFG_HS400_CK_MODE_EXT BIT(22) 24 #define MSDC_CFG_CKMOD_EXT_M 0x300000 25 #define MSDC_CFG_CKMOD_EXT_S 20 26 #define MSDC_CFG_CKDIV_EXT_M 0xfff00 27 #define MSDC_CFG_CKDIV_EXT_S 8 28 #define MSDC_CFG_HS400_CK_MODE BIT(18) 29 #define MSDC_CFG_CKMOD_M 0x30000 30 #define MSDC_CFG_CKMOD_S 16 31 #define MSDC_CFG_CKDIV_M 0xff00 32 #define MSDC_CFG_CKDIV_S 8 33 #define MSDC_CFG_CKSTB BIT(7) 34 #define MSDC_CFG_PIO BIT(3) 35 #define MSDC_CFG_RST BIT(2) 36 #define MSDC_CFG_CKPDN BIT(1) 37 #define MSDC_CFG_MODE BIT(0) 38 39 /* MSDC_IOCON */ 40 #define MSDC_IOCON_W_DSPL BIT(8) 41 #define MSDC_IOCON_DSPL BIT(2) 42 #define MSDC_IOCON_RSPL BIT(1) 43 44 /* MSDC_PS */ 45 #define MSDC_PS_DAT0 BIT(16) 46 #define MSDC_PS_CDDBCE_M 0xf000 47 #define MSDC_PS_CDDBCE_S 12 48 #define MSDC_PS_CDSTS BIT(1) 49 #define MSDC_PS_CDEN BIT(0) 50 51 /* #define MSDC_INT(EN) */ 52 #define MSDC_INT_ACMDRDY BIT(3) 53 #define MSDC_INT_ACMDTMO BIT(4) 54 #define MSDC_INT_ACMDCRCERR BIT(5) 55 #define MSDC_INT_CMDRDY BIT(8) 56 #define MSDC_INT_CMDTMO BIT(9) 57 #define MSDC_INT_RSPCRCERR BIT(10) 58 #define MSDC_INT_XFER_COMPL BIT(12) 59 #define MSDC_INT_DATTMO BIT(14) 60 #define MSDC_INT_DATCRCERR BIT(15) 61 62 /* MSDC_FIFOCS */ 63 #define MSDC_FIFOCS_CLR BIT(31) 64 #define MSDC_FIFOCS_TXCNT_M 0xff0000 65 #define MSDC_FIFOCS_TXCNT_S 16 66 #define MSDC_FIFOCS_RXCNT_M 0xff 67 #define MSDC_FIFOCS_RXCNT_S 0 68 69 /* #define SDC_CFG */ 70 #define SDC_CFG_DTOC_M 0xff000000 71 #define SDC_CFG_DTOC_S 24 72 #define SDC_CFG_SDIOIDE BIT(20) 73 #define SDC_CFG_SDIO BIT(19) 74 #define SDC_CFG_BUSWIDTH_M 0x30000 75 #define SDC_CFG_BUSWIDTH_S 16 76 77 /* SDC_CMD */ 78 #define SDC_CMD_BLK_LEN_M 0xfff0000 79 #define SDC_CMD_BLK_LEN_S 16 80 #define SDC_CMD_STOP BIT(14) 81 #define SDC_CMD_WR BIT(13) 82 #define SDC_CMD_DTYPE_M 0x1800 83 #define SDC_CMD_DTYPE_S 11 84 #define SDC_CMD_RSPTYP_M 0x380 85 #define SDC_CMD_RSPTYP_S 7 86 #define SDC_CMD_CMD_M 0x3f 87 #define SDC_CMD_CMD_S 0 88 89 /* SDC_STS */ 90 #define SDC_STS_CMDBUSY BIT(1) 91 #define SDC_STS_SDCBUSY BIT(0) 92 93 /* SDC_ADV_CFG0 */ 94 #define SDC_RX_ENHANCE_EN BIT(20) 95 96 /* PATCH_BIT0 */ 97 #define MSDC_INT_DAT_LATCH_CK_SEL_M 0x380 98 #define MSDC_INT_DAT_LATCH_CK_SEL_S 7 99 100 /* PATCH_BIT1 */ 101 #define MSDC_PB1_STOP_DLY_M 0xf00 102 #define MSDC_PB1_STOP_DLY_S 8 103 104 /* PATCH_BIT2 */ 105 #define MSDC_PB2_CRCSTSENSEL_M 0xe0000000 106 #define MSDC_PB2_CRCSTSENSEL_S 29 107 #define MSDC_PB2_CFGCRCSTS BIT(28) 108 #define MSDC_PB2_RESPSTSENSEL_M 0x70000 109 #define MSDC_PB2_RESPSTSENSEL_S 16 110 #define MSDC_PB2_CFGRESP BIT(15) 111 #define MSDC_PB2_RESPWAIT_M 0x0c 112 #define MSDC_PB2_RESPWAIT_S 2 113 114 /* PAD_TUNE */ 115 #define MSDC_PAD_TUNE_CMDRRDLY_M 0x7c00000 116 #define MSDC_PAD_TUNE_CMDRRDLY_S 22 117 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) 118 #define MSDC_PAD_TUNE_CMDRDLY_M 0x1f0000 119 #define MSDC_PAD_TUNE_CMDRDLY_S 16 120 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) 121 #define MSDC_PAD_TUNE_RD_SEL BIT(13) 122 #define MSDC_PAD_TUNE_DATRRDLY_M 0x1f00 123 #define MSDC_PAD_TUNE_DATRRDLY_S 8 124 #define MSDC_PAD_TUNE_DATWRDLY_M 0x1f 125 #define MSDC_PAD_TUNE_DATWRDLY_S 0 126 127 /* EMMC50_CFG0 */ 128 #define EMMC50_CFG_CFCSTS_SEL BIT(4) 129 130 /* SDC_FIFO_CFG */ 131 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) 132 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) 133 134 /* SDC_CFG_BUSWIDTH */ 135 #define MSDC_BUS_1BITS 0x0 136 #define MSDC_BUS_4BITS 0x1 137 #define MSDC_BUS_8BITS 0x2 138 139 #define MSDC_FIFO_SIZE 128 140 141 #define PAD_DELAY_MAX 32 142 143 #define DEFAULT_CD_DEBOUNCE 8 144 145 #define CMD_INTS_MASK \ 146 (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) 147 148 #define DATA_INTS_MASK \ 149 (MSDC_INT_XFER_COMPL | MSDC_INT_DATTMO | MSDC_INT_DATCRCERR) 150 151 /* Register offset */ 152 struct mtk_sd_regs { 153 u32 msdc_cfg; 154 u32 msdc_iocon; 155 u32 msdc_ps; 156 u32 msdc_int; 157 u32 msdc_inten; 158 u32 msdc_fifocs; 159 u32 msdc_txdata; 160 u32 msdc_rxdata; 161 u32 reserved0[4]; 162 u32 sdc_cfg; 163 u32 sdc_cmd; 164 u32 sdc_arg; 165 u32 sdc_sts; 166 u32 sdc_resp[4]; 167 u32 sdc_blk_num; 168 u32 sdc_vol_chg; 169 u32 sdc_csts; 170 u32 sdc_csts_en; 171 u32 sdc_datcrc_sts; 172 u32 sdc_adv_cfg0; 173 u32 reserved1[2]; 174 u32 emmc_cfg0; 175 u32 emmc_cfg1; 176 u32 emmc_sts; 177 u32 emmc_iocon; 178 u32 sd_acmd_resp; 179 u32 sd_acmd19_trg; 180 u32 sd_acmd19_sts; 181 u32 dma_sa_high4bit; 182 u32 dma_sa; 183 u32 dma_ca; 184 u32 dma_ctrl; 185 u32 dma_cfg; 186 u32 sw_dbg_sel; 187 u32 sw_dbg_out; 188 u32 dma_length; 189 u32 reserved2; 190 u32 patch_bit0; 191 u32 patch_bit1; 192 u32 patch_bit2; 193 u32 reserved3; 194 u32 dat0_tune_crc; 195 u32 dat1_tune_crc; 196 u32 dat2_tune_crc; 197 u32 dat3_tune_crc; 198 u32 cmd_tune_crc; 199 u32 sdio_tune_wind; 200 u32 reserved4[5]; 201 u32 pad_tune; 202 u32 pad_tune0; 203 u32 pad_tune1; 204 u32 dat_rd_dly[4]; 205 u32 reserved5[2]; 206 u32 hw_dbg_sel; 207 u32 main_ver; 208 u32 eco_ver; 209 u32 reserved6[27]; 210 u32 pad_ds_tune; 211 u32 reserved7[31]; 212 u32 emmc50_cfg0; 213 u32 reserved8[7]; 214 u32 sdc_fifo_cfg; 215 }; 216 217 struct msdc_compatible { 218 u8 clk_div_bits; 219 bool pad_tune0; 220 bool async_fifo; 221 bool data_tune; 222 bool busy_check; 223 bool stop_clk_fix; 224 bool enhance_rx; 225 }; 226 227 struct msdc_delay_phase { 228 u8 maxlen; 229 u8 start; 230 u8 final_phase; 231 }; 232 233 struct msdc_plat { 234 struct mmc_config cfg; 235 struct mmc mmc; 236 }; 237 238 struct msdc_tune_para { 239 u32 iocon; 240 u32 pad_tune; 241 }; 242 243 struct msdc_host { 244 struct mtk_sd_regs *base; 245 struct mmc *mmc; 246 247 struct msdc_compatible *dev_comp; 248 249 struct clk src_clk; /* for SD/MMC bus clock */ 250 struct clk h_clk; /* MSDC core clock */ 251 252 u32 src_clk_freq; /* source clock */ 253 u32 mclk; /* mmc framework required bus clock */ 254 u32 sclk; /* actual calculated bus clock */ 255 256 /* operation timeout clocks */ 257 u32 timeout_ns; 258 u32 timeout_clks; 259 260 /* tuning options */ 261 u32 hs400_ds_delay; 262 u32 hs200_cmd_int_delay; 263 u32 hs200_write_int_delay; 264 u32 latch_ck; 265 u32 r_smpl; /* sample edge */ 266 bool hs400_mode; 267 268 /* whether to use gpio detection or built-in hw detection */ 269 bool builtin_cd; 270 271 /* card detection / write protection GPIOs */ 272 #if IS_ENABLED(DM_GPIO) 273 struct gpio_desc gpio_wp; 274 struct gpio_desc gpio_cd; 275 #endif 276 277 uint last_resp_type; 278 uint last_data_write; 279 280 enum bus_mode timing; 281 282 struct msdc_tune_para def_tune_para; 283 struct msdc_tune_para saved_tune_para; 284 }; 285 msdc_reset_hw(struct msdc_host * host)286 static void msdc_reset_hw(struct msdc_host *host) 287 { 288 u32 reg; 289 290 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_RST); 291 292 readl_poll_timeout(&host->base->msdc_cfg, reg, 293 !(reg & MSDC_CFG_RST), 1000000); 294 } 295 msdc_fifo_clr(struct msdc_host * host)296 static void msdc_fifo_clr(struct msdc_host *host) 297 { 298 u32 reg; 299 300 setbits_le32(&host->base->msdc_fifocs, MSDC_FIFOCS_CLR); 301 302 readl_poll_timeout(&host->base->msdc_fifocs, reg, 303 !(reg & MSDC_FIFOCS_CLR), 1000000); 304 } 305 msdc_fifo_rx_bytes(struct msdc_host * host)306 static u32 msdc_fifo_rx_bytes(struct msdc_host *host) 307 { 308 return (readl(&host->base->msdc_fifocs) & 309 MSDC_FIFOCS_RXCNT_M) >> MSDC_FIFOCS_RXCNT_S; 310 } 311 msdc_fifo_tx_bytes(struct msdc_host * host)312 static u32 msdc_fifo_tx_bytes(struct msdc_host *host) 313 { 314 return (readl(&host->base->msdc_fifocs) & 315 MSDC_FIFOCS_TXCNT_M) >> MSDC_FIFOCS_TXCNT_S; 316 } 317 msdc_cmd_find_resp(struct msdc_host * host,struct mmc_cmd * cmd)318 static u32 msdc_cmd_find_resp(struct msdc_host *host, struct mmc_cmd *cmd) 319 { 320 u32 resp; 321 322 switch (cmd->resp_type) { 323 /* Actually, R1, R5, R6, R7 are the same */ 324 case MMC_RSP_R1: 325 resp = 0x1; 326 break; 327 case MMC_RSP_R1b: 328 resp = 0x7; 329 break; 330 case MMC_RSP_R2: 331 resp = 0x2; 332 break; 333 case MMC_RSP_R3: 334 resp = 0x3; 335 break; 336 case MMC_RSP_NONE: 337 default: 338 resp = 0x0; 339 break; 340 } 341 342 return resp; 343 } 344 msdc_cmd_prepare_raw_cmd(struct msdc_host * host,struct mmc_cmd * cmd,struct mmc_data * data)345 static u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 346 struct mmc_cmd *cmd, 347 struct mmc_data *data) 348 { 349 u32 opcode = cmd->cmdidx; 350 u32 resp_type = msdc_cmd_find_resp(host, cmd); 351 uint blocksize = 0; 352 u32 dtype = 0; 353 u32 rawcmd = 0; 354 355 switch (opcode) { 356 case MMC_CMD_WRITE_MULTIPLE_BLOCK: 357 case MMC_CMD_READ_MULTIPLE_BLOCK: 358 dtype = 2; 359 break; 360 case MMC_CMD_WRITE_SINGLE_BLOCK: 361 case MMC_CMD_READ_SINGLE_BLOCK: 362 case SD_CMD_APP_SEND_SCR: 363 dtype = 1; 364 break; 365 case SD_CMD_SWITCH_FUNC: /* same as MMC_CMD_SWITCH */ 366 case SD_CMD_SEND_IF_COND: /* same as MMC_CMD_SEND_EXT_CSD */ 367 case SD_CMD_APP_SD_STATUS: /* same as MMC_CMD_SEND_STATUS */ 368 if (data) 369 dtype = 1; 370 } 371 372 if (data) { 373 if (data->flags == MMC_DATA_WRITE) 374 rawcmd |= SDC_CMD_WR; 375 376 if (data->blocks > 1) 377 dtype = 2; 378 379 blocksize = data->blocksize; 380 } 381 382 rawcmd |= ((opcode << SDC_CMD_CMD_S) & SDC_CMD_CMD_M) | 383 ((resp_type << SDC_CMD_RSPTYP_S) & SDC_CMD_RSPTYP_M) | 384 ((blocksize << SDC_CMD_BLK_LEN_S) & SDC_CMD_BLK_LEN_M) | 385 ((dtype << SDC_CMD_DTYPE_S) & SDC_CMD_DTYPE_M); 386 387 if (opcode == MMC_CMD_STOP_TRANSMISSION) 388 rawcmd |= SDC_CMD_STOP; 389 390 return rawcmd; 391 } 392 msdc_cmd_done(struct msdc_host * host,int events,struct mmc_cmd * cmd)393 static int msdc_cmd_done(struct msdc_host *host, int events, 394 struct mmc_cmd *cmd) 395 { 396 u32 *rsp = cmd->response; 397 int ret = 0; 398 399 if (cmd->resp_type & MMC_RSP_PRESENT) { 400 if (cmd->resp_type & MMC_RSP_136) { 401 rsp[0] = readl(&host->base->sdc_resp[3]); 402 rsp[1] = readl(&host->base->sdc_resp[2]); 403 rsp[2] = readl(&host->base->sdc_resp[1]); 404 rsp[3] = readl(&host->base->sdc_resp[0]); 405 } else { 406 rsp[0] = readl(&host->base->sdc_resp[0]); 407 } 408 } 409 410 if (!(events & MSDC_INT_CMDRDY)) { 411 if (cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK && 412 cmd->cmdidx != MMC_CMD_SEND_TUNING_BLOCK_HS200) 413 /* 414 * should not clear fifo/interrupt as the tune data 415 * may have alreay come. 416 */ 417 msdc_reset_hw(host); 418 419 if (events & MSDC_INT_CMDTMO) 420 ret = -ETIMEDOUT; 421 else 422 ret = -EIO; 423 } 424 425 return ret; 426 } 427 msdc_cmd_is_ready(struct msdc_host * host)428 static bool msdc_cmd_is_ready(struct msdc_host *host) 429 { 430 int ret; 431 u32 reg; 432 433 /* The max busy time we can endure is 20ms */ 434 ret = readl_poll_timeout(&host->base->sdc_sts, reg, 435 !(reg & SDC_STS_CMDBUSY), 20000); 436 437 if (ret) { 438 pr_err("CMD bus busy detected\n"); 439 msdc_reset_hw(host); 440 return false; 441 } 442 443 if (host->last_resp_type == MMC_RSP_R1b && host->last_data_write) { 444 ret = readl_poll_timeout(&host->base->msdc_ps, reg, 445 reg & MSDC_PS_DAT0, 1000000); 446 447 if (ret) { 448 pr_err("Card stuck in programming state!\n"); 449 msdc_reset_hw(host); 450 return false; 451 } 452 } 453 454 return true; 455 } 456 msdc_start_command(struct msdc_host * host,struct mmc_cmd * cmd,struct mmc_data * data)457 static int msdc_start_command(struct msdc_host *host, struct mmc_cmd *cmd, 458 struct mmc_data *data) 459 { 460 u32 rawcmd; 461 u32 status; 462 u32 blocks = 0; 463 int ret; 464 465 if (!msdc_cmd_is_ready(host)) 466 return -EIO; 467 468 msdc_fifo_clr(host); 469 470 host->last_resp_type = cmd->resp_type; 471 host->last_data_write = 0; 472 473 rawcmd = msdc_cmd_prepare_raw_cmd(host, cmd, data); 474 475 if (data) 476 blocks = data->blocks; 477 478 writel(CMD_INTS_MASK, &host->base->msdc_int); 479 writel(blocks, &host->base->sdc_blk_num); 480 writel(cmd->cmdarg, &host->base->sdc_arg); 481 writel(rawcmd, &host->base->sdc_cmd); 482 483 ret = readl_poll_timeout(&host->base->msdc_int, status, 484 status & CMD_INTS_MASK, 1000000); 485 486 if (ret) 487 status = MSDC_INT_CMDTMO; 488 489 return msdc_cmd_done(host, status, cmd); 490 } 491 msdc_fifo_read(struct msdc_host * host,u8 * buf,u32 size)492 static void msdc_fifo_read(struct msdc_host *host, u8 *buf, u32 size) 493 { 494 u32 *wbuf; 495 496 while ((size_t)buf % 4) { 497 *buf++ = readb(&host->base->msdc_rxdata); 498 size--; 499 } 500 501 wbuf = (u32 *)buf; 502 while (size >= 4) { 503 *wbuf++ = readl(&host->base->msdc_rxdata); 504 size -= 4; 505 } 506 507 buf = (u8 *)wbuf; 508 while (size) { 509 *buf++ = readb(&host->base->msdc_rxdata); 510 size--; 511 } 512 } 513 msdc_fifo_write(struct msdc_host * host,const u8 * buf,u32 size)514 static void msdc_fifo_write(struct msdc_host *host, const u8 *buf, u32 size) 515 { 516 const u32 *wbuf; 517 518 while ((size_t)buf % 4) { 519 writeb(*buf++, &host->base->msdc_txdata); 520 size--; 521 } 522 523 wbuf = (const u32 *)buf; 524 while (size >= 4) { 525 writel(*wbuf++, &host->base->msdc_txdata); 526 size -= 4; 527 } 528 529 buf = (const u8 *)wbuf; 530 while (size) { 531 writeb(*buf++, &host->base->msdc_txdata); 532 size--; 533 } 534 } 535 msdc_pio_read(struct msdc_host * host,u8 * ptr,u32 size)536 static int msdc_pio_read(struct msdc_host *host, u8 *ptr, u32 size) 537 { 538 u32 status; 539 u32 chksz; 540 int ret = 0; 541 542 while (1) { 543 status = readl(&host->base->msdc_int); 544 writel(status, &host->base->msdc_int); 545 status &= DATA_INTS_MASK; 546 547 if (status & MSDC_INT_DATCRCERR) { 548 ret = -EIO; 549 break; 550 } 551 552 if (status & MSDC_INT_DATTMO) { 553 ret = -ETIMEDOUT; 554 break; 555 } 556 557 chksz = min(size, (u32)MSDC_FIFO_SIZE); 558 559 if (msdc_fifo_rx_bytes(host) >= chksz) { 560 msdc_fifo_read(host, ptr, chksz); 561 ptr += chksz; 562 size -= chksz; 563 } 564 565 if (status & MSDC_INT_XFER_COMPL) { 566 if (size) { 567 pr_err("data not fully read\n"); 568 ret = -EIO; 569 } 570 571 break; 572 } 573 } 574 575 return ret; 576 } 577 msdc_pio_write(struct msdc_host * host,const u8 * ptr,u32 size)578 static int msdc_pio_write(struct msdc_host *host, const u8 *ptr, u32 size) 579 { 580 u32 status; 581 u32 chksz; 582 int ret = 0; 583 584 while (1) { 585 status = readl(&host->base->msdc_int); 586 writel(status, &host->base->msdc_int); 587 status &= DATA_INTS_MASK; 588 589 if (status & MSDC_INT_DATCRCERR) { 590 ret = -EIO; 591 break; 592 } 593 594 if (status & MSDC_INT_DATTMO) { 595 ret = -ETIMEDOUT; 596 break; 597 } 598 599 if (status & MSDC_INT_XFER_COMPL) { 600 if (size) { 601 pr_err("data not fully written\n"); 602 ret = -EIO; 603 } 604 605 break; 606 } 607 608 chksz = min(size, (u32)MSDC_FIFO_SIZE); 609 610 if (MSDC_FIFO_SIZE - msdc_fifo_tx_bytes(host) >= chksz) { 611 msdc_fifo_write(host, ptr, chksz); 612 ptr += chksz; 613 size -= chksz; 614 } 615 } 616 617 return ret; 618 } 619 msdc_start_data(struct msdc_host * host,struct mmc_data * data)620 static int msdc_start_data(struct msdc_host *host, struct mmc_data *data) 621 { 622 u32 size; 623 int ret; 624 625 if (data->flags == MMC_DATA_WRITE) 626 host->last_data_write = 1; 627 628 writel(DATA_INTS_MASK, &host->base->msdc_int); 629 630 size = data->blocks * data->blocksize; 631 632 if (data->flags == MMC_DATA_WRITE) 633 ret = msdc_pio_write(host, (const u8 *)data->src, size); 634 else 635 ret = msdc_pio_read(host, (u8 *)data->dest, size); 636 637 if (ret) { 638 msdc_reset_hw(host); 639 msdc_fifo_clr(host); 640 } 641 642 return ret; 643 } 644 msdc_ops_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)645 static int msdc_ops_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, 646 struct mmc_data *data) 647 { 648 struct msdc_host *host = dev_get_priv(dev); 649 int ret; 650 651 ret = msdc_start_command(host, cmd, data); 652 if (ret) 653 return ret; 654 655 if (data) 656 return msdc_start_data(host, data); 657 658 return 0; 659 } 660 msdc_set_timeout(struct msdc_host * host,u32 ns,u32 clks)661 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 662 { 663 u32 timeout, clk_ns; 664 u32 mode = 0; 665 666 host->timeout_ns = ns; 667 host->timeout_clks = clks; 668 669 if (host->sclk == 0) { 670 timeout = 0; 671 } else { 672 clk_ns = 1000000000UL / host->sclk; 673 timeout = (ns + clk_ns - 1) / clk_ns + clks; 674 /* unit is 1048576 sclk cycles */ 675 timeout = (timeout + (0x1 << 20) - 1) >> 20; 676 if (host->dev_comp->clk_div_bits == 8) 677 mode = (readl(&host->base->msdc_cfg) & 678 MSDC_CFG_CKMOD_M) >> MSDC_CFG_CKMOD_S; 679 else 680 mode = (readl(&host->base->msdc_cfg) & 681 MSDC_CFG_CKMOD_EXT_M) >> MSDC_CFG_CKMOD_EXT_S; 682 /* DDR mode will double the clk cycles for data timeout */ 683 timeout = mode >= 2 ? timeout * 2 : timeout; 684 timeout = timeout > 1 ? timeout - 1 : 0; 685 timeout = timeout > 255 ? 255 : timeout; 686 } 687 688 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, 689 timeout << SDC_CFG_DTOC_S); 690 } 691 msdc_set_buswidth(struct msdc_host * host,u32 width)692 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 693 { 694 u32 val = readl(&host->base->sdc_cfg); 695 696 val &= ~SDC_CFG_BUSWIDTH_M; 697 698 switch (width) { 699 default: 700 case 1: 701 val |= (MSDC_BUS_1BITS << SDC_CFG_BUSWIDTH_S); 702 break; 703 case 4: 704 val |= (MSDC_BUS_4BITS << SDC_CFG_BUSWIDTH_S); 705 break; 706 case 8: 707 val |= (MSDC_BUS_8BITS << SDC_CFG_BUSWIDTH_S); 708 break; 709 } 710 711 writel(val, &host->base->sdc_cfg); 712 } 713 msdc_set_mclk(struct msdc_host * host,enum bus_mode timing,u32 hz)714 static void msdc_set_mclk(struct msdc_host *host, enum bus_mode timing, u32 hz) 715 { 716 u32 mode; 717 u32 div; 718 u32 sclk; 719 u32 reg; 720 721 if (!hz) { 722 host->mclk = 0; 723 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); 724 return; 725 } 726 727 if (host->dev_comp->clk_div_bits == 8) 728 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_HS400_CK_MODE); 729 else 730 clrbits_le32(&host->base->msdc_cfg, 731 MSDC_CFG_HS400_CK_MODE_EXT); 732 733 if (timing == UHS_DDR50 || timing == MMC_DDR_52 || 734 timing == MMC_HS_400) { 735 if (timing == MMC_HS_400) 736 mode = 0x3; 737 else 738 mode = 0x2; /* ddr mode and use divisor */ 739 740 if (hz >= (host->src_clk_freq >> 2)) { 741 div = 0; /* mean div = 1/4 */ 742 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 743 } else { 744 div = (host->src_clk_freq + ((hz << 2) - 1)) / 745 (hz << 2); 746 sclk = (host->src_clk_freq >> 2) / div; 747 div = (div >> 1); 748 } 749 750 if (timing == MMC_HS_400 && hz >= (host->src_clk_freq >> 1)) { 751 if (host->dev_comp->clk_div_bits == 8) 752 setbits_le32(&host->base->msdc_cfg, 753 MSDC_CFG_HS400_CK_MODE); 754 else 755 setbits_le32(&host->base->msdc_cfg, 756 MSDC_CFG_HS400_CK_MODE_EXT); 757 758 sclk = host->src_clk_freq >> 1; 759 div = 0; /* div is ignore when bit18 is set */ 760 } 761 } else if (hz >= host->src_clk_freq) { 762 mode = 0x1; /* no divisor */ 763 div = 0; 764 sclk = host->src_clk_freq; 765 } else { 766 mode = 0x0; /* use divisor */ 767 if (hz >= (host->src_clk_freq >> 1)) { 768 div = 0; /* mean div = 1/2 */ 769 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 770 } else { 771 div = (host->src_clk_freq + ((hz << 2) - 1)) / 772 (hz << 2); 773 sclk = (host->src_clk_freq >> 2) / div; 774 } 775 } 776 777 clrbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); 778 779 if (host->dev_comp->clk_div_bits == 8) { 780 div = min(div, (u32)(MSDC_CFG_CKDIV_M >> MSDC_CFG_CKDIV_S)); 781 clrsetbits_le32(&host->base->msdc_cfg, 782 MSDC_CFG_CKMOD_M | MSDC_CFG_CKDIV_M, 783 (mode << MSDC_CFG_CKMOD_S) | 784 (div << MSDC_CFG_CKDIV_S)); 785 } else { 786 div = min(div, (u32)(MSDC_CFG_CKDIV_EXT_M >> 787 MSDC_CFG_CKDIV_EXT_S)); 788 clrsetbits_le32(&host->base->msdc_cfg, 789 MSDC_CFG_CKMOD_EXT_M | MSDC_CFG_CKDIV_EXT_M, 790 (mode << MSDC_CFG_CKMOD_EXT_S) | 791 (div << MSDC_CFG_CKDIV_EXT_S)); 792 } 793 794 readl_poll_timeout(&host->base->msdc_cfg, reg, 795 reg & MSDC_CFG_CKSTB, 1000000); 796 797 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_CKPDN); 798 host->sclk = sclk; 799 host->mclk = hz; 800 host->timing = timing; 801 802 /* needed because clk changed. */ 803 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 804 805 /* 806 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 807 * tune result of hs200/200Mhz is not suitable for 50Mhz 808 */ 809 if (host->sclk <= 52000000) { 810 writel(host->def_tune_para.iocon, &host->base->msdc_iocon); 811 writel(host->def_tune_para.pad_tune, 812 &host->base->pad_tune); 813 } else { 814 writel(host->saved_tune_para.iocon, &host->base->msdc_iocon); 815 writel(host->saved_tune_para.pad_tune, 816 &host->base->pad_tune); 817 } 818 819 dev_dbg(dev, "sclk: %d, timing: %d\n", host->sclk, timing); 820 } 821 msdc_ops_set_ios(struct udevice * dev)822 static int msdc_ops_set_ios(struct udevice *dev) 823 { 824 struct msdc_plat *plat = dev_get_platdata(dev); 825 struct msdc_host *host = dev_get_priv(dev); 826 struct mmc *mmc = &plat->mmc; 827 uint clock = mmc->clock; 828 829 msdc_set_buswidth(host, mmc->bus_width); 830 831 if (mmc->clk_disable) 832 clock = 0; 833 else if (clock < mmc->cfg->f_min) 834 clock = mmc->cfg->f_min; 835 836 if (host->mclk != clock || host->timing != mmc->selected_mode) 837 msdc_set_mclk(host, mmc->selected_mode, clock); 838 839 return 0; 840 } 841 msdc_ops_get_cd(struct udevice * dev)842 static int msdc_ops_get_cd(struct udevice *dev) 843 { 844 struct msdc_host *host = dev_get_priv(dev); 845 u32 val; 846 847 if (host->builtin_cd) { 848 val = readl(&host->base->msdc_ps); 849 return !(val & MSDC_PS_CDSTS); 850 } 851 852 #if IS_ENABLED(DM_GPIO) 853 if (!host->gpio_cd.dev) 854 return 1; 855 856 return dm_gpio_get_value(&host->gpio_cd); 857 #else 858 return 1; 859 #endif 860 } 861 msdc_ops_get_wp(struct udevice * dev)862 static int msdc_ops_get_wp(struct udevice *dev) 863 { 864 #if IS_ENABLED(DM_GPIO) 865 struct msdc_host *host = dev_get_priv(dev); 866 867 if (!host->gpio_wp.dev) 868 return 0; 869 870 return !dm_gpio_get_value(&host->gpio_wp); 871 #else 872 return 0; 873 #endif 874 } 875 876 #ifdef MMC_SUPPORTS_TUNING test_delay_bit(u32 delay,u32 bit)877 static u32 test_delay_bit(u32 delay, u32 bit) 878 { 879 bit %= PAD_DELAY_MAX; 880 return delay & (1 << bit); 881 } 882 get_delay_len(u32 delay,u32 start_bit)883 static int get_delay_len(u32 delay, u32 start_bit) 884 { 885 int i; 886 887 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 888 if (test_delay_bit(delay, start_bit + i) == 0) 889 return i; 890 } 891 892 return PAD_DELAY_MAX - start_bit; 893 } 894 get_best_delay(struct msdc_host * host,u32 delay)895 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 896 { 897 int start = 0, len = 0; 898 int start_final = 0, len_final = 0; 899 u8 final_phase = 0xff; 900 struct msdc_delay_phase delay_phase = { 0, }; 901 902 if (delay == 0) { 903 dev_err(dev, "phase error: [map:%x]\n", delay); 904 delay_phase.final_phase = final_phase; 905 return delay_phase; 906 } 907 908 while (start < PAD_DELAY_MAX) { 909 len = get_delay_len(delay, start); 910 if (len_final < len) { 911 start_final = start; 912 len_final = len; 913 } 914 915 start += len ? len : 1; 916 if (len >= 12 && start_final < 4) 917 break; 918 } 919 920 /* The rule is to find the smallest delay cell */ 921 if (start_final == 0) 922 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 923 else 924 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 925 926 dev_info(dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 927 delay, len_final, final_phase); 928 929 delay_phase.maxlen = len_final; 930 delay_phase.start = start_final; 931 delay_phase.final_phase = final_phase; 932 return delay_phase; 933 } 934 msdc_tune_response(struct udevice * dev,u32 opcode)935 static int msdc_tune_response(struct udevice *dev, u32 opcode) 936 { 937 struct msdc_plat *plat = dev_get_platdata(dev); 938 struct msdc_host *host = dev_get_priv(dev); 939 struct mmc *mmc = &plat->mmc; 940 u32 rise_delay = 0, fall_delay = 0; 941 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, }; 942 struct msdc_delay_phase internal_delay_phase; 943 u8 final_delay, final_maxlen; 944 u32 internal_delay = 0; 945 void __iomem *tune_reg = &host->base->pad_tune; 946 int cmd_err; 947 int i, j; 948 949 if (host->dev_comp->pad_tune0) 950 tune_reg = &host->base->pad_tune0; 951 952 if (mmc->selected_mode == MMC_HS_200 || 953 mmc->selected_mode == UHS_SDR104) 954 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, 955 host->hs200_cmd_int_delay << 956 MSDC_PAD_TUNE_CMDRRDLY_S); 957 958 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); 959 960 for (i = 0; i < PAD_DELAY_MAX; i++) { 961 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, 962 i << MSDC_PAD_TUNE_CMDRDLY_S); 963 964 for (j = 0; j < 3; j++) { 965 mmc_send_tuning(mmc, opcode, &cmd_err); 966 if (!cmd_err) { 967 rise_delay |= (1 << i); 968 } else { 969 rise_delay &= ~(1 << i); 970 break; 971 } 972 } 973 } 974 975 final_rise_delay = get_best_delay(host, rise_delay); 976 /* if rising edge has enough margin, do not scan falling edge */ 977 if (final_rise_delay.maxlen >= 12 || 978 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 979 goto skip_fall; 980 981 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); 982 for (i = 0; i < PAD_DELAY_MAX; i++) { 983 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, 984 i << MSDC_PAD_TUNE_CMDRDLY_S); 985 986 for (j = 0; j < 3; j++) { 987 mmc_send_tuning(mmc, opcode, &cmd_err); 988 if (!cmd_err) { 989 fall_delay |= (1 << i); 990 } else { 991 fall_delay &= ~(1 << i); 992 break; 993 } 994 } 995 } 996 997 final_fall_delay = get_best_delay(host, fall_delay); 998 999 skip_fall: 1000 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1001 if (final_maxlen == final_rise_delay.maxlen) { 1002 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); 1003 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, 1004 final_rise_delay.final_phase << 1005 MSDC_PAD_TUNE_CMDRDLY_S); 1006 final_delay = final_rise_delay.final_phase; 1007 } else { 1008 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); 1009 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRDLY_M, 1010 final_fall_delay.final_phase << 1011 MSDC_PAD_TUNE_CMDRDLY_S); 1012 final_delay = final_fall_delay.final_phase; 1013 } 1014 1015 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 1016 goto skip_internal; 1017 1018 for (i = 0; i < PAD_DELAY_MAX; i++) { 1019 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, 1020 i << MSDC_PAD_TUNE_CMDRRDLY_S); 1021 1022 mmc_send_tuning(mmc, opcode, &cmd_err); 1023 if (!cmd_err) 1024 internal_delay |= (1 << i); 1025 } 1026 1027 dev_err(dev, "Final internal delay: 0x%x\n", internal_delay); 1028 1029 internal_delay_phase = get_best_delay(host, internal_delay); 1030 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_CMDRRDLY_M, 1031 internal_delay_phase.final_phase << 1032 MSDC_PAD_TUNE_CMDRRDLY_S); 1033 1034 skip_internal: 1035 dev_err(dev, "Final cmd pad delay: %x\n", final_delay); 1036 return final_delay == 0xff ? -EIO : 0; 1037 } 1038 msdc_tune_data(struct udevice * dev,u32 opcode)1039 static int msdc_tune_data(struct udevice *dev, u32 opcode) 1040 { 1041 struct msdc_plat *plat = dev_get_platdata(dev); 1042 struct msdc_host *host = dev_get_priv(dev); 1043 struct mmc *mmc = &plat->mmc; 1044 u32 rise_delay = 0, fall_delay = 0; 1045 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0, }; 1046 u8 final_delay, final_maxlen; 1047 void __iomem *tune_reg = &host->base->pad_tune; 1048 int cmd_err; 1049 int i, ret; 1050 1051 if (host->dev_comp->pad_tune0) 1052 tune_reg = &host->base->pad_tune0; 1053 1054 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); 1055 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); 1056 1057 for (i = 0; i < PAD_DELAY_MAX; i++) { 1058 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, 1059 i << MSDC_PAD_TUNE_DATRRDLY_S); 1060 1061 ret = mmc_send_tuning(mmc, opcode, &cmd_err); 1062 if (!ret) { 1063 rise_delay |= (1 << i); 1064 } else if (cmd_err) { 1065 /* in this case, retune response is needed */ 1066 ret = msdc_tune_response(dev, opcode); 1067 if (ret) 1068 break; 1069 } 1070 } 1071 1072 final_rise_delay = get_best_delay(host, rise_delay); 1073 if (final_rise_delay.maxlen >= 12 || 1074 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1075 goto skip_fall; 1076 1077 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); 1078 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); 1079 1080 for (i = 0; i < PAD_DELAY_MAX; i++) { 1081 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, 1082 i << MSDC_PAD_TUNE_DATRRDLY_S); 1083 1084 ret = mmc_send_tuning(mmc, opcode, &cmd_err); 1085 if (!ret) { 1086 fall_delay |= (1 << i); 1087 } else if (cmd_err) { 1088 /* in this case, retune response is needed */ 1089 ret = msdc_tune_response(dev, opcode); 1090 if (ret) 1091 break; 1092 } 1093 } 1094 1095 final_fall_delay = get_best_delay(host, fall_delay); 1096 1097 skip_fall: 1098 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1099 if (final_maxlen == final_rise_delay.maxlen) { 1100 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); 1101 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); 1102 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, 1103 final_rise_delay.final_phase << 1104 MSDC_PAD_TUNE_DATRRDLY_S); 1105 final_delay = final_rise_delay.final_phase; 1106 } else { 1107 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_DSPL); 1108 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_W_DSPL); 1109 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATRRDLY_M, 1110 final_fall_delay.final_phase << 1111 MSDC_PAD_TUNE_DATRRDLY_S); 1112 final_delay = final_fall_delay.final_phase; 1113 } 1114 1115 if (mmc->selected_mode == MMC_HS_200 || 1116 mmc->selected_mode == UHS_SDR104) 1117 clrsetbits_le32(tune_reg, MSDC_PAD_TUNE_DATWRDLY_M, 1118 host->hs200_write_int_delay << 1119 MSDC_PAD_TUNE_DATWRDLY_S); 1120 1121 dev_err(dev, "Final data pad delay: %x\n", final_delay); 1122 1123 return final_delay == 0xff ? -EIO : 0; 1124 } 1125 msdc_execute_tuning(struct udevice * dev,uint opcode)1126 static int msdc_execute_tuning(struct udevice *dev, uint opcode) 1127 { 1128 struct msdc_plat *plat = dev_get_platdata(dev); 1129 struct msdc_host *host = dev_get_priv(dev); 1130 struct mmc *mmc = &plat->mmc; 1131 int ret; 1132 1133 if (mmc->selected_mode == MMC_HS_400) { 1134 writel(host->hs400_ds_delay, &host->base->pad_ds_tune); 1135 /* for hs400 mode it must be set to 0 */ 1136 clrbits_le32(&host->base->patch_bit2, MSDC_PB2_CFGCRCSTS); 1137 host->hs400_mode = true; 1138 } 1139 1140 ret = msdc_tune_response(dev, opcode); 1141 if (ret == -EIO) { 1142 dev_err(dev, "Tune response fail!\n"); 1143 return ret; 1144 } 1145 1146 if (!host->hs400_mode) { 1147 ret = msdc_tune_data(dev, opcode); 1148 if (ret == -EIO) 1149 dev_err(dev, "Tune data fail!\n"); 1150 } 1151 1152 host->saved_tune_para.iocon = readl(&host->base->msdc_iocon); 1153 host->saved_tune_para.pad_tune = readl(&host->base->pad_tune); 1154 1155 return ret; 1156 } 1157 #endif 1158 msdc_init_hw(struct msdc_host * host)1159 static void msdc_init_hw(struct msdc_host *host) 1160 { 1161 u32 val; 1162 void __iomem *tune_reg = &host->base->pad_tune; 1163 1164 if (host->dev_comp->pad_tune0) 1165 tune_reg = &host->base->pad_tune0; 1166 1167 /* Configure to MMC/SD mode, clock free running */ 1168 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_MODE); 1169 1170 /* Use PIO mode */ 1171 setbits_le32(&host->base->msdc_cfg, MSDC_CFG_PIO); 1172 1173 /* Reset */ 1174 msdc_reset_hw(host); 1175 1176 /* Enable/disable hw card detection according to fdt option */ 1177 if (host->builtin_cd) 1178 clrsetbits_le32(&host->base->msdc_ps, 1179 MSDC_PS_CDDBCE_M, 1180 (DEFAULT_CD_DEBOUNCE << MSDC_PS_CDDBCE_S) | 1181 MSDC_PS_CDEN); 1182 else 1183 clrbits_le32(&host->base->msdc_ps, MSDC_PS_CDEN); 1184 1185 /* Clear all interrupts */ 1186 val = readl(&host->base->msdc_int); 1187 writel(val, &host->base->msdc_int); 1188 1189 /* Enable data & cmd interrupts */ 1190 writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten); 1191 1192 writel(0, tune_reg); 1193 writel(0, &host->base->msdc_iocon); 1194 1195 if (host->r_smpl) 1196 setbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); 1197 else 1198 clrbits_le32(&host->base->msdc_iocon, MSDC_IOCON_RSPL); 1199 1200 writel(0x403c0046, &host->base->patch_bit0); 1201 writel(0xffff4089, &host->base->patch_bit1); 1202 1203 if (host->dev_comp->stop_clk_fix) 1204 clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M, 1205 3 << MSDC_PB1_STOP_DLY_S); 1206 1207 if (host->dev_comp->busy_check) 1208 clrbits_le32(&host->base->patch_bit1, (1 << 7)); 1209 1210 setbits_le32(&host->base->emmc50_cfg0, EMMC50_CFG_CFCSTS_SEL); 1211 1212 if (host->dev_comp->async_fifo) { 1213 clrsetbits_le32(&host->base->patch_bit2, MSDC_PB2_RESPWAIT_M, 1214 3 << MSDC_PB2_RESPWAIT_S); 1215 1216 if (host->dev_comp->enhance_rx) { 1217 setbits_le32(&host->base->sdc_adv_cfg0, 1218 SDC_RX_ENHANCE_EN); 1219 } else { 1220 clrsetbits_le32(&host->base->patch_bit2, 1221 MSDC_PB2_RESPSTSENSEL_M, 1222 2 << MSDC_PB2_RESPSTSENSEL_S); 1223 clrsetbits_le32(&host->base->patch_bit2, 1224 MSDC_PB2_CRCSTSENSEL_M, 1225 2 << MSDC_PB2_CRCSTSENSEL_S); 1226 } 1227 1228 /* use async fifo to avoid tune internal delay */ 1229 clrbits_le32(&host->base->patch_bit2, 1230 MSDC_PB2_CFGRESP); 1231 clrbits_le32(&host->base->patch_bit2, 1232 MSDC_PB2_CFGCRCSTS); 1233 } 1234 1235 if (host->dev_comp->data_tune) { 1236 setbits_le32(tune_reg, 1237 MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); 1238 clrsetbits_le32(&host->base->patch_bit0, 1239 MSDC_INT_DAT_LATCH_CK_SEL_M, 1240 host->latch_ck << 1241 MSDC_INT_DAT_LATCH_CK_SEL_S); 1242 } else { 1243 /* choose clock tune */ 1244 setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL); 1245 } 1246 1247 /* Configure to enable SDIO mode otherwise sdio cmd5 won't work */ 1248 setbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIO); 1249 1250 /* disable detecting SDIO device interrupt function */ 1251 clrbits_le32(&host->base->sdc_cfg, SDC_CFG_SDIOIDE); 1252 1253 /* Configure to default data timeout */ 1254 clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M, 1255 3 << SDC_CFG_DTOC_S); 1256 1257 if (host->dev_comp->stop_clk_fix) { 1258 clrbits_le32(&host->base->sdc_fifo_cfg, 1259 SDC_FIFO_CFG_WRVALIDSEL); 1260 clrbits_le32(&host->base->sdc_fifo_cfg, 1261 SDC_FIFO_CFG_RDVALIDSEL); 1262 } 1263 1264 host->def_tune_para.iocon = readl(&host->base->msdc_iocon); 1265 host->def_tune_para.pad_tune = readl(&host->base->pad_tune); 1266 } 1267 msdc_ungate_clock(struct msdc_host * host)1268 static void msdc_ungate_clock(struct msdc_host *host) 1269 { 1270 clk_enable(&host->src_clk); 1271 clk_enable(&host->h_clk); 1272 } 1273 msdc_drv_probe(struct udevice * dev)1274 static int msdc_drv_probe(struct udevice *dev) 1275 { 1276 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); 1277 struct msdc_plat *plat = dev_get_platdata(dev); 1278 struct msdc_host *host = dev_get_priv(dev); 1279 struct mmc_config *cfg = &plat->cfg; 1280 1281 cfg->name = dev->name; 1282 1283 host->dev_comp = (struct msdc_compatible *)dev_get_driver_data(dev); 1284 1285 host->src_clk_freq = clk_get_rate(&host->src_clk); 1286 1287 if (host->dev_comp->clk_div_bits == 8) 1288 cfg->f_min = host->src_clk_freq / (4 * 255); 1289 else 1290 cfg->f_min = host->src_clk_freq / (4 * 4095); 1291 cfg->f_max = host->src_clk_freq / 2; 1292 1293 cfg->b_max = 1024; 1294 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; 1295 1296 host->mmc = &plat->mmc; 1297 host->timeout_ns = 100000000; 1298 host->timeout_clks = 3 * 1048576; 1299 1300 #ifdef CONFIG_PINCTRL 1301 pinctrl_select_state(dev, "default"); 1302 #endif 1303 1304 msdc_ungate_clock(host); 1305 msdc_init_hw(host); 1306 1307 upriv->mmc = &plat->mmc; 1308 1309 return 0; 1310 } 1311 msdc_ofdata_to_platdata(struct udevice * dev)1312 static int msdc_ofdata_to_platdata(struct udevice *dev) 1313 { 1314 struct msdc_plat *plat = dev_get_platdata(dev); 1315 struct msdc_host *host = dev_get_priv(dev); 1316 struct mmc_config *cfg = &plat->cfg; 1317 int ret; 1318 1319 host->base = (void *)dev_read_addr(dev); 1320 if (!host->base) 1321 return -EINVAL; 1322 1323 ret = mmc_of_parse(dev, cfg); 1324 if (ret) 1325 return ret; 1326 1327 ret = clk_get_by_name(dev, "source", &host->src_clk); 1328 if (ret < 0) 1329 return ret; 1330 1331 ret = clk_get_by_name(dev, "hclk", &host->h_clk); 1332 if (ret < 0) 1333 return ret; 1334 1335 #if IS_ENABLED(DM_GPIO) 1336 gpio_request_by_name(dev, "wp-gpios", 0, &host->gpio_wp, GPIOD_IS_IN); 1337 gpio_request_by_name(dev, "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN); 1338 #endif 1339 1340 host->hs400_ds_delay = dev_read_u32_default(dev, "hs400-ds-delay", 0); 1341 host->hs200_cmd_int_delay = 1342 dev_read_u32_default(dev, "cmd_int_delay", 0); 1343 host->hs200_write_int_delay = 1344 dev_read_u32_default(dev, "write_int_delay", 0); 1345 host->latch_ck = dev_read_u32_default(dev, "latch-ck", 0); 1346 host->r_smpl = dev_read_u32_default(dev, "r_smpl", 0); 1347 host->builtin_cd = dev_read_u32_default(dev, "builtin-cd", 0); 1348 1349 return 0; 1350 } 1351 msdc_drv_bind(struct udevice * dev)1352 static int msdc_drv_bind(struct udevice *dev) 1353 { 1354 struct msdc_plat *plat = dev_get_platdata(dev); 1355 1356 return mmc_bind(dev, &plat->mmc, &plat->cfg); 1357 } 1358 1359 static const struct dm_mmc_ops msdc_ops = { 1360 .send_cmd = msdc_ops_send_cmd, 1361 .set_ios = msdc_ops_set_ios, 1362 .get_cd = msdc_ops_get_cd, 1363 .get_wp = msdc_ops_get_wp, 1364 #ifdef MMC_SUPPORTS_TUNING 1365 .execute_tuning = msdc_execute_tuning, 1366 #endif 1367 }; 1368 1369 static const struct msdc_compatible mt7623_compat = { 1370 .clk_div_bits = 12, 1371 .pad_tune0 = true, 1372 .async_fifo = true, 1373 .data_tune = true, 1374 .busy_check = false, 1375 .stop_clk_fix = false, 1376 .enhance_rx = false 1377 }; 1378 1379 static const struct udevice_id msdc_ids[] = { 1380 { .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat }, 1381 {} 1382 }; 1383 1384 U_BOOT_DRIVER(mtk_sd_drv) = { 1385 .name = "mtk_sd", 1386 .id = UCLASS_MMC, 1387 .of_match = msdc_ids, 1388 .ofdata_to_platdata = msdc_ofdata_to_platdata, 1389 .bind = msdc_drv_bind, 1390 .probe = msdc_drv_probe, 1391 .ops = &msdc_ops, 1392 .platdata_auto_alloc_size = sizeof(struct msdc_plat), 1393 .priv_auto_alloc_size = sizeof(struct msdc_host), 1394 }; 1395