1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Synopsys DesignWare I2C adapter driver (master only).
4 *
5 * Based on the TI DAVINCI I2C adapter driver.
6 *
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
10 */
11 #include <linux/delay.h>
12 #include <linux/err.h>
13 #include <linux/errno.h>
14 #include <linux/export.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/pinctrl/consumer.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/reset.h>
24
25 #include "i2c-designware-core.h"
26
27 #define AMD_TIMEOUT_MIN_US 25
28 #define AMD_TIMEOUT_MAX_US 250
29 #define AMD_MASTERCFG_MASK GENMASK(15, 0)
30
i2c_dw_configure_fifo_master(struct dw_i2c_dev * dev)31 static void i2c_dw_configure_fifo_master(struct dw_i2c_dev *dev)
32 {
33 /* Configure Tx/Rx FIFO threshold levels */
34 regmap_write(dev->map, DW_IC_TX_TL, dev->tx_fifo_depth / 2);
35 regmap_write(dev->map, DW_IC_RX_TL, 0);
36
37 /* Configure the I2C master */
38 regmap_write(dev->map, DW_IC_CON, dev->master_cfg);
39 }
40
i2c_dw_set_timings_master(struct dw_i2c_dev * dev)41 static int i2c_dw_set_timings_master(struct dw_i2c_dev *dev)
42 {
43 unsigned int comp_param1;
44 u32 sda_falling_time, scl_falling_time;
45 struct i2c_timings *t = &dev->timings;
46 const char *fp_str = "";
47 u32 ic_clk;
48 int ret;
49
50 ret = i2c_dw_acquire_lock(dev);
51 if (ret)
52 return ret;
53
54 ret = regmap_read(dev->map, DW_IC_COMP_PARAM_1, &comp_param1);
55 i2c_dw_release_lock(dev);
56 if (ret)
57 return ret;
58
59 /* Set standard and fast speed dividers for high/low periods */
60 sda_falling_time = t->sda_fall_ns ?: 300; /* ns */
61 scl_falling_time = t->scl_fall_ns ?: 300; /* ns */
62
63 /* Calculate SCL timing parameters for standard mode if not set */
64 if (!dev->ss_hcnt || !dev->ss_lcnt) {
65 ic_clk = i2c_dw_clk_rate(dev);
66 dev->ss_hcnt =
67 i2c_dw_scl_hcnt(ic_clk,
68 4000, /* tHD;STA = tHIGH = 4.0 us */
69 sda_falling_time,
70 0, /* 0: DW default, 1: Ideal */
71 0); /* No offset */
72 dev->ss_lcnt =
73 i2c_dw_scl_lcnt(ic_clk,
74 4700, /* tLOW = 4.7 us */
75 scl_falling_time,
76 0); /* No offset */
77 }
78 dev_dbg(dev->dev, "Standard Mode HCNT:LCNT = %d:%d\n",
79 dev->ss_hcnt, dev->ss_lcnt);
80
81 /*
82 * Set SCL timing parameters for fast mode or fast mode plus. Only
83 * difference is the timing parameter values since the registers are
84 * the same.
85 */
86 if (t->bus_freq_hz == I2C_MAX_FAST_MODE_PLUS_FREQ) {
87 /*
88 * Check are Fast Mode Plus parameters available. Calculate
89 * SCL timing parameters for Fast Mode Plus if not set.
90 */
91 if (dev->fp_hcnt && dev->fp_lcnt) {
92 dev->fs_hcnt = dev->fp_hcnt;
93 dev->fs_lcnt = dev->fp_lcnt;
94 } else {
95 ic_clk = i2c_dw_clk_rate(dev);
96 dev->fs_hcnt =
97 i2c_dw_scl_hcnt(ic_clk,
98 260, /* tHIGH = 260 ns */
99 sda_falling_time,
100 0, /* DW default */
101 0); /* No offset */
102 dev->fs_lcnt =
103 i2c_dw_scl_lcnt(ic_clk,
104 500, /* tLOW = 500 ns */
105 scl_falling_time,
106 0); /* No offset */
107 }
108 fp_str = " Plus";
109 }
110 /*
111 * Calculate SCL timing parameters for fast mode if not set. They are
112 * needed also in high speed mode.
113 */
114 if (!dev->fs_hcnt || !dev->fs_lcnt) {
115 ic_clk = i2c_dw_clk_rate(dev);
116 dev->fs_hcnt =
117 i2c_dw_scl_hcnt(ic_clk,
118 600, /* tHD;STA = tHIGH = 0.6 us */
119 sda_falling_time,
120 0, /* 0: DW default, 1: Ideal */
121 0); /* No offset */
122 dev->fs_lcnt =
123 i2c_dw_scl_lcnt(ic_clk,
124 1300, /* tLOW = 1.3 us */
125 scl_falling_time,
126 0); /* No offset */
127 }
128 dev_dbg(dev->dev, "Fast Mode%s HCNT:LCNT = %d:%d\n",
129 fp_str, dev->fs_hcnt, dev->fs_lcnt);
130
131 /* Check is high speed possible and fall back to fast mode if not */
132 if ((dev->master_cfg & DW_IC_CON_SPEED_MASK) ==
133 DW_IC_CON_SPEED_HIGH) {
134 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
135 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
136 dev_err(dev->dev, "High Speed not supported!\n");
137 t->bus_freq_hz = I2C_MAX_FAST_MODE_FREQ;
138 dev->master_cfg &= ~DW_IC_CON_SPEED_MASK;
139 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
140 dev->hs_hcnt = 0;
141 dev->hs_lcnt = 0;
142 } else if (!dev->hs_hcnt || !dev->hs_lcnt) {
143 ic_clk = i2c_dw_clk_rate(dev);
144 dev->hs_hcnt =
145 i2c_dw_scl_hcnt(ic_clk,
146 160, /* tHIGH = 160 ns */
147 sda_falling_time,
148 0, /* DW default */
149 0); /* No offset */
150 dev->hs_lcnt =
151 i2c_dw_scl_lcnt(ic_clk,
152 320, /* tLOW = 320 ns */
153 scl_falling_time,
154 0); /* No offset */
155 }
156 dev_dbg(dev->dev, "High Speed Mode HCNT:LCNT = %d:%d\n",
157 dev->hs_hcnt, dev->hs_lcnt);
158 }
159
160 ret = i2c_dw_set_sda_hold(dev);
161 if (ret)
162 return ret;
163
164 dev_dbg(dev->dev, "Bus speed: %s\n", i2c_freq_mode_string(t->bus_freq_hz));
165 return 0;
166 }
167
168 /**
169 * i2c_dw_init_master() - Initialize the designware I2C master hardware
170 * @dev: device private data
171 *
172 * This functions configures and enables the I2C master.
173 * This function is called during I2C init function, and in case of timeout at
174 * run time.
175 */
i2c_dw_init_master(struct dw_i2c_dev * dev)176 static int i2c_dw_init_master(struct dw_i2c_dev *dev)
177 {
178 int ret;
179
180 ret = i2c_dw_acquire_lock(dev);
181 if (ret)
182 return ret;
183
184 /* Disable the adapter */
185 __i2c_dw_disable(dev);
186
187 /* Write standard speed timing parameters */
188 regmap_write(dev->map, DW_IC_SS_SCL_HCNT, dev->ss_hcnt);
189 regmap_write(dev->map, DW_IC_SS_SCL_LCNT, dev->ss_lcnt);
190
191 /* Write fast mode/fast mode plus timing parameters */
192 regmap_write(dev->map, DW_IC_FS_SCL_HCNT, dev->fs_hcnt);
193 regmap_write(dev->map, DW_IC_FS_SCL_LCNT, dev->fs_lcnt);
194
195 /* Write high speed timing parameters if supported */
196 if (dev->hs_hcnt && dev->hs_lcnt) {
197 regmap_write(dev->map, DW_IC_HS_SCL_HCNT, dev->hs_hcnt);
198 regmap_write(dev->map, DW_IC_HS_SCL_LCNT, dev->hs_lcnt);
199 }
200
201 /* Write SDA hold time if supported */
202 if (dev->sda_hold_time)
203 regmap_write(dev->map, DW_IC_SDA_HOLD, dev->sda_hold_time);
204
205 i2c_dw_configure_fifo_master(dev);
206 i2c_dw_release_lock(dev);
207
208 return 0;
209 }
210
i2c_dw_xfer_init(struct dw_i2c_dev * dev)211 static void i2c_dw_xfer_init(struct dw_i2c_dev *dev)
212 {
213 struct i2c_msg *msgs = dev->msgs;
214 u32 ic_con = 0, ic_tar = 0;
215 unsigned int dummy;
216
217 /* Disable the adapter */
218 __i2c_dw_disable(dev);
219
220 /* If the slave address is ten bit address, enable 10BITADDR */
221 if (msgs[dev->msg_write_idx].flags & I2C_M_TEN) {
222 ic_con = DW_IC_CON_10BITADDR_MASTER;
223 /*
224 * If I2C_DYNAMIC_TAR_UPDATE is set, the 10-bit addressing
225 * mode has to be enabled via bit 12 of IC_TAR register.
226 * We set it always as I2C_DYNAMIC_TAR_UPDATE can't be
227 * detected from registers.
228 */
229 ic_tar = DW_IC_TAR_10BITADDR_MASTER;
230 }
231
232 regmap_update_bits(dev->map, DW_IC_CON, DW_IC_CON_10BITADDR_MASTER,
233 ic_con);
234
235 /*
236 * Set the slave (target) address and enable 10-bit addressing mode
237 * if applicable.
238 */
239 regmap_write(dev->map, DW_IC_TAR,
240 msgs[dev->msg_write_idx].addr | ic_tar);
241
242 /* Enforce disabled interrupts (due to HW issues) */
243 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
244
245 /* Enable the adapter */
246 __i2c_dw_enable(dev);
247
248 /* Dummy read to avoid the register getting stuck on Bay Trail */
249 regmap_read(dev->map, DW_IC_ENABLE_STATUS, &dummy);
250
251 /* Clear and enable interrupts */
252 regmap_read(dev->map, DW_IC_CLR_INTR, &dummy);
253 regmap_write(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_MASTER_MASK);
254 }
255
256 /*
257 * This function waits for the controller to be idle before disabling I2C
258 * When the controller is not in the IDLE state, the MST_ACTIVITY bit
259 * (IC_STATUS[5]) is set.
260 *
261 * Values:
262 * 0x1 (ACTIVE): Controller not idle
263 * 0x0 (IDLE): Controller is idle
264 *
265 * The function is called after completing the current transfer.
266 *
267 * Returns:
268 * False when the controller is in the IDLE state.
269 * True when the controller is in the ACTIVE state.
270 */
i2c_dw_is_controller_active(struct dw_i2c_dev * dev)271 static bool i2c_dw_is_controller_active(struct dw_i2c_dev *dev)
272 {
273 u32 status;
274
275 regmap_read(dev->map, DW_IC_STATUS, &status);
276 if (!(status & DW_IC_STATUS_MASTER_ACTIVITY))
277 return false;
278
279 return regmap_read_poll_timeout(dev->map, DW_IC_STATUS, status,
280 !(status & DW_IC_STATUS_MASTER_ACTIVITY),
281 1100, 20000) != 0;
282 }
283
i2c_dw_check_stopbit(struct dw_i2c_dev * dev)284 static int i2c_dw_check_stopbit(struct dw_i2c_dev *dev)
285 {
286 u32 val;
287 int ret;
288
289 ret = regmap_read_poll_timeout(dev->map, DW_IC_INTR_STAT, val,
290 !(val & DW_IC_INTR_STOP_DET),
291 1100, 20000);
292 if (ret)
293 dev_err(dev->dev, "i2c timeout error %d\n", ret);
294
295 return ret;
296 }
297
i2c_dw_status(struct dw_i2c_dev * dev)298 static int i2c_dw_status(struct dw_i2c_dev *dev)
299 {
300 int status;
301
302 status = i2c_dw_wait_bus_not_busy(dev);
303 if (status)
304 return status;
305
306 return i2c_dw_check_stopbit(dev);
307 }
308
309 /*
310 * Initiate and continue master read/write transaction with polling
311 * based transfer routine afterward write messages into the Tx buffer.
312 */
amd_i2c_dw_xfer_quirk(struct i2c_adapter * adap,struct i2c_msg * msgs,int num_msgs)313 static int amd_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs, int num_msgs)
314 {
315 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
316 int msg_wrt_idx, msg_itr_lmt, buf_len, data_idx;
317 int cmd = 0, status;
318 u8 *tx_buf;
319 unsigned int val;
320
321 /*
322 * In order to enable the interrupt for UCSI i.e. AMD NAVI GPU card,
323 * it is mandatory to set the right value in specific register
324 * (offset:0x474) as per the hardware IP specification.
325 */
326 regmap_write(dev->map, AMD_UCSI_INTR_REG, AMD_UCSI_INTR_EN);
327
328 dev->msgs = msgs;
329 dev->msgs_num = num_msgs;
330 dev->msg_write_idx = 0;
331 i2c_dw_xfer_init(dev);
332 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
333
334 /* Initiate messages read/write transaction */
335 for (msg_wrt_idx = 0; msg_wrt_idx < num_msgs; msg_wrt_idx++) {
336 tx_buf = msgs[msg_wrt_idx].buf;
337 buf_len = msgs[msg_wrt_idx].len;
338
339 if (!(msgs[msg_wrt_idx].flags & I2C_M_RD))
340 regmap_write(dev->map, DW_IC_TX_TL, buf_len - 1);
341 /*
342 * Initiate the i2c read/write transaction of buffer length,
343 * and poll for bus busy status. For the last message transfer,
344 * update the command with stopbit enable.
345 */
346 for (msg_itr_lmt = buf_len; msg_itr_lmt > 0; msg_itr_lmt--) {
347 if (msg_wrt_idx == num_msgs - 1 && msg_itr_lmt == 1)
348 cmd |= BIT(9);
349
350 if (msgs[msg_wrt_idx].flags & I2C_M_RD) {
351 /* Due to hardware bug, need to write the same command twice. */
352 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100);
353 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | cmd);
354 if (cmd) {
355 regmap_write(dev->map, DW_IC_TX_TL, 2 * (buf_len - 1));
356 regmap_write(dev->map, DW_IC_RX_TL, 2 * (buf_len - 1));
357 /*
358 * Need to check the stop bit. However, it cannot be
359 * detected from the registers so we check it always
360 * when read/write the last byte.
361 */
362 status = i2c_dw_status(dev);
363 if (status)
364 return status;
365
366 for (data_idx = 0; data_idx < buf_len; data_idx++) {
367 regmap_read(dev->map, DW_IC_DATA_CMD, &val);
368 tx_buf[data_idx] = val;
369 }
370 status = i2c_dw_check_stopbit(dev);
371 if (status)
372 return status;
373 }
374 } else {
375 regmap_write(dev->map, DW_IC_DATA_CMD, *tx_buf++ | cmd);
376 usleep_range(AMD_TIMEOUT_MIN_US, AMD_TIMEOUT_MAX_US);
377 }
378 }
379 status = i2c_dw_check_stopbit(dev);
380 if (status)
381 return status;
382 }
383
384 return 0;
385 }
386
i2c_dw_poll_tx_empty(struct dw_i2c_dev * dev)387 static int i2c_dw_poll_tx_empty(struct dw_i2c_dev *dev)
388 {
389 u32 val;
390
391 return regmap_read_poll_timeout(dev->map, DW_IC_RAW_INTR_STAT, val,
392 val & DW_IC_INTR_TX_EMPTY,
393 100, 1000);
394 }
395
i2c_dw_poll_rx_full(struct dw_i2c_dev * dev)396 static int i2c_dw_poll_rx_full(struct dw_i2c_dev *dev)
397 {
398 u32 val;
399
400 return regmap_read_poll_timeout(dev->map, DW_IC_RAW_INTR_STAT, val,
401 val & DW_IC_INTR_RX_FULL,
402 100, 1000);
403 }
404
txgbe_i2c_dw_xfer_quirk(struct i2c_adapter * adap,struct i2c_msg * msgs,int num_msgs)405 static int txgbe_i2c_dw_xfer_quirk(struct i2c_adapter *adap, struct i2c_msg *msgs,
406 int num_msgs)
407 {
408 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
409 int msg_idx, buf_len, data_idx, ret;
410 unsigned int val, stop = 0;
411 u8 *buf;
412
413 dev->msgs = msgs;
414 dev->msgs_num = num_msgs;
415 i2c_dw_xfer_init(dev);
416 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
417
418 for (msg_idx = 0; msg_idx < num_msgs; msg_idx++) {
419 buf = msgs[msg_idx].buf;
420 buf_len = msgs[msg_idx].len;
421
422 for (data_idx = 0; data_idx < buf_len; data_idx++) {
423 if (msg_idx == num_msgs - 1 && data_idx == buf_len - 1)
424 stop |= BIT(9);
425
426 if (msgs[msg_idx].flags & I2C_M_RD) {
427 regmap_write(dev->map, DW_IC_DATA_CMD, 0x100 | stop);
428
429 ret = i2c_dw_poll_rx_full(dev);
430 if (ret)
431 return ret;
432
433 regmap_read(dev->map, DW_IC_DATA_CMD, &val);
434 buf[data_idx] = val;
435 } else {
436 ret = i2c_dw_poll_tx_empty(dev);
437 if (ret)
438 return ret;
439
440 regmap_write(dev->map, DW_IC_DATA_CMD,
441 buf[data_idx] | stop);
442 }
443 }
444 }
445
446 return num_msgs;
447 }
448
449 /*
450 * Initiate (and continue) low level master read/write transaction.
451 * This function is only called from i2c_dw_isr, and pumping i2c_msg
452 * messages into the tx buffer. Even if the size of i2c_msg data is
453 * longer than the size of the tx buffer, it handles everything.
454 */
455 static void
i2c_dw_xfer_msg(struct dw_i2c_dev * dev)456 i2c_dw_xfer_msg(struct dw_i2c_dev *dev)
457 {
458 struct i2c_msg *msgs = dev->msgs;
459 u32 intr_mask;
460 int tx_limit, rx_limit;
461 u32 addr = msgs[dev->msg_write_idx].addr;
462 u32 buf_len = dev->tx_buf_len;
463 u8 *buf = dev->tx_buf;
464 bool need_restart = false;
465 unsigned int flr;
466
467 intr_mask = DW_IC_INTR_MASTER_MASK;
468
469 for (; dev->msg_write_idx < dev->msgs_num; dev->msg_write_idx++) {
470 u32 flags = msgs[dev->msg_write_idx].flags;
471
472 /*
473 * If target address has changed, we need to
474 * reprogram the target address in the I2C
475 * adapter when we are done with this transfer.
476 */
477 if (msgs[dev->msg_write_idx].addr != addr) {
478 dev_err(dev->dev,
479 "%s: invalid target address\n", __func__);
480 dev->msg_err = -EINVAL;
481 break;
482 }
483
484 if (!(dev->status & STATUS_WRITE_IN_PROGRESS)) {
485 /* new i2c_msg */
486 buf = msgs[dev->msg_write_idx].buf;
487 buf_len = msgs[dev->msg_write_idx].len;
488
489 /* If both IC_EMPTYFIFO_HOLD_MASTER_EN and
490 * IC_RESTART_EN are set, we must manually
491 * set restart bit between messages.
492 */
493 if ((dev->master_cfg & DW_IC_CON_RESTART_EN) &&
494 (dev->msg_write_idx > 0))
495 need_restart = true;
496 }
497
498 regmap_read(dev->map, DW_IC_TXFLR, &flr);
499 tx_limit = dev->tx_fifo_depth - flr;
500
501 regmap_read(dev->map, DW_IC_RXFLR, &flr);
502 rx_limit = dev->rx_fifo_depth - flr;
503
504 while (buf_len > 0 && tx_limit > 0 && rx_limit > 0) {
505 u32 cmd = 0;
506
507 /*
508 * If IC_EMPTYFIFO_HOLD_MASTER_EN is set we must
509 * manually set the stop bit. However, it cannot be
510 * detected from the registers so we set it always
511 * when writing/reading the last byte.
512 */
513
514 /*
515 * i2c-core always sets the buffer length of
516 * I2C_FUNC_SMBUS_BLOCK_DATA to 1. The length will
517 * be adjusted when receiving the first byte.
518 * Thus we can't stop the transaction here.
519 */
520 if (dev->msg_write_idx == dev->msgs_num - 1 &&
521 buf_len == 1 && !(flags & I2C_M_RECV_LEN))
522 cmd |= BIT(9);
523
524 if (need_restart) {
525 cmd |= BIT(10);
526 need_restart = false;
527 }
528
529 if (msgs[dev->msg_write_idx].flags & I2C_M_RD) {
530
531 /* Avoid rx buffer overrun */
532 if (dev->rx_outstanding >= dev->rx_fifo_depth)
533 break;
534
535 regmap_write(dev->map, DW_IC_DATA_CMD,
536 cmd | 0x100);
537 rx_limit--;
538 dev->rx_outstanding++;
539 } else {
540 regmap_write(dev->map, DW_IC_DATA_CMD,
541 cmd | *buf++);
542 }
543 tx_limit--; buf_len--;
544 }
545
546 dev->tx_buf = buf;
547 dev->tx_buf_len = buf_len;
548
549 /*
550 * Because we don't know the buffer length in the
551 * I2C_FUNC_SMBUS_BLOCK_DATA case, we can't stop the
552 * transaction here. Also disable the TX_EMPTY IRQ
553 * while waiting for the data length byte to avoid the
554 * bogus interrupts flood.
555 */
556 if (flags & I2C_M_RECV_LEN) {
557 dev->status |= STATUS_WRITE_IN_PROGRESS;
558 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
559 break;
560 } else if (buf_len > 0) {
561 /* more bytes to be written */
562 dev->status |= STATUS_WRITE_IN_PROGRESS;
563 break;
564 } else
565 dev->status &= ~STATUS_WRITE_IN_PROGRESS;
566 }
567
568 /*
569 * If i2c_msg index search is completed, we don't need TX_EMPTY
570 * interrupt any more.
571 */
572 if (dev->msg_write_idx == dev->msgs_num)
573 intr_mask &= ~DW_IC_INTR_TX_EMPTY;
574
575 if (dev->msg_err)
576 intr_mask = 0;
577
578 regmap_write(dev->map, DW_IC_INTR_MASK, intr_mask);
579 }
580
581 static u8
i2c_dw_recv_len(struct dw_i2c_dev * dev,u8 len)582 i2c_dw_recv_len(struct dw_i2c_dev *dev, u8 len)
583 {
584 struct i2c_msg *msgs = dev->msgs;
585 u32 flags = msgs[dev->msg_read_idx].flags;
586
587 /*
588 * Adjust the buffer length and mask the flag
589 * after receiving the first byte.
590 */
591 len += (flags & I2C_CLIENT_PEC) ? 2 : 1;
592 dev->tx_buf_len = len - min_t(u8, len, dev->rx_outstanding);
593 msgs[dev->msg_read_idx].len = len;
594 msgs[dev->msg_read_idx].flags &= ~I2C_M_RECV_LEN;
595
596 /*
597 * Received buffer length, re-enable TX_EMPTY interrupt
598 * to resume the SMBUS transaction.
599 */
600 regmap_update_bits(dev->map, DW_IC_INTR_MASK, DW_IC_INTR_TX_EMPTY,
601 DW_IC_INTR_TX_EMPTY);
602
603 return len;
604 }
605
606 static void
i2c_dw_read(struct dw_i2c_dev * dev)607 i2c_dw_read(struct dw_i2c_dev *dev)
608 {
609 struct i2c_msg *msgs = dev->msgs;
610 unsigned int rx_valid;
611
612 for (; dev->msg_read_idx < dev->msgs_num; dev->msg_read_idx++) {
613 unsigned int tmp;
614 u32 len;
615 u8 *buf;
616
617 if (!(msgs[dev->msg_read_idx].flags & I2C_M_RD))
618 continue;
619
620 if (!(dev->status & STATUS_READ_IN_PROGRESS)) {
621 len = msgs[dev->msg_read_idx].len;
622 buf = msgs[dev->msg_read_idx].buf;
623 } else {
624 len = dev->rx_buf_len;
625 buf = dev->rx_buf;
626 }
627
628 regmap_read(dev->map, DW_IC_RXFLR, &rx_valid);
629
630 for (; len > 0 && rx_valid > 0; len--, rx_valid--) {
631 u32 flags = msgs[dev->msg_read_idx].flags;
632
633 regmap_read(dev->map, DW_IC_DATA_CMD, &tmp);
634 tmp &= DW_IC_DATA_CMD_DAT;
635 /* Ensure length byte is a valid value */
636 if (flags & I2C_M_RECV_LEN) {
637 /*
638 * if IC_EMPTYFIFO_HOLD_MASTER_EN is set, which cannot be
639 * detected from the registers, the controller can be
640 * disabled if the STOP bit is set. But it is only set
641 * after receiving block data response length in
642 * I2C_FUNC_SMBUS_BLOCK_DATA case. That needs to read
643 * another byte with STOP bit set when the block data
644 * response length is invalid to complete the transaction.
645 */
646 if (!tmp || tmp > I2C_SMBUS_BLOCK_MAX)
647 tmp = 1;
648
649 len = i2c_dw_recv_len(dev, tmp);
650 }
651 *buf++ = tmp;
652 dev->rx_outstanding--;
653 }
654
655 if (len > 0) {
656 dev->status |= STATUS_READ_IN_PROGRESS;
657 dev->rx_buf_len = len;
658 dev->rx_buf = buf;
659 return;
660 } else
661 dev->status &= ~STATUS_READ_IN_PROGRESS;
662 }
663 }
664
665 /*
666 * Prepare controller for a transaction and call i2c_dw_xfer_msg.
667 */
668 static int
i2c_dw_xfer(struct i2c_adapter * adap,struct i2c_msg msgs[],int num)669 i2c_dw_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
670 {
671 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
672 int ret;
673
674 dev_dbg(dev->dev, "%s: msgs: %d\n", __func__, num);
675
676 pm_runtime_get_sync(dev->dev);
677
678 /*
679 * Initiate I2C message transfer when polling mode is enabled,
680 * As it is polling based transfer mechanism, which does not support
681 * interrupt based functionalities of existing DesignWare driver.
682 */
683 switch (dev->flags & MODEL_MASK) {
684 case MODEL_AMD_NAVI_GPU:
685 ret = amd_i2c_dw_xfer_quirk(adap, msgs, num);
686 goto done_nolock;
687 case MODEL_WANGXUN_SP:
688 ret = txgbe_i2c_dw_xfer_quirk(adap, msgs, num);
689 goto done_nolock;
690 default:
691 break;
692 }
693
694 reinit_completion(&dev->cmd_complete);
695 dev->msgs = msgs;
696 dev->msgs_num = num;
697 dev->cmd_err = 0;
698 dev->msg_write_idx = 0;
699 dev->msg_read_idx = 0;
700 dev->msg_err = 0;
701 dev->status = 0;
702 dev->abort_source = 0;
703 dev->rx_outstanding = 0;
704
705 ret = i2c_dw_acquire_lock(dev);
706 if (ret)
707 goto done_nolock;
708
709 ret = i2c_dw_wait_bus_not_busy(dev);
710 if (ret < 0)
711 goto done;
712
713 /* Start the transfers */
714 i2c_dw_xfer_init(dev);
715
716 /* Wait for tx to complete */
717 if (!wait_for_completion_timeout(&dev->cmd_complete, adap->timeout)) {
718 dev_err(dev->dev, "controller timed out\n");
719 /* i2c_dw_init implicitly disables the adapter */
720 i2c_recover_bus(&dev->adapter);
721 i2c_dw_init_master(dev);
722 ret = -ETIMEDOUT;
723 goto done;
724 }
725
726 /*
727 * This happens rarely (~1:500) and is hard to reproduce. Debug trace
728 * showed that IC_STATUS had value of 0x23 when STOP_DET occurred,
729 * if disable IC_ENABLE.ENABLE immediately that can result in
730 * IC_RAW_INTR_STAT.MASTER_ON_HOLD holding SCL low. Check if
731 * controller is still ACTIVE before disabling I2C.
732 */
733 if (i2c_dw_is_controller_active(dev))
734 dev_err(dev->dev, "controller active\n");
735
736 /*
737 * We must disable the adapter before returning and signaling the end
738 * of the current transfer. Otherwise the hardware might continue
739 * generating interrupts which in turn causes a race condition with
740 * the following transfer. Needs some more investigation if the
741 * additional interrupts are a hardware bug or this driver doesn't
742 * handle them correctly yet.
743 */
744 __i2c_dw_disable_nowait(dev);
745
746 if (dev->msg_err) {
747 ret = dev->msg_err;
748 goto done;
749 }
750
751 /* No error */
752 if (likely(!dev->cmd_err && !dev->status)) {
753 ret = num;
754 goto done;
755 }
756
757 /* We have an error */
758 if (dev->cmd_err == DW_IC_ERR_TX_ABRT) {
759 ret = i2c_dw_handle_tx_abort(dev);
760 goto done;
761 }
762
763 if (dev->status)
764 dev_err(dev->dev,
765 "transfer terminated early - interrupt latency too high?\n");
766
767 ret = -EIO;
768
769 done:
770 i2c_dw_release_lock(dev);
771
772 done_nolock:
773 pm_runtime_mark_last_busy(dev->dev);
774 pm_runtime_put_autosuspend(dev->dev);
775
776 return ret;
777 }
778
779 static const struct i2c_algorithm i2c_dw_algo = {
780 .master_xfer = i2c_dw_xfer,
781 .functionality = i2c_dw_func,
782 };
783
784 static const struct i2c_adapter_quirks i2c_dw_quirks = {
785 .flags = I2C_AQ_NO_ZERO_LEN,
786 };
787
i2c_dw_read_clear_intrbits(struct dw_i2c_dev * dev)788 static u32 i2c_dw_read_clear_intrbits(struct dw_i2c_dev *dev)
789 {
790 unsigned int stat, dummy;
791
792 /*
793 * The IC_INTR_STAT register just indicates "enabled" interrupts.
794 * The unmasked raw version of interrupt status bits is available
795 * in the IC_RAW_INTR_STAT register.
796 *
797 * That is,
798 * stat = readl(IC_INTR_STAT);
799 * equals to,
800 * stat = readl(IC_RAW_INTR_STAT) & readl(IC_INTR_MASK);
801 *
802 * The raw version might be useful for debugging purposes.
803 */
804 regmap_read(dev->map, DW_IC_INTR_STAT, &stat);
805
806 /*
807 * Do not use the IC_CLR_INTR register to clear interrupts, or
808 * you'll miss some interrupts, triggered during the period from
809 * readl(IC_INTR_STAT) to readl(IC_CLR_INTR).
810 *
811 * Instead, use the separately-prepared IC_CLR_* registers.
812 */
813 if (stat & DW_IC_INTR_RX_UNDER)
814 regmap_read(dev->map, DW_IC_CLR_RX_UNDER, &dummy);
815 if (stat & DW_IC_INTR_RX_OVER)
816 regmap_read(dev->map, DW_IC_CLR_RX_OVER, &dummy);
817 if (stat & DW_IC_INTR_TX_OVER)
818 regmap_read(dev->map, DW_IC_CLR_TX_OVER, &dummy);
819 if (stat & DW_IC_INTR_RD_REQ)
820 regmap_read(dev->map, DW_IC_CLR_RD_REQ, &dummy);
821 if (stat & DW_IC_INTR_TX_ABRT) {
822 /*
823 * The IC_TX_ABRT_SOURCE register is cleared whenever
824 * the IC_CLR_TX_ABRT is read. Preserve it beforehand.
825 */
826 regmap_read(dev->map, DW_IC_TX_ABRT_SOURCE, &dev->abort_source);
827 regmap_read(dev->map, DW_IC_CLR_TX_ABRT, &dummy);
828 }
829 if (stat & DW_IC_INTR_RX_DONE)
830 regmap_read(dev->map, DW_IC_CLR_RX_DONE, &dummy);
831 if (stat & DW_IC_INTR_ACTIVITY)
832 regmap_read(dev->map, DW_IC_CLR_ACTIVITY, &dummy);
833 if ((stat & DW_IC_INTR_STOP_DET) &&
834 ((dev->rx_outstanding == 0) || (stat & DW_IC_INTR_RX_FULL)))
835 regmap_read(dev->map, DW_IC_CLR_STOP_DET, &dummy);
836 if (stat & DW_IC_INTR_START_DET)
837 regmap_read(dev->map, DW_IC_CLR_START_DET, &dummy);
838 if (stat & DW_IC_INTR_GEN_CALL)
839 regmap_read(dev->map, DW_IC_CLR_GEN_CALL, &dummy);
840
841 return stat;
842 }
843
844 /*
845 * Interrupt service routine. This gets called whenever an I2C master interrupt
846 * occurs.
847 */
i2c_dw_isr(int this_irq,void * dev_id)848 static irqreturn_t i2c_dw_isr(int this_irq, void *dev_id)
849 {
850 struct dw_i2c_dev *dev = dev_id;
851 unsigned int stat, enabled;
852
853 regmap_read(dev->map, DW_IC_ENABLE, &enabled);
854 regmap_read(dev->map, DW_IC_RAW_INTR_STAT, &stat);
855 if (!enabled || !(stat & ~DW_IC_INTR_ACTIVITY))
856 return IRQ_NONE;
857 if (pm_runtime_suspended(dev->dev) || stat == GENMASK(31, 0))
858 return IRQ_NONE;
859 dev_dbg(dev->dev, "enabled=%#x stat=%#x\n", enabled, stat);
860
861 stat = i2c_dw_read_clear_intrbits(dev);
862
863 if (!(dev->status & STATUS_ACTIVE)) {
864 /*
865 * Unexpected interrupt in driver point of view. State
866 * variables are either unset or stale so acknowledge and
867 * disable interrupts for suppressing further interrupts if
868 * interrupt really came from this HW (E.g. firmware has left
869 * the HW active).
870 */
871 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
872 return IRQ_HANDLED;
873 }
874
875 if (stat & DW_IC_INTR_TX_ABRT) {
876 dev->cmd_err |= DW_IC_ERR_TX_ABRT;
877 dev->status &= ~STATUS_MASK;
878 dev->rx_outstanding = 0;
879
880 /*
881 * Anytime TX_ABRT is set, the contents of the tx/rx
882 * buffers are flushed. Make sure to skip them.
883 */
884 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
885 goto tx_aborted;
886 }
887
888 if (stat & DW_IC_INTR_RX_FULL)
889 i2c_dw_read(dev);
890
891 if (stat & DW_IC_INTR_TX_EMPTY)
892 i2c_dw_xfer_msg(dev);
893
894 /*
895 * No need to modify or disable the interrupt mask here.
896 * i2c_dw_xfer_msg() will take care of it according to
897 * the current transmit status.
898 */
899
900 tx_aborted:
901 if (((stat & (DW_IC_INTR_TX_ABRT | DW_IC_INTR_STOP_DET)) || dev->msg_err) &&
902 (dev->rx_outstanding == 0))
903 complete(&dev->cmd_complete);
904 else if (unlikely(dev->flags & ACCESS_INTR_MASK)) {
905 /* Workaround to trigger pending interrupt */
906 regmap_read(dev->map, DW_IC_INTR_MASK, &stat);
907 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
908 regmap_write(dev->map, DW_IC_INTR_MASK, stat);
909 }
910
911 return IRQ_HANDLED;
912 }
913
i2c_dw_configure_master(struct dw_i2c_dev * dev)914 void i2c_dw_configure_master(struct dw_i2c_dev *dev)
915 {
916 struct i2c_timings *t = &dev->timings;
917
918 dev->functionality = I2C_FUNC_10BIT_ADDR | DW_IC_DEFAULT_FUNCTIONALITY;
919
920 dev->master_cfg = DW_IC_CON_MASTER | DW_IC_CON_SLAVE_DISABLE |
921 DW_IC_CON_RESTART_EN;
922
923 dev->mode = DW_IC_MASTER;
924
925 switch (t->bus_freq_hz) {
926 case I2C_MAX_STANDARD_MODE_FREQ:
927 dev->master_cfg |= DW_IC_CON_SPEED_STD;
928 break;
929 case I2C_MAX_HIGH_SPEED_MODE_FREQ:
930 dev->master_cfg |= DW_IC_CON_SPEED_HIGH;
931 break;
932 default:
933 dev->master_cfg |= DW_IC_CON_SPEED_FAST;
934 }
935 }
936 EXPORT_SYMBOL_GPL(i2c_dw_configure_master);
937
i2c_dw_prepare_recovery(struct i2c_adapter * adap)938 static void i2c_dw_prepare_recovery(struct i2c_adapter *adap)
939 {
940 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
941
942 i2c_dw_disable(dev);
943 reset_control_assert(dev->rst);
944 i2c_dw_prepare_clk(dev, false);
945 }
946
i2c_dw_unprepare_recovery(struct i2c_adapter * adap)947 static void i2c_dw_unprepare_recovery(struct i2c_adapter *adap)
948 {
949 struct dw_i2c_dev *dev = i2c_get_adapdata(adap);
950
951 i2c_dw_prepare_clk(dev, true);
952 reset_control_deassert(dev->rst);
953 i2c_dw_init_master(dev);
954 }
955
i2c_dw_init_recovery_info(struct dw_i2c_dev * dev)956 static int i2c_dw_init_recovery_info(struct dw_i2c_dev *dev)
957 {
958 struct i2c_bus_recovery_info *rinfo = &dev->rinfo;
959 struct i2c_adapter *adap = &dev->adapter;
960 struct gpio_desc *gpio;
961
962 gpio = devm_gpiod_get_optional(dev->dev, "scl", GPIOD_OUT_HIGH);
963 if (IS_ERR_OR_NULL(gpio))
964 return PTR_ERR_OR_ZERO(gpio);
965
966 rinfo->scl_gpiod = gpio;
967
968 gpio = devm_gpiod_get_optional(dev->dev, "sda", GPIOD_IN);
969 if (IS_ERR(gpio))
970 return PTR_ERR(gpio);
971 rinfo->sda_gpiod = gpio;
972
973 rinfo->pinctrl = devm_pinctrl_get(dev->dev);
974 if (IS_ERR(rinfo->pinctrl)) {
975 if (PTR_ERR(rinfo->pinctrl) == -EPROBE_DEFER)
976 return PTR_ERR(rinfo->pinctrl);
977
978 rinfo->pinctrl = NULL;
979 dev_err(dev->dev, "getting pinctrl info failed: bus recovery might not work\n");
980 } else if (!rinfo->pinctrl) {
981 dev_dbg(dev->dev, "pinctrl is disabled, bus recovery might not work\n");
982 }
983
984 rinfo->recover_bus = i2c_generic_scl_recovery;
985 rinfo->prepare_recovery = i2c_dw_prepare_recovery;
986 rinfo->unprepare_recovery = i2c_dw_unprepare_recovery;
987 adap->bus_recovery_info = rinfo;
988
989 dev_info(dev->dev, "running with gpio recovery mode! scl%s",
990 rinfo->sda_gpiod ? ",sda" : "");
991
992 return 0;
993 }
994
i2c_dw_probe_master(struct dw_i2c_dev * dev)995 int i2c_dw_probe_master(struct dw_i2c_dev *dev)
996 {
997 struct i2c_adapter *adap = &dev->adapter;
998 unsigned long irq_flags;
999 unsigned int ic_con;
1000 int ret;
1001
1002 init_completion(&dev->cmd_complete);
1003
1004 dev->init = i2c_dw_init_master;
1005
1006 ret = i2c_dw_init_regmap(dev);
1007 if (ret)
1008 return ret;
1009
1010 ret = i2c_dw_set_timings_master(dev);
1011 if (ret)
1012 return ret;
1013
1014 ret = i2c_dw_set_fifo_size(dev);
1015 if (ret)
1016 return ret;
1017
1018 /* Lock the bus for accessing DW_IC_CON */
1019 ret = i2c_dw_acquire_lock(dev);
1020 if (ret)
1021 return ret;
1022
1023 /*
1024 * On AMD platforms BIOS advertises the bus clear feature
1025 * and enables the SCL/SDA stuck low. SMU FW does the
1026 * bus recovery process. Driver should not ignore this BIOS
1027 * advertisement of bus clear feature.
1028 */
1029 ret = regmap_read(dev->map, DW_IC_CON, &ic_con);
1030 i2c_dw_release_lock(dev);
1031 if (ret)
1032 return ret;
1033
1034 if (ic_con & DW_IC_CON_BUS_CLEAR_CTRL)
1035 dev->master_cfg |= DW_IC_CON_BUS_CLEAR_CTRL;
1036
1037 ret = dev->init(dev);
1038 if (ret)
1039 return ret;
1040
1041 snprintf(adap->name, sizeof(adap->name),
1042 "Synopsys DesignWare I2C adapter");
1043 adap->retries = 3;
1044 adap->algo = &i2c_dw_algo;
1045 adap->quirks = &i2c_dw_quirks;
1046 adap->dev.parent = dev->dev;
1047 i2c_set_adapdata(adap, dev);
1048
1049 if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
1050 irq_flags = IRQF_NO_SUSPEND;
1051 } else {
1052 irq_flags = IRQF_SHARED | IRQF_COND_SUSPEND;
1053 }
1054
1055 ret = i2c_dw_acquire_lock(dev);
1056 if (ret)
1057 return ret;
1058
1059 regmap_write(dev->map, DW_IC_INTR_MASK, 0);
1060 i2c_dw_release_lock(dev);
1061
1062 if (!(dev->flags & ACCESS_POLLING)) {
1063 ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr,
1064 irq_flags, dev_name(dev->dev), dev);
1065 if (ret) {
1066 dev_err(dev->dev, "failure requesting irq %i: %d\n",
1067 dev->irq, ret);
1068 return ret;
1069 }
1070 }
1071
1072 ret = i2c_dw_init_recovery_info(dev);
1073 if (ret)
1074 return ret;
1075
1076 /*
1077 * Increment PM usage count during adapter registration in order to
1078 * avoid possible spurious runtime suspend when adapter device is
1079 * registered to the device core and immediate resume in case bus has
1080 * registered I2C slaves that do I2C transfers in their probe.
1081 */
1082 pm_runtime_get_noresume(dev->dev);
1083 ret = i2c_add_numbered_adapter(adap);
1084 if (ret)
1085 dev_err(dev->dev, "failure adding adapter: %d\n", ret);
1086 pm_runtime_put_noidle(dev->dev);
1087
1088 return ret;
1089 }
1090 EXPORT_SYMBOL_GPL(i2c_dw_probe_master);
1091
1092 MODULE_DESCRIPTION("Synopsys DesignWare I2C bus master adapter");
1093 MODULE_LICENSE("GPL");
1094