xref: /openbmc/linux/sound/soc/amd/acp/amd.h (revision 4062afe9)
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /*
3  * This file is provided under a dual BSD/GPLv2 license. When using or
4  * redistributing this file, you may do so under either license.
5  *
6  * Copyright(c) 2021 Advanced Micro Devices, Inc. All rights reserved.
7  *
8  * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
9  */
10 
11 #ifndef __AMD_ACP_H
12 #define __AMD_ACP_H
13 
14 #include <sound/pcm.h>
15 #include <sound/soc.h>
16 #include <sound/soc-acpi.h>
17 #include <sound/soc-dai.h>
18 
19 #include "chip_offset_byte.h"
20 
21 #define ACP3X_DEV			3
22 #define ACP6X_DEV			6
23 
24 #define DMIC_INSTANCE			0x00
25 #define I2S_SP_INSTANCE			0x01
26 #define I2S_BT_INSTANCE			0x02
27 #define I2S_HS_INSTANCE			0x03
28 
29 #define MEM_WINDOW_START		0x4080000
30 
31 #define ACP_I2S_REG_START		0x1242400
32 #define ACP_I2S_REG_END			0x1242810
33 #define ACP3x_I2STDM_REG_START		0x1242400
34 #define ACP3x_I2STDM_REG_END		0x1242410
35 #define ACP3x_BT_TDM_REG_START		0x1242800
36 #define ACP3x_BT_TDM_REG_END		0x1242810
37 
38 #define THRESHOLD(bit, base)	((bit) + (base))
39 #define I2S_RX_THRESHOLD(base)	THRESHOLD(7, base)
40 #define I2S_TX_THRESHOLD(base)	THRESHOLD(8, base)
41 #define BT_TX_THRESHOLD(base)	THRESHOLD(6, base)
42 #define BT_RX_THRESHOLD(base)	THRESHOLD(5, base)
43 #define HS_TX_THRESHOLD(base)	THRESHOLD(4, base)
44 #define HS_RX_THRESHOLD(base)	THRESHOLD(3, base)
45 
46 #define ACP_SRAM_SP_PB_PTE_OFFSET	0x0
47 #define ACP_SRAM_SP_CP_PTE_OFFSET	0x100
48 #define ACP_SRAM_BT_PB_PTE_OFFSET	0x200
49 #define ACP_SRAM_BT_CP_PTE_OFFSET	0x300
50 #define ACP_SRAM_PDM_PTE_OFFSET		0x400
51 #define ACP_SRAM_HS_PB_PTE_OFFSET       0x500
52 #define ACP_SRAM_HS_CP_PTE_OFFSET       0x600
53 #define PAGE_SIZE_4K_ENABLE		0x2
54 
55 #define I2S_SP_TX_MEM_WINDOW_START	0x4000000
56 #define I2S_SP_RX_MEM_WINDOW_START	0x4020000
57 #define I2S_BT_TX_MEM_WINDOW_START	0x4040000
58 #define I2S_BT_RX_MEM_WINDOW_START	0x4060000
59 #define I2S_HS_TX_MEM_WINDOW_START      0x40A0000
60 #define I2S_HS_RX_MEM_WINDOW_START      0x40C0000
61 
62 #define SP_PB_FIFO_ADDR_OFFSET		0x500
63 #define SP_CAPT_FIFO_ADDR_OFFSET	0x700
64 #define BT_PB_FIFO_ADDR_OFFSET		0x900
65 #define BT_CAPT_FIFO_ADDR_OFFSET	0xB00
66 #define HS_PB_FIFO_ADDR_OFFSET		0xD00
67 #define HS_CAPT_FIFO_ADDR_OFFSET	0xF00
68 #define PLAYBACK_MIN_NUM_PERIODS	2
69 #define PLAYBACK_MAX_NUM_PERIODS	8
70 #define PLAYBACK_MAX_PERIOD_SIZE	8192
71 #define PLAYBACK_MIN_PERIOD_SIZE	1024
72 #define CAPTURE_MIN_NUM_PERIODS		2
73 #define CAPTURE_MAX_NUM_PERIODS		8
74 #define CAPTURE_MAX_PERIOD_SIZE		8192
75 #define CAPTURE_MIN_PERIOD_SIZE		1024
76 
77 #define MAX_BUFFER			65536
78 #define MIN_BUFFER			MAX_BUFFER
79 #define FIFO_SIZE			0x100
80 #define DMA_SIZE			0x40
81 #define FRM_LEN				0x100
82 
83 #define ACP3x_ITER_IRER_SAMP_LEN_MASK	0x38
84 
85 #define ACP_MAX_STREAM			8
86 
87 #define TDM_ENABLE	1
88 #define TDM_DISABLE	0
89 
90 #define SLOT_WIDTH_8	0x8
91 #define SLOT_WIDTH_16	0x10
92 #define SLOT_WIDTH_24	0x18
93 #define SLOT_WIDTH_32	0x20
94 
95 #define ACP6X_PGFSM_CONTROL                     0x1024
96 #define ACP6X_PGFSM_STATUS                      0x1028
97 
98 #define ACP_SOFT_RST_DONE_MASK	0x00010001
99 
100 #define ACP_PGFSM_CNTL_POWER_ON_MASK            0x01
101 #define ACP_PGFSM_CNTL_POWER_OFF_MASK           0x00
102 #define ACP_PGFSM_STATUS_MASK                   0x03
103 #define ACP_POWERED_ON                          0x00
104 #define ACP_POWER_ON_IN_PROGRESS                0x01
105 #define ACP_POWERED_OFF                         0x02
106 #define ACP_POWER_OFF_IN_PROGRESS               0x03
107 
108 #define ACP_ERROR_MASK                          0x20000000
109 #define ACP_EXT_INTR_STAT_CLEAR_MASK            0xffffffff
110 
111 #define ACP_TIMEOUT		500
112 #define DELAY_US		5
113 #define ACP_SUSPEND_DELAY_MS   2000
114 
115 #define PDM_DMA_STAT            0x10
116 #define PDM_DMA_INTR_MASK       0x10000
117 #define PDM_DEC_64              0x2
118 #define PDM_CLK_FREQ_MASK       0x07
119 #define PDM_MISC_CTRL_MASK      0x10
120 #define PDM_ENABLE              0x01
121 #define PDM_DISABLE             0x00
122 #define DMA_EN_MASK             0x02
123 #define DELAY_US                5
124 #define PDM_TIMEOUT             1000
125 #define ACP_REGION2_OFFSET      0x02000000
126 
127 struct acp_chip_info {
128 	char *name;		/* Platform name */
129 	unsigned int acp_rev;	/* ACP Revision id */
130 	void __iomem *base;	/* ACP memory PCI base */
131 	struct platform_device *chip_pdev;
132 };
133 
134 struct acp_stream {
135 	struct list_head list;
136 	struct snd_pcm_substream *substream;
137 	int irq_bit;
138 	int dai_id;
139 	int id;
140 	int dir;
141 	u64 bytescount;
142 	u32 reg_offset;
143 	u32 pte_offset;
144 	u32 fifo_offset;
145 };
146 
147 struct acp_resource {
148 	int offset;
149 	int no_of_ctrls;
150 	int irqp_used;
151 	bool soc_mclk;
152 	u32 irq_reg_offset;
153 	u32 i2s_pin_cfg_offset;
154 	int i2s_mode;
155 	u64 scratch_reg_offset;
156 	u64 sram_pte_offset;
157 };
158 
159 struct acp_dev_data {
160 	char *name;
161 	struct device *dev;
162 	void __iomem *acp_base;
163 	unsigned int i2s_irq;
164 
165 	bool tdm_mode;
166 	/* SOC specific dais */
167 	struct snd_soc_dai_driver *dai_driver;
168 	int num_dai;
169 
170 	struct list_head stream_list;
171 	spinlock_t acp_lock;
172 
173 	struct snd_soc_acpi_mach *machines;
174 	struct platform_device *mach_dev;
175 
176 	u32 bclk_div;
177 	u32 lrclk_div;
178 
179 	struct acp_resource *rsrc;
180 	u32 ch_mask;
181 	u32 tdm_tx_fmt[3];
182 	u32 tdm_rx_fmt[3];
183 	u32 xfer_tx_resolution[3];
184 	u32 xfer_rx_resolution[3];
185 };
186 
187 union acp_i2stdm_mstrclkgen {
188 	struct {
189 		u32 i2stdm_master_mode : 1;
190 		u32 i2stdm_format_mode : 1;
191 		u32 i2stdm_lrclk_div_val : 9;
192 		u32 i2stdm_bclk_div_val : 11;
193 		u32:10;
194 	} bitfields, bits;
195 	u32  u32_all;
196 };
197 
198 extern const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops;
199 extern const struct snd_soc_dai_ops acp_dmic_dai_ops;
200 
201 int acp_platform_register(struct device *dev);
202 int acp_platform_unregister(struct device *dev);
203 
204 int acp_machine_select(struct acp_dev_data *adata);
205 
206 int smn_read(struct pci_dev *dev, u32 smn_addr);
207 int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data);
208 
209 int acp_init(struct acp_chip_info *chip);
210 int acp_deinit(void __iomem *base);
211 void acp_enable_interrupts(struct acp_dev_data *adata);
212 void acp_disable_interrupts(struct acp_dev_data *adata);
213 /* Machine configuration */
214 int snd_amd_acp_find_config(struct pci_dev *pci);
215 
216 void config_pte_for_stream(struct acp_dev_data *adata, struct acp_stream *stream);
217 void config_acp_dma(struct acp_dev_data *adata, struct acp_stream *stream, int size);
218 void restore_acp_pdm_params(struct snd_pcm_substream *substream,
219 			    struct acp_dev_data *adata);
220 
221 int restore_acp_i2s_params(struct snd_pcm_substream *substream,
222 			   struct acp_dev_data *adata, struct acp_stream *stream);
223 
acp_get_byte_count(struct acp_dev_data * adata,int dai_id,int direction)224 static inline u64 acp_get_byte_count(struct acp_dev_data *adata, int dai_id, int direction)
225 {
226 	u64 byte_count = 0, low = 0, high = 0;
227 
228 	if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
229 		switch (dai_id) {
230 		case I2S_BT_INSTANCE:
231 			high = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_HIGH);
232 			low = readl(adata->acp_base + ACP_BT_TX_LINEARPOSITIONCNTR_LOW);
233 			break;
234 		case I2S_SP_INSTANCE:
235 			high = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_HIGH);
236 			low = readl(adata->acp_base + ACP_I2S_TX_LINEARPOSITIONCNTR_LOW);
237 			break;
238 		case I2S_HS_INSTANCE:
239 			high = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_HIGH);
240 			low = readl(adata->acp_base + ACP_HS_TX_LINEARPOSITIONCNTR_LOW);
241 			break;
242 		default:
243 			dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
244 			goto POINTER_RETURN_BYTES;
245 		}
246 	} else {
247 		switch (dai_id) {
248 		case I2S_BT_INSTANCE:
249 			high = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_HIGH);
250 			low = readl(adata->acp_base + ACP_BT_RX_LINEARPOSITIONCNTR_LOW);
251 			break;
252 		case I2S_SP_INSTANCE:
253 			high = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_HIGH);
254 			low = readl(adata->acp_base + ACP_I2S_RX_LINEARPOSITIONCNTR_LOW);
255 			break;
256 		case I2S_HS_INSTANCE:
257 			high = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_HIGH);
258 			low = readl(adata->acp_base + ACP_HS_RX_LINEARPOSITIONCNTR_LOW);
259 			break;
260 		case DMIC_INSTANCE:
261 			high = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_HIGH);
262 			low = readl(adata->acp_base + ACP_WOV_RX_LINEARPOSITIONCNTR_LOW);
263 			break;
264 		default:
265 			dev_err(adata->dev, "Invalid dai id %x\n", dai_id);
266 			goto POINTER_RETURN_BYTES;
267 		}
268 	}
269 	/* Get 64 bit value from two 32 bit registers */
270 	byte_count = (high << 32) | low;
271 
272 POINTER_RETURN_BYTES:
273 	return byte_count;
274 }
275 
acp_set_i2s_clk(struct acp_dev_data * adata,int dai_id)276 static inline void acp_set_i2s_clk(struct acp_dev_data *adata, int dai_id)
277 {
278 	union acp_i2stdm_mstrclkgen mclkgen;
279 	u32 master_reg;
280 
281 	switch (dai_id) {
282 	case I2S_SP_INSTANCE:
283 		master_reg = ACP_I2STDM0_MSTRCLKGEN;
284 		break;
285 	case I2S_BT_INSTANCE:
286 		master_reg = ACP_I2STDM1_MSTRCLKGEN;
287 		break;
288 	case I2S_HS_INSTANCE:
289 		master_reg = ACP_I2STDM2_MSTRCLKGEN;
290 		break;
291 	default:
292 		master_reg = ACP_I2STDM0_MSTRCLKGEN;
293 		break;
294 	}
295 
296 	mclkgen.bits.i2stdm_master_mode = 0x1;
297 	mclkgen.bits.i2stdm_format_mode = 0x00;
298 
299 	mclkgen.bits.i2stdm_bclk_div_val = adata->bclk_div;
300 	mclkgen.bits.i2stdm_lrclk_div_val = adata->lrclk_div;
301 	writel(mclkgen.u32_all, adata->acp_base + master_reg);
302 }
303 #endif
304