1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
4 *
5 * Copyright (C) 2002 - 2011 Paul Mundt
6 * Copyright (C) 2015 Glider bvba
7 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
8 *
9 * based off of the old drivers/char/sh-sci.c by:
10 *
11 * Copyright (C) 1999, 2000 Niibe Yutaka
12 * Copyright (C) 2000 Sugioka Toshinobu
13 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
14 * Modified to support SecureEdge. David McCullough (2002)
15 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
16 * Removed SH7300 support (Jul 2007).
17 */
18 #undef DEBUG
19
20 #include <linux/clk.h>
21 #include <linux/console.h>
22 #include <linux/ctype.h>
23 #include <linux/cpufreq.h>
24 #include <linux/delay.h>
25 #include <linux/dmaengine.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/err.h>
28 #include <linux/errno.h>
29 #include <linux/init.h>
30 #include <linux/interrupt.h>
31 #include <linux/ioport.h>
32 #include <linux/ktime.h>
33 #include <linux/major.h>
34 #include <linux/minmax.h>
35 #include <linux/module.h>
36 #include <linux/mm.h>
37 #include <linux/of.h>
38 #include <linux/platform_device.h>
39 #include <linux/pm_runtime.h>
40 #include <linux/reset.h>
41 #include <linux/scatterlist.h>
42 #include <linux/serial.h>
43 #include <linux/serial_sci.h>
44 #include <linux/sh_dma.h>
45 #include <linux/slab.h>
46 #include <linux/string.h>
47 #include <linux/sysrq.h>
48 #include <linux/timer.h>
49 #include <linux/tty.h>
50 #include <linux/tty_flip.h>
51
52 #ifdef CONFIG_SUPERH
53 #include <asm/sh_bios.h>
54 #include <asm/platform_early.h>
55 #endif
56
57 #include "serial_mctrl_gpio.h"
58 #include "sh-sci.h"
59
60 /* Offsets into the sci_port->irqs array */
61 enum {
62 SCIx_ERI_IRQ,
63 SCIx_RXI_IRQ,
64 SCIx_TXI_IRQ,
65 SCIx_BRI_IRQ,
66 SCIx_DRI_IRQ,
67 SCIx_TEI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71 };
72
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79 enum SCI_CLKS {
80 SCI_FCK, /* Functional Clock */
81 SCI_SCK, /* Optional External Clock */
82 SCI_BRG_INT, /* Optional BRG Internal Clock Source */
83 SCI_SCIF_CLK, /* Optional BRG External Clock Source */
84 SCI_NUM_CLKS
85 };
86
87 /* Bit x set means sampling rate x + 1 is supported */
88 #define SCI_SR(x) BIT((x) - 1)
89 #define SCI_SR_RANGE(x, y) GENMASK((y) - 1, (x) - 1)
90
91 #define SCI_SR_SCIFAB SCI_SR(5) | SCI_SR(7) | SCI_SR(11) | \
92 SCI_SR(13) | SCI_SR(16) | SCI_SR(17) | \
93 SCI_SR(19) | SCI_SR(27)
94
95 #define min_sr(_port) ffs((_port)->sampling_rate_mask)
96 #define max_sr(_port) fls((_port)->sampling_rate_mask)
97
98 /* Iterate over all supported sampling rates, from high to low */
99 #define for_each_sr(_sr, _port) \
100 for ((_sr) = max_sr(_port); (_sr) >= min_sr(_port); (_sr)--) \
101 if ((_port)->sampling_rate_mask & SCI_SR((_sr)))
102
103 struct plat_sci_reg {
104 u8 offset, size;
105 };
106
107 struct sci_suspend_regs {
108 u16 scdl;
109 u16 sccks;
110 u16 scsmr;
111 u16 scscr;
112 u16 scfcr;
113 u16 scsptr;
114 u16 hssrr;
115 u16 scpcr;
116 u16 scpdr;
117 u8 scbrr;
118 u8 semr;
119 };
120
121 struct sci_port_params {
122 const struct plat_sci_reg regs[SCIx_NR_REGS];
123 unsigned int fifosize;
124 unsigned int overrun_reg;
125 unsigned int overrun_mask;
126 unsigned int sampling_rate_mask;
127 unsigned int error_mask;
128 unsigned int error_clear;
129 };
130
131 struct sci_port {
132 struct uart_port port;
133
134 /* Platform configuration */
135 const struct sci_port_params *params;
136 const struct plat_sci_port *cfg;
137 unsigned int sampling_rate_mask;
138 resource_size_t reg_size;
139 struct mctrl_gpios *gpios;
140
141 /* Clocks */
142 struct clk *clks[SCI_NUM_CLKS];
143 unsigned long clk_rates[SCI_NUM_CLKS];
144
145 int irqs[SCIx_NR_IRQS];
146 char *irqstr[SCIx_NR_IRQS];
147
148 struct dma_chan *chan_tx;
149 struct dma_chan *chan_rx;
150
151 struct reset_control *rstc;
152
153 #ifdef CONFIG_SERIAL_SH_SCI_DMA
154 struct dma_chan *chan_tx_saved;
155 struct dma_chan *chan_rx_saved;
156 dma_cookie_t cookie_tx;
157 dma_cookie_t cookie_rx[2];
158 dma_cookie_t active_rx;
159 dma_addr_t tx_dma_addr;
160 unsigned int tx_dma_len;
161 struct scatterlist sg_rx[2];
162 void *rx_buf[2];
163 size_t buf_len_rx;
164 struct work_struct work_tx;
165 struct hrtimer rx_timer;
166 unsigned int rx_timeout; /* microseconds */
167 #endif
168 unsigned int rx_frame;
169 int rx_trigger;
170 struct timer_list rx_fifo_timer;
171 int rx_fifo_timeout;
172 struct sci_suspend_regs suspend_regs;
173 u16 hscif_tot;
174
175 bool has_rtscts;
176 bool autorts;
177 bool tx_occurred;
178 };
179
180 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
181
182 static struct sci_port sci_ports[SCI_NPORTS];
183 static unsigned long sci_ports_in_use;
184 static struct uart_driver sci_uart_driver;
185 static bool sci_uart_earlycon;
186 static bool sci_uart_earlycon_dev_probing;
187
188 static inline struct sci_port *
to_sci_port(struct uart_port * uart)189 to_sci_port(struct uart_port *uart)
190 {
191 return container_of(uart, struct sci_port, port);
192 }
193
194 static const struct sci_port_params sci_port_params[SCIx_NR_REGTYPES] = {
195 /*
196 * Common SCI definitions, dependent on the port's regshift
197 * value.
198 */
199 [SCIx_SCI_REGTYPE] = {
200 .regs = {
201 [SCSMR] = { 0x00, 8 },
202 [SCBRR] = { 0x01, 8 },
203 [SCSCR] = { 0x02, 8 },
204 [SCxTDR] = { 0x03, 8 },
205 [SCxSR] = { 0x04, 8 },
206 [SCxRDR] = { 0x05, 8 },
207 },
208 .fifosize = 1,
209 .overrun_reg = SCxSR,
210 .overrun_mask = SCI_ORER,
211 .sampling_rate_mask = SCI_SR(32),
212 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
213 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
214 },
215
216 /*
217 * Common definitions for legacy IrDA ports.
218 */
219 [SCIx_IRDA_REGTYPE] = {
220 .regs = {
221 [SCSMR] = { 0x00, 8 },
222 [SCBRR] = { 0x02, 8 },
223 [SCSCR] = { 0x04, 8 },
224 [SCxTDR] = { 0x06, 8 },
225 [SCxSR] = { 0x08, 16 },
226 [SCxRDR] = { 0x0a, 8 },
227 [SCFCR] = { 0x0c, 8 },
228 [SCFDR] = { 0x0e, 16 },
229 },
230 .fifosize = 1,
231 .overrun_reg = SCxSR,
232 .overrun_mask = SCI_ORER,
233 .sampling_rate_mask = SCI_SR(32),
234 .error_mask = SCI_DEFAULT_ERROR_MASK | SCI_ORER,
235 .error_clear = SCI_ERROR_CLEAR & ~SCI_ORER,
236 },
237
238 /*
239 * Common SCIFA definitions.
240 */
241 [SCIx_SCIFA_REGTYPE] = {
242 .regs = {
243 [SCSMR] = { 0x00, 16 },
244 [SCBRR] = { 0x04, 8 },
245 [SCSCR] = { 0x08, 16 },
246 [SCxTDR] = { 0x20, 8 },
247 [SCxSR] = { 0x14, 16 },
248 [SCxRDR] = { 0x24, 8 },
249 [SCFCR] = { 0x18, 16 },
250 [SCFDR] = { 0x1c, 16 },
251 [SCPCR] = { 0x30, 16 },
252 [SCPDR] = { 0x34, 16 },
253 },
254 .fifosize = 64,
255 .overrun_reg = SCxSR,
256 .overrun_mask = SCIFA_ORER,
257 .sampling_rate_mask = SCI_SR_SCIFAB,
258 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
259 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
260 },
261
262 /*
263 * Common SCIFB definitions.
264 */
265 [SCIx_SCIFB_REGTYPE] = {
266 .regs = {
267 [SCSMR] = { 0x00, 16 },
268 [SCBRR] = { 0x04, 8 },
269 [SCSCR] = { 0x08, 16 },
270 [SCxTDR] = { 0x40, 8 },
271 [SCxSR] = { 0x14, 16 },
272 [SCxRDR] = { 0x60, 8 },
273 [SCFCR] = { 0x18, 16 },
274 [SCTFDR] = { 0x38, 16 },
275 [SCRFDR] = { 0x3c, 16 },
276 [SCPCR] = { 0x30, 16 },
277 [SCPDR] = { 0x34, 16 },
278 },
279 .fifosize = 256,
280 .overrun_reg = SCxSR,
281 .overrun_mask = SCIFA_ORER,
282 .sampling_rate_mask = SCI_SR_SCIFAB,
283 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
284 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
285 },
286
287 /*
288 * Common SH-2(A) SCIF definitions for ports with FIFO data
289 * count registers.
290 */
291 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
292 .regs = {
293 [SCSMR] = { 0x00, 16 },
294 [SCBRR] = { 0x04, 8 },
295 [SCSCR] = { 0x08, 16 },
296 [SCxTDR] = { 0x0c, 8 },
297 [SCxSR] = { 0x10, 16 },
298 [SCxRDR] = { 0x14, 8 },
299 [SCFCR] = { 0x18, 16 },
300 [SCFDR] = { 0x1c, 16 },
301 [SCSPTR] = { 0x20, 16 },
302 [SCLSR] = { 0x24, 16 },
303 },
304 .fifosize = 16,
305 .overrun_reg = SCLSR,
306 .overrun_mask = SCLSR_ORER,
307 .sampling_rate_mask = SCI_SR(32),
308 .error_mask = SCIF_DEFAULT_ERROR_MASK,
309 .error_clear = SCIF_ERROR_CLEAR,
310 },
311
312 /*
313 * The "SCIFA" that is in RZ/A2, RZ/G2L and RZ/T.
314 * It looks like a normal SCIF with FIFO data, but with a
315 * compressed address space. Also, the break out of interrupts
316 * are different: ERI/BRI, RXI, TXI, TEI, DRI.
317 */
318 [SCIx_RZ_SCIFA_REGTYPE] = {
319 .regs = {
320 [SCSMR] = { 0x00, 16 },
321 [SCBRR] = { 0x02, 8 },
322 [SCSCR] = { 0x04, 16 },
323 [SCxTDR] = { 0x06, 8 },
324 [SCxSR] = { 0x08, 16 },
325 [SCxRDR] = { 0x0A, 8 },
326 [SCFCR] = { 0x0C, 16 },
327 [SCFDR] = { 0x0E, 16 },
328 [SCSPTR] = { 0x10, 16 },
329 [SCLSR] = { 0x12, 16 },
330 [SEMR] = { 0x14, 8 },
331 },
332 .fifosize = 16,
333 .overrun_reg = SCLSR,
334 .overrun_mask = SCLSR_ORER,
335 .sampling_rate_mask = SCI_SR(32),
336 .error_mask = SCIF_DEFAULT_ERROR_MASK,
337 .error_clear = SCIF_ERROR_CLEAR,
338 },
339
340 /*
341 * Common SH-3 SCIF definitions.
342 */
343 [SCIx_SH3_SCIF_REGTYPE] = {
344 .regs = {
345 [SCSMR] = { 0x00, 8 },
346 [SCBRR] = { 0x02, 8 },
347 [SCSCR] = { 0x04, 8 },
348 [SCxTDR] = { 0x06, 8 },
349 [SCxSR] = { 0x08, 16 },
350 [SCxRDR] = { 0x0a, 8 },
351 [SCFCR] = { 0x0c, 8 },
352 [SCFDR] = { 0x0e, 16 },
353 },
354 .fifosize = 16,
355 .overrun_reg = SCLSR,
356 .overrun_mask = SCLSR_ORER,
357 .sampling_rate_mask = SCI_SR(32),
358 .error_mask = SCIF_DEFAULT_ERROR_MASK,
359 .error_clear = SCIF_ERROR_CLEAR,
360 },
361
362 /*
363 * Common SH-4(A) SCIF(B) definitions.
364 */
365 [SCIx_SH4_SCIF_REGTYPE] = {
366 .regs = {
367 [SCSMR] = { 0x00, 16 },
368 [SCBRR] = { 0x04, 8 },
369 [SCSCR] = { 0x08, 16 },
370 [SCxTDR] = { 0x0c, 8 },
371 [SCxSR] = { 0x10, 16 },
372 [SCxRDR] = { 0x14, 8 },
373 [SCFCR] = { 0x18, 16 },
374 [SCFDR] = { 0x1c, 16 },
375 [SCSPTR] = { 0x20, 16 },
376 [SCLSR] = { 0x24, 16 },
377 },
378 .fifosize = 16,
379 .overrun_reg = SCLSR,
380 .overrun_mask = SCLSR_ORER,
381 .sampling_rate_mask = SCI_SR(32),
382 .error_mask = SCIF_DEFAULT_ERROR_MASK,
383 .error_clear = SCIF_ERROR_CLEAR,
384 },
385
386 /*
387 * Common SCIF definitions for ports with a Baud Rate Generator for
388 * External Clock (BRG).
389 */
390 [SCIx_SH4_SCIF_BRG_REGTYPE] = {
391 .regs = {
392 [SCSMR] = { 0x00, 16 },
393 [SCBRR] = { 0x04, 8 },
394 [SCSCR] = { 0x08, 16 },
395 [SCxTDR] = { 0x0c, 8 },
396 [SCxSR] = { 0x10, 16 },
397 [SCxRDR] = { 0x14, 8 },
398 [SCFCR] = { 0x18, 16 },
399 [SCFDR] = { 0x1c, 16 },
400 [SCSPTR] = { 0x20, 16 },
401 [SCLSR] = { 0x24, 16 },
402 [SCDL] = { 0x30, 16 },
403 [SCCKS] = { 0x34, 16 },
404 },
405 .fifosize = 16,
406 .overrun_reg = SCLSR,
407 .overrun_mask = SCLSR_ORER,
408 .sampling_rate_mask = SCI_SR(32),
409 .error_mask = SCIF_DEFAULT_ERROR_MASK,
410 .error_clear = SCIF_ERROR_CLEAR,
411 },
412
413 /*
414 * Common HSCIF definitions.
415 */
416 [SCIx_HSCIF_REGTYPE] = {
417 .regs = {
418 [SCSMR] = { 0x00, 16 },
419 [SCBRR] = { 0x04, 8 },
420 [SCSCR] = { 0x08, 16 },
421 [SCxTDR] = { 0x0c, 8 },
422 [SCxSR] = { 0x10, 16 },
423 [SCxRDR] = { 0x14, 8 },
424 [SCFCR] = { 0x18, 16 },
425 [SCFDR] = { 0x1c, 16 },
426 [SCSPTR] = { 0x20, 16 },
427 [SCLSR] = { 0x24, 16 },
428 [HSSRR] = { 0x40, 16 },
429 [SCDL] = { 0x30, 16 },
430 [SCCKS] = { 0x34, 16 },
431 [HSRTRGR] = { 0x54, 16 },
432 [HSTTRGR] = { 0x58, 16 },
433 },
434 .fifosize = 128,
435 .overrun_reg = SCLSR,
436 .overrun_mask = SCLSR_ORER,
437 .sampling_rate_mask = SCI_SR_RANGE(8, 32),
438 .error_mask = SCIF_DEFAULT_ERROR_MASK,
439 .error_clear = SCIF_ERROR_CLEAR,
440 },
441
442 /*
443 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
444 * register.
445 */
446 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
447 .regs = {
448 [SCSMR] = { 0x00, 16 },
449 [SCBRR] = { 0x04, 8 },
450 [SCSCR] = { 0x08, 16 },
451 [SCxTDR] = { 0x0c, 8 },
452 [SCxSR] = { 0x10, 16 },
453 [SCxRDR] = { 0x14, 8 },
454 [SCFCR] = { 0x18, 16 },
455 [SCFDR] = { 0x1c, 16 },
456 [SCLSR] = { 0x24, 16 },
457 },
458 .fifosize = 16,
459 .overrun_reg = SCLSR,
460 .overrun_mask = SCLSR_ORER,
461 .sampling_rate_mask = SCI_SR(32),
462 .error_mask = SCIF_DEFAULT_ERROR_MASK,
463 .error_clear = SCIF_ERROR_CLEAR,
464 },
465
466 /*
467 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
468 * count registers.
469 */
470 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
471 .regs = {
472 [SCSMR] = { 0x00, 16 },
473 [SCBRR] = { 0x04, 8 },
474 [SCSCR] = { 0x08, 16 },
475 [SCxTDR] = { 0x0c, 8 },
476 [SCxSR] = { 0x10, 16 },
477 [SCxRDR] = { 0x14, 8 },
478 [SCFCR] = { 0x18, 16 },
479 [SCFDR] = { 0x1c, 16 },
480 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
481 [SCRFDR] = { 0x20, 16 },
482 [SCSPTR] = { 0x24, 16 },
483 [SCLSR] = { 0x28, 16 },
484 },
485 .fifosize = 16,
486 .overrun_reg = SCLSR,
487 .overrun_mask = SCLSR_ORER,
488 .sampling_rate_mask = SCI_SR(32),
489 .error_mask = SCIF_DEFAULT_ERROR_MASK,
490 .error_clear = SCIF_ERROR_CLEAR,
491 },
492
493 /*
494 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
495 * registers.
496 */
497 [SCIx_SH7705_SCIF_REGTYPE] = {
498 .regs = {
499 [SCSMR] = { 0x00, 16 },
500 [SCBRR] = { 0x04, 8 },
501 [SCSCR] = { 0x08, 16 },
502 [SCxTDR] = { 0x20, 8 },
503 [SCxSR] = { 0x14, 16 },
504 [SCxRDR] = { 0x24, 8 },
505 [SCFCR] = { 0x18, 16 },
506 [SCFDR] = { 0x1c, 16 },
507 },
508 .fifosize = 64,
509 .overrun_reg = SCxSR,
510 .overrun_mask = SCIFA_ORER,
511 .sampling_rate_mask = SCI_SR(16),
512 .error_mask = SCIF_DEFAULT_ERROR_MASK | SCIFA_ORER,
513 .error_clear = SCIF_ERROR_CLEAR & ~SCIFA_ORER,
514 },
515 };
516
517 #define sci_getreg(up, offset) (&to_sci_port(up)->params->regs[offset])
518
519 /*
520 * The "offset" here is rather misleading, in that it refers to an enum
521 * value relative to the port mapping rather than the fixed offset
522 * itself, which needs to be manually retrieved from the platform's
523 * register map for the given port.
524 */
sci_serial_in(struct uart_port * p,int offset)525 static unsigned int sci_serial_in(struct uart_port *p, int offset)
526 {
527 const struct plat_sci_reg *reg = sci_getreg(p, offset);
528
529 if (reg->size == 8)
530 return ioread8(p->membase + (reg->offset << p->regshift));
531 else if (reg->size == 16)
532 return ioread16(p->membase + (reg->offset << p->regshift));
533 else
534 WARN(1, "Invalid register access\n");
535
536 return 0;
537 }
538
sci_serial_out(struct uart_port * p,int offset,int value)539 static void sci_serial_out(struct uart_port *p, int offset, int value)
540 {
541 const struct plat_sci_reg *reg = sci_getreg(p, offset);
542
543 if (reg->size == 8)
544 iowrite8(value, p->membase + (reg->offset << p->regshift));
545 else if (reg->size == 16)
546 iowrite16(value, p->membase + (reg->offset << p->regshift));
547 else
548 WARN(1, "Invalid register access\n");
549 }
550
sci_port_enable(struct sci_port * sci_port)551 static void sci_port_enable(struct sci_port *sci_port)
552 {
553 unsigned int i;
554
555 if (!sci_port->port.dev)
556 return;
557
558 pm_runtime_get_sync(sci_port->port.dev);
559
560 for (i = 0; i < SCI_NUM_CLKS; i++) {
561 clk_prepare_enable(sci_port->clks[i]);
562 sci_port->clk_rates[i] = clk_get_rate(sci_port->clks[i]);
563 }
564 sci_port->port.uartclk = sci_port->clk_rates[SCI_FCK];
565 }
566
sci_port_disable(struct sci_port * sci_port)567 static void sci_port_disable(struct sci_port *sci_port)
568 {
569 unsigned int i;
570
571 if (!sci_port->port.dev)
572 return;
573
574 for (i = SCI_NUM_CLKS; i-- > 0; )
575 clk_disable_unprepare(sci_port->clks[i]);
576
577 pm_runtime_put_sync(sci_port->port.dev);
578 }
579
port_rx_irq_mask(struct uart_port * port)580 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
581 {
582 /*
583 * Not all ports (such as SCIFA) will support REIE. Rather than
584 * special-casing the port type, we check the port initialization
585 * IRQ enable mask to see whether the IRQ is desired at all. If
586 * it's unset, it's logically inferred that there's no point in
587 * testing for it.
588 */
589 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
590 }
591
sci_start_tx(struct uart_port * port)592 static void sci_start_tx(struct uart_port *port)
593 {
594 struct sci_port *s = to_sci_port(port);
595 unsigned short ctrl;
596
597 #ifdef CONFIG_SERIAL_SH_SCI_DMA
598 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
599 u16 new, scr = serial_port_in(port, SCSCR);
600 if (s->chan_tx)
601 new = scr | SCSCR_TDRQE;
602 else
603 new = scr & ~SCSCR_TDRQE;
604 if (new != scr)
605 serial_port_out(port, SCSCR, new);
606 }
607
608 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
609 dma_submit_error(s->cookie_tx)) {
610 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
611 /* Switch irq from SCIF to DMA */
612 disable_irq_nosync(s->irqs[SCIx_TXI_IRQ]);
613
614 s->cookie_tx = 0;
615 schedule_work(&s->work_tx);
616 }
617 #endif
618
619 if (!s->chan_tx || s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE ||
620 port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
621 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
622 ctrl = serial_port_in(port, SCSCR);
623
624 /*
625 * For SCI, TE (transmit enable) must be set after setting TIE
626 * (transmit interrupt enable) or in the same instruction to start
627 * the transmit process.
628 */
629 if (port->type == PORT_SCI)
630 ctrl |= SCSCR_TE;
631
632 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
633 }
634 }
635
sci_stop_tx(struct uart_port * port)636 static void sci_stop_tx(struct uart_port *port)
637 {
638 unsigned short ctrl;
639
640 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
641 ctrl = serial_port_in(port, SCSCR);
642
643 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
644 ctrl &= ~SCSCR_TDRQE;
645
646 ctrl &= ~SCSCR_TIE;
647
648 serial_port_out(port, SCSCR, ctrl);
649
650 #ifdef CONFIG_SERIAL_SH_SCI_DMA
651 if (to_sci_port(port)->chan_tx &&
652 !dma_submit_error(to_sci_port(port)->cookie_tx)) {
653 dmaengine_terminate_async(to_sci_port(port)->chan_tx);
654 to_sci_port(port)->cookie_tx = -EINVAL;
655 }
656 #endif
657 }
658
sci_start_rx(struct uart_port * port)659 static void sci_start_rx(struct uart_port *port)
660 {
661 unsigned short ctrl;
662
663 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
664
665 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
666 ctrl &= ~SCSCR_RDRQE;
667
668 serial_port_out(port, SCSCR, ctrl);
669 }
670
sci_stop_rx(struct uart_port * port)671 static void sci_stop_rx(struct uart_port *port)
672 {
673 unsigned short ctrl;
674
675 ctrl = serial_port_in(port, SCSCR);
676
677 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
678 ctrl &= ~SCSCR_RDRQE;
679
680 ctrl &= ~port_rx_irq_mask(port);
681
682 serial_port_out(port, SCSCR, ctrl);
683 }
684
sci_clear_SCxSR(struct uart_port * port,unsigned int mask)685 static void sci_clear_SCxSR(struct uart_port *port, unsigned int mask)
686 {
687 if (port->type == PORT_SCI) {
688 /* Just store the mask */
689 serial_port_out(port, SCxSR, mask);
690 } else if (to_sci_port(port)->params->overrun_mask == SCIFA_ORER) {
691 /* SCIFA/SCIFB and SCIF on SH7705/SH7720/SH7721 */
692 /* Only clear the status bits we want to clear */
693 serial_port_out(port, SCxSR,
694 serial_port_in(port, SCxSR) & mask);
695 } else {
696 /* Store the mask, clear parity/framing errors */
697 serial_port_out(port, SCxSR, mask & ~(SCIF_FERC | SCIF_PERC));
698 }
699 }
700
701 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
702 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
703
704 #ifdef CONFIG_CONSOLE_POLL
sci_poll_get_char(struct uart_port * port)705 static int sci_poll_get_char(struct uart_port *port)
706 {
707 unsigned short status;
708 int c;
709
710 do {
711 status = serial_port_in(port, SCxSR);
712 if (status & SCxSR_ERRORS(port)) {
713 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
714 continue;
715 }
716 break;
717 } while (1);
718
719 if (!(status & SCxSR_RDxF(port)))
720 return NO_POLL_CHAR;
721
722 c = serial_port_in(port, SCxRDR);
723
724 /* Dummy read */
725 serial_port_in(port, SCxSR);
726 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
727
728 return c;
729 }
730 #endif
731
sci_poll_put_char(struct uart_port * port,unsigned char c)732 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
733 {
734 unsigned short status;
735
736 do {
737 status = serial_port_in(port, SCxSR);
738 } while (!(status & SCxSR_TDxE(port)));
739
740 serial_port_out(port, SCxTDR, c);
741 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
742 }
743 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE ||
744 CONFIG_SERIAL_SH_SCI_EARLYCON */
745
sci_init_pins(struct uart_port * port,unsigned int cflag)746 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
747 {
748 struct sci_port *s = to_sci_port(port);
749
750 /*
751 * Use port-specific handler if provided.
752 */
753 if (s->cfg->ops && s->cfg->ops->init_pins) {
754 s->cfg->ops->init_pins(port, cflag);
755 return;
756 }
757
758 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
759 u16 data = serial_port_in(port, SCPDR);
760 u16 ctrl = serial_port_in(port, SCPCR);
761
762 /* Enable RXD and TXD pin functions */
763 ctrl &= ~(SCPCR_RXDC | SCPCR_TXDC);
764 if (to_sci_port(port)->has_rtscts) {
765 /* RTS# is output, active low, unless autorts */
766 if (!(port->mctrl & TIOCM_RTS)) {
767 ctrl |= SCPCR_RTSC;
768 data |= SCPDR_RTSD;
769 } else if (!s->autorts) {
770 ctrl |= SCPCR_RTSC;
771 data &= ~SCPDR_RTSD;
772 } else {
773 /* Enable RTS# pin function */
774 ctrl &= ~SCPCR_RTSC;
775 }
776 /* Enable CTS# pin function */
777 ctrl &= ~SCPCR_CTSC;
778 }
779 serial_port_out(port, SCPDR, data);
780 serial_port_out(port, SCPCR, ctrl);
781 } else if (sci_getreg(port, SCSPTR)->size) {
782 u16 status = serial_port_in(port, SCSPTR);
783
784 /* RTS# is always output; and active low, unless autorts */
785 status |= SCSPTR_RTSIO;
786 if (!(port->mctrl & TIOCM_RTS))
787 status |= SCSPTR_RTSDT;
788 else if (!s->autorts)
789 status &= ~SCSPTR_RTSDT;
790 /* CTS# and SCK are inputs */
791 status &= ~(SCSPTR_CTSIO | SCSPTR_SCKIO);
792 serial_port_out(port, SCSPTR, status);
793 }
794 }
795
sci_txfill(struct uart_port * port)796 static int sci_txfill(struct uart_port *port)
797 {
798 struct sci_port *s = to_sci_port(port);
799 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
800 const struct plat_sci_reg *reg;
801
802 reg = sci_getreg(port, SCTFDR);
803 if (reg->size)
804 return serial_port_in(port, SCTFDR) & fifo_mask;
805
806 reg = sci_getreg(port, SCFDR);
807 if (reg->size)
808 return serial_port_in(port, SCFDR) >> 8;
809
810 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
811 }
812
sci_txroom(struct uart_port * port)813 static int sci_txroom(struct uart_port *port)
814 {
815 return port->fifosize - sci_txfill(port);
816 }
817
sci_rxfill(struct uart_port * port)818 static int sci_rxfill(struct uart_port *port)
819 {
820 struct sci_port *s = to_sci_port(port);
821 unsigned int fifo_mask = (s->params->fifosize << 1) - 1;
822 const struct plat_sci_reg *reg;
823
824 reg = sci_getreg(port, SCRFDR);
825 if (reg->size)
826 return serial_port_in(port, SCRFDR) & fifo_mask;
827
828 reg = sci_getreg(port, SCFDR);
829 if (reg->size)
830 return serial_port_in(port, SCFDR) & fifo_mask;
831
832 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
833 }
834
835 /* ********************************************************************** *
836 * the interrupt related routines *
837 * ********************************************************************** */
838
sci_transmit_chars(struct uart_port * port)839 static void sci_transmit_chars(struct uart_port *port)
840 {
841 struct circ_buf *xmit = &port->state->xmit;
842 unsigned int stopped = uart_tx_stopped(port);
843 struct sci_port *s = to_sci_port(port);
844 unsigned short status;
845 unsigned short ctrl;
846 int count;
847
848 status = serial_port_in(port, SCxSR);
849 if (!(status & SCxSR_TDxE(port))) {
850 ctrl = serial_port_in(port, SCSCR);
851 if (uart_circ_empty(xmit))
852 ctrl &= ~SCSCR_TIE;
853 else
854 ctrl |= SCSCR_TIE;
855 serial_port_out(port, SCSCR, ctrl);
856 return;
857 }
858
859 count = sci_txroom(port);
860
861 do {
862 unsigned char c;
863
864 if (port->x_char) {
865 c = port->x_char;
866 port->x_char = 0;
867 } else if (!uart_circ_empty(xmit) && !stopped) {
868 c = xmit->buf[xmit->tail];
869 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
870 } else if (port->type == PORT_SCI && uart_circ_empty(xmit)) {
871 ctrl = serial_port_in(port, SCSCR);
872 ctrl &= ~SCSCR_TE;
873 serial_port_out(port, SCSCR, ctrl);
874 return;
875 } else {
876 break;
877 }
878
879 serial_port_out(port, SCxTDR, c);
880 s->tx_occurred = true;
881
882 port->icount.tx++;
883 } while (--count > 0);
884
885 sci_clear_SCxSR(port, SCxSR_TDxE_CLEAR(port));
886
887 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
888 uart_write_wakeup(port);
889 if (uart_circ_empty(xmit)) {
890 if (port->type == PORT_SCI) {
891 ctrl = serial_port_in(port, SCSCR);
892 ctrl &= ~SCSCR_TIE;
893 ctrl |= SCSCR_TEIE;
894 serial_port_out(port, SCSCR, ctrl);
895 }
896
897 sci_stop_tx(port);
898 }
899 }
900
sci_receive_chars(struct uart_port * port)901 static void sci_receive_chars(struct uart_port *port)
902 {
903 struct tty_port *tport = &port->state->port;
904 int i, count, copied = 0;
905 unsigned short status;
906 unsigned char flag;
907
908 status = serial_port_in(port, SCxSR);
909 if (!(status & SCxSR_RDxF(port)))
910 return;
911
912 while (1) {
913 /* Don't copy more bytes than there is room for in the buffer */
914 count = tty_buffer_request_room(tport, sci_rxfill(port));
915
916 /* If for any reason we can't copy more data, we're done! */
917 if (count == 0)
918 break;
919
920 if (port->type == PORT_SCI) {
921 char c = serial_port_in(port, SCxRDR);
922 if (uart_handle_sysrq_char(port, c))
923 count = 0;
924 else
925 tty_insert_flip_char(tport, c, TTY_NORMAL);
926 } else {
927 for (i = 0; i < count; i++) {
928 char c;
929
930 if (port->type == PORT_SCIF ||
931 port->type == PORT_HSCIF) {
932 status = serial_port_in(port, SCxSR);
933 c = serial_port_in(port, SCxRDR);
934 } else {
935 c = serial_port_in(port, SCxRDR);
936 status = serial_port_in(port, SCxSR);
937 }
938 if (uart_handle_sysrq_char(port, c)) {
939 count--; i--;
940 continue;
941 }
942
943 /* Store data and status */
944 if (status & SCxSR_FER(port)) {
945 flag = TTY_FRAME;
946 port->icount.frame++;
947 } else if (status & SCxSR_PER(port)) {
948 flag = TTY_PARITY;
949 port->icount.parity++;
950 } else
951 flag = TTY_NORMAL;
952
953 tty_insert_flip_char(tport, c, flag);
954 }
955 }
956
957 serial_port_in(port, SCxSR); /* dummy read */
958 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
959
960 copied += count;
961 port->icount.rx += count;
962 }
963
964 if (copied) {
965 /* Tell the rest of the system the news. New characters! */
966 tty_flip_buffer_push(tport);
967 } else {
968 /* TTY buffers full; read from RX reg to prevent lockup */
969 serial_port_in(port, SCxRDR);
970 serial_port_in(port, SCxSR); /* dummy read */
971 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
972 }
973 }
974
sci_handle_errors(struct uart_port * port)975 static int sci_handle_errors(struct uart_port *port)
976 {
977 int copied = 0;
978 unsigned short status = serial_port_in(port, SCxSR);
979 struct tty_port *tport = &port->state->port;
980 struct sci_port *s = to_sci_port(port);
981
982 /* Handle overruns */
983 if (status & s->params->overrun_mask) {
984 port->icount.overrun++;
985
986 /* overrun error */
987 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
988 copied++;
989 }
990
991 if (status & SCxSR_FER(port)) {
992 /* frame error */
993 port->icount.frame++;
994
995 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
996 copied++;
997 }
998
999 if (status & SCxSR_PER(port)) {
1000 /* parity error */
1001 port->icount.parity++;
1002
1003 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
1004 copied++;
1005 }
1006
1007 if (copied)
1008 tty_flip_buffer_push(tport);
1009
1010 return copied;
1011 }
1012
sci_handle_fifo_overrun(struct uart_port * port)1013 static int sci_handle_fifo_overrun(struct uart_port *port)
1014 {
1015 struct tty_port *tport = &port->state->port;
1016 struct sci_port *s = to_sci_port(port);
1017 const struct plat_sci_reg *reg;
1018 int copied = 0;
1019 u16 status;
1020
1021 reg = sci_getreg(port, s->params->overrun_reg);
1022 if (!reg->size)
1023 return 0;
1024
1025 status = serial_port_in(port, s->params->overrun_reg);
1026 if (status & s->params->overrun_mask) {
1027 status &= ~s->params->overrun_mask;
1028 serial_port_out(port, s->params->overrun_reg, status);
1029
1030 port->icount.overrun++;
1031
1032 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1033 tty_flip_buffer_push(tport);
1034 copied++;
1035 }
1036
1037 return copied;
1038 }
1039
sci_handle_breaks(struct uart_port * port)1040 static int sci_handle_breaks(struct uart_port *port)
1041 {
1042 int copied = 0;
1043 unsigned short status = serial_port_in(port, SCxSR);
1044 struct tty_port *tport = &port->state->port;
1045
1046 if (uart_handle_break(port))
1047 return 0;
1048
1049 if (status & SCxSR_BRK(port)) {
1050 port->icount.brk++;
1051
1052 /* Notify of BREAK */
1053 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
1054 copied++;
1055 }
1056
1057 if (copied)
1058 tty_flip_buffer_push(tport);
1059
1060 copied += sci_handle_fifo_overrun(port);
1061
1062 return copied;
1063 }
1064
scif_set_rtrg(struct uart_port * port,int rx_trig)1065 static int scif_set_rtrg(struct uart_port *port, int rx_trig)
1066 {
1067 unsigned int bits;
1068
1069 if (rx_trig >= port->fifosize)
1070 rx_trig = port->fifosize - 1;
1071 if (rx_trig < 1)
1072 rx_trig = 1;
1073
1074 /* HSCIF can be set to an arbitrary level. */
1075 if (sci_getreg(port, HSRTRGR)->size) {
1076 serial_port_out(port, HSRTRGR, rx_trig);
1077 return rx_trig;
1078 }
1079
1080 switch (port->type) {
1081 case PORT_SCIF:
1082 if (rx_trig < 4) {
1083 bits = 0;
1084 rx_trig = 1;
1085 } else if (rx_trig < 8) {
1086 bits = SCFCR_RTRG0;
1087 rx_trig = 4;
1088 } else if (rx_trig < 14) {
1089 bits = SCFCR_RTRG1;
1090 rx_trig = 8;
1091 } else {
1092 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1093 rx_trig = 14;
1094 }
1095 break;
1096 case PORT_SCIFA:
1097 case PORT_SCIFB:
1098 if (rx_trig < 16) {
1099 bits = 0;
1100 rx_trig = 1;
1101 } else if (rx_trig < 32) {
1102 bits = SCFCR_RTRG0;
1103 rx_trig = 16;
1104 } else if (rx_trig < 48) {
1105 bits = SCFCR_RTRG1;
1106 rx_trig = 32;
1107 } else {
1108 bits = SCFCR_RTRG0 | SCFCR_RTRG1;
1109 rx_trig = 48;
1110 }
1111 break;
1112 default:
1113 WARN(1, "unknown FIFO configuration");
1114 return 1;
1115 }
1116
1117 serial_port_out(port, SCFCR,
1118 (serial_port_in(port, SCFCR) &
1119 ~(SCFCR_RTRG1 | SCFCR_RTRG0)) | bits);
1120
1121 return rx_trig;
1122 }
1123
scif_rtrg_enabled(struct uart_port * port)1124 static int scif_rtrg_enabled(struct uart_port *port)
1125 {
1126 if (sci_getreg(port, HSRTRGR)->size)
1127 return serial_port_in(port, HSRTRGR) != 0;
1128 else
1129 return (serial_port_in(port, SCFCR) &
1130 (SCFCR_RTRG0 | SCFCR_RTRG1)) != 0;
1131 }
1132
rx_fifo_timer_fn(struct timer_list * t)1133 static void rx_fifo_timer_fn(struct timer_list *t)
1134 {
1135 struct sci_port *s = from_timer(s, t, rx_fifo_timer);
1136 struct uart_port *port = &s->port;
1137
1138 dev_dbg(port->dev, "Rx timed out\n");
1139 scif_set_rtrg(port, 1);
1140 }
1141
rx_fifo_trigger_show(struct device * dev,struct device_attribute * attr,char * buf)1142 static ssize_t rx_fifo_trigger_show(struct device *dev,
1143 struct device_attribute *attr, char *buf)
1144 {
1145 struct uart_port *port = dev_get_drvdata(dev);
1146 struct sci_port *sci = to_sci_port(port);
1147
1148 return sprintf(buf, "%d\n", sci->rx_trigger);
1149 }
1150
rx_fifo_trigger_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1151 static ssize_t rx_fifo_trigger_store(struct device *dev,
1152 struct device_attribute *attr,
1153 const char *buf, size_t count)
1154 {
1155 struct uart_port *port = dev_get_drvdata(dev);
1156 struct sci_port *sci = to_sci_port(port);
1157 int ret;
1158 long r;
1159
1160 ret = kstrtol(buf, 0, &r);
1161 if (ret)
1162 return ret;
1163
1164 sci->rx_trigger = scif_set_rtrg(port, r);
1165 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1166 scif_set_rtrg(port, 1);
1167
1168 return count;
1169 }
1170
1171 static DEVICE_ATTR_RW(rx_fifo_trigger);
1172
rx_fifo_timeout_show(struct device * dev,struct device_attribute * attr,char * buf)1173 static ssize_t rx_fifo_timeout_show(struct device *dev,
1174 struct device_attribute *attr,
1175 char *buf)
1176 {
1177 struct uart_port *port = dev_get_drvdata(dev);
1178 struct sci_port *sci = to_sci_port(port);
1179 int v;
1180
1181 if (port->type == PORT_HSCIF)
1182 v = sci->hscif_tot >> HSSCR_TOT_SHIFT;
1183 else
1184 v = sci->rx_fifo_timeout;
1185
1186 return sprintf(buf, "%d\n", v);
1187 }
1188
rx_fifo_timeout_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)1189 static ssize_t rx_fifo_timeout_store(struct device *dev,
1190 struct device_attribute *attr,
1191 const char *buf,
1192 size_t count)
1193 {
1194 struct uart_port *port = dev_get_drvdata(dev);
1195 struct sci_port *sci = to_sci_port(port);
1196 int ret;
1197 long r;
1198
1199 ret = kstrtol(buf, 0, &r);
1200 if (ret)
1201 return ret;
1202
1203 if (port->type == PORT_HSCIF) {
1204 if (r < 0 || r > 3)
1205 return -EINVAL;
1206 sci->hscif_tot = r << HSSCR_TOT_SHIFT;
1207 } else {
1208 sci->rx_fifo_timeout = r;
1209 scif_set_rtrg(port, 1);
1210 if (r > 0)
1211 timer_setup(&sci->rx_fifo_timer, rx_fifo_timer_fn, 0);
1212 }
1213
1214 return count;
1215 }
1216
1217 static DEVICE_ATTR_RW(rx_fifo_timeout);
1218
1219
1220 #ifdef CONFIG_SERIAL_SH_SCI_DMA
sci_dma_tx_complete(void * arg)1221 static void sci_dma_tx_complete(void *arg)
1222 {
1223 struct sci_port *s = arg;
1224 struct uart_port *port = &s->port;
1225 struct circ_buf *xmit = &port->state->xmit;
1226 unsigned long flags;
1227
1228 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1229
1230 spin_lock_irqsave(&port->lock, flags);
1231
1232 uart_xmit_advance(port, s->tx_dma_len);
1233
1234 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1235 uart_write_wakeup(port);
1236
1237 s->tx_occurred = true;
1238
1239 if (!uart_circ_empty(xmit)) {
1240 s->cookie_tx = 0;
1241 schedule_work(&s->work_tx);
1242 } else {
1243 s->cookie_tx = -EINVAL;
1244 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1245 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1246 u16 ctrl = serial_port_in(port, SCSCR);
1247 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1248 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1249 /* Switch irq from DMA to SCIF */
1250 dmaengine_pause(s->chan_tx_saved);
1251 enable_irq(s->irqs[SCIx_TXI_IRQ]);
1252 }
1253 }
1254 }
1255
1256 spin_unlock_irqrestore(&port->lock, flags);
1257 }
1258
1259 /* Locking: called with port lock held */
sci_dma_rx_push(struct sci_port * s,void * buf,size_t count)1260 static int sci_dma_rx_push(struct sci_port *s, void *buf, size_t count)
1261 {
1262 struct uart_port *port = &s->port;
1263 struct tty_port *tport = &port->state->port;
1264 int copied;
1265
1266 copied = tty_insert_flip_string(tport, buf, count);
1267 if (copied < count)
1268 port->icount.buf_overrun++;
1269
1270 port->icount.rx += copied;
1271
1272 return copied;
1273 }
1274
sci_dma_rx_find_active(struct sci_port * s)1275 static int sci_dma_rx_find_active(struct sci_port *s)
1276 {
1277 unsigned int i;
1278
1279 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1280 if (s->active_rx == s->cookie_rx[i])
1281 return i;
1282
1283 return -1;
1284 }
1285
sci_dma_rx_chan_invalidate(struct sci_port * s)1286 static void sci_dma_rx_chan_invalidate(struct sci_port *s)
1287 {
1288 unsigned int i;
1289
1290 s->chan_rx = NULL;
1291 for (i = 0; i < ARRAY_SIZE(s->cookie_rx); i++)
1292 s->cookie_rx[i] = -EINVAL;
1293 s->active_rx = 0;
1294 }
1295
sci_dma_rx_release(struct sci_port * s)1296 static void sci_dma_rx_release(struct sci_port *s)
1297 {
1298 struct dma_chan *chan = s->chan_rx_saved;
1299 struct uart_port *port = &s->port;
1300 unsigned long flags;
1301
1302 uart_port_lock_irqsave(port, &flags);
1303 s->chan_rx_saved = NULL;
1304 sci_dma_rx_chan_invalidate(s);
1305 uart_port_unlock_irqrestore(port, flags);
1306
1307 dmaengine_terminate_sync(chan);
1308 dma_free_coherent(chan->device->dev, s->buf_len_rx * 2, s->rx_buf[0],
1309 sg_dma_address(&s->sg_rx[0]));
1310 dma_release_channel(chan);
1311 }
1312
start_hrtimer_us(struct hrtimer * hrt,unsigned long usec)1313 static void start_hrtimer_us(struct hrtimer *hrt, unsigned long usec)
1314 {
1315 long sec = usec / 1000000;
1316 long nsec = (usec % 1000000) * 1000;
1317 ktime_t t = ktime_set(sec, nsec);
1318
1319 hrtimer_start(hrt, t, HRTIMER_MODE_REL);
1320 }
1321
sci_dma_rx_reenable_irq(struct sci_port * s)1322 static void sci_dma_rx_reenable_irq(struct sci_port *s)
1323 {
1324 struct uart_port *port = &s->port;
1325 u16 scr;
1326
1327 /* Direct new serial port interrupts back to CPU */
1328 scr = serial_port_in(port, SCSCR);
1329 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1330 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1331 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1332 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1333 scif_set_rtrg(port, s->rx_trigger);
1334 else
1335 scr &= ~SCSCR_RDRQE;
1336 }
1337 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1338 }
1339
sci_dma_rx_complete(void * arg)1340 static void sci_dma_rx_complete(void *arg)
1341 {
1342 struct sci_port *s = arg;
1343 struct dma_chan *chan = s->chan_rx;
1344 struct uart_port *port = &s->port;
1345 struct dma_async_tx_descriptor *desc;
1346 unsigned long flags;
1347 int active, count = 0;
1348
1349 dev_dbg(port->dev, "%s(%d) active cookie %d\n", __func__, port->line,
1350 s->active_rx);
1351
1352 spin_lock_irqsave(&port->lock, flags);
1353
1354 active = sci_dma_rx_find_active(s);
1355 if (active >= 0)
1356 count = sci_dma_rx_push(s, s->rx_buf[active], s->buf_len_rx);
1357
1358 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1359
1360 if (count)
1361 tty_flip_buffer_push(&port->state->port);
1362
1363 desc = dmaengine_prep_slave_sg(s->chan_rx, &s->sg_rx[active], 1,
1364 DMA_DEV_TO_MEM,
1365 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1366 if (!desc)
1367 goto fail;
1368
1369 desc->callback = sci_dma_rx_complete;
1370 desc->callback_param = s;
1371 s->cookie_rx[active] = dmaengine_submit(desc);
1372 if (dma_submit_error(s->cookie_rx[active]))
1373 goto fail;
1374
1375 s->active_rx = s->cookie_rx[!active];
1376
1377 dma_async_issue_pending(chan);
1378
1379 spin_unlock_irqrestore(&port->lock, flags);
1380 dev_dbg(port->dev, "%s: cookie %d #%d, new active cookie %d\n",
1381 __func__, s->cookie_rx[active], active, s->active_rx);
1382 return;
1383
1384 fail:
1385 spin_unlock_irqrestore(&port->lock, flags);
1386 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1387 /* Switch to PIO */
1388 spin_lock_irqsave(&port->lock, flags);
1389 dmaengine_terminate_async(chan);
1390 sci_dma_rx_chan_invalidate(s);
1391 sci_dma_rx_reenable_irq(s);
1392 spin_unlock_irqrestore(&port->lock, flags);
1393 }
1394
sci_dma_tx_release(struct sci_port * s)1395 static void sci_dma_tx_release(struct sci_port *s)
1396 {
1397 struct dma_chan *chan = s->chan_tx_saved;
1398
1399 cancel_work_sync(&s->work_tx);
1400 s->chan_tx_saved = s->chan_tx = NULL;
1401 s->cookie_tx = -EINVAL;
1402 dmaengine_terminate_sync(chan);
1403 dma_unmap_single(chan->device->dev, s->tx_dma_addr, UART_XMIT_SIZE,
1404 DMA_TO_DEVICE);
1405 dma_release_channel(chan);
1406 }
1407
sci_dma_rx_submit(struct sci_port * s,bool port_lock_held)1408 static int sci_dma_rx_submit(struct sci_port *s, bool port_lock_held)
1409 {
1410 struct dma_chan *chan = s->chan_rx;
1411 struct uart_port *port = &s->port;
1412 unsigned long flags;
1413 int i;
1414
1415 for (i = 0; i < 2; i++) {
1416 struct scatterlist *sg = &s->sg_rx[i];
1417 struct dma_async_tx_descriptor *desc;
1418
1419 desc = dmaengine_prep_slave_sg(chan,
1420 sg, 1, DMA_DEV_TO_MEM,
1421 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1422 if (!desc)
1423 goto fail;
1424
1425 desc->callback = sci_dma_rx_complete;
1426 desc->callback_param = s;
1427 s->cookie_rx[i] = dmaengine_submit(desc);
1428 if (dma_submit_error(s->cookie_rx[i]))
1429 goto fail;
1430
1431 }
1432
1433 s->active_rx = s->cookie_rx[0];
1434
1435 dma_async_issue_pending(chan);
1436 return 0;
1437
1438 fail:
1439 /* Switch to PIO */
1440 if (!port_lock_held)
1441 spin_lock_irqsave(&port->lock, flags);
1442 if (i)
1443 dmaengine_terminate_async(chan);
1444 sci_dma_rx_chan_invalidate(s);
1445 sci_start_rx(port);
1446 if (!port_lock_held)
1447 spin_unlock_irqrestore(&port->lock, flags);
1448 return -EAGAIN;
1449 }
1450
sci_dma_tx_work_fn(struct work_struct * work)1451 static void sci_dma_tx_work_fn(struct work_struct *work)
1452 {
1453 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1454 struct dma_async_tx_descriptor *desc;
1455 struct dma_chan *chan = s->chan_tx;
1456 struct uart_port *port = &s->port;
1457 struct circ_buf *xmit = &port->state->xmit;
1458 unsigned long flags;
1459 dma_addr_t buf;
1460 int head, tail;
1461
1462 /*
1463 * DMA is idle now.
1464 * Port xmit buffer is already mapped, and it is one page... Just adjust
1465 * offsets and lengths. Since it is a circular buffer, we have to
1466 * transmit till the end, and then the rest. Take the port lock to get a
1467 * consistent xmit buffer state.
1468 */
1469 spin_lock_irq(&port->lock);
1470 head = xmit->head;
1471 tail = xmit->tail;
1472 buf = s->tx_dma_addr + tail;
1473 s->tx_dma_len = CIRC_CNT_TO_END(head, tail, UART_XMIT_SIZE);
1474 if (!s->tx_dma_len) {
1475 /* Transmit buffer has been flushed */
1476 spin_unlock_irq(&port->lock);
1477 return;
1478 }
1479
1480 desc = dmaengine_prep_slave_single(chan, buf, s->tx_dma_len,
1481 DMA_MEM_TO_DEV,
1482 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1483 if (!desc) {
1484 spin_unlock_irq(&port->lock);
1485 dev_warn(port->dev, "Failed preparing Tx DMA descriptor\n");
1486 goto switch_to_pio;
1487 }
1488
1489 dma_sync_single_for_device(chan->device->dev, buf, s->tx_dma_len,
1490 DMA_TO_DEVICE);
1491
1492 desc->callback = sci_dma_tx_complete;
1493 desc->callback_param = s;
1494 s->cookie_tx = dmaengine_submit(desc);
1495 if (dma_submit_error(s->cookie_tx)) {
1496 spin_unlock_irq(&port->lock);
1497 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1498 goto switch_to_pio;
1499 }
1500
1501 spin_unlock_irq(&port->lock);
1502 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1503 __func__, xmit->buf, tail, head, s->cookie_tx);
1504
1505 dma_async_issue_pending(chan);
1506 return;
1507
1508 switch_to_pio:
1509 spin_lock_irqsave(&port->lock, flags);
1510 s->chan_tx = NULL;
1511 sci_start_tx(port);
1512 spin_unlock_irqrestore(&port->lock, flags);
1513 return;
1514 }
1515
sci_dma_rx_timer_fn(struct hrtimer * t)1516 static enum hrtimer_restart sci_dma_rx_timer_fn(struct hrtimer *t)
1517 {
1518 struct sci_port *s = container_of(t, struct sci_port, rx_timer);
1519 struct dma_chan *chan = s->chan_rx;
1520 struct uart_port *port = &s->port;
1521 struct dma_tx_state state;
1522 enum dma_status status;
1523 unsigned long flags;
1524 unsigned int read;
1525 int active, count;
1526
1527 dev_dbg(port->dev, "DMA Rx timed out\n");
1528
1529 spin_lock_irqsave(&port->lock, flags);
1530
1531 active = sci_dma_rx_find_active(s);
1532 if (active < 0) {
1533 spin_unlock_irqrestore(&port->lock, flags);
1534 return HRTIMER_NORESTART;
1535 }
1536
1537 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1538 if (status == DMA_COMPLETE) {
1539 spin_unlock_irqrestore(&port->lock, flags);
1540 dev_dbg(port->dev, "Cookie %d #%d has already completed\n",
1541 s->active_rx, active);
1542
1543 /* Let packet complete handler take care of the packet */
1544 return HRTIMER_NORESTART;
1545 }
1546
1547 dmaengine_pause(chan);
1548
1549 /*
1550 * sometimes DMA transfer doesn't stop even if it is stopped and
1551 * data keeps on coming until transaction is complete so check
1552 * for DMA_COMPLETE again
1553 * Let packet complete handler take care of the packet
1554 */
1555 status = dmaengine_tx_status(s->chan_rx, s->active_rx, &state);
1556 if (status == DMA_COMPLETE) {
1557 spin_unlock_irqrestore(&port->lock, flags);
1558 dev_dbg(port->dev, "Transaction complete after DMA engine was stopped");
1559 return HRTIMER_NORESTART;
1560 }
1561
1562 /* Handle incomplete DMA receive */
1563 dmaengine_terminate_async(s->chan_rx);
1564 read = sg_dma_len(&s->sg_rx[active]) - state.residue;
1565
1566 if (read) {
1567 count = sci_dma_rx_push(s, s->rx_buf[active], read);
1568 if (count)
1569 tty_flip_buffer_push(&port->state->port);
1570 }
1571
1572 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1573 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1574 sci_dma_rx_submit(s, true);
1575
1576 sci_dma_rx_reenable_irq(s);
1577
1578 spin_unlock_irqrestore(&port->lock, flags);
1579
1580 return HRTIMER_NORESTART;
1581 }
1582
sci_request_dma_chan(struct uart_port * port,enum dma_transfer_direction dir)1583 static struct dma_chan *sci_request_dma_chan(struct uart_port *port,
1584 enum dma_transfer_direction dir)
1585 {
1586 struct dma_chan *chan;
1587 struct dma_slave_config cfg;
1588 int ret;
1589
1590 chan = dma_request_slave_channel(port->dev,
1591 dir == DMA_MEM_TO_DEV ? "tx" : "rx");
1592 if (!chan) {
1593 dev_dbg(port->dev, "dma_request_slave_channel failed\n");
1594 return NULL;
1595 }
1596
1597 memset(&cfg, 0, sizeof(cfg));
1598 cfg.direction = dir;
1599 cfg.dst_addr = port->mapbase +
1600 (sci_getreg(port, SCxTDR)->offset << port->regshift);
1601 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1602 cfg.src_addr = port->mapbase +
1603 (sci_getreg(port, SCxRDR)->offset << port->regshift);
1604 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1605
1606 ret = dmaengine_slave_config(chan, &cfg);
1607 if (ret) {
1608 dev_warn(port->dev, "dmaengine_slave_config failed %d\n", ret);
1609 dma_release_channel(chan);
1610 return NULL;
1611 }
1612
1613 return chan;
1614 }
1615
sci_request_dma(struct uart_port * port)1616 static void sci_request_dma(struct uart_port *port)
1617 {
1618 struct sci_port *s = to_sci_port(port);
1619 struct dma_chan *chan;
1620
1621 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1622
1623 /*
1624 * DMA on console may interfere with Kernel log messages which use
1625 * plain putchar(). So, simply don't use it with a console.
1626 */
1627 if (uart_console(port))
1628 return;
1629
1630 if (!port->dev->of_node)
1631 return;
1632
1633 s->cookie_tx = -EINVAL;
1634
1635 /*
1636 * Don't request a dma channel if no channel was specified
1637 * in the device tree.
1638 */
1639 if (!of_property_present(port->dev->of_node, "dmas"))
1640 return;
1641
1642 chan = sci_request_dma_chan(port, DMA_MEM_TO_DEV);
1643 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1644 if (chan) {
1645 /* UART circular tx buffer is an aligned page. */
1646 s->tx_dma_addr = dma_map_single(chan->device->dev,
1647 port->state->xmit.buf,
1648 UART_XMIT_SIZE,
1649 DMA_TO_DEVICE);
1650 if (dma_mapping_error(chan->device->dev, s->tx_dma_addr)) {
1651 dev_warn(port->dev, "Failed mapping Tx DMA descriptor\n");
1652 dma_release_channel(chan);
1653 } else {
1654 dev_dbg(port->dev, "%s: mapped %lu@%p to %pad\n",
1655 __func__, UART_XMIT_SIZE,
1656 port->state->xmit.buf, &s->tx_dma_addr);
1657
1658 INIT_WORK(&s->work_tx, sci_dma_tx_work_fn);
1659 s->chan_tx_saved = s->chan_tx = chan;
1660 }
1661 }
1662
1663 chan = sci_request_dma_chan(port, DMA_DEV_TO_MEM);
1664 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1665 if (chan) {
1666 unsigned int i;
1667 dma_addr_t dma;
1668 void *buf;
1669
1670 s->buf_len_rx = 2 * max_t(size_t, 16, port->fifosize);
1671 buf = dma_alloc_coherent(chan->device->dev, s->buf_len_rx * 2,
1672 &dma, GFP_KERNEL);
1673 if (!buf) {
1674 dev_warn(port->dev,
1675 "Failed to allocate Rx dma buffer, using PIO\n");
1676 dma_release_channel(chan);
1677 return;
1678 }
1679
1680 for (i = 0; i < 2; i++) {
1681 struct scatterlist *sg = &s->sg_rx[i];
1682
1683 sg_init_table(sg, 1);
1684 s->rx_buf[i] = buf;
1685 sg_dma_address(sg) = dma;
1686 sg_dma_len(sg) = s->buf_len_rx;
1687
1688 buf += s->buf_len_rx;
1689 dma += s->buf_len_rx;
1690 }
1691
1692 hrtimer_init(&s->rx_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
1693 s->rx_timer.function = sci_dma_rx_timer_fn;
1694
1695 s->chan_rx_saved = s->chan_rx = chan;
1696
1697 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1698 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE)
1699 sci_dma_rx_submit(s, false);
1700 }
1701 }
1702
sci_free_dma(struct uart_port * port)1703 static void sci_free_dma(struct uart_port *port)
1704 {
1705 struct sci_port *s = to_sci_port(port);
1706
1707 if (s->chan_tx_saved)
1708 sci_dma_tx_release(s);
1709 if (s->chan_rx_saved)
1710 sci_dma_rx_release(s);
1711 }
1712
sci_flush_buffer(struct uart_port * port)1713 static void sci_flush_buffer(struct uart_port *port)
1714 {
1715 struct sci_port *s = to_sci_port(port);
1716
1717 /*
1718 * In uart_flush_buffer(), the xmit circular buffer has just been
1719 * cleared, so we have to reset tx_dma_len accordingly, and stop any
1720 * pending transfers
1721 */
1722 s->tx_dma_len = 0;
1723 if (s->chan_tx) {
1724 dmaengine_terminate_async(s->chan_tx);
1725 s->cookie_tx = -EINVAL;
1726 }
1727 }
1728
sci_dma_check_tx_occurred(struct sci_port * s)1729 static void sci_dma_check_tx_occurred(struct sci_port *s)
1730 {
1731 struct dma_tx_state state;
1732 enum dma_status status;
1733
1734 if (!s->chan_tx)
1735 return;
1736
1737 status = dmaengine_tx_status(s->chan_tx, s->cookie_tx, &state);
1738 if (status == DMA_COMPLETE || status == DMA_IN_PROGRESS)
1739 s->tx_occurred = true;
1740 }
1741 #else /* !CONFIG_SERIAL_SH_SCI_DMA */
sci_request_dma(struct uart_port * port)1742 static inline void sci_request_dma(struct uart_port *port)
1743 {
1744 }
1745
sci_free_dma(struct uart_port * port)1746 static inline void sci_free_dma(struct uart_port *port)
1747 {
1748 }
1749
sci_dma_check_tx_occurred(struct sci_port * s)1750 static void sci_dma_check_tx_occurred(struct sci_port *s)
1751 {
1752 }
1753
1754 #define sci_flush_buffer NULL
1755 #endif /* !CONFIG_SERIAL_SH_SCI_DMA */
1756
sci_rx_interrupt(int irq,void * ptr)1757 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
1758 {
1759 struct uart_port *port = ptr;
1760 struct sci_port *s = to_sci_port(port);
1761
1762 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1763 if (s->chan_rx) {
1764 u16 scr = serial_port_in(port, SCSCR);
1765 u16 ssr = serial_port_in(port, SCxSR);
1766
1767 /* Disable future Rx interrupts */
1768 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB ||
1769 s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1770 disable_irq_nosync(s->irqs[SCIx_RXI_IRQ]);
1771 if (s->cfg->regtype == SCIx_RZ_SCIFA_REGTYPE) {
1772 scif_set_rtrg(port, 1);
1773 scr |= SCSCR_RIE;
1774 } else {
1775 scr |= SCSCR_RDRQE;
1776 }
1777 } else {
1778 if (sci_dma_rx_submit(s, false) < 0)
1779 goto handle_pio;
1780
1781 scr &= ~SCSCR_RIE;
1782 }
1783 serial_port_out(port, SCSCR, scr);
1784 /* Clear current interrupt */
1785 serial_port_out(port, SCxSR,
1786 ssr & ~(SCIF_DR | SCxSR_RDxF(port)));
1787 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u us\n",
1788 jiffies, s->rx_timeout);
1789 start_hrtimer_us(&s->rx_timer, s->rx_timeout);
1790
1791 return IRQ_HANDLED;
1792 }
1793
1794 handle_pio:
1795 #endif
1796
1797 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0) {
1798 if (!scif_rtrg_enabled(port))
1799 scif_set_rtrg(port, s->rx_trigger);
1800
1801 mod_timer(&s->rx_fifo_timer, jiffies + DIV_ROUND_UP(
1802 s->rx_frame * HZ * s->rx_fifo_timeout, 1000000));
1803 }
1804
1805 /* I think sci_receive_chars has to be called irrespective
1806 * of whether the I_IXOFF is set, otherwise, how is the interrupt
1807 * to be disabled?
1808 */
1809 sci_receive_chars(port);
1810
1811 return IRQ_HANDLED;
1812 }
1813
sci_tx_interrupt(int irq,void * ptr)1814 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
1815 {
1816 struct uart_port *port = ptr;
1817 unsigned long flags;
1818
1819 spin_lock_irqsave(&port->lock, flags);
1820 sci_transmit_chars(port);
1821 spin_unlock_irqrestore(&port->lock, flags);
1822
1823 return IRQ_HANDLED;
1824 }
1825
sci_tx_end_interrupt(int irq,void * ptr)1826 static irqreturn_t sci_tx_end_interrupt(int irq, void *ptr)
1827 {
1828 struct uart_port *port = ptr;
1829 unsigned long flags;
1830 unsigned short ctrl;
1831
1832 if (port->type != PORT_SCI)
1833 return sci_tx_interrupt(irq, ptr);
1834
1835 spin_lock_irqsave(&port->lock, flags);
1836 ctrl = serial_port_in(port, SCSCR);
1837 ctrl &= ~(SCSCR_TE | SCSCR_TEIE);
1838 serial_port_out(port, SCSCR, ctrl);
1839 spin_unlock_irqrestore(&port->lock, flags);
1840
1841 return IRQ_HANDLED;
1842 }
1843
sci_br_interrupt(int irq,void * ptr)1844 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
1845 {
1846 struct uart_port *port = ptr;
1847
1848 /* Handle BREAKs */
1849 sci_handle_breaks(port);
1850
1851 /* drop invalid character received before break was detected */
1852 serial_port_in(port, SCxRDR);
1853
1854 sci_clear_SCxSR(port, SCxSR_BREAK_CLEAR(port));
1855
1856 return IRQ_HANDLED;
1857 }
1858
sci_er_interrupt(int irq,void * ptr)1859 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
1860 {
1861 struct uart_port *port = ptr;
1862 struct sci_port *s = to_sci_port(port);
1863
1864 if (s->irqs[SCIx_ERI_IRQ] == s->irqs[SCIx_BRI_IRQ]) {
1865 /* Break and Error interrupts are muxed */
1866 unsigned short ssr_status = serial_port_in(port, SCxSR);
1867
1868 /* Break Interrupt */
1869 if (ssr_status & SCxSR_BRK(port))
1870 sci_br_interrupt(irq, ptr);
1871
1872 /* Break only? */
1873 if (!(ssr_status & SCxSR_ERRORS(port)))
1874 return IRQ_HANDLED;
1875 }
1876
1877 /* Handle errors */
1878 if (port->type == PORT_SCI) {
1879 if (sci_handle_errors(port)) {
1880 /* discard character in rx buffer */
1881 serial_port_in(port, SCxSR);
1882 sci_clear_SCxSR(port, SCxSR_RDxF_CLEAR(port));
1883 }
1884 } else {
1885 sci_handle_fifo_overrun(port);
1886 if (!s->chan_rx)
1887 sci_receive_chars(port);
1888 }
1889
1890 sci_clear_SCxSR(port, SCxSR_ERROR_CLEAR(port));
1891
1892 /* Kick the transmission */
1893 if (!s->chan_tx)
1894 sci_tx_interrupt(irq, ptr);
1895
1896 return IRQ_HANDLED;
1897 }
1898
sci_mpxed_interrupt(int irq,void * ptr)1899 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
1900 {
1901 unsigned short ssr_status, scr_status, err_enabled, orer_status = 0;
1902 struct uart_port *port = ptr;
1903 struct sci_port *s = to_sci_port(port);
1904 irqreturn_t ret = IRQ_NONE;
1905
1906 ssr_status = serial_port_in(port, SCxSR);
1907 scr_status = serial_port_in(port, SCSCR);
1908 if (s->params->overrun_reg == SCxSR)
1909 orer_status = ssr_status;
1910 else if (sci_getreg(port, s->params->overrun_reg)->size)
1911 orer_status = serial_port_in(port, s->params->overrun_reg);
1912
1913 err_enabled = scr_status & port_rx_irq_mask(port);
1914
1915 /* Tx Interrupt */
1916 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1917 !s->chan_tx)
1918 ret = sci_tx_interrupt(irq, ptr);
1919
1920 /*
1921 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1922 * DR flags
1923 */
1924 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1925 (scr_status & SCSCR_RIE))
1926 ret = sci_rx_interrupt(irq, ptr);
1927
1928 /* Error Interrupt */
1929 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1930 ret = sci_er_interrupt(irq, ptr);
1931
1932 /* Break Interrupt */
1933 if (s->irqs[SCIx_ERI_IRQ] != s->irqs[SCIx_BRI_IRQ] &&
1934 (ssr_status & SCxSR_BRK(port)) && err_enabled)
1935 ret = sci_br_interrupt(irq, ptr);
1936
1937 /* Overrun Interrupt */
1938 if (orer_status & s->params->overrun_mask) {
1939 sci_handle_fifo_overrun(port);
1940 ret = IRQ_HANDLED;
1941 }
1942
1943 return ret;
1944 }
1945
1946 static const struct sci_irq_desc {
1947 const char *desc;
1948 irq_handler_t handler;
1949 } sci_irq_desc[] = {
1950 /*
1951 * Split out handlers, the default case.
1952 */
1953 [SCIx_ERI_IRQ] = {
1954 .desc = "rx err",
1955 .handler = sci_er_interrupt,
1956 },
1957
1958 [SCIx_RXI_IRQ] = {
1959 .desc = "rx full",
1960 .handler = sci_rx_interrupt,
1961 },
1962
1963 [SCIx_TXI_IRQ] = {
1964 .desc = "tx empty",
1965 .handler = sci_tx_interrupt,
1966 },
1967
1968 [SCIx_BRI_IRQ] = {
1969 .desc = "break",
1970 .handler = sci_br_interrupt,
1971 },
1972
1973 [SCIx_DRI_IRQ] = {
1974 .desc = "rx ready",
1975 .handler = sci_rx_interrupt,
1976 },
1977
1978 [SCIx_TEI_IRQ] = {
1979 .desc = "tx end",
1980 .handler = sci_tx_end_interrupt,
1981 },
1982
1983 /*
1984 * Special muxed handler.
1985 */
1986 [SCIx_MUX_IRQ] = {
1987 .desc = "mux",
1988 .handler = sci_mpxed_interrupt,
1989 },
1990 };
1991
sci_request_irq(struct sci_port * port)1992 static int sci_request_irq(struct sci_port *port)
1993 {
1994 struct uart_port *up = &port->port;
1995 int i, j, w, ret = 0;
1996
1997 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1998 const struct sci_irq_desc *desc;
1999 int irq;
2000
2001 /* Check if already registered (muxed) */
2002 for (w = 0; w < i; w++)
2003 if (port->irqs[w] == port->irqs[i])
2004 w = i + 1;
2005 if (w > i)
2006 continue;
2007
2008 if (SCIx_IRQ_IS_MUXED(port)) {
2009 i = SCIx_MUX_IRQ;
2010 irq = up->irq;
2011 } else {
2012 irq = port->irqs[i];
2013
2014 /*
2015 * Certain port types won't support all of the
2016 * available interrupt sources.
2017 */
2018 if (unlikely(irq < 0))
2019 continue;
2020 }
2021
2022 desc = sci_irq_desc + i;
2023 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
2024 dev_name(up->dev), desc->desc);
2025 if (!port->irqstr[j]) {
2026 ret = -ENOMEM;
2027 goto out_nomem;
2028 }
2029
2030 ret = request_irq(irq, desc->handler, up->irqflags,
2031 port->irqstr[j], port);
2032 if (unlikely(ret)) {
2033 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
2034 goto out_noirq;
2035 }
2036 }
2037
2038 return 0;
2039
2040 out_noirq:
2041 while (--i >= 0)
2042 free_irq(port->irqs[i], port);
2043
2044 out_nomem:
2045 while (--j >= 0)
2046 kfree(port->irqstr[j]);
2047
2048 return ret;
2049 }
2050
sci_free_irq(struct sci_port * port)2051 static void sci_free_irq(struct sci_port *port)
2052 {
2053 int i, j;
2054
2055 /*
2056 * Intentionally in reverse order so we iterate over the muxed
2057 * IRQ first.
2058 */
2059 for (i = 0; i < SCIx_NR_IRQS; i++) {
2060 int irq = port->irqs[i];
2061
2062 /*
2063 * Certain port types won't support all of the available
2064 * interrupt sources.
2065 */
2066 if (unlikely(irq < 0))
2067 continue;
2068
2069 /* Check if already freed (irq was muxed) */
2070 for (j = 0; j < i; j++)
2071 if (port->irqs[j] == irq)
2072 j = i + 1;
2073 if (j > i)
2074 continue;
2075
2076 free_irq(port->irqs[i], port);
2077 kfree(port->irqstr[i]);
2078
2079 if (SCIx_IRQ_IS_MUXED(port)) {
2080 /* If there's only one IRQ, we're done. */
2081 return;
2082 }
2083 }
2084 }
2085
sci_tx_empty(struct uart_port * port)2086 static unsigned int sci_tx_empty(struct uart_port *port)
2087 {
2088 unsigned short status = serial_port_in(port, SCxSR);
2089 unsigned short in_tx_fifo = sci_txfill(port);
2090 struct sci_port *s = to_sci_port(port);
2091
2092 sci_dma_check_tx_occurred(s);
2093
2094 if (!s->tx_occurred)
2095 return TIOCSER_TEMT;
2096
2097 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
2098 }
2099
sci_set_rts(struct uart_port * port,bool state)2100 static void sci_set_rts(struct uart_port *port, bool state)
2101 {
2102 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2103 u16 data = serial_port_in(port, SCPDR);
2104
2105 /* Active low */
2106 if (state)
2107 data &= ~SCPDR_RTSD;
2108 else
2109 data |= SCPDR_RTSD;
2110 serial_port_out(port, SCPDR, data);
2111
2112 /* RTS# is output */
2113 serial_port_out(port, SCPCR,
2114 serial_port_in(port, SCPCR) | SCPCR_RTSC);
2115 } else if (sci_getreg(port, SCSPTR)->size) {
2116 u16 ctrl = serial_port_in(port, SCSPTR);
2117
2118 /* Active low */
2119 if (state)
2120 ctrl &= ~SCSPTR_RTSDT;
2121 else
2122 ctrl |= SCSPTR_RTSDT;
2123 serial_port_out(port, SCSPTR, ctrl);
2124 }
2125 }
2126
sci_get_cts(struct uart_port * port)2127 static bool sci_get_cts(struct uart_port *port)
2128 {
2129 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2130 /* Active low */
2131 return !(serial_port_in(port, SCPDR) & SCPDR_CTSD);
2132 } else if (sci_getreg(port, SCSPTR)->size) {
2133 /* Active low */
2134 return !(serial_port_in(port, SCSPTR) & SCSPTR_CTSDT);
2135 }
2136
2137 return true;
2138 }
2139
2140 /*
2141 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
2142 * CTS/RTS is supported in hardware by at least one port and controlled
2143 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
2144 * handled via the ->init_pins() op, which is a bit of a one-way street,
2145 * lacking any ability to defer pin control -- this will later be
2146 * converted over to the GPIO framework).
2147 *
2148 * Other modes (such as loopback) are supported generically on certain
2149 * port types, but not others. For these it's sufficient to test for the
2150 * existence of the support register and simply ignore the port type.
2151 */
sci_set_mctrl(struct uart_port * port,unsigned int mctrl)2152 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
2153 {
2154 struct sci_port *s = to_sci_port(port);
2155
2156 if (mctrl & TIOCM_LOOP) {
2157 const struct plat_sci_reg *reg;
2158
2159 /*
2160 * Standard loopback mode for SCFCR ports.
2161 */
2162 reg = sci_getreg(port, SCFCR);
2163 if (reg->size)
2164 serial_port_out(port, SCFCR,
2165 serial_port_in(port, SCFCR) |
2166 SCFCR_LOOP);
2167 }
2168
2169 mctrl_gpio_set(s->gpios, mctrl);
2170
2171 if (!s->has_rtscts)
2172 return;
2173
2174 if (!(mctrl & TIOCM_RTS)) {
2175 /* Disable Auto RTS */
2176 serial_port_out(port, SCFCR,
2177 serial_port_in(port, SCFCR) & ~SCFCR_MCE);
2178
2179 /* Clear RTS */
2180 sci_set_rts(port, 0);
2181 } else if (s->autorts) {
2182 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
2183 /* Enable RTS# pin function */
2184 serial_port_out(port, SCPCR,
2185 serial_port_in(port, SCPCR) & ~SCPCR_RTSC);
2186 }
2187
2188 /* Enable Auto RTS */
2189 serial_port_out(port, SCFCR,
2190 serial_port_in(port, SCFCR) | SCFCR_MCE);
2191 } else {
2192 /* Set RTS */
2193 sci_set_rts(port, 1);
2194 }
2195 }
2196
sci_get_mctrl(struct uart_port * port)2197 static unsigned int sci_get_mctrl(struct uart_port *port)
2198 {
2199 struct sci_port *s = to_sci_port(port);
2200 struct mctrl_gpios *gpios = s->gpios;
2201 unsigned int mctrl = 0;
2202
2203 mctrl_gpio_get(gpios, &mctrl);
2204
2205 /*
2206 * CTS/RTS is handled in hardware when supported, while nothing
2207 * else is wired up.
2208 */
2209 if (s->autorts) {
2210 if (sci_get_cts(port))
2211 mctrl |= TIOCM_CTS;
2212 } else if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_CTS)) {
2213 mctrl |= TIOCM_CTS;
2214 }
2215 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DSR))
2216 mctrl |= TIOCM_DSR;
2217 if (!mctrl_gpio_to_gpiod(gpios, UART_GPIO_DCD))
2218 mctrl |= TIOCM_CAR;
2219
2220 return mctrl;
2221 }
2222
sci_enable_ms(struct uart_port * port)2223 static void sci_enable_ms(struct uart_port *port)
2224 {
2225 mctrl_gpio_enable_ms(to_sci_port(port)->gpios);
2226 }
2227
sci_break_ctl(struct uart_port * port,int break_state)2228 static void sci_break_ctl(struct uart_port *port, int break_state)
2229 {
2230 unsigned short scscr, scsptr;
2231 unsigned long flags;
2232
2233 /* check whether the port has SCSPTR */
2234 if (!sci_getreg(port, SCSPTR)->size) {
2235 /*
2236 * Not supported by hardware. Most parts couple break and rx
2237 * interrupts together, with break detection always enabled.
2238 */
2239 return;
2240 }
2241
2242 spin_lock_irqsave(&port->lock, flags);
2243 scsptr = serial_port_in(port, SCSPTR);
2244 scscr = serial_port_in(port, SCSCR);
2245
2246 if (break_state == -1) {
2247 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
2248 scscr &= ~SCSCR_TE;
2249 } else {
2250 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
2251 scscr |= SCSCR_TE;
2252 }
2253
2254 serial_port_out(port, SCSPTR, scsptr);
2255 serial_port_out(port, SCSCR, scscr);
2256 spin_unlock_irqrestore(&port->lock, flags);
2257 }
2258
sci_startup(struct uart_port * port)2259 static int sci_startup(struct uart_port *port)
2260 {
2261 struct sci_port *s = to_sci_port(port);
2262 int ret;
2263
2264 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2265
2266 s->tx_occurred = false;
2267 sci_request_dma(port);
2268
2269 ret = sci_request_irq(s);
2270 if (unlikely(ret < 0)) {
2271 sci_free_dma(port);
2272 return ret;
2273 }
2274
2275 return 0;
2276 }
2277
sci_shutdown(struct uart_port * port)2278 static void sci_shutdown(struct uart_port *port)
2279 {
2280 struct sci_port *s = to_sci_port(port);
2281 unsigned long flags;
2282 u16 scr;
2283
2284 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
2285
2286 s->autorts = false;
2287 mctrl_gpio_disable_ms_sync(to_sci_port(port)->gpios);
2288
2289 spin_lock_irqsave(&port->lock, flags);
2290 sci_stop_rx(port);
2291 sci_stop_tx(port);
2292 /*
2293 * Stop RX and TX, disable related interrupts, keep clock source
2294 * and HSCIF TOT bits
2295 */
2296 scr = serial_port_in(port, SCSCR);
2297 serial_port_out(port, SCSCR, scr &
2298 (SCSCR_CKE1 | SCSCR_CKE0 | s->hscif_tot));
2299 spin_unlock_irqrestore(&port->lock, flags);
2300
2301 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2302 if (s->chan_rx_saved) {
2303 dev_dbg(port->dev, "%s(%d) deleting rx_timer\n", __func__,
2304 port->line);
2305 hrtimer_cancel(&s->rx_timer);
2306 }
2307 #endif
2308
2309 if (s->rx_trigger > 1 && s->rx_fifo_timeout > 0)
2310 del_timer_sync(&s->rx_fifo_timer);
2311 sci_free_irq(s);
2312 sci_free_dma(port);
2313 }
2314
sci_sck_calc(struct sci_port * s,unsigned int bps,unsigned int * srr)2315 static int sci_sck_calc(struct sci_port *s, unsigned int bps,
2316 unsigned int *srr)
2317 {
2318 unsigned long freq = s->clk_rates[SCI_SCK];
2319 int err, min_err = INT_MAX;
2320 unsigned int sr;
2321
2322 if (s->port.type != PORT_HSCIF)
2323 freq *= 2;
2324
2325 for_each_sr(sr, s) {
2326 err = DIV_ROUND_CLOSEST(freq, sr) - bps;
2327 if (abs(err) >= abs(min_err))
2328 continue;
2329
2330 min_err = err;
2331 *srr = sr - 1;
2332
2333 if (!err)
2334 break;
2335 }
2336
2337 dev_dbg(s->port.dev, "SCK: %u%+d bps using SR %u\n", bps, min_err,
2338 *srr + 1);
2339 return min_err;
2340 }
2341
sci_brg_calc(struct sci_port * s,unsigned int bps,unsigned long freq,unsigned int * dlr,unsigned int * srr)2342 static int sci_brg_calc(struct sci_port *s, unsigned int bps,
2343 unsigned long freq, unsigned int *dlr,
2344 unsigned int *srr)
2345 {
2346 int err, min_err = INT_MAX;
2347 unsigned int sr, dl;
2348
2349 if (s->port.type != PORT_HSCIF)
2350 freq *= 2;
2351
2352 for_each_sr(sr, s) {
2353 dl = DIV_ROUND_CLOSEST(freq, sr * bps);
2354 dl = clamp(dl, 1U, 65535U);
2355
2356 err = DIV_ROUND_CLOSEST(freq, sr * dl) - bps;
2357 if (abs(err) >= abs(min_err))
2358 continue;
2359
2360 min_err = err;
2361 *dlr = dl;
2362 *srr = sr - 1;
2363
2364 if (!err)
2365 break;
2366 }
2367
2368 dev_dbg(s->port.dev, "BRG: %u%+d bps using DL %u SR %u\n", bps,
2369 min_err, *dlr, *srr + 1);
2370 return min_err;
2371 }
2372
2373 /* calculate sample rate, BRR, and clock select */
sci_scbrr_calc(struct sci_port * s,unsigned int bps,unsigned int * brr,unsigned int * srr,unsigned int * cks)2374 static int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
2375 unsigned int *brr, unsigned int *srr,
2376 unsigned int *cks)
2377 {
2378 unsigned long freq = s->clk_rates[SCI_FCK];
2379 unsigned int sr, br, prediv, scrate, c;
2380 int err, min_err = INT_MAX;
2381
2382 if (s->port.type != PORT_HSCIF)
2383 freq *= 2;
2384
2385 /*
2386 * Find the combination of sample rate and clock select with the
2387 * smallest deviation from the desired baud rate.
2388 * Prefer high sample rates to maximise the receive margin.
2389 *
2390 * M: Receive margin (%)
2391 * N: Ratio of bit rate to clock (N = sampling rate)
2392 * D: Clock duty (D = 0 to 1.0)
2393 * L: Frame length (L = 9 to 12)
2394 * F: Absolute value of clock frequency deviation
2395 *
2396 * M = |(0.5 - 1 / 2 * N) - ((L - 0.5) * F) -
2397 * (|D - 0.5| / N * (1 + F))|
2398 * NOTE: Usually, treat D for 0.5, F is 0 by this calculation.
2399 */
2400 for_each_sr(sr, s) {
2401 for (c = 0; c <= 3; c++) {
2402 /* integerized formulas from HSCIF documentation */
2403 prediv = sr << (2 * c + 1);
2404
2405 /*
2406 * We need to calculate:
2407 *
2408 * br = freq / (prediv * bps) clamped to [1..256]
2409 * err = freq / (br * prediv) - bps
2410 *
2411 * Watch out for overflow when calculating the desired
2412 * sampling clock rate!
2413 */
2414 if (bps > UINT_MAX / prediv)
2415 break;
2416
2417 scrate = prediv * bps;
2418 br = DIV_ROUND_CLOSEST(freq, scrate);
2419 br = clamp(br, 1U, 256U);
2420
2421 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps;
2422 if (abs(err) >= abs(min_err))
2423 continue;
2424
2425 min_err = err;
2426 *brr = br - 1;
2427 *srr = sr - 1;
2428 *cks = c;
2429
2430 if (!err)
2431 goto found;
2432 }
2433 }
2434
2435 found:
2436 dev_dbg(s->port.dev, "BRR: %u%+d bps using N %u SR %u cks %u\n", bps,
2437 min_err, *brr, *srr + 1, *cks);
2438 return min_err;
2439 }
2440
sci_reset(struct uart_port * port)2441 static void sci_reset(struct uart_port *port)
2442 {
2443 const struct plat_sci_reg *reg;
2444 unsigned int status;
2445 struct sci_port *s = to_sci_port(port);
2446
2447 serial_port_out(port, SCSCR, s->hscif_tot); /* TE=0, RE=0, CKE1=0 */
2448
2449 reg = sci_getreg(port, SCFCR);
2450 if (reg->size)
2451 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
2452
2453 sci_clear_SCxSR(port,
2454 SCxSR_RDxF_CLEAR(port) & SCxSR_ERROR_CLEAR(port) &
2455 SCxSR_BREAK_CLEAR(port));
2456 if (sci_getreg(port, SCLSR)->size) {
2457 status = serial_port_in(port, SCLSR);
2458 status &= ~(SCLSR_TO | SCLSR_ORER);
2459 serial_port_out(port, SCLSR, status);
2460 }
2461
2462 if (s->rx_trigger > 1) {
2463 if (s->rx_fifo_timeout) {
2464 scif_set_rtrg(port, 1);
2465 timer_setup(&s->rx_fifo_timer, rx_fifo_timer_fn, 0);
2466 } else {
2467 if (port->type == PORT_SCIFA ||
2468 port->type == PORT_SCIFB)
2469 scif_set_rtrg(port, 1);
2470 else
2471 scif_set_rtrg(port, s->rx_trigger);
2472 }
2473 }
2474 }
2475
sci_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)2476 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
2477 const struct ktermios *old)
2478 {
2479 unsigned int baud, smr_val = SCSMR_ASYNC, scr_val = 0, i, bits;
2480 unsigned int brr = 255, cks = 0, srr = 15, dl = 0, sccks = 0;
2481 unsigned int brr1 = 255, cks1 = 0, srr1 = 15, dl1 = 0;
2482 struct sci_port *s = to_sci_port(port);
2483 const struct plat_sci_reg *reg;
2484 int min_err = INT_MAX, err;
2485 unsigned long max_freq = 0;
2486 int best_clk = -1;
2487 unsigned long flags;
2488
2489 if ((termios->c_cflag & CSIZE) == CS7) {
2490 smr_val |= SCSMR_CHR;
2491 } else {
2492 termios->c_cflag &= ~CSIZE;
2493 termios->c_cflag |= CS8;
2494 }
2495 if (termios->c_cflag & PARENB)
2496 smr_val |= SCSMR_PE;
2497 if (termios->c_cflag & PARODD)
2498 smr_val |= SCSMR_PE | SCSMR_ODD;
2499 if (termios->c_cflag & CSTOPB)
2500 smr_val |= SCSMR_STOP;
2501
2502 /*
2503 * earlyprintk comes here early on with port->uartclk set to zero.
2504 * the clock framework is not up and running at this point so here
2505 * we assume that 115200 is the maximum baud rate. please note that
2506 * the baud rate is not programmed during earlyprintk - it is assumed
2507 * that the previous boot loader has enabled required clocks and
2508 * setup the baud rate generator hardware for us already.
2509 */
2510 if (!port->uartclk) {
2511 baud = uart_get_baud_rate(port, termios, old, 0, 115200);
2512 goto done;
2513 }
2514
2515 for (i = 0; i < SCI_NUM_CLKS; i++)
2516 max_freq = max(max_freq, s->clk_rates[i]);
2517
2518 baud = uart_get_baud_rate(port, termios, old, 0, max_freq / min_sr(s));
2519 if (!baud)
2520 goto done;
2521
2522 /*
2523 * There can be multiple sources for the sampling clock. Find the one
2524 * that gives us the smallest deviation from the desired baud rate.
2525 */
2526
2527 /* Optional Undivided External Clock */
2528 if (s->clk_rates[SCI_SCK] && port->type != PORT_SCIFA &&
2529 port->type != PORT_SCIFB) {
2530 err = sci_sck_calc(s, baud, &srr1);
2531 if (abs(err) < abs(min_err)) {
2532 best_clk = SCI_SCK;
2533 scr_val = SCSCR_CKE1;
2534 sccks = SCCKS_CKS;
2535 min_err = err;
2536 srr = srr1;
2537 if (!err)
2538 goto done;
2539 }
2540 }
2541
2542 /* Optional BRG Frequency Divided External Clock */
2543 if (s->clk_rates[SCI_SCIF_CLK] && sci_getreg(port, SCDL)->size) {
2544 err = sci_brg_calc(s, baud, s->clk_rates[SCI_SCIF_CLK], &dl1,
2545 &srr1);
2546 if (abs(err) < abs(min_err)) {
2547 best_clk = SCI_SCIF_CLK;
2548 scr_val = SCSCR_CKE1;
2549 sccks = 0;
2550 min_err = err;
2551 dl = dl1;
2552 srr = srr1;
2553 if (!err)
2554 goto done;
2555 }
2556 }
2557
2558 /* Optional BRG Frequency Divided Internal Clock */
2559 if (s->clk_rates[SCI_BRG_INT] && sci_getreg(port, SCDL)->size) {
2560 err = sci_brg_calc(s, baud, s->clk_rates[SCI_BRG_INT], &dl1,
2561 &srr1);
2562 if (abs(err) < abs(min_err)) {
2563 best_clk = SCI_BRG_INT;
2564 scr_val = SCSCR_CKE1;
2565 sccks = SCCKS_XIN;
2566 min_err = err;
2567 dl = dl1;
2568 srr = srr1;
2569 if (!min_err)
2570 goto done;
2571 }
2572 }
2573
2574 /* Divided Functional Clock using standard Bit Rate Register */
2575 err = sci_scbrr_calc(s, baud, &brr1, &srr1, &cks1);
2576 if (abs(err) < abs(min_err)) {
2577 best_clk = SCI_FCK;
2578 scr_val = 0;
2579 min_err = err;
2580 brr = brr1;
2581 srr = srr1;
2582 cks = cks1;
2583 }
2584
2585 done:
2586 if (best_clk >= 0)
2587 dev_dbg(port->dev, "Using clk %pC for %u%+d bps\n",
2588 s->clks[best_clk], baud, min_err);
2589
2590 sci_port_enable(s);
2591
2592 /*
2593 * Program the optional External Baud Rate Generator (BRG) first.
2594 * It controls the mux to select (H)SCK or frequency divided clock.
2595 */
2596 if (best_clk >= 0 && sci_getreg(port, SCCKS)->size) {
2597 serial_port_out(port, SCDL, dl);
2598 serial_port_out(port, SCCKS, sccks);
2599 }
2600
2601 spin_lock_irqsave(&port->lock, flags);
2602
2603 sci_reset(port);
2604
2605 uart_update_timeout(port, termios->c_cflag, baud);
2606
2607 /* byte size and parity */
2608 bits = tty_get_frame_size(termios->c_cflag);
2609
2610 if (sci_getreg(port, SEMR)->size)
2611 serial_port_out(port, SEMR, 0);
2612
2613 if (best_clk >= 0) {
2614 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
2615 switch (srr + 1) {
2616 case 5: smr_val |= SCSMR_SRC_5; break;
2617 case 7: smr_val |= SCSMR_SRC_7; break;
2618 case 11: smr_val |= SCSMR_SRC_11; break;
2619 case 13: smr_val |= SCSMR_SRC_13; break;
2620 case 16: smr_val |= SCSMR_SRC_16; break;
2621 case 17: smr_val |= SCSMR_SRC_17; break;
2622 case 19: smr_val |= SCSMR_SRC_19; break;
2623 case 27: smr_val |= SCSMR_SRC_27; break;
2624 }
2625 smr_val |= cks;
2626 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2627 serial_port_out(port, SCSMR, smr_val);
2628 serial_port_out(port, SCBRR, brr);
2629 if (sci_getreg(port, HSSRR)->size) {
2630 unsigned int hssrr = srr | HSCIF_SRE;
2631 /* Calculate deviation from intended rate at the
2632 * center of the last stop bit in sampling clocks.
2633 */
2634 int last_stop = bits * 2 - 1;
2635 int deviation = DIV_ROUND_CLOSEST(min_err * last_stop *
2636 (int)(srr + 1),
2637 2 * (int)baud);
2638
2639 if (abs(deviation) >= 2) {
2640 /* At least two sampling clocks off at the
2641 * last stop bit; we can increase the error
2642 * margin by shifting the sampling point.
2643 */
2644 int shift = clamp(deviation / 2, -8, 7);
2645
2646 hssrr |= (shift << HSCIF_SRHP_SHIFT) &
2647 HSCIF_SRHP_MASK;
2648 hssrr |= HSCIF_SRDE;
2649 }
2650 serial_port_out(port, HSSRR, hssrr);
2651 }
2652
2653 /* Wait one bit interval */
2654 udelay((1000000 + (baud - 1)) / baud);
2655 } else {
2656 /* Don't touch the bit rate configuration */
2657 scr_val = s->cfg->scscr & (SCSCR_CKE1 | SCSCR_CKE0);
2658 smr_val |= serial_port_in(port, SCSMR) &
2659 (SCSMR_CKEDG | SCSMR_SRC_MASK | SCSMR_CKS);
2660 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2661 serial_port_out(port, SCSMR, smr_val);
2662 }
2663
2664 sci_init_pins(port, termios->c_cflag);
2665
2666 port->status &= ~UPSTAT_AUTOCTS;
2667 s->autorts = false;
2668 reg = sci_getreg(port, SCFCR);
2669 if (reg->size) {
2670 unsigned short ctrl = serial_port_in(port, SCFCR);
2671
2672 if ((port->flags & UPF_HARD_FLOW) &&
2673 (termios->c_cflag & CRTSCTS)) {
2674 /* There is no CTS interrupt to restart the hardware */
2675 port->status |= UPSTAT_AUTOCTS;
2676 /* MCE is enabled when RTS is raised */
2677 s->autorts = true;
2678 }
2679
2680 /*
2681 * As we've done a sci_reset() above, ensure we don't
2682 * interfere with the FIFOs while toggling MCE. As the
2683 * reset values could still be set, simply mask them out.
2684 */
2685 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
2686
2687 serial_port_out(port, SCFCR, ctrl);
2688 }
2689 if (port->flags & UPF_HARD_FLOW) {
2690 /* Refresh (Auto) RTS */
2691 sci_set_mctrl(port, port->mctrl);
2692 }
2693
2694 /*
2695 * For SCI, TE (transmit enable) must be set after setting TIE
2696 * (transmit interrupt enable) or in the same instruction to
2697 * start the transmitting process. So skip setting TE here for SCI.
2698 */
2699 if (port->type != PORT_SCI)
2700 scr_val |= SCSCR_TE;
2701 scr_val |= SCSCR_RE | (s->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0));
2702 serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
2703 if ((srr + 1 == 5) &&
2704 (port->type == PORT_SCIFA || port->type == PORT_SCIFB)) {
2705 /*
2706 * In asynchronous mode, when the sampling rate is 1/5, first
2707 * received data may become invalid on some SCIFA and SCIFB.
2708 * To avoid this problem wait more than 1 serial data time (1
2709 * bit time x serial data number) after setting SCSCR.RE = 1.
2710 */
2711 udelay(DIV_ROUND_UP(10 * 1000000, baud));
2712 }
2713
2714 /* Calculate delay for 2 DMA buffers (4 FIFO). */
2715 s->rx_frame = (10000 * bits) / (baud / 100);
2716 #ifdef CONFIG_SERIAL_SH_SCI_DMA
2717 s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
2718 #endif
2719
2720 if ((termios->c_cflag & CREAD) != 0)
2721 sci_start_rx(port);
2722
2723 spin_unlock_irqrestore(&port->lock, flags);
2724
2725 sci_port_disable(s);
2726
2727 if (UART_ENABLE_MS(port, termios->c_cflag))
2728 sci_enable_ms(port);
2729 }
2730
sci_pm(struct uart_port * port,unsigned int state,unsigned int oldstate)2731 static void sci_pm(struct uart_port *port, unsigned int state,
2732 unsigned int oldstate)
2733 {
2734 struct sci_port *sci_port = to_sci_port(port);
2735
2736 switch (state) {
2737 case UART_PM_STATE_OFF:
2738 sci_port_disable(sci_port);
2739 break;
2740 default:
2741 sci_port_enable(sci_port);
2742 break;
2743 }
2744 }
2745
sci_type(struct uart_port * port)2746 static const char *sci_type(struct uart_port *port)
2747 {
2748 switch (port->type) {
2749 case PORT_IRDA:
2750 return "irda";
2751 case PORT_SCI:
2752 return "sci";
2753 case PORT_SCIF:
2754 return "scif";
2755 case PORT_SCIFA:
2756 return "scifa";
2757 case PORT_SCIFB:
2758 return "scifb";
2759 case PORT_HSCIF:
2760 return "hscif";
2761 }
2762
2763 return NULL;
2764 }
2765
sci_remap_port(struct uart_port * port)2766 static int sci_remap_port(struct uart_port *port)
2767 {
2768 struct sci_port *sport = to_sci_port(port);
2769
2770 /*
2771 * Nothing to do if there's already an established membase.
2772 */
2773 if (port->membase)
2774 return 0;
2775
2776 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2777 port->membase = ioremap(port->mapbase, sport->reg_size);
2778 if (unlikely(!port->membase)) {
2779 dev_err(port->dev, "can't remap port#%d\n", port->line);
2780 return -ENXIO;
2781 }
2782 } else {
2783 /*
2784 * For the simple (and majority of) cases where we don't
2785 * need to do any remapping, just cast the cookie
2786 * directly.
2787 */
2788 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2789 }
2790
2791 return 0;
2792 }
2793
sci_release_port(struct uart_port * port)2794 static void sci_release_port(struct uart_port *port)
2795 {
2796 struct sci_port *sport = to_sci_port(port);
2797
2798 if (port->dev->of_node || (port->flags & UPF_IOREMAP)) {
2799 iounmap(port->membase);
2800 port->membase = NULL;
2801 }
2802
2803 release_mem_region(port->mapbase, sport->reg_size);
2804 }
2805
sci_request_port(struct uart_port * port)2806 static int sci_request_port(struct uart_port *port)
2807 {
2808 struct resource *res;
2809 struct sci_port *sport = to_sci_port(port);
2810 int ret;
2811
2812 res = request_mem_region(port->mapbase, sport->reg_size,
2813 dev_name(port->dev));
2814 if (unlikely(res == NULL)) {
2815 dev_err(port->dev, "request_mem_region failed.");
2816 return -EBUSY;
2817 }
2818
2819 ret = sci_remap_port(port);
2820 if (unlikely(ret != 0)) {
2821 release_resource(res);
2822 return ret;
2823 }
2824
2825 return 0;
2826 }
2827
sci_config_port(struct uart_port * port,int flags)2828 static void sci_config_port(struct uart_port *port, int flags)
2829 {
2830 if (flags & UART_CONFIG_TYPE) {
2831 struct sci_port *sport = to_sci_port(port);
2832
2833 port->type = sport->cfg->type;
2834 sci_request_port(port);
2835 }
2836 }
2837
sci_verify_port(struct uart_port * port,struct serial_struct * ser)2838 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2839 {
2840 if (ser->baud_base < 2400)
2841 /* No paper tape reader for Mitch.. */
2842 return -EINVAL;
2843
2844 return 0;
2845 }
2846
2847 static const struct uart_ops sci_uart_ops = {
2848 .tx_empty = sci_tx_empty,
2849 .set_mctrl = sci_set_mctrl,
2850 .get_mctrl = sci_get_mctrl,
2851 .start_tx = sci_start_tx,
2852 .stop_tx = sci_stop_tx,
2853 .stop_rx = sci_stop_rx,
2854 .enable_ms = sci_enable_ms,
2855 .break_ctl = sci_break_ctl,
2856 .startup = sci_startup,
2857 .shutdown = sci_shutdown,
2858 .flush_buffer = sci_flush_buffer,
2859 .set_termios = sci_set_termios,
2860 .pm = sci_pm,
2861 .type = sci_type,
2862 .release_port = sci_release_port,
2863 .request_port = sci_request_port,
2864 .config_port = sci_config_port,
2865 .verify_port = sci_verify_port,
2866 #ifdef CONFIG_CONSOLE_POLL
2867 .poll_get_char = sci_poll_get_char,
2868 .poll_put_char = sci_poll_put_char,
2869 #endif
2870 };
2871
sci_init_clocks(struct sci_port * sci_port,struct device * dev)2872 static int sci_init_clocks(struct sci_port *sci_port, struct device *dev)
2873 {
2874 const char *clk_names[] = {
2875 [SCI_FCK] = "fck",
2876 [SCI_SCK] = "sck",
2877 [SCI_BRG_INT] = "brg_int",
2878 [SCI_SCIF_CLK] = "scif_clk",
2879 };
2880 struct clk *clk;
2881 unsigned int i;
2882
2883 if (sci_port->cfg->type == PORT_HSCIF)
2884 clk_names[SCI_SCK] = "hsck";
2885
2886 for (i = 0; i < SCI_NUM_CLKS; i++) {
2887 clk = devm_clk_get_optional(dev, clk_names[i]);
2888 if (IS_ERR(clk))
2889 return PTR_ERR(clk);
2890
2891 if (!clk && i == SCI_FCK) {
2892 /*
2893 * Not all SH platforms declare a clock lookup entry
2894 * for SCI devices, in which case we need to get the
2895 * global "peripheral_clk" clock.
2896 */
2897 clk = devm_clk_get(dev, "peripheral_clk");
2898 if (IS_ERR(clk))
2899 return dev_err_probe(dev, PTR_ERR(clk),
2900 "failed to get %s\n",
2901 clk_names[i]);
2902 }
2903
2904 if (!clk)
2905 dev_dbg(dev, "failed to get %s\n", clk_names[i]);
2906 else
2907 dev_dbg(dev, "clk %s is %pC rate %lu\n", clk_names[i],
2908 clk, clk_get_rate(clk));
2909 sci_port->clks[i] = clk;
2910 }
2911 return 0;
2912 }
2913
2914 static const struct sci_port_params *
sci_probe_regmap(const struct plat_sci_port * cfg)2915 sci_probe_regmap(const struct plat_sci_port *cfg)
2916 {
2917 unsigned int regtype;
2918
2919 if (cfg->regtype != SCIx_PROBE_REGTYPE)
2920 return &sci_port_params[cfg->regtype];
2921
2922 switch (cfg->type) {
2923 case PORT_SCI:
2924 regtype = SCIx_SCI_REGTYPE;
2925 break;
2926 case PORT_IRDA:
2927 regtype = SCIx_IRDA_REGTYPE;
2928 break;
2929 case PORT_SCIFA:
2930 regtype = SCIx_SCIFA_REGTYPE;
2931 break;
2932 case PORT_SCIFB:
2933 regtype = SCIx_SCIFB_REGTYPE;
2934 break;
2935 case PORT_SCIF:
2936 /*
2937 * The SH-4 is a bit of a misnomer here, although that's
2938 * where this particular port layout originated. This
2939 * configuration (or some slight variation thereof)
2940 * remains the dominant model for all SCIFs.
2941 */
2942 regtype = SCIx_SH4_SCIF_REGTYPE;
2943 break;
2944 case PORT_HSCIF:
2945 regtype = SCIx_HSCIF_REGTYPE;
2946 break;
2947 default:
2948 pr_err("Can't probe register map for given port\n");
2949 return NULL;
2950 }
2951
2952 return &sci_port_params[regtype];
2953 }
2954
sci_init_single(struct platform_device * dev,struct sci_port * sci_port,unsigned int index,const struct plat_sci_port * p,bool early)2955 static int sci_init_single(struct platform_device *dev,
2956 struct sci_port *sci_port, unsigned int index,
2957 const struct plat_sci_port *p, bool early)
2958 {
2959 struct uart_port *port = &sci_port->port;
2960 const struct resource *res;
2961 unsigned int i;
2962 int ret;
2963
2964 sci_port->cfg = p;
2965
2966 port->ops = &sci_uart_ops;
2967 port->iotype = UPIO_MEM;
2968 port->line = index;
2969 port->has_sysrq = IS_ENABLED(CONFIG_SERIAL_SH_SCI_CONSOLE);
2970
2971 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2972 if (res == NULL)
2973 return -ENOMEM;
2974
2975 port->mapbase = res->start;
2976 sci_port->reg_size = resource_size(res);
2977
2978 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i) {
2979 if (i)
2980 sci_port->irqs[i] = platform_get_irq_optional(dev, i);
2981 else
2982 sci_port->irqs[i] = platform_get_irq(dev, i);
2983 }
2984
2985 /*
2986 * The fourth interrupt on SCI port is transmit end interrupt, so
2987 * shuffle the interrupts.
2988 */
2989 if (p->type == PORT_SCI)
2990 swap(sci_port->irqs[SCIx_BRI_IRQ], sci_port->irqs[SCIx_TEI_IRQ]);
2991
2992 /* The SCI generates several interrupts. They can be muxed together or
2993 * connected to different interrupt lines. In the muxed case only one
2994 * interrupt resource is specified as there is only one interrupt ID.
2995 * In the non-muxed case, up to 6 interrupt signals might be generated
2996 * from the SCI, however those signals might have their own individual
2997 * interrupt ID numbers, or muxed together with another interrupt.
2998 */
2999 if (sci_port->irqs[0] < 0)
3000 return -ENXIO;
3001
3002 if (sci_port->irqs[1] < 0)
3003 for (i = 1; i < ARRAY_SIZE(sci_port->irqs); i++)
3004 sci_port->irqs[i] = sci_port->irqs[0];
3005
3006 sci_port->params = sci_probe_regmap(p);
3007 if (unlikely(sci_port->params == NULL))
3008 return -EINVAL;
3009
3010 switch (p->type) {
3011 case PORT_SCIFB:
3012 sci_port->rx_trigger = 48;
3013 break;
3014 case PORT_HSCIF:
3015 sci_port->rx_trigger = 64;
3016 break;
3017 case PORT_SCIFA:
3018 sci_port->rx_trigger = 32;
3019 break;
3020 case PORT_SCIF:
3021 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE)
3022 /* RX triggering not implemented for this IP */
3023 sci_port->rx_trigger = 1;
3024 else
3025 sci_port->rx_trigger = 8;
3026 break;
3027 default:
3028 sci_port->rx_trigger = 1;
3029 break;
3030 }
3031
3032 sci_port->rx_fifo_timeout = 0;
3033 sci_port->hscif_tot = 0;
3034
3035 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
3036 * match the SoC datasheet, this should be investigated. Let platform
3037 * data override the sampling rate for now.
3038 */
3039 sci_port->sampling_rate_mask = p->sampling_rate
3040 ? SCI_SR(p->sampling_rate)
3041 : sci_port->params->sampling_rate_mask;
3042
3043 if (!early) {
3044 ret = sci_init_clocks(sci_port, &dev->dev);
3045 if (ret < 0)
3046 return ret;
3047 }
3048
3049 port->type = p->type;
3050 port->flags = UPF_FIXED_PORT | UPF_BOOT_AUTOCONF | p->flags;
3051 port->fifosize = sci_port->params->fifosize;
3052
3053 if (port->type == PORT_SCI && !dev->dev.of_node) {
3054 if (sci_port->reg_size >= 0x20)
3055 port->regshift = 2;
3056 else
3057 port->regshift = 1;
3058 }
3059
3060 /*
3061 * The UART port needs an IRQ value, so we peg this to the RX IRQ
3062 * for the multi-IRQ ports, which is where we are primarily
3063 * concerned with the shutdown path synchronization.
3064 *
3065 * For the muxed case there's nothing more to do.
3066 */
3067 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
3068 port->irqflags = 0;
3069
3070 port->serial_in = sci_serial_in;
3071 port->serial_out = sci_serial_out;
3072
3073 return 0;
3074 }
3075
3076 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) || \
3077 defined(CONFIG_SERIAL_SH_SCI_EARLYCON)
serial_console_putchar(struct uart_port * port,unsigned char ch)3078 static void serial_console_putchar(struct uart_port *port, unsigned char ch)
3079 {
3080 sci_poll_put_char(port, ch);
3081 }
3082
3083 /*
3084 * Print a string to the serial port trying not to disturb
3085 * any possible real use of the port...
3086 */
serial_console_write(struct console * co,const char * s,unsigned count)3087 static void serial_console_write(struct console *co, const char *s,
3088 unsigned count)
3089 {
3090 struct sci_port *sci_port = &sci_ports[co->index];
3091 struct uart_port *port = &sci_port->port;
3092 unsigned short bits, ctrl, ctrl_temp;
3093 unsigned long flags;
3094 int locked = 1;
3095
3096 if (port->sysrq)
3097 locked = 0;
3098 else if (oops_in_progress)
3099 locked = spin_trylock_irqsave(&port->lock, flags);
3100 else
3101 spin_lock_irqsave(&port->lock, flags);
3102
3103 /* first save SCSCR then disable interrupts, keep clock source */
3104 ctrl = serial_port_in(port, SCSCR);
3105 ctrl_temp = SCSCR_RE | SCSCR_TE |
3106 (sci_port->cfg->scscr & ~(SCSCR_CKE1 | SCSCR_CKE0)) |
3107 (ctrl & (SCSCR_CKE1 | SCSCR_CKE0));
3108 serial_port_out(port, SCSCR, ctrl_temp | sci_port->hscif_tot);
3109
3110 uart_console_write(port, s, count, serial_console_putchar);
3111
3112 /* wait until fifo is empty and last bit has been transmitted */
3113 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
3114 while ((serial_port_in(port, SCxSR) & bits) != bits)
3115 cpu_relax();
3116
3117 /* restore the SCSCR */
3118 serial_port_out(port, SCSCR, ctrl);
3119
3120 if (locked)
3121 spin_unlock_irqrestore(&port->lock, flags);
3122 }
3123
serial_console_setup(struct console * co,char * options)3124 static int serial_console_setup(struct console *co, char *options)
3125 {
3126 struct sci_port *sci_port;
3127 struct uart_port *port;
3128 int baud = 115200;
3129 int bits = 8;
3130 int parity = 'n';
3131 int flow = 'n';
3132 int ret;
3133
3134 /*
3135 * Refuse to handle any bogus ports.
3136 */
3137 if (co->index < 0 || co->index >= SCI_NPORTS)
3138 return -ENODEV;
3139
3140 sci_port = &sci_ports[co->index];
3141 port = &sci_port->port;
3142
3143 /*
3144 * Refuse to handle uninitialized ports.
3145 */
3146 if (!port->ops)
3147 return -ENODEV;
3148
3149 ret = sci_remap_port(port);
3150 if (unlikely(ret != 0))
3151 return ret;
3152
3153 if (options)
3154 uart_parse_options(options, &baud, &parity, &bits, &flow);
3155
3156 return uart_set_options(port, co, baud, parity, bits, flow);
3157 }
3158
3159 static struct console serial_console = {
3160 .name = "ttySC",
3161 .device = uart_console_device,
3162 .write = serial_console_write,
3163 .setup = serial_console_setup,
3164 .flags = CON_PRINTBUFFER,
3165 .index = -1,
3166 .data = &sci_uart_driver,
3167 };
3168
3169 #ifdef CONFIG_SUPERH
3170 static char early_serial_buf[32];
3171
early_serial_console_setup(struct console * co,char * options)3172 static int early_serial_console_setup(struct console *co, char *options)
3173 {
3174 /*
3175 * This early console is always registered using the earlyprintk=
3176 * parameter, which does not call add_preferred_console(). Thus
3177 * @options is always NULL and the options for this early console
3178 * are passed using a custom buffer.
3179 */
3180 WARN_ON(options);
3181
3182 return serial_console_setup(co, early_serial_buf);
3183 }
3184
3185 static struct console early_serial_console = {
3186 .name = "early_ttySC",
3187 .write = serial_console_write,
3188 .setup = early_serial_console_setup,
3189 .flags = CON_PRINTBUFFER,
3190 .index = -1,
3191 };
3192
sci_probe_earlyprintk(struct platform_device * pdev)3193 static int sci_probe_earlyprintk(struct platform_device *pdev)
3194 {
3195 const struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
3196
3197 if (early_serial_console.data)
3198 return -EEXIST;
3199
3200 early_serial_console.index = pdev->id;
3201
3202 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
3203
3204 if (!strstr(early_serial_buf, "keep"))
3205 early_serial_console.flags |= CON_BOOT;
3206
3207 register_console(&early_serial_console);
3208 return 0;
3209 }
3210 #endif
3211
3212 #define SCI_CONSOLE (&serial_console)
3213
3214 #else
sci_probe_earlyprintk(struct platform_device * pdev)3215 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
3216 {
3217 return -EINVAL;
3218 }
3219
3220 #define SCI_CONSOLE NULL
3221
3222 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE || CONFIG_SERIAL_SH_SCI_EARLYCON */
3223
3224 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
3225
3226 static DEFINE_MUTEX(sci_uart_registration_lock);
3227 static struct uart_driver sci_uart_driver = {
3228 .owner = THIS_MODULE,
3229 .driver_name = "sci",
3230 .dev_name = "ttySC",
3231 .major = SCI_MAJOR,
3232 .minor = SCI_MINOR_START,
3233 .nr = SCI_NPORTS,
3234 .cons = SCI_CONSOLE,
3235 };
3236
sci_remove(struct platform_device * dev)3237 static int sci_remove(struct platform_device *dev)
3238 {
3239 struct sci_port *port = platform_get_drvdata(dev);
3240 unsigned int type = port->port.type; /* uart_remove_... clears it */
3241
3242 sci_ports_in_use &= ~BIT(port->port.line);
3243 uart_remove_one_port(&sci_uart_driver, &port->port);
3244
3245 if (port->port.fifosize > 1)
3246 device_remove_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3247 if (type == PORT_SCIFA || type == PORT_SCIFB || type == PORT_HSCIF)
3248 device_remove_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3249
3250 return 0;
3251 }
3252
3253
3254 #define SCI_OF_DATA(type, regtype) (void *)((type) << 16 | (regtype))
3255 #define SCI_OF_TYPE(data) ((unsigned long)(data) >> 16)
3256 #define SCI_OF_REGTYPE(data) ((unsigned long)(data) & 0xffff)
3257
3258 static const struct of_device_id of_sci_match[] __maybe_unused = {
3259 /* SoC-specific types */
3260 {
3261 .compatible = "renesas,scif-r7s72100",
3262 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH2_SCIF_FIFODATA_REGTYPE),
3263 },
3264 {
3265 .compatible = "renesas,scif-r7s9210",
3266 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3267 },
3268 {
3269 .compatible = "renesas,scif-r9a07g044",
3270 .data = SCI_OF_DATA(PORT_SCIF, SCIx_RZ_SCIFA_REGTYPE),
3271 },
3272 /* Family-specific types */
3273 {
3274 .compatible = "renesas,rcar-gen1-scif",
3275 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3276 }, {
3277 .compatible = "renesas,rcar-gen2-scif",
3278 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3279 }, {
3280 .compatible = "renesas,rcar-gen3-scif",
3281 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3282 }, {
3283 .compatible = "renesas,rcar-gen4-scif",
3284 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_BRG_REGTYPE),
3285 },
3286 /* Generic types */
3287 {
3288 .compatible = "renesas,scif",
3289 .data = SCI_OF_DATA(PORT_SCIF, SCIx_SH4_SCIF_REGTYPE),
3290 }, {
3291 .compatible = "renesas,scifa",
3292 .data = SCI_OF_DATA(PORT_SCIFA, SCIx_SCIFA_REGTYPE),
3293 }, {
3294 .compatible = "renesas,scifb",
3295 .data = SCI_OF_DATA(PORT_SCIFB, SCIx_SCIFB_REGTYPE),
3296 }, {
3297 .compatible = "renesas,hscif",
3298 .data = SCI_OF_DATA(PORT_HSCIF, SCIx_HSCIF_REGTYPE),
3299 }, {
3300 .compatible = "renesas,sci",
3301 .data = SCI_OF_DATA(PORT_SCI, SCIx_SCI_REGTYPE),
3302 }, {
3303 /* Terminator */
3304 },
3305 };
3306 MODULE_DEVICE_TABLE(of, of_sci_match);
3307
sci_reset_control_assert(void * data)3308 static void sci_reset_control_assert(void *data)
3309 {
3310 reset_control_assert(data);
3311 }
3312
sci_parse_dt(struct platform_device * pdev,unsigned int * dev_id)3313 static struct plat_sci_port *sci_parse_dt(struct platform_device *pdev,
3314 unsigned int *dev_id)
3315 {
3316 struct device_node *np = pdev->dev.of_node;
3317 struct reset_control *rstc;
3318 struct plat_sci_port *p;
3319 struct sci_port *sp;
3320 const void *data;
3321 int id, ret;
3322
3323 if (!IS_ENABLED(CONFIG_OF) || !np)
3324 return ERR_PTR(-EINVAL);
3325
3326 data = of_device_get_match_data(&pdev->dev);
3327
3328 rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
3329 if (IS_ERR(rstc))
3330 return ERR_PTR(dev_err_probe(&pdev->dev, PTR_ERR(rstc),
3331 "failed to get reset ctrl\n"));
3332
3333 ret = reset_control_deassert(rstc);
3334 if (ret) {
3335 dev_err(&pdev->dev, "failed to deassert reset %d\n", ret);
3336 return ERR_PTR(ret);
3337 }
3338
3339 ret = devm_add_action_or_reset(&pdev->dev, sci_reset_control_assert, rstc);
3340 if (ret) {
3341 dev_err(&pdev->dev, "failed to register assert devm action, %d\n",
3342 ret);
3343 return ERR_PTR(ret);
3344 }
3345
3346 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
3347 if (!p)
3348 return ERR_PTR(-ENOMEM);
3349
3350 /* Get the line number from the aliases node. */
3351 id = of_alias_get_id(np, "serial");
3352 if (id < 0 && ~sci_ports_in_use)
3353 id = ffz(sci_ports_in_use);
3354 if (id < 0) {
3355 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
3356 return ERR_PTR(-EINVAL);
3357 }
3358 if (id >= ARRAY_SIZE(sci_ports)) {
3359 dev_err(&pdev->dev, "serial%d out of range\n", id);
3360 return ERR_PTR(-EINVAL);
3361 }
3362
3363 sp = &sci_ports[id];
3364 sp->rstc = rstc;
3365 *dev_id = id;
3366
3367 p->type = SCI_OF_TYPE(data);
3368 p->regtype = SCI_OF_REGTYPE(data);
3369
3370 sp->has_rtscts = of_property_read_bool(np, "uart-has-rtscts");
3371
3372 return p;
3373 }
3374
sci_probe_single(struct platform_device * dev,unsigned int index,struct plat_sci_port * p,struct sci_port * sciport,struct resource * sci_res)3375 static int sci_probe_single(struct platform_device *dev,
3376 unsigned int index,
3377 struct plat_sci_port *p,
3378 struct sci_port *sciport,
3379 struct resource *sci_res)
3380 {
3381 int ret;
3382
3383 /* Sanity check */
3384 if (unlikely(index >= SCI_NPORTS)) {
3385 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
3386 index+1, SCI_NPORTS);
3387 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
3388 return -EINVAL;
3389 }
3390 BUILD_BUG_ON(SCI_NPORTS > sizeof(sci_ports_in_use) * 8);
3391 if (sci_ports_in_use & BIT(index))
3392 return -EBUSY;
3393
3394 mutex_lock(&sci_uart_registration_lock);
3395 if (!sci_uart_driver.state) {
3396 ret = uart_register_driver(&sci_uart_driver);
3397 if (ret) {
3398 mutex_unlock(&sci_uart_registration_lock);
3399 return ret;
3400 }
3401 }
3402 mutex_unlock(&sci_uart_registration_lock);
3403
3404 ret = sci_init_single(dev, sciport, index, p, false);
3405 if (ret)
3406 return ret;
3407
3408 sciport->port.dev = &dev->dev;
3409 ret = devm_pm_runtime_enable(&dev->dev);
3410 if (ret)
3411 return ret;
3412
3413 sciport->gpios = mctrl_gpio_init(&sciport->port, 0);
3414 if (IS_ERR(sciport->gpios))
3415 return PTR_ERR(sciport->gpios);
3416
3417 if (sciport->has_rtscts) {
3418 if (mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_CTS) ||
3419 mctrl_gpio_to_gpiod(sciport->gpios, UART_GPIO_RTS)) {
3420 dev_err(&dev->dev, "Conflicting RTS/CTS config\n");
3421 return -EINVAL;
3422 }
3423 sciport->port.flags |= UPF_HARD_FLOW;
3424 }
3425
3426 if (sci_uart_earlycon && sci_ports[0].port.mapbase == sci_res->start) {
3427 /*
3428 * Skip cleanup the sci_port[0] in early_console_exit(), this
3429 * port is the same as the earlycon one.
3430 */
3431 sci_uart_earlycon_dev_probing = true;
3432 }
3433
3434 return uart_add_one_port(&sci_uart_driver, &sciport->port);
3435 }
3436
sci_probe(struct platform_device * dev)3437 static int sci_probe(struct platform_device *dev)
3438 {
3439 struct plat_sci_port *p;
3440 struct resource *res;
3441 struct sci_port *sp;
3442 unsigned int dev_id;
3443 int ret;
3444
3445 /*
3446 * If we've come here via earlyprintk initialization, head off to
3447 * the special early probe. We don't have sufficient device state
3448 * to make it beyond this yet.
3449 */
3450 #ifdef CONFIG_SUPERH
3451 if (is_sh_early_platform_device(dev))
3452 return sci_probe_earlyprintk(dev);
3453 #endif
3454
3455 if (dev->dev.of_node) {
3456 p = sci_parse_dt(dev, &dev_id);
3457 if (IS_ERR(p))
3458 return PTR_ERR(p);
3459 } else {
3460 p = dev->dev.platform_data;
3461 if (p == NULL) {
3462 dev_err(&dev->dev, "no platform data supplied\n");
3463 return -EINVAL;
3464 }
3465
3466 dev_id = dev->id;
3467 }
3468
3469 sp = &sci_ports[dev_id];
3470
3471 /*
3472 * In case:
3473 * - the probed port alias is zero (as the one used by earlycon), and
3474 * - the earlycon is still active (e.g., "earlycon keep_bootcon" in
3475 * bootargs)
3476 *
3477 * defer the probe of this serial. This is a debug scenario and the user
3478 * must be aware of it.
3479 *
3480 * Except when the probed port is the same as the earlycon port.
3481 */
3482
3483 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3484 if (!res)
3485 return -ENODEV;
3486
3487 if (sci_uart_earlycon && sp == &sci_ports[0] && sp->port.mapbase != res->start)
3488 return dev_err_probe(&dev->dev, -EBUSY, "sci_port[0] is used by earlycon!\n");
3489
3490 platform_set_drvdata(dev, sp);
3491
3492 ret = sci_probe_single(dev, dev_id, p, sp, res);
3493 if (ret)
3494 return ret;
3495
3496 if (sp->port.fifosize > 1) {
3497 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_trigger);
3498 if (ret)
3499 return ret;
3500 }
3501 if (sp->port.type == PORT_SCIFA || sp->port.type == PORT_SCIFB ||
3502 sp->port.type == PORT_HSCIF) {
3503 ret = device_create_file(&dev->dev, &dev_attr_rx_fifo_timeout);
3504 if (ret) {
3505 if (sp->port.fifosize > 1) {
3506 device_remove_file(&dev->dev,
3507 &dev_attr_rx_fifo_trigger);
3508 }
3509 return ret;
3510 }
3511 }
3512
3513 #ifdef CONFIG_SH_STANDARD_BIOS
3514 sh_bios_gdb_detach();
3515 #endif
3516
3517 sci_ports_in_use |= BIT(dev_id);
3518 return 0;
3519 }
3520
sci_console_save(struct sci_port * s)3521 static void sci_console_save(struct sci_port *s)
3522 {
3523 struct sci_suspend_regs *regs = &s->suspend_regs;
3524 struct uart_port *port = &s->port;
3525
3526 if (sci_getreg(port, SCDL)->size)
3527 regs->scdl = sci_serial_in(port, SCDL);
3528 if (sci_getreg(port, SCCKS)->size)
3529 regs->sccks = sci_serial_in(port, SCCKS);
3530 if (sci_getreg(port, SCSMR)->size)
3531 regs->scsmr = sci_serial_in(port, SCSMR);
3532 if (sci_getreg(port, SCSCR)->size)
3533 regs->scscr = sci_serial_in(port, SCSCR);
3534 if (sci_getreg(port, SCFCR)->size)
3535 regs->scfcr = sci_serial_in(port, SCFCR);
3536 if (sci_getreg(port, SCSPTR)->size)
3537 regs->scsptr = sci_serial_in(port, SCSPTR);
3538 if (sci_getreg(port, SCBRR)->size)
3539 regs->scbrr = sci_serial_in(port, SCBRR);
3540 if (sci_getreg(port, HSSRR)->size)
3541 regs->hssrr = sci_serial_in(port, HSSRR);
3542 if (sci_getreg(port, SCPCR)->size)
3543 regs->scpcr = sci_serial_in(port, SCPCR);
3544 if (sci_getreg(port, SCPDR)->size)
3545 regs->scpdr = sci_serial_in(port, SCPDR);
3546 if (sci_getreg(port, SEMR)->size)
3547 regs->semr = sci_serial_in(port, SEMR);
3548 }
3549
sci_console_restore(struct sci_port * s)3550 static void sci_console_restore(struct sci_port *s)
3551 {
3552 struct sci_suspend_regs *regs = &s->suspend_regs;
3553 struct uart_port *port = &s->port;
3554
3555 if (sci_getreg(port, SCDL)->size)
3556 sci_serial_out(port, SCDL, regs->scdl);
3557 if (sci_getreg(port, SCCKS)->size)
3558 sci_serial_out(port, SCCKS, regs->sccks);
3559 if (sci_getreg(port, SCSMR)->size)
3560 sci_serial_out(port, SCSMR, regs->scsmr);
3561 if (sci_getreg(port, SCSCR)->size)
3562 sci_serial_out(port, SCSCR, regs->scscr);
3563 if (sci_getreg(port, SCFCR)->size)
3564 sci_serial_out(port, SCFCR, regs->scfcr);
3565 if (sci_getreg(port, SCSPTR)->size)
3566 sci_serial_out(port, SCSPTR, regs->scsptr);
3567 if (sci_getreg(port, SCBRR)->size)
3568 sci_serial_out(port, SCBRR, regs->scbrr);
3569 if (sci_getreg(port, HSSRR)->size)
3570 sci_serial_out(port, HSSRR, regs->hssrr);
3571 if (sci_getreg(port, SCPCR)->size)
3572 sci_serial_out(port, SCPCR, regs->scpcr);
3573 if (sci_getreg(port, SCPDR)->size)
3574 sci_serial_out(port, SCPDR, regs->scpdr);
3575 if (sci_getreg(port, SEMR)->size)
3576 sci_serial_out(port, SEMR, regs->semr);
3577 }
3578
sci_suspend(struct device * dev)3579 static __maybe_unused int sci_suspend(struct device *dev)
3580 {
3581 struct sci_port *sport = dev_get_drvdata(dev);
3582
3583 if (sport) {
3584 uart_suspend_port(&sci_uart_driver, &sport->port);
3585
3586 if (!console_suspend_enabled && uart_console(&sport->port))
3587 sci_console_save(sport);
3588 else
3589 return reset_control_assert(sport->rstc);
3590 }
3591
3592 return 0;
3593 }
3594
sci_resume(struct device * dev)3595 static __maybe_unused int sci_resume(struct device *dev)
3596 {
3597 struct sci_port *sport = dev_get_drvdata(dev);
3598
3599 if (sport) {
3600 if (!console_suspend_enabled && uart_console(&sport->port)) {
3601 sci_console_restore(sport);
3602 } else {
3603 int ret = reset_control_deassert(sport->rstc);
3604
3605 if (ret)
3606 return ret;
3607 }
3608
3609 uart_resume_port(&sci_uart_driver, &sport->port);
3610 }
3611
3612 return 0;
3613 }
3614
3615 static SIMPLE_DEV_PM_OPS(sci_dev_pm_ops, sci_suspend, sci_resume);
3616
3617 static struct platform_driver sci_driver = {
3618 .probe = sci_probe,
3619 .remove = sci_remove,
3620 .driver = {
3621 .name = "sh-sci",
3622 .pm = &sci_dev_pm_ops,
3623 .of_match_table = of_match_ptr(of_sci_match),
3624 },
3625 };
3626
sci_init(void)3627 static int __init sci_init(void)
3628 {
3629 pr_info("%s\n", banner);
3630
3631 return platform_driver_register(&sci_driver);
3632 }
3633
sci_exit(void)3634 static void __exit sci_exit(void)
3635 {
3636 platform_driver_unregister(&sci_driver);
3637
3638 if (sci_uart_driver.state)
3639 uart_unregister_driver(&sci_uart_driver);
3640 }
3641
3642 #if defined(CONFIG_SUPERH) && defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
3643 sh_early_platform_init_buffer("earlyprintk", &sci_driver,
3644 early_serial_buf, ARRAY_SIZE(early_serial_buf));
3645 #endif
3646 #ifdef CONFIG_SERIAL_SH_SCI_EARLYCON
3647 static struct plat_sci_port port_cfg;
3648
early_console_exit(struct console * co)3649 static int early_console_exit(struct console *co)
3650 {
3651 struct sci_port *sci_port = &sci_ports[0];
3652
3653 /*
3654 * Clean the slot used by earlycon. A new SCI device might
3655 * map to this slot.
3656 */
3657 if (!sci_uart_earlycon_dev_probing) {
3658 memset(sci_port, 0, sizeof(*sci_port));
3659 sci_uart_earlycon = false;
3660 }
3661
3662 return 0;
3663 }
3664
early_console_setup(struct earlycon_device * device,int type)3665 static int __init early_console_setup(struct earlycon_device *device,
3666 int type)
3667 {
3668 if (!device->port.membase)
3669 return -ENODEV;
3670
3671 device->port.serial_in = sci_serial_in;
3672 device->port.serial_out = sci_serial_out;
3673 device->port.type = type;
3674 memcpy(&sci_ports[0].port, &device->port, sizeof(struct uart_port));
3675 port_cfg.type = type;
3676 sci_ports[0].cfg = &port_cfg;
3677 sci_ports[0].params = sci_probe_regmap(&port_cfg);
3678 sci_uart_earlycon = true;
3679 port_cfg.scscr = sci_serial_in(&sci_ports[0].port, SCSCR);
3680 sci_serial_out(&sci_ports[0].port, SCSCR,
3681 SCSCR_RE | SCSCR_TE | port_cfg.scscr);
3682
3683 device->con->write = serial_console_write;
3684 device->con->exit = early_console_exit;
3685
3686 return 0;
3687 }
sci_early_console_setup(struct earlycon_device * device,const char * opt)3688 static int __init sci_early_console_setup(struct earlycon_device *device,
3689 const char *opt)
3690 {
3691 return early_console_setup(device, PORT_SCI);
3692 }
scif_early_console_setup(struct earlycon_device * device,const char * opt)3693 static int __init scif_early_console_setup(struct earlycon_device *device,
3694 const char *opt)
3695 {
3696 return early_console_setup(device, PORT_SCIF);
3697 }
rzscifa_early_console_setup(struct earlycon_device * device,const char * opt)3698 static int __init rzscifa_early_console_setup(struct earlycon_device *device,
3699 const char *opt)
3700 {
3701 port_cfg.regtype = SCIx_RZ_SCIFA_REGTYPE;
3702 return early_console_setup(device, PORT_SCIF);
3703 }
3704
scifa_early_console_setup(struct earlycon_device * device,const char * opt)3705 static int __init scifa_early_console_setup(struct earlycon_device *device,
3706 const char *opt)
3707 {
3708 return early_console_setup(device, PORT_SCIFA);
3709 }
scifb_early_console_setup(struct earlycon_device * device,const char * opt)3710 static int __init scifb_early_console_setup(struct earlycon_device *device,
3711 const char *opt)
3712 {
3713 return early_console_setup(device, PORT_SCIFB);
3714 }
hscif_early_console_setup(struct earlycon_device * device,const char * opt)3715 static int __init hscif_early_console_setup(struct earlycon_device *device,
3716 const char *opt)
3717 {
3718 return early_console_setup(device, PORT_HSCIF);
3719 }
3720
3721 OF_EARLYCON_DECLARE(sci, "renesas,sci", sci_early_console_setup);
3722 OF_EARLYCON_DECLARE(scif, "renesas,scif", scif_early_console_setup);
3723 OF_EARLYCON_DECLARE(scif, "renesas,scif-r7s9210", rzscifa_early_console_setup);
3724 OF_EARLYCON_DECLARE(scif, "renesas,scif-r9a07g044", rzscifa_early_console_setup);
3725 OF_EARLYCON_DECLARE(scifa, "renesas,scifa", scifa_early_console_setup);
3726 OF_EARLYCON_DECLARE(scifb, "renesas,scifb", scifb_early_console_setup);
3727 OF_EARLYCON_DECLARE(hscif, "renesas,hscif", hscif_early_console_setup);
3728 #endif /* CONFIG_SERIAL_SH_SCI_EARLYCON */
3729
3730 module_init(sci_init);
3731 module_exit(sci_exit);
3732
3733 MODULE_LICENSE("GPL");
3734 MODULE_ALIAS("platform:sh-sci");
3735 MODULE_AUTHOR("Paul Mundt");
3736 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
3737