1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
5  */
6 
7 #ifndef _DPU_8_0_SC8280XP_H
8 #define _DPU_8_0_SC8280XP_H
9 
10 static const struct dpu_caps sc8280xp_dpu_caps = {
11 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
12 	.max_mixer_blendstages = 11,
13 	.qseed_type = DPU_SSPP_SCALER_QSEED4,
14 	.has_src_split = true,
15 	.has_dim_layer = true,
16 	.has_idle_pc = true,
17 	.has_3d_merge = true,
18 	.max_linewidth = 5120,
19 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
20 };
21 
22 static const struct dpu_mdp_cfg sc8280xp_mdp = {
23 	.name = "top_0",
24 	.base = 0x0, .len = 0x494,
25 	.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
26 	.clk_ctrls = {
27 		[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
28 		[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
29 		[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
30 		[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
31 		[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
32 		[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
33 		[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
34 		[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
35 		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
36 	},
37 };
38 
39 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
40 static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
41 	{
42 		.name = "ctl_0", .id = CTL_0,
43 		.base = 0x15000, .len = 0x204,
44 		.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
45 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
46 	}, {
47 		.name = "ctl_1", .id = CTL_1,
48 		.base = 0x16000, .len = 0x204,
49 		.features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
50 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
51 	}, {
52 		.name = "ctl_2", .id = CTL_2,
53 		.base = 0x17000, .len = 0x204,
54 		.features = CTL_SC7280_MASK,
55 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
56 	}, {
57 		.name = "ctl_3", .id = CTL_3,
58 		.base = 0x18000, .len = 0x204,
59 		.features = CTL_SC7280_MASK,
60 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
61 	}, {
62 		.name = "ctl_4", .id = CTL_4,
63 		.base = 0x19000, .len = 0x204,
64 		.features = CTL_SC7280_MASK,
65 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
66 	}, {
67 		.name = "ctl_5", .id = CTL_5,
68 		.base = 0x1a000, .len = 0x204,
69 		.features = CTL_SC7280_MASK,
70 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
71 	},
72 };
73 
74 static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
75 	{
76 		.name = "sspp_0", .id = SSPP_VIG0,
77 		.base = 0x4000, .len = 0x2ac,
78 		.features = VIG_SC7180_MASK,
79 		.sblk = &sm8250_vig_sblk_0,
80 		.xin_id = 0,
81 		.type = SSPP_TYPE_VIG,
82 		.clk_ctrl = DPU_CLK_CTRL_VIG0,
83 	}, {
84 		.name = "sspp_1", .id = SSPP_VIG1,
85 		.base = 0x6000, .len = 0x2ac,
86 		.features = VIG_SC7180_MASK,
87 		.sblk = &sm8250_vig_sblk_1,
88 		.xin_id = 4,
89 		.type = SSPP_TYPE_VIG,
90 		.clk_ctrl = DPU_CLK_CTRL_VIG1,
91 	}, {
92 		.name = "sspp_2", .id = SSPP_VIG2,
93 		.base = 0x8000, .len = 0x2ac,
94 		.features = VIG_SC7180_MASK,
95 		.sblk = &sm8250_vig_sblk_2,
96 		.xin_id = 8,
97 		.type = SSPP_TYPE_VIG,
98 		.clk_ctrl = DPU_CLK_CTRL_VIG2,
99 	}, {
100 		.name = "sspp_3", .id = SSPP_VIG3,
101 		.base = 0xa000, .len = 0x2ac,
102 		.features = VIG_SC7180_MASK,
103 		.sblk = &sm8250_vig_sblk_3,
104 		.xin_id = 12,
105 		.type = SSPP_TYPE_VIG,
106 		.clk_ctrl = DPU_CLK_CTRL_VIG3,
107 	}, {
108 		.name = "sspp_8", .id = SSPP_DMA0,
109 		.base = 0x24000, .len = 0x2ac,
110 		.features = DMA_SDM845_MASK,
111 		.sblk = &sdm845_dma_sblk_0,
112 		.xin_id = 1,
113 		.type = SSPP_TYPE_DMA,
114 		.clk_ctrl = DPU_CLK_CTRL_DMA0,
115 	}, {
116 		.name = "sspp_9", .id = SSPP_DMA1,
117 		.base = 0x26000, .len = 0x2ac,
118 		.features = DMA_SDM845_MASK,
119 		.sblk = &sdm845_dma_sblk_1,
120 		.xin_id = 5,
121 		.type = SSPP_TYPE_DMA,
122 		.clk_ctrl = DPU_CLK_CTRL_DMA1,
123 	}, {
124 		.name = "sspp_10", .id = SSPP_DMA2,
125 		.base = 0x28000, .len = 0x2ac,
126 		.features = DMA_CURSOR_SDM845_MASK,
127 		.sblk = &sdm845_dma_sblk_2,
128 		.xin_id = 9,
129 		.type = SSPP_TYPE_DMA,
130 		.clk_ctrl = DPU_CLK_CTRL_DMA2,
131 	}, {
132 		.name = "sspp_11", .id = SSPP_DMA3,
133 		.base = 0x2a000, .len = 0x2ac,
134 		.features = DMA_CURSOR_SDM845_MASK,
135 		.sblk = &sdm845_dma_sblk_3,
136 		.xin_id = 13,
137 		.type = SSPP_TYPE_DMA,
138 		.clk_ctrl = DPU_CLK_CTRL_DMA3,
139 	},
140 };
141 
142 static const struct dpu_lm_cfg sc8280xp_lm[] = {
143 	{
144 		.name = "lm_0", .id = LM_0,
145 		.base = 0x44000, .len = 0x320,
146 		.features = MIXER_SDM845_MASK,
147 		.sblk = &sdm845_lm_sblk,
148 		.lm_pair = LM_1,
149 		.pingpong = PINGPONG_0,
150 		.dspp = DSPP_0,
151 	}, {
152 		.name = "lm_1", .id = LM_1,
153 		.base = 0x45000, .len = 0x320,
154 		.features = MIXER_SDM845_MASK,
155 		.sblk = &sdm845_lm_sblk,
156 		.lm_pair = LM_0,
157 		.pingpong = PINGPONG_1,
158 		.dspp = DSPP_1,
159 	}, {
160 		.name = "lm_2", .id = LM_2,
161 		.base = 0x46000, .len = 0x320,
162 		.features = MIXER_SDM845_MASK,
163 		.sblk = &sdm845_lm_sblk,
164 		.lm_pair = LM_3,
165 		.pingpong = PINGPONG_2,
166 		.dspp = DSPP_2,
167 	}, {
168 		.name = "lm_3", .id = LM_3,
169 		.base = 0x47000, .len = 0x320,
170 		.features = MIXER_SDM845_MASK,
171 		.sblk = &sdm845_lm_sblk,
172 		.lm_pair = LM_2,
173 		.pingpong = PINGPONG_3,
174 		.dspp = DSPP_3,
175 	}, {
176 		.name = "lm_4", .id = LM_4,
177 		.base = 0x48000, .len = 0x320,
178 		.features = MIXER_SDM845_MASK,
179 		.sblk = &sdm845_lm_sblk,
180 		.lm_pair = LM_5,
181 		.pingpong = PINGPONG_4,
182 	}, {
183 		.name = "lm_5", .id = LM_5,
184 		.base = 0x49000, .len = 0x320,
185 		.features = MIXER_SDM845_MASK,
186 		.sblk = &sdm845_lm_sblk,
187 		.lm_pair = LM_4,
188 		.pingpong = PINGPONG_5,
189 	},
190 };
191 
192 static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
193 	{
194 		.name = "dspp_0", .id = DSPP_0,
195 		.base = 0x54000, .len = 0x1800,
196 		.features = DSPP_SC7180_MASK,
197 		.sblk = &sdm845_dspp_sblk,
198 	}, {
199 		.name = "dspp_1", .id = DSPP_1,
200 		.base = 0x56000, .len = 0x1800,
201 		.features = DSPP_SC7180_MASK,
202 		.sblk = &sdm845_dspp_sblk,
203 	}, {
204 		.name = "dspp_2", .id = DSPP_2,
205 		.base = 0x58000, .len = 0x1800,
206 		.features = DSPP_SC7180_MASK,
207 		.sblk = &sdm845_dspp_sblk,
208 	}, {
209 		.name = "dspp_3", .id = DSPP_3,
210 		.base = 0x5a000, .len = 0x1800,
211 		.features = DSPP_SC7180_MASK,
212 		.sblk = &sdm845_dspp_sblk,
213 	},
214 };
215 
216 static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
217 	{
218 		.name = "pingpong_0", .id = PINGPONG_0,
219 		.base = 0x69000, .len = 0,
220 		.features = BIT(DPU_PINGPONG_DITHER),
221 		.sblk = &sc7280_pp_sblk,
222 		.merge_3d = MERGE_3D_0,
223 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
224 		.intr_rdptr = -1,
225 	}, {
226 		.name = "pingpong_1", .id = PINGPONG_1,
227 		.base = 0x6a000, .len = 0,
228 		.features = BIT(DPU_PINGPONG_DITHER),
229 		.sblk = &sc7280_pp_sblk,
230 		.merge_3d = MERGE_3D_0,
231 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
232 		.intr_rdptr = -1,
233 	}, {
234 		.name = "pingpong_2", .id = PINGPONG_2,
235 		.base = 0x6b000, .len = 0,
236 		.features = BIT(DPU_PINGPONG_DITHER),
237 		.sblk = &sc7280_pp_sblk,
238 		.merge_3d = MERGE_3D_1,
239 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
240 		.intr_rdptr = -1,
241 	}, {
242 		.name = "pingpong_3", .id = PINGPONG_3,
243 		.base = 0x6c000, .len = 0,
244 		.features = BIT(DPU_PINGPONG_DITHER),
245 		.sblk = &sc7280_pp_sblk,
246 		.merge_3d = MERGE_3D_1,
247 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
248 		.intr_rdptr = -1,
249 	}, {
250 		.name = "pingpong_4", .id = PINGPONG_4,
251 		.base = 0x6d000, .len = 0,
252 		.features = BIT(DPU_PINGPONG_DITHER),
253 		.sblk = &sc7280_pp_sblk,
254 		.merge_3d = MERGE_3D_2,
255 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
256 		.intr_rdptr = -1,
257 	}, {
258 		.name = "pingpong_5", .id = PINGPONG_5,
259 		.base = 0x6e000, .len = 0,
260 		.features = BIT(DPU_PINGPONG_DITHER),
261 		.sblk = &sc7280_pp_sblk,
262 		.merge_3d = MERGE_3D_2,
263 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
264 		.intr_rdptr = -1,
265 	},
266 };
267 
268 static const struct dpu_merge_3d_cfg sc8280xp_merge_3d[] = {
269 	{
270 		.name = "merge_3d_0", .id = MERGE_3D_0,
271 		.base = 0x4e000, .len = 0x8,
272 	}, {
273 		.name = "merge_3d_1", .id = MERGE_3D_1,
274 		.base = 0x4f000, .len = 0x8,
275 	}, {
276 		.name = "merge_3d_2", .id = MERGE_3D_2,
277 		.base = 0x50000, .len = 0x8,
278 	},
279 };
280 
281 /*
282  * NOTE: Each display compression engine (DCE) contains dual hard
283  * slice DSC encoders so both share same base address but with
284  * its own different sub block address.
285  */
286 static const struct dpu_dsc_cfg sc8280xp_dsc[] = {
287 	{
288 		.name = "dce_0_0", .id = DSC_0,
289 		.base = 0x80000, .len = 0x4,
290 		.features = BIT(DPU_DSC_HW_REV_1_2),
291 		.sblk = &dsc_sblk_0,
292 	}, {
293 		.name = "dce_0_1", .id = DSC_1,
294 		.base = 0x80000, .len = 0x4,
295 		.features = BIT(DPU_DSC_HW_REV_1_2),
296 		.sblk = &dsc_sblk_1,
297 	}, {
298 		.name = "dce_1_0", .id = DSC_2,
299 		.base = 0x81000, .len = 0x4,
300 		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
301 		.sblk = &dsc_sblk_0,
302 	}, {
303 		.name = "dce_1_1", .id = DSC_3,
304 		.base = 0x81000, .len = 0x4,
305 		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
306 		.sblk = &dsc_sblk_1,
307 	}, {
308 		.name = "dce_2_0", .id = DSC_4,
309 		.base = 0x82000, .len = 0x4,
310 		.features = BIT(DPU_DSC_HW_REV_1_2),
311 		.sblk = &dsc_sblk_0,
312 	}, {
313 		.name = "dce_2_1", .id = DSC_5,
314 		.base = 0x82000, .len = 0x4,
315 		.features = BIT(DPU_DSC_HW_REV_1_2),
316 		.sblk = &dsc_sblk_1,
317 	},
318 };
319 
320 /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
321 static const struct dpu_intf_cfg sc8280xp_intf[] = {
322 	{
323 		.name = "intf_0", .id = INTF_0,
324 		.base = 0x34000, .len = 0x280,
325 		.features = INTF_SC7280_MASK,
326 		.type = INTF_DP,
327 		.controller_id = MSM_DP_CONTROLLER_0,
328 		.prog_fetch_lines_worst_case = 24,
329 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
330 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
331 		.intr_tear_rd_ptr = -1,
332 	}, {
333 		.name = "intf_1", .id = INTF_1,
334 		.base = 0x35000, .len = 0x300,
335 		.features = INTF_SC7280_MASK,
336 		.type = INTF_DSI,
337 		.controller_id = MSM_DSI_CONTROLLER_0,
338 		.prog_fetch_lines_worst_case = 24,
339 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
340 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
341 		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
342 	}, {
343 		.name = "intf_2", .id = INTF_2,
344 		.base = 0x36000, .len = 0x300,
345 		.features = INTF_SC7280_MASK,
346 		.type = INTF_DSI,
347 		.controller_id = MSM_DSI_CONTROLLER_1,
348 		.prog_fetch_lines_worst_case = 24,
349 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
350 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
351 		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
352 	}, {
353 		.name = "intf_3", .id = INTF_3,
354 		.base = 0x37000, .len = 0x280,
355 		.features = INTF_SC7280_MASK,
356 		.type = INTF_NONE,
357 		.controller_id = MSM_DP_CONTROLLER_0,
358 		.prog_fetch_lines_worst_case = 24,
359 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
360 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
361 		.intr_tear_rd_ptr = -1,
362 	}, {
363 		.name = "intf_4", .id = INTF_4,
364 		.base = 0x38000, .len = 0x280,
365 		.features = INTF_SC7280_MASK,
366 		.type = INTF_DP,
367 		.controller_id = MSM_DP_CONTROLLER_1,
368 		.prog_fetch_lines_worst_case = 24,
369 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
370 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
371 		.intr_tear_rd_ptr = -1,
372 	}, {
373 		.name = "intf_5", .id = INTF_5,
374 		.base = 0x39000, .len = 0x280,
375 		.features = INTF_SC7280_MASK,
376 		.type = INTF_DP,
377 		.controller_id = MSM_DP_CONTROLLER_3,
378 		.prog_fetch_lines_worst_case = 24,
379 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
380 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
381 		.intr_tear_rd_ptr = -1,
382 	}, {
383 		.name = "intf_6", .id = INTF_6,
384 		.base = 0x3a000, .len = 0x280,
385 		.features = INTF_SC7280_MASK,
386 		.type = INTF_DP,
387 		.controller_id = MSM_DP_CONTROLLER_2,
388 		.prog_fetch_lines_worst_case = 24,
389 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
390 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
391 		.intr_tear_rd_ptr = -1,
392 	}, {
393 		.name = "intf_7", .id = INTF_7,
394 		.base = 0x3b000, .len = 0x280,
395 		.features = INTF_SC7280_MASK,
396 		.type = INTF_NONE,
397 		.controller_id = MSM_DP_CONTROLLER_2,
398 		.prog_fetch_lines_worst_case = 24,
399 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
400 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
401 		.intr_tear_rd_ptr = -1,
402 	}, {
403 		.name = "intf_8", .id = INTF_8,
404 		.base = 0x3c000, .len = 0x280,
405 		.features = INTF_SC7280_MASK,
406 		.type = INTF_NONE,
407 		.controller_id = MSM_DP_CONTROLLER_1,
408 		.prog_fetch_lines_worst_case = 24,
409 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
410 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
411 		.intr_tear_rd_ptr = -1,
412 	},
413 };
414 
415 static const struct dpu_perf_cfg sc8280xp_perf_data = {
416 	.max_bw_low = 13600000,
417 	.max_bw_high = 18200000,
418 	.min_core_ib = 2500000,
419 	.min_llcc_ib = 0,
420 	.min_dram_ib = 800000,
421 	.danger_lut_tbl = {0xf, 0xffff, 0x0},
422 	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
423 	.qos_lut_tbl = {
424 		{.nentry = ARRAY_SIZE(sc8180x_qos_linear),
425 		.entries = sc8180x_qos_linear
426 		},
427 		{.nentry = ARRAY_SIZE(sc8180x_qos_macrotile),
428 		.entries = sc8180x_qos_macrotile
429 		},
430 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
431 		.entries = sc7180_qos_nrt
432 		},
433 		/* TODO: macrotile-qseed is different from macrotile */
434 	},
435 	.cdp_cfg = {
436 		{.rd_enable = 1, .wr_enable = 1},
437 		{.rd_enable = 1, .wr_enable = 0}
438 	},
439 	.clk_inefficiency_factor = 105,
440 	.bw_inefficiency_factor = 120,
441 };
442 
443 static const struct dpu_mdss_version sc8280xp_mdss_ver = {
444 	.core_major_ver = 8,
445 	.core_minor_ver = 0,
446 };
447 
448 const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
449 	.mdss_ver = &sc8280xp_mdss_ver,
450 	.caps = &sc8280xp_dpu_caps,
451 	.mdp = &sc8280xp_mdp,
452 	.ctl_count = ARRAY_SIZE(sc8280xp_ctl),
453 	.ctl = sc8280xp_ctl,
454 	.sspp_count = ARRAY_SIZE(sc8280xp_sspp),
455 	.sspp = sc8280xp_sspp,
456 	.mixer_count = ARRAY_SIZE(sc8280xp_lm),
457 	.mixer = sc8280xp_lm,
458 	.dspp_count = ARRAY_SIZE(sc8280xp_dspp),
459 	.dspp = sc8280xp_dspp,
460 	.pingpong_count = ARRAY_SIZE(sc8280xp_pp),
461 	.pingpong = sc8280xp_pp,
462 	.dsc_count = ARRAY_SIZE(sc8280xp_dsc),
463 	.dsc = sc8280xp_dsc,
464 	.merge_3d_count = ARRAY_SIZE(sc8280xp_merge_3d),
465 	.merge_3d = sc8280xp_merge_3d,
466 	.intf_count = ARRAY_SIZE(sc8280xp_intf),
467 	.intf = sc8280xp_intf,
468 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
469 	.vbif = sdm845_vbif,
470 	.perf = &sc8280xp_perf_data,
471 };
472 
473 #endif
474