1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * boot-common.c
4 *
5 * Common bootmode functions for omap based boards
6 *
7 * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8 */
9
10 #include <common.h>
11 #include <ahci.h>
12 #include <environment.h>
13 #include <spl.h>
14 #include <asm/omap_common.h>
15 #include <asm/arch/omap.h>
16 #include <asm/arch/mmc_host_def.h>
17 #include <asm/arch/sys_proto.h>
18 #include <watchdog.h>
19 #include <scsi.h>
20 #include <i2c.h>
21
22 DECLARE_GLOBAL_DATA_PTR;
23
omap_sys_boot_device(void)24 __weak u32 omap_sys_boot_device(void)
25 {
26 return BOOT_DEVICE_NONE;
27 }
28
save_omap_boot_params(void)29 void save_omap_boot_params(void)
30 {
31 u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
32 struct omap_boot_parameters *omap_boot_params;
33 int sys_boot_device = 0;
34 u32 boot_device;
35 u32 boot_mode;
36
37 if ((boot_params < NON_SECURE_SRAM_START) ||
38 (boot_params > NON_SECURE_SRAM_END))
39 return;
40
41 omap_boot_params = (struct omap_boot_parameters *)boot_params;
42
43 boot_device = omap_boot_params->boot_device;
44 boot_mode = MMCSD_MODE_UNDEFINED;
45
46 /* Boot device */
47
48 #ifdef BOOT_DEVICE_NAND_I2C
49 /*
50 * Re-map NAND&I2C boot-device to the "normal" NAND boot-device.
51 * Otherwise the SPL boot IF can't handle this device correctly.
52 * Somehow booting with Hynix 4GBit NAND H27U4G8 on Siemens
53 * Draco leads to this boot-device passed to SPL from the BootROM.
54 */
55 if (boot_device == BOOT_DEVICE_NAND_I2C)
56 boot_device = BOOT_DEVICE_NAND;
57 #endif
58 #ifdef BOOT_DEVICE_QSPI_4
59 /*
60 * We get different values for QSPI_1 and QSPI_4 being used, but
61 * don't actually care about this difference. Rather than
62 * mangle the later code, if we're coming in as QSPI_4 just
63 * change to the QSPI_1 value.
64 */
65 if (boot_device == BOOT_DEVICE_QSPI_4)
66 boot_device = BOOT_DEVICE_SPI;
67 #endif
68 #ifdef CONFIG_TI816X
69 /*
70 * On PG2.0 and later TI816x the values we get when booting are not the
71 * same as on PG1.0, which is what the defines are based on. Update
72 * them as needed.
73 */
74 if (get_cpu_rev() != 1) {
75 if (boot_device == 0x05) {
76 omap_boot_params->boot_device = BOOT_DEVICE_NAND;
77 boot_device = BOOT_DEVICE_NAND;
78 }
79 if (boot_device == 0x08) {
80 omap_boot_params->boot_device = BOOT_DEVICE_MMC1;
81 boot_device = BOOT_DEVICE_MMC1;
82 }
83 }
84 #endif
85 /*
86 * When booting from peripheral booting, the boot device is not usable
87 * as-is (unless there is support for it), so the boot device is instead
88 * figured out using the SYS_BOOT pins.
89 */
90 switch (boot_device) {
91 #if defined(BOOT_DEVICE_UART) && !defined(CONFIG_SPL_YMODEM_SUPPORT)
92 case BOOT_DEVICE_UART:
93 sys_boot_device = 1;
94 break;
95 #endif
96 #if defined(BOOT_DEVICE_USB) && !defined(CONFIG_SPL_USB_STORAGE)
97 case BOOT_DEVICE_USB:
98 sys_boot_device = 1;
99 break;
100 #endif
101 #if defined(BOOT_DEVICE_USBETH) && !defined(CONFIG_SPL_USB_ETHER)
102 case BOOT_DEVICE_USBETH:
103 sys_boot_device = 1;
104 break;
105 #endif
106 #if defined(BOOT_DEVICE_CPGMAC) && !defined(CONFIG_SPL_ETH_SUPPORT)
107 case BOOT_DEVICE_CPGMAC:
108 sys_boot_device = 1;
109 break;
110 #endif
111 #if defined(BOOT_DEVICE_DFU) && !defined(CONFIG_SPL_DFU)
112 case BOOT_DEVICE_DFU:
113 sys_boot_device = 1;
114 break;
115 #endif
116 }
117
118 if (sys_boot_device) {
119 boot_device = omap_sys_boot_device();
120
121 /* MMC raw mode will fallback to FS mode. */
122 if ((boot_device >= MMC_BOOT_DEVICES_START) &&
123 (boot_device <= MMC_BOOT_DEVICES_END))
124 boot_mode = MMCSD_MODE_RAW;
125 }
126
127 gd->arch.omap_boot_device = boot_device;
128
129 /* Boot mode */
130
131 #ifdef CONFIG_OMAP34XX
132 if ((boot_device >= MMC_BOOT_DEVICES_START) &&
133 (boot_device <= MMC_BOOT_DEVICES_END)) {
134 switch (boot_device) {
135 case BOOT_DEVICE_MMC1:
136 boot_mode = MMCSD_MODE_FS;
137 break;
138 case BOOT_DEVICE_MMC2:
139 boot_mode = MMCSD_MODE_RAW;
140 break;
141 }
142 }
143 #else
144 /*
145 * If the boot device was dynamically changed and doesn't match what
146 * the bootrom initially booted, we cannot use the boot device
147 * descriptor to figure out the boot mode.
148 */
149 if ((boot_device == omap_boot_params->boot_device) &&
150 (boot_device >= MMC_BOOT_DEVICES_START) &&
151 (boot_device <= MMC_BOOT_DEVICES_END)) {
152 boot_params = omap_boot_params->boot_device_descriptor;
153 if ((boot_params < NON_SECURE_SRAM_START) ||
154 (boot_params > NON_SECURE_SRAM_END))
155 return;
156
157 boot_params = *((u32 *)(boot_params + DEVICE_DATA_OFFSET));
158 if ((boot_params < NON_SECURE_SRAM_START) ||
159 (boot_params > NON_SECURE_SRAM_END))
160 return;
161
162 boot_mode = *((u32 *)(boot_params + BOOT_MODE_OFFSET));
163
164 if (boot_mode != MMCSD_MODE_FS &&
165 boot_mode != MMCSD_MODE_RAW)
166 #ifdef CONFIG_SUPPORT_EMMC_BOOT
167 boot_mode = MMCSD_MODE_EMMCBOOT;
168 #else
169 boot_mode = MMCSD_MODE_UNDEFINED;
170 #endif
171 }
172 #endif
173
174 gd->arch.omap_boot_mode = boot_mode;
175
176 #if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \
177 !defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
178
179 /* CH flags */
180
181 gd->arch.omap_ch_flags = omap_boot_params->ch_flags;
182 #endif
183 }
184
185 #ifdef CONFIG_SPL_BUILD
spl_boot_device(void)186 u32 spl_boot_device(void)
187 {
188 return gd->arch.omap_boot_device;
189 }
190
spl_boot_mode(const u32 boot_device)191 u32 spl_boot_mode(const u32 boot_device)
192 {
193 return gd->arch.omap_boot_mode;
194 }
195
spl_board_init(void)196 void spl_board_init(void)
197 {
198 #ifdef CONFIG_SPL_SERIAL_SUPPORT
199 /* Prepare console output */
200 preloader_console_init();
201 #endif
202 #if defined(CONFIG_SPL_NAND_SUPPORT) || defined(CONFIG_SPL_ONENAND_SUPPORT)
203 gpmc_init();
204 #endif
205 #if defined(CONFIG_SPL_I2C_SUPPORT) && !defined(CONFIG_DM_I2C)
206 i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
207 #endif
208 #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT)
209 arch_misc_init();
210 #endif
211 #if defined(CONFIG_HW_WATCHDOG)
212 hw_watchdog_init();
213 #endif
214 #ifdef CONFIG_AM33XX
215 am33xx_spl_board_init();
216 #endif
217 }
218
jump_to_image_no_args(struct spl_image_info * spl_image)219 void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
220 {
221 typedef void __noreturn (*image_entry_noargs_t)(u32 *);
222 image_entry_noargs_t image_entry =
223 (image_entry_noargs_t) spl_image->entry_point;
224
225 u32 boot_params = *((u32 *)OMAP_SRAM_SCRATCH_BOOT_PARAMS);
226
227 debug("image entry point: 0x%lX\n", spl_image->entry_point);
228 /* Pass the saved boot_params from rom code */
229 image_entry((u32 *)boot_params);
230 }
231 #endif
232
233 #ifdef CONFIG_SCSI_AHCI_PLAT
arch_preboot_os(void)234 void arch_preboot_os(void)
235 {
236 ahci_reset((void __iomem *)DWC_AHSATA_BASE);
237 }
238 #endif
239