1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved.
4  * Copyright (c) 2023, Linaro Limited
5  */
6 
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/mod_devicetable.h>
11 #include <linux/module.h>
12 #include <linux/platform_device.h>
13 #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h>
14 
15 #include "bcm-voter.h"
16 #include "icc-rpmh.h"
17 
18 #define SA8775P_MASTER_GPU_TCU				0
19 #define SA8775P_MASTER_PCIE_TCU				1
20 #define SA8775P_MASTER_SYS_TCU				2
21 #define SA8775P_MASTER_APPSS_PROC			3
22 #define SA8775P_MASTER_LLCC				4
23 #define SA8775P_MASTER_CNOC_LPASS_AG_NOC		5
24 #define SA8775P_MASTER_GIC_AHB				6
25 #define SA8775P_MASTER_CDSP_NOC_CFG			7
26 #define SA8775P_MASTER_CDSPB_NOC_CFG			8
27 #define SA8775P_MASTER_QDSS_BAM				9
28 #define SA8775P_MASTER_QUP_0				10
29 #define SA8775P_MASTER_QUP_1				11
30 #define SA8775P_MASTER_QUP_2				12
31 #define SA8775P_MASTER_A1NOC_SNOC			13
32 #define SA8775P_MASTER_A2NOC_SNOC			14
33 #define SA8775P_MASTER_CAMNOC_HF			15
34 #define SA8775P_MASTER_CAMNOC_ICP			16
35 #define SA8775P_MASTER_CAMNOC_SF			17
36 #define SA8775P_MASTER_COMPUTE_NOC			18
37 #define SA8775P_MASTER_COMPUTE_NOC_1			19
38 #define SA8775P_MASTER_CNOC_A2NOC			20
39 #define SA8775P_MASTER_CNOC_DC_NOC			21
40 #define SA8775P_MASTER_GEM_NOC_CFG			22
41 #define SA8775P_MASTER_GEM_NOC_CNOC			23
42 #define SA8775P_MASTER_GEM_NOC_PCIE_SNOC		24
43 #define SA8775P_MASTER_GPDSP_SAIL			25
44 #define SA8775P_MASTER_GFX3D				26
45 #define SA8775P_MASTER_LPASS_ANOC			27
46 #define SA8775P_MASTER_MDP0				28
47 #define SA8775P_MASTER_MDP1				29
48 #define SA8775P_MASTER_MDP_CORE1_0			30
49 #define SA8775P_MASTER_MDP_CORE1_1			31
50 #define SA8775P_MASTER_MNOC_HF_MEM_NOC			32
51 #define SA8775P_MASTER_CNOC_MNOC_HF_CFG			33
52 #define SA8775P_MASTER_MNOC_SF_MEM_NOC			34
53 #define SA8775P_MASTER_CNOC_MNOC_SF_CFG			35
54 #define SA8775P_MASTER_ANOC_PCIE_GEM_NOC		36
55 #define SA8775P_MASTER_SNOC_CFG				37
56 #define SA8775P_MASTER_SNOC_GC_MEM_NOC			38
57 #define SA8775P_MASTER_SNOC_SF_MEM_NOC			39
58 #define SA8775P_MASTER_VIDEO_P0				40
59 #define SA8775P_MASTER_VIDEO_P1				41
60 #define SA8775P_MASTER_VIDEO_PROC			42
61 #define SA8775P_MASTER_VIDEO_V_PROC			43
62 #define SA8775P_MASTER_QUP_CORE_0			44
63 #define SA8775P_MASTER_QUP_CORE_1			45
64 #define SA8775P_MASTER_QUP_CORE_2			46
65 #define SA8775P_MASTER_QUP_CORE_3			47
66 #define SA8775P_MASTER_CRYPTO_CORE0			48
67 #define SA8775P_MASTER_CRYPTO_CORE1			49
68 #define SA8775P_MASTER_DSP0				50
69 #define SA8775P_MASTER_DSP1				51
70 #define SA8775P_MASTER_IPA				52
71 #define SA8775P_MASTER_LPASS_PROC			53
72 #define SA8775P_MASTER_CDSP_PROC			54
73 #define SA8775P_MASTER_CDSP_PROC_B			55
74 #define SA8775P_MASTER_PIMEM				56
75 #define SA8775P_MASTER_QUP_3				57
76 #define SA8775P_MASTER_EMAC				58
77 #define SA8775P_MASTER_EMAC_1				59
78 #define SA8775P_MASTER_GIC				60
79 #define SA8775P_MASTER_PCIE_0				61
80 #define SA8775P_MASTER_PCIE_1				62
81 #define SA8775P_MASTER_QDSS_ETR_0			63
82 #define SA8775P_MASTER_QDSS_ETR_1			64
83 #define SA8775P_MASTER_SDC				65
84 #define SA8775P_MASTER_UFS_CARD				66
85 #define SA8775P_MASTER_UFS_MEM				67
86 #define SA8775P_MASTER_USB2				68
87 #define SA8775P_MASTER_USB3_0				69
88 #define SA8775P_MASTER_USB3_1				70
89 #define SA8775P_SLAVE_EBI1				512
90 #define SA8775P_SLAVE_AHB2PHY_0				513
91 #define SA8775P_SLAVE_AHB2PHY_1				514
92 #define SA8775P_SLAVE_AHB2PHY_2				515
93 #define SA8775P_SLAVE_AHB2PHY_3				516
94 #define SA8775P_SLAVE_ANOC_THROTTLE_CFG			517
95 #define SA8775P_SLAVE_AOSS				518
96 #define SA8775P_SLAVE_APPSS				519
97 #define SA8775P_SLAVE_BOOT_ROM				520
98 #define SA8775P_SLAVE_CAMERA_CFG			521
99 #define SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG		522
100 #define SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG		523
101 #define SA8775P_SLAVE_CLK_CTL				524
102 #define SA8775P_SLAVE_CDSP_CFG				525
103 #define SA8775P_SLAVE_CDSP1_CFG				526
104 #define SA8775P_SLAVE_RBCPR_CX_CFG			527
105 #define SA8775P_SLAVE_RBCPR_MMCX_CFG			528
106 #define SA8775P_SLAVE_RBCPR_MX_CFG			529
107 #define SA8775P_SLAVE_CPR_NSPCX				530
108 #define SA8775P_SLAVE_CRYPTO_0_CFG			531
109 #define SA8775P_SLAVE_CX_RDPM				532
110 #define SA8775P_SLAVE_DISPLAY_CFG			533
111 #define SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG		534
112 #define SA8775P_SLAVE_DISPLAY1_CFG			535
113 #define SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG		536
114 #define SA8775P_SLAVE_EMAC_CFG				537
115 #define SA8775P_SLAVE_EMAC1_CFG				538
116 #define SA8775P_SLAVE_GP_DSP0_CFG			539
117 #define SA8775P_SLAVE_GP_DSP1_CFG			540
118 #define SA8775P_SLAVE_GPDSP0_THROTTLE_CFG		541
119 #define SA8775P_SLAVE_GPDSP1_THROTTLE_CFG		542
120 #define SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG		543
121 #define SA8775P_SLAVE_GFX3D_CFG				544
122 #define SA8775P_SLAVE_HWKM				545
123 #define SA8775P_SLAVE_IMEM_CFG				546
124 #define SA8775P_SLAVE_IPA_CFG				547
125 #define SA8775P_SLAVE_IPC_ROUTER_CFG			548
126 #define SA8775P_SLAVE_LLCC_CFG				549
127 #define SA8775P_SLAVE_LPASS				550
128 #define SA8775P_SLAVE_LPASS_CORE_CFG			551
129 #define SA8775P_SLAVE_LPASS_LPI_CFG			552
130 #define SA8775P_SLAVE_LPASS_MPU_CFG			553
131 #define SA8775P_SLAVE_LPASS_THROTTLE_CFG		554
132 #define SA8775P_SLAVE_LPASS_TOP_CFG			555
133 #define SA8775P_SLAVE_MX_RDPM				556
134 #define SA8775P_SLAVE_MXC_RDPM				557
135 #define SA8775P_SLAVE_PCIE_0_CFG			558
136 #define SA8775P_SLAVE_PCIE_1_CFG			559
137 #define SA8775P_SLAVE_PCIE_RSC_CFG			560
138 #define SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG		561
139 #define SA8775P_SLAVE_PCIE_THROTTLE_CFG			562
140 #define SA8775P_SLAVE_PDM				563
141 #define SA8775P_SLAVE_PIMEM_CFG				564
142 #define SA8775P_SLAVE_PKA_WRAPPER_CFG			565
143 #define SA8775P_SLAVE_QDSS_CFG				566
144 #define SA8775P_SLAVE_QM_CFG				567
145 #define SA8775P_SLAVE_QM_MPU_CFG			568
146 #define SA8775P_SLAVE_QUP_0				569
147 #define SA8775P_SLAVE_QUP_1				570
148 #define SA8775P_SLAVE_QUP_2				571
149 #define SA8775P_SLAVE_QUP_3				572
150 #define SA8775P_SLAVE_SAIL_THROTTLE_CFG			573
151 #define SA8775P_SLAVE_SDC1				574
152 #define SA8775P_SLAVE_SECURITY				575
153 #define SA8775P_SLAVE_SNOC_THROTTLE_CFG			576
154 #define SA8775P_SLAVE_TCSR				577
155 #define SA8775P_SLAVE_TLMM				578
156 #define SA8775P_SLAVE_TSC_CFG				579
157 #define SA8775P_SLAVE_UFS_CARD_CFG			580
158 #define SA8775P_SLAVE_UFS_MEM_CFG			581
159 #define SA8775P_SLAVE_USB2				582
160 #define SA8775P_SLAVE_USB3_0				583
161 #define SA8775P_SLAVE_USB3_1				584
162 #define SA8775P_SLAVE_VENUS_CFG				585
163 #define SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG		586
164 #define SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG		587
165 #define SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG		588
166 #define SA8775P_SLAVE_A1NOC_SNOC			589
167 #define SA8775P_SLAVE_A2NOC_SNOC			590
168 #define SA8775P_SLAVE_DDRSS_CFG				591
169 #define SA8775P_SLAVE_GEM_NOC_CNOC			592
170 #define SA8775P_SLAVE_GEM_NOC_CFG			593
171 #define SA8775P_SLAVE_SNOC_GEM_NOC_GC			594
172 #define SA8775P_SLAVE_SNOC_GEM_NOC_SF			595
173 #define SA8775P_SLAVE_GP_DSP_SAIL_NOC			596
174 #define SA8775P_SLAVE_GPDSP_NOC_CFG			597
175 #define SA8775P_SLAVE_HCP_A				598
176 #define SA8775P_SLAVE_LLCC				599
177 #define SA8775P_SLAVE_MNOC_HF_MEM_NOC			600
178 #define SA8775P_SLAVE_MNOC_SF_MEM_NOC			601
179 #define SA8775P_SLAVE_CNOC_MNOC_HF_CFG			602
180 #define SA8775P_SLAVE_CNOC_MNOC_SF_CFG			603
181 #define SA8775P_SLAVE_CDSP_MEM_NOC			604
182 #define SA8775P_SLAVE_CDSPB_MEM_NOC			605
183 #define SA8775P_SLAVE_HCP_B				606
184 #define SA8775P_SLAVE_GEM_NOC_PCIE_CNOC			607
185 #define SA8775P_SLAVE_PCIE_ANOC_CFG			608
186 #define SA8775P_SLAVE_ANOC_PCIE_GEM_NOC			609
187 #define SA8775P_SLAVE_SNOC_CFG				610
188 #define SA8775P_SLAVE_LPASS_SNOC			611
189 #define SA8775P_SLAVE_QUP_CORE_0			612
190 #define SA8775P_SLAVE_QUP_CORE_1			613
191 #define SA8775P_SLAVE_QUP_CORE_2			614
192 #define SA8775P_SLAVE_QUP_CORE_3			615
193 #define SA8775P_SLAVE_BOOT_IMEM				616
194 #define SA8775P_SLAVE_IMEM				617
195 #define SA8775P_SLAVE_PIMEM				618
196 #define SA8775P_SLAVE_SERVICE_NSP_NOC			619
197 #define SA8775P_SLAVE_SERVICE_NSPB_NOC			620
198 #define SA8775P_SLAVE_SERVICE_GEM_NOC_1			621
199 #define SA8775P_SLAVE_SERVICE_MNOC_HF			622
200 #define SA8775P_SLAVE_SERVICE_MNOC_SF			623
201 #define SA8775P_SLAVE_SERVICES_LPASS_AML_NOC		624
202 #define SA8775P_SLAVE_SERVICE_LPASS_AG_NOC		625
203 #define SA8775P_SLAVE_SERVICE_GEM_NOC_2			626
204 #define SA8775P_SLAVE_SERVICE_SNOC			627
205 #define SA8775P_SLAVE_SERVICE_GEM_NOC			628
206 #define SA8775P_SLAVE_SERVICE_GEM_NOC2			629
207 #define SA8775P_SLAVE_PCIE_0				630
208 #define SA8775P_SLAVE_PCIE_1				631
209 #define SA8775P_SLAVE_QDSS_STM				632
210 #define SA8775P_SLAVE_TCU				633
211 
212 static struct qcom_icc_node qxm_qup3 = {
213 	.name = "qxm_qup3",
214 	.id = SA8775P_MASTER_QUP_3,
215 	.channels = 1,
216 	.buswidth = 8,
217 	.num_links = 1,
218 	.links = { SA8775P_SLAVE_A1NOC_SNOC },
219 };
220 
221 static struct qcom_icc_node xm_emac_0 = {
222 	.name = "xm_emac_0",
223 	.id = SA8775P_MASTER_EMAC,
224 	.channels = 1,
225 	.buswidth = 8,
226 	.num_links = 1,
227 	.links = { SA8775P_SLAVE_A1NOC_SNOC },
228 };
229 
230 static struct qcom_icc_node xm_emac_1 = {
231 	.name = "xm_emac_1",
232 	.id = SA8775P_MASTER_EMAC_1,
233 	.channels = 1,
234 	.buswidth = 8,
235 	.num_links = 1,
236 	.links = { SA8775P_SLAVE_A1NOC_SNOC },
237 };
238 
239 static struct qcom_icc_node xm_sdc1 = {
240 	.name = "xm_sdc1",
241 	.id = SA8775P_MASTER_SDC,
242 	.channels = 1,
243 	.buswidth = 8,
244 	.num_links = 1,
245 	.links = { SA8775P_SLAVE_A1NOC_SNOC },
246 };
247 
248 static struct qcom_icc_node xm_ufs_mem = {
249 	.name = "xm_ufs_mem",
250 	.id = SA8775P_MASTER_UFS_MEM,
251 	.channels = 1,
252 	.buswidth = 8,
253 	.num_links = 1,
254 	.links = { SA8775P_SLAVE_A1NOC_SNOC },
255 };
256 
257 static struct qcom_icc_node xm_usb2_2 = {
258 	.name = "xm_usb2_2",
259 	.id = SA8775P_MASTER_USB2,
260 	.channels = 1,
261 	.buswidth = 8,
262 	.num_links = 1,
263 	.links = { SA8775P_SLAVE_A1NOC_SNOC },
264 };
265 
266 static struct qcom_icc_node xm_usb3_0 = {
267 	.name = "xm_usb3_0",
268 	.id = SA8775P_MASTER_USB3_0,
269 	.channels = 1,
270 	.buswidth = 8,
271 	.num_links = 1,
272 	.links = { SA8775P_SLAVE_A1NOC_SNOC },
273 };
274 
275 static struct qcom_icc_node xm_usb3_1 = {
276 	.name = "xm_usb3_1",
277 	.id = SA8775P_MASTER_USB3_1,
278 	.channels = 1,
279 	.buswidth = 8,
280 	.num_links = 1,
281 	.links = { SA8775P_SLAVE_A1NOC_SNOC },
282 };
283 
284 static struct qcom_icc_node qhm_qdss_bam = {
285 	.name = "qhm_qdss_bam",
286 	.id = SA8775P_MASTER_QDSS_BAM,
287 	.channels = 1,
288 	.buswidth = 4,
289 	.num_links = 1,
290 	.links = { SA8775P_SLAVE_A2NOC_SNOC },
291 };
292 
293 static struct qcom_icc_node qhm_qup0 = {
294 	.name = "qhm_qup0",
295 	.id = SA8775P_MASTER_QUP_0,
296 	.channels = 1,
297 	.buswidth = 4,
298 	.num_links = 1,
299 	.links = { SA8775P_SLAVE_A2NOC_SNOC },
300 };
301 
302 static struct qcom_icc_node qhm_qup1 = {
303 	.name = "qhm_qup1",
304 	.id = SA8775P_MASTER_QUP_1,
305 	.channels = 1,
306 	.buswidth = 4,
307 	.num_links = 1,
308 	.links = { SA8775P_SLAVE_A2NOC_SNOC },
309 };
310 
311 static struct qcom_icc_node qhm_qup2 = {
312 	.name = "qhm_qup2",
313 	.id = SA8775P_MASTER_QUP_2,
314 	.channels = 1,
315 	.buswidth = 4,
316 	.num_links = 1,
317 	.links = { SA8775P_SLAVE_A2NOC_SNOC },
318 };
319 
320 static struct qcom_icc_node qnm_cnoc_datapath = {
321 	.name = "qnm_cnoc_datapath",
322 	.id = SA8775P_MASTER_CNOC_A2NOC,
323 	.channels = 1,
324 	.buswidth = 8,
325 	.num_links = 1,
326 	.links = { SA8775P_SLAVE_A2NOC_SNOC },
327 };
328 
329 static struct qcom_icc_node qxm_crypto_0 = {
330 	.name = "qxm_crypto_0",
331 	.id = SA8775P_MASTER_CRYPTO_CORE0,
332 	.channels = 1,
333 	.buswidth = 8,
334 	.num_links = 1,
335 	.links = { SA8775P_SLAVE_A2NOC_SNOC },
336 };
337 
338 static struct qcom_icc_node qxm_crypto_1 = {
339 	.name = "qxm_crypto_1",
340 	.id = SA8775P_MASTER_CRYPTO_CORE1,
341 	.channels = 1,
342 	.buswidth = 8,
343 	.num_links = 1,
344 	.links = { SA8775P_SLAVE_A2NOC_SNOC },
345 };
346 
347 static struct qcom_icc_node qxm_ipa = {
348 	.name = "qxm_ipa",
349 	.id = SA8775P_MASTER_IPA,
350 	.channels = 1,
351 	.buswidth = 8,
352 	.num_links = 1,
353 	.links = { SA8775P_SLAVE_A2NOC_SNOC },
354 };
355 
356 static struct qcom_icc_node xm_qdss_etr_0 = {
357 	.name = "xm_qdss_etr_0",
358 	.id = SA8775P_MASTER_QDSS_ETR_0,
359 	.channels = 1,
360 	.buswidth = 8,
361 	.num_links = 1,
362 	.links = { SA8775P_SLAVE_A2NOC_SNOC },
363 };
364 
365 static struct qcom_icc_node xm_qdss_etr_1 = {
366 	.name = "xm_qdss_etr_1",
367 	.id = SA8775P_MASTER_QDSS_ETR_1,
368 	.channels = 1,
369 	.buswidth = 8,
370 	.num_links = 1,
371 	.links = { SA8775P_SLAVE_A2NOC_SNOC },
372 };
373 
374 static struct qcom_icc_node xm_ufs_card = {
375 	.name = "xm_ufs_card",
376 	.id = SA8775P_MASTER_UFS_CARD,
377 	.channels = 1,
378 	.buswidth = 8,
379 	.num_links = 1,
380 	.links = { SA8775P_SLAVE_A2NOC_SNOC },
381 };
382 
383 static struct qcom_icc_node qup0_core_master = {
384 	.name = "qup0_core_master",
385 	.id = SA8775P_MASTER_QUP_CORE_0,
386 	.channels = 1,
387 	.buswidth = 4,
388 	.num_links = 1,
389 	.links = { SA8775P_SLAVE_QUP_CORE_0 },
390 };
391 
392 static struct qcom_icc_node qup1_core_master = {
393 	.name = "qup1_core_master",
394 	.id = SA8775P_MASTER_QUP_CORE_1,
395 	.channels = 1,
396 	.buswidth = 4,
397 	.num_links = 1,
398 	.links = { SA8775P_SLAVE_QUP_CORE_1 },
399 };
400 
401 static struct qcom_icc_node qup2_core_master = {
402 	.name = "qup2_core_master",
403 	.id = SA8775P_MASTER_QUP_CORE_2,
404 	.channels = 1,
405 	.buswidth = 4,
406 	.num_links = 1,
407 	.links = { SA8775P_SLAVE_QUP_CORE_2 },
408 };
409 
410 static struct qcom_icc_node qup3_core_master = {
411 	.name = "qup3_core_master",
412 	.id = SA8775P_MASTER_QUP_CORE_3,
413 	.channels = 1,
414 	.buswidth = 4,
415 	.num_links = 1,
416 	.links = { SA8775P_SLAVE_QUP_CORE_3 },
417 };
418 
419 static struct qcom_icc_node qnm_gemnoc_cnoc = {
420 	.name = "qnm_gemnoc_cnoc",
421 	.id = SA8775P_MASTER_GEM_NOC_CNOC,
422 	.channels = 1,
423 	.buswidth = 16,
424 	.num_links = 82,
425 	.links = { SA8775P_SLAVE_AHB2PHY_0,
426 		   SA8775P_SLAVE_AHB2PHY_1,
427 		   SA8775P_SLAVE_AHB2PHY_2,
428 		   SA8775P_SLAVE_AHB2PHY_3,
429 		   SA8775P_SLAVE_ANOC_THROTTLE_CFG,
430 		   SA8775P_SLAVE_AOSS,
431 		   SA8775P_SLAVE_APPSS,
432 		   SA8775P_SLAVE_BOOT_ROM,
433 		   SA8775P_SLAVE_CAMERA_CFG,
434 		   SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG,
435 		   SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG,
436 		   SA8775P_SLAVE_CLK_CTL,
437 		   SA8775P_SLAVE_CDSP_CFG,
438 		   SA8775P_SLAVE_CDSP1_CFG,
439 		   SA8775P_SLAVE_RBCPR_CX_CFG,
440 		   SA8775P_SLAVE_RBCPR_MMCX_CFG,
441 		   SA8775P_SLAVE_RBCPR_MX_CFG,
442 		   SA8775P_SLAVE_CPR_NSPCX,
443 		   SA8775P_SLAVE_CRYPTO_0_CFG,
444 		   SA8775P_SLAVE_CX_RDPM,
445 		   SA8775P_SLAVE_DISPLAY_CFG,
446 		   SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG,
447 		   SA8775P_SLAVE_DISPLAY1_CFG,
448 		   SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG,
449 		   SA8775P_SLAVE_EMAC_CFG,
450 		   SA8775P_SLAVE_EMAC1_CFG,
451 		   SA8775P_SLAVE_GP_DSP0_CFG,
452 		   SA8775P_SLAVE_GP_DSP1_CFG,
453 		   SA8775P_SLAVE_GPDSP0_THROTTLE_CFG,
454 		   SA8775P_SLAVE_GPDSP1_THROTTLE_CFG,
455 		   SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG,
456 		   SA8775P_SLAVE_GFX3D_CFG,
457 		   SA8775P_SLAVE_HWKM,
458 		   SA8775P_SLAVE_IMEM_CFG,
459 		   SA8775P_SLAVE_IPA_CFG,
460 		   SA8775P_SLAVE_IPC_ROUTER_CFG,
461 		   SA8775P_SLAVE_LPASS,
462 		   SA8775P_SLAVE_LPASS_THROTTLE_CFG,
463 		   SA8775P_SLAVE_MX_RDPM,
464 		   SA8775P_SLAVE_MXC_RDPM,
465 		   SA8775P_SLAVE_PCIE_0_CFG,
466 		   SA8775P_SLAVE_PCIE_1_CFG,
467 		   SA8775P_SLAVE_PCIE_RSC_CFG,
468 		   SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG,
469 		   SA8775P_SLAVE_PCIE_THROTTLE_CFG,
470 		   SA8775P_SLAVE_PDM,
471 		   SA8775P_SLAVE_PIMEM_CFG,
472 		   SA8775P_SLAVE_PKA_WRAPPER_CFG,
473 		   SA8775P_SLAVE_QDSS_CFG,
474 		   SA8775P_SLAVE_QM_CFG,
475 		   SA8775P_SLAVE_QM_MPU_CFG,
476 		   SA8775P_SLAVE_QUP_0,
477 		   SA8775P_SLAVE_QUP_1,
478 		   SA8775P_SLAVE_QUP_2,
479 		   SA8775P_SLAVE_QUP_3,
480 		   SA8775P_SLAVE_SAIL_THROTTLE_CFG,
481 		   SA8775P_SLAVE_SDC1,
482 		   SA8775P_SLAVE_SECURITY,
483 		   SA8775P_SLAVE_SNOC_THROTTLE_CFG,
484 		   SA8775P_SLAVE_TCSR,
485 		   SA8775P_SLAVE_TLMM,
486 		   SA8775P_SLAVE_TSC_CFG,
487 		   SA8775P_SLAVE_UFS_CARD_CFG,
488 		   SA8775P_SLAVE_UFS_MEM_CFG,
489 		   SA8775P_SLAVE_USB2,
490 		   SA8775P_SLAVE_USB3_0,
491 		   SA8775P_SLAVE_USB3_1,
492 		   SA8775P_SLAVE_VENUS_CFG,
493 		   SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG,
494 		   SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
495 		   SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
496 		   SA8775P_SLAVE_DDRSS_CFG,
497 		   SA8775P_SLAVE_GPDSP_NOC_CFG,
498 		   SA8775P_SLAVE_CNOC_MNOC_HF_CFG,
499 		   SA8775P_SLAVE_CNOC_MNOC_SF_CFG,
500 		   SA8775P_SLAVE_PCIE_ANOC_CFG,
501 		   SA8775P_SLAVE_SNOC_CFG,
502 		   SA8775P_SLAVE_BOOT_IMEM,
503 		   SA8775P_SLAVE_IMEM,
504 		   SA8775P_SLAVE_PIMEM,
505 		   SA8775P_SLAVE_QDSS_STM,
506 		   SA8775P_SLAVE_TCU
507 	},
508 };
509 
510 static struct qcom_icc_node qnm_gemnoc_pcie = {
511 	.name = "qnm_gemnoc_pcie",
512 	.id = SA8775P_MASTER_GEM_NOC_PCIE_SNOC,
513 	.channels = 1,
514 	.buswidth = 16,
515 	.num_links = 2,
516 	.links = { SA8775P_SLAVE_PCIE_0,
517 		   SA8775P_SLAVE_PCIE_1
518 	},
519 };
520 
521 static struct qcom_icc_node qnm_cnoc_dc_noc = {
522 	.name = "qnm_cnoc_dc_noc",
523 	.id = SA8775P_MASTER_CNOC_DC_NOC,
524 	.channels = 1,
525 	.buswidth = 4,
526 	.num_links = 2,
527 	.links = { SA8775P_SLAVE_LLCC_CFG,
528 		   SA8775P_SLAVE_GEM_NOC_CFG
529 	},
530 };
531 
532 static struct qcom_icc_node alm_gpu_tcu = {
533 	.name = "alm_gpu_tcu",
534 	.id = SA8775P_MASTER_GPU_TCU,
535 	.channels = 1,
536 	.buswidth = 8,
537 	.num_links = 2,
538 	.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
539 		   SA8775P_SLAVE_LLCC
540 	},
541 };
542 
543 static struct qcom_icc_node alm_pcie_tcu = {
544 	.name = "alm_pcie_tcu",
545 	.id = SA8775P_MASTER_PCIE_TCU,
546 	.channels = 1,
547 	.buswidth = 8,
548 	.num_links = 2,
549 	.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
550 		   SA8775P_SLAVE_LLCC
551 	},
552 };
553 
554 static struct qcom_icc_node alm_sys_tcu = {
555 	.name = "alm_sys_tcu",
556 	.id = SA8775P_MASTER_SYS_TCU,
557 	.channels = 1,
558 	.buswidth = 8,
559 	.num_links = 2,
560 	.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
561 		   SA8775P_SLAVE_LLCC
562 	},
563 };
564 
565 static struct qcom_icc_node chm_apps = {
566 	.name = "chm_apps",
567 	.id = SA8775P_MASTER_APPSS_PROC,
568 	.channels = 4,
569 	.buswidth = 32,
570 	.num_links = 3,
571 	.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
572 		   SA8775P_SLAVE_LLCC,
573 		   SA8775P_SLAVE_GEM_NOC_PCIE_CNOC
574 	},
575 };
576 
577 static struct qcom_icc_node qnm_cmpnoc0 = {
578 	.name = "qnm_cmpnoc0",
579 	.id = SA8775P_MASTER_COMPUTE_NOC,
580 	.channels = 2,
581 	.buswidth = 32,
582 	.num_links = 2,
583 	.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
584 		   SA8775P_SLAVE_LLCC
585 	},
586 };
587 
588 static struct qcom_icc_node qnm_cmpnoc1 = {
589 	.name = "qnm_cmpnoc1",
590 	.id = SA8775P_MASTER_COMPUTE_NOC_1,
591 	.channels = 2,
592 	.buswidth = 32,
593 	.num_links = 2,
594 	.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
595 		   SA8775P_SLAVE_LLCC
596 	},
597 };
598 
599 static struct qcom_icc_node qnm_gemnoc_cfg = {
600 	.name = "qnm_gemnoc_cfg",
601 	.id = SA8775P_MASTER_GEM_NOC_CFG,
602 	.channels = 1,
603 	.buswidth = 4,
604 	.num_links = 4,
605 	.links = { SA8775P_SLAVE_SERVICE_GEM_NOC_1,
606 		   SA8775P_SLAVE_SERVICE_GEM_NOC_2,
607 		   SA8775P_SLAVE_SERVICE_GEM_NOC,
608 		   SA8775P_SLAVE_SERVICE_GEM_NOC2
609 	},
610 };
611 
612 static struct qcom_icc_node qnm_gpdsp_sail = {
613 	.name = "qnm_gpdsp_sail",
614 	.id = SA8775P_MASTER_GPDSP_SAIL,
615 	.channels = 1,
616 	.buswidth = 16,
617 	.num_links = 2,
618 	.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
619 		   SA8775P_SLAVE_LLCC
620 	},
621 };
622 
623 static struct qcom_icc_node qnm_gpu = {
624 	.name = "qnm_gpu",
625 	.id = SA8775P_MASTER_GFX3D,
626 	.channels = 2,
627 	.buswidth = 32,
628 	.num_links = 2,
629 	.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
630 		   SA8775P_SLAVE_LLCC
631 	},
632 };
633 
634 static struct qcom_icc_node qnm_mnoc_hf = {
635 	.name = "qnm_mnoc_hf",
636 	.id = SA8775P_MASTER_MNOC_HF_MEM_NOC,
637 	.channels = 2,
638 	.buswidth = 32,
639 	.num_links = 2,
640 	.links = { SA8775P_SLAVE_LLCC,
641 		   SA8775P_SLAVE_GEM_NOC_PCIE_CNOC
642 	},
643 };
644 
645 static struct qcom_icc_node qnm_mnoc_sf = {
646 	.name = "qnm_mnoc_sf",
647 	.id = SA8775P_MASTER_MNOC_SF_MEM_NOC,
648 	.channels = 2,
649 	.buswidth = 32,
650 	.num_links = 3,
651 	.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
652 		   SA8775P_SLAVE_LLCC,
653 		   SA8775P_SLAVE_GEM_NOC_PCIE_CNOC
654 	},
655 };
656 
657 static struct qcom_icc_node qnm_pcie = {
658 	.name = "qnm_pcie",
659 	.id = SA8775P_MASTER_ANOC_PCIE_GEM_NOC,
660 	.channels = 1,
661 	.buswidth = 32,
662 	.num_links = 2,
663 	.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
664 		   SA8775P_SLAVE_LLCC
665 	},
666 };
667 
668 static struct qcom_icc_node qnm_snoc_gc = {
669 	.name = "qnm_snoc_gc",
670 	.id = SA8775P_MASTER_SNOC_GC_MEM_NOC,
671 	.channels = 1,
672 	.buswidth = 8,
673 	.num_links = 1,
674 	.links = { SA8775P_SLAVE_LLCC },
675 };
676 
677 static struct qcom_icc_node qnm_snoc_sf = {
678 	.name = "qnm_snoc_sf",
679 	.id = SA8775P_MASTER_SNOC_SF_MEM_NOC,
680 	.channels = 1,
681 	.buswidth = 16,
682 	.num_links = 3,
683 	.links = { SA8775P_SLAVE_GEM_NOC_CNOC,
684 		   SA8775P_SLAVE_LLCC,
685 		   SA8775P_SLAVE_GEM_NOC_PCIE_CNOC },
686 };
687 
688 static struct qcom_icc_node qxm_dsp0 = {
689 	.name = "qxm_dsp0",
690 	.id = SA8775P_MASTER_DSP0,
691 	.channels = 1,
692 	.buswidth = 16,
693 	.num_links = 1,
694 	.links = { SA8775P_SLAVE_GP_DSP_SAIL_NOC },
695 };
696 
697 static struct qcom_icc_node qxm_dsp1 = {
698 	.name = "qxm_dsp1",
699 	.id = SA8775P_MASTER_DSP1,
700 	.channels = 1,
701 	.buswidth = 16,
702 	.num_links = 1,
703 	.links = { SA8775P_SLAVE_GP_DSP_SAIL_NOC },
704 };
705 
706 static struct qcom_icc_node qhm_config_noc = {
707 	.name = "qhm_config_noc",
708 	.id = SA8775P_MASTER_CNOC_LPASS_AG_NOC,
709 	.channels = 1,
710 	.buswidth = 4,
711 	.num_links = 6,
712 	.links = { SA8775P_SLAVE_LPASS_CORE_CFG,
713 		   SA8775P_SLAVE_LPASS_LPI_CFG,
714 		   SA8775P_SLAVE_LPASS_MPU_CFG,
715 		   SA8775P_SLAVE_LPASS_TOP_CFG,
716 		   SA8775P_SLAVE_SERVICES_LPASS_AML_NOC,
717 		   SA8775P_SLAVE_SERVICE_LPASS_AG_NOC
718 	},
719 };
720 
721 static struct qcom_icc_node qxm_lpass_dsp = {
722 	.name = "qxm_lpass_dsp",
723 	.id = SA8775P_MASTER_LPASS_PROC,
724 	.channels = 1,
725 	.buswidth = 8,
726 	.num_links = 4,
727 	.links = { SA8775P_SLAVE_LPASS_TOP_CFG,
728 		   SA8775P_SLAVE_LPASS_SNOC,
729 		   SA8775P_SLAVE_SERVICES_LPASS_AML_NOC,
730 		   SA8775P_SLAVE_SERVICE_LPASS_AG_NOC
731 	},
732 };
733 
734 static struct qcom_icc_node llcc_mc = {
735 	.name = "llcc_mc",
736 	.id = SA8775P_MASTER_LLCC,
737 	.channels = 8,
738 	.buswidth = 4,
739 	.num_links = 1,
740 	.links = { SA8775P_SLAVE_EBI1 },
741 };
742 
743 static struct qcom_icc_node qnm_camnoc_hf = {
744 	.name = "qnm_camnoc_hf",
745 	.id = SA8775P_MASTER_CAMNOC_HF,
746 	.channels = 1,
747 	.buswidth = 32,
748 	.num_links = 1,
749 	.links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
750 };
751 
752 static struct qcom_icc_node qnm_camnoc_icp = {
753 	.name = "qnm_camnoc_icp",
754 	.id = SA8775P_MASTER_CAMNOC_ICP,
755 	.channels = 1,
756 	.buswidth = 8,
757 	.num_links = 1,
758 	.links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
759 };
760 
761 static struct qcom_icc_node qnm_camnoc_sf = {
762 	.name = "qnm_camnoc_sf",
763 	.id = SA8775P_MASTER_CAMNOC_SF,
764 	.channels = 1,
765 	.buswidth = 32,
766 	.num_links = 1,
767 	.links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
768 };
769 
770 static struct qcom_icc_node qnm_mdp0_0 = {
771 	.name = "qnm_mdp0_0",
772 	.id = SA8775P_MASTER_MDP0,
773 	.channels = 1,
774 	.buswidth = 32,
775 	.num_links = 1,
776 	.links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
777 };
778 
779 static struct qcom_icc_node qnm_mdp0_1 = {
780 	.name = "qnm_mdp0_1",
781 	.id = SA8775P_MASTER_MDP1,
782 	.channels = 1,
783 	.buswidth = 32,
784 	.num_links = 1,
785 	.links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
786 };
787 
788 static struct qcom_icc_node qnm_mdp1_0 = {
789 	.name = "qnm_mdp1_0",
790 	.id = SA8775P_MASTER_MDP_CORE1_0,
791 	.channels = 1,
792 	.buswidth = 32,
793 	.num_links = 1,
794 	.links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
795 };
796 
797 static struct qcom_icc_node qnm_mdp1_1 = {
798 	.name = "qnm_mdp1_1",
799 	.id = SA8775P_MASTER_MDP_CORE1_1,
800 	.channels = 1,
801 	.buswidth = 32,
802 	.num_links = 1,
803 	.links = { SA8775P_SLAVE_MNOC_HF_MEM_NOC },
804 };
805 
806 static struct qcom_icc_node qnm_mnoc_hf_cfg = {
807 	.name = "qnm_mnoc_hf_cfg",
808 	.id = SA8775P_MASTER_CNOC_MNOC_HF_CFG,
809 	.channels = 1,
810 	.buswidth = 4,
811 	.num_links = 1,
812 	.links = { SA8775P_SLAVE_SERVICE_MNOC_HF },
813 };
814 
815 static struct qcom_icc_node qnm_mnoc_sf_cfg = {
816 	.name = "qnm_mnoc_sf_cfg",
817 	.id = SA8775P_MASTER_CNOC_MNOC_SF_CFG,
818 	.channels = 1,
819 	.buswidth = 4,
820 	.num_links = 1,
821 	.links = { SA8775P_SLAVE_SERVICE_MNOC_SF },
822 };
823 
824 static struct qcom_icc_node qnm_video0 = {
825 	.name = "qnm_video0",
826 	.id = SA8775P_MASTER_VIDEO_P0,
827 	.channels = 1,
828 	.buswidth = 32,
829 	.num_links = 1,
830 	.links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
831 };
832 
833 static struct qcom_icc_node qnm_video1 = {
834 	.name = "qnm_video1",
835 	.id = SA8775P_MASTER_VIDEO_P1,
836 	.channels = 1,
837 	.buswidth = 32,
838 	.num_links = 1,
839 	.links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
840 };
841 
842 static struct qcom_icc_node qnm_video_cvp = {
843 	.name = "qnm_video_cvp",
844 	.id = SA8775P_MASTER_VIDEO_PROC,
845 	.channels = 1,
846 	.buswidth = 32,
847 	.num_links = 1,
848 	.links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
849 };
850 
851 static struct qcom_icc_node qnm_video_v_cpu = {
852 	.name = "qnm_video_v_cpu",
853 	.id = SA8775P_MASTER_VIDEO_V_PROC,
854 	.channels = 1,
855 	.buswidth = 8,
856 	.num_links = 1,
857 	.links = { SA8775P_SLAVE_MNOC_SF_MEM_NOC },
858 };
859 
860 static struct qcom_icc_node qhm_nsp_noc_config = {
861 	.name = "qhm_nsp_noc_config",
862 	.id = SA8775P_MASTER_CDSP_NOC_CFG,
863 	.channels = 1,
864 	.buswidth = 4,
865 	.num_links = 1,
866 	.links = { SA8775P_SLAVE_SERVICE_NSP_NOC },
867 };
868 
869 static struct qcom_icc_node qxm_nsp = {
870 	.name = "qxm_nsp",
871 	.id = SA8775P_MASTER_CDSP_PROC,
872 	.channels = 2,
873 	.buswidth = 32,
874 	.num_links = 2,
875 	.links = { SA8775P_SLAVE_HCP_A, SLAVE_CDSP_MEM_NOC },
876 };
877 
878 static struct qcom_icc_node qhm_nspb_noc_config = {
879 	.name = "qhm_nspb_noc_config",
880 	.id = SA8775P_MASTER_CDSPB_NOC_CFG,
881 	.channels = 1,
882 	.buswidth = 4,
883 	.num_links = 1,
884 	.links = { SA8775P_SLAVE_SERVICE_NSPB_NOC },
885 };
886 
887 static struct qcom_icc_node qxm_nspb = {
888 	.name = "qxm_nspb",
889 	.id = SA8775P_MASTER_CDSP_PROC_B,
890 	.channels = 2,
891 	.buswidth = 32,
892 	.num_links = 2,
893 	.links = { SA8775P_SLAVE_HCP_B, SLAVE_CDSPB_MEM_NOC },
894 };
895 
896 static struct qcom_icc_node xm_pcie3_0 = {
897 	.name = "xm_pcie3_0",
898 	.id = SA8775P_MASTER_PCIE_0,
899 	.channels = 1,
900 	.buswidth = 16,
901 	.num_links = 1,
902 	.links = { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC },
903 };
904 
905 static struct qcom_icc_node xm_pcie3_1 = {
906 	.name = "xm_pcie3_1",
907 	.id = SA8775P_MASTER_PCIE_1,
908 	.channels = 1,
909 	.buswidth = 32,
910 	.num_links = 1,
911 	.links = { SA8775P_SLAVE_ANOC_PCIE_GEM_NOC },
912 };
913 
914 static struct qcom_icc_node qhm_gic = {
915 	.name = "qhm_gic",
916 	.id = SA8775P_MASTER_GIC_AHB,
917 	.channels = 1,
918 	.buswidth = 4,
919 	.num_links = 1,
920 	.links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF },
921 };
922 
923 static struct qcom_icc_node qnm_aggre1_noc = {
924 	.name = "qnm_aggre1_noc",
925 	.id = SA8775P_MASTER_A1NOC_SNOC,
926 	.channels = 1,
927 	.buswidth = 32,
928 	.num_links = 1,
929 	.links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF },
930 };
931 
932 static struct qcom_icc_node qnm_aggre2_noc = {
933 	.name = "qnm_aggre2_noc",
934 	.id = SA8775P_MASTER_A2NOC_SNOC,
935 	.channels = 1,
936 	.buswidth = 16,
937 	.num_links = 1,
938 	.links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF },
939 };
940 
941 static struct qcom_icc_node qnm_lpass_noc = {
942 	.name = "qnm_lpass_noc",
943 	.id = SA8775P_MASTER_LPASS_ANOC,
944 	.channels = 1,
945 	.buswidth = 16,
946 	.num_links = 1,
947 	.links = { SA8775P_SLAVE_SNOC_GEM_NOC_SF },
948 };
949 
950 static struct qcom_icc_node qnm_snoc_cfg = {
951 	.name = "qnm_snoc_cfg",
952 	.id = SA8775P_MASTER_SNOC_CFG,
953 	.channels = 1,
954 	.buswidth = 4,
955 	.num_links = 1,
956 	.links = { SA8775P_SLAVE_SERVICE_SNOC },
957 };
958 
959 static struct qcom_icc_node qxm_pimem = {
960 	.name = "qxm_pimem",
961 	.id = SA8775P_MASTER_PIMEM,
962 	.channels = 1,
963 	.buswidth = 8,
964 	.num_links = 1,
965 	.links = { SA8775P_SLAVE_SNOC_GEM_NOC_GC },
966 };
967 
968 static struct qcom_icc_node xm_gic = {
969 	.name = "xm_gic",
970 	.id = SA8775P_MASTER_GIC,
971 	.channels = 1,
972 	.buswidth = 8,
973 	.num_links = 1,
974 	.links = { SA8775P_SLAVE_SNOC_GEM_NOC_GC },
975 };
976 
977 static struct qcom_icc_node qns_a1noc_snoc = {
978 	.name = "qns_a1noc_snoc",
979 	.id = SA8775P_SLAVE_A1NOC_SNOC,
980 	.channels = 1,
981 	.buswidth = 32,
982 	.num_links = 1,
983 	.links = { SA8775P_MASTER_A1NOC_SNOC },
984 };
985 
986 static struct qcom_icc_node qns_a2noc_snoc = {
987 	.name = "qns_a2noc_snoc",
988 	.id = SA8775P_SLAVE_A2NOC_SNOC,
989 	.channels = 1,
990 	.buswidth = 16,
991 	.num_links = 1,
992 	.links = { SA8775P_MASTER_A2NOC_SNOC },
993 };
994 
995 static struct qcom_icc_node qup0_core_slave = {
996 	.name = "qup0_core_slave",
997 	.id = SA8775P_SLAVE_QUP_CORE_0,
998 	.channels = 1,
999 	.buswidth = 4,
1000 };
1001 
1002 static struct qcom_icc_node qup1_core_slave = {
1003 	.name = "qup1_core_slave",
1004 	.id = SA8775P_SLAVE_QUP_CORE_1,
1005 	.channels = 1,
1006 	.buswidth = 4,
1007 };
1008 
1009 static struct qcom_icc_node qup2_core_slave = {
1010 	.name = "qup2_core_slave",
1011 	.id = SA8775P_SLAVE_QUP_CORE_2,
1012 	.channels = 1,
1013 	.buswidth = 4,
1014 };
1015 
1016 static struct qcom_icc_node qup3_core_slave = {
1017 	.name = "qup3_core_slave",
1018 	.id = SA8775P_SLAVE_QUP_CORE_3,
1019 	.channels = 1,
1020 	.buswidth = 4,
1021 };
1022 
1023 static struct qcom_icc_node qhs_ahb2phy0 = {
1024 	.name = "qhs_ahb2phy0",
1025 	.id = SA8775P_SLAVE_AHB2PHY_0,
1026 	.channels = 1,
1027 	.buswidth = 4,
1028 };
1029 
1030 static struct qcom_icc_node qhs_ahb2phy1 = {
1031 	.name = "qhs_ahb2phy1",
1032 	.id = SA8775P_SLAVE_AHB2PHY_1,
1033 	.channels = 1,
1034 	.buswidth = 4,
1035 };
1036 
1037 static struct qcom_icc_node qhs_ahb2phy2 = {
1038 	.name = "qhs_ahb2phy2",
1039 	.id = SA8775P_SLAVE_AHB2PHY_2,
1040 	.channels = 1,
1041 	.buswidth = 4,
1042 };
1043 
1044 static struct qcom_icc_node qhs_ahb2phy3 = {
1045 	.name = "qhs_ahb2phy3",
1046 	.id = SA8775P_SLAVE_AHB2PHY_3,
1047 	.channels = 1,
1048 	.buswidth = 4,
1049 };
1050 
1051 static struct qcom_icc_node qhs_anoc_throttle_cfg = {
1052 	.name = "qhs_anoc_throttle_cfg",
1053 	.id = SA8775P_SLAVE_ANOC_THROTTLE_CFG,
1054 	.channels = 1,
1055 	.buswidth = 4,
1056 };
1057 
1058 static struct qcom_icc_node qhs_aoss = {
1059 	.name = "qhs_aoss",
1060 	.id = SA8775P_SLAVE_AOSS,
1061 	.channels = 1,
1062 	.buswidth = 4,
1063 };
1064 
1065 static struct qcom_icc_node qhs_apss = {
1066 	.name = "qhs_apss",
1067 	.id = SA8775P_SLAVE_APPSS,
1068 	.channels = 1,
1069 	.buswidth = 8,
1070 };
1071 
1072 static struct qcom_icc_node qhs_boot_rom = {
1073 	.name = "qhs_boot_rom",
1074 	.id = SA8775P_SLAVE_BOOT_ROM,
1075 	.channels = 1,
1076 	.buswidth = 4,
1077 };
1078 
1079 static struct qcom_icc_node qhs_camera_cfg = {
1080 	.name = "qhs_camera_cfg",
1081 	.id = SA8775P_SLAVE_CAMERA_CFG,
1082 	.channels = 1,
1083 	.buswidth = 4,
1084 };
1085 
1086 static struct qcom_icc_node qhs_camera_nrt_throttle_cfg = {
1087 	.name = "qhs_camera_nrt_throttle_cfg",
1088 	.id = SA8775P_SLAVE_CAMERA_NRT_THROTTLE_CFG,
1089 	.channels = 1,
1090 	.buswidth = 4,
1091 };
1092 
1093 static struct qcom_icc_node qhs_camera_rt_throttle_cfg = {
1094 	.name = "qhs_camera_rt_throttle_cfg",
1095 	.id = SA8775P_SLAVE_CAMERA_RT_THROTTLE_CFG,
1096 	.channels = 1,
1097 	.buswidth = 4,
1098 };
1099 
1100 static struct qcom_icc_node qhs_clk_ctl = {
1101 	.name = "qhs_clk_ctl",
1102 	.id = SA8775P_SLAVE_CLK_CTL,
1103 	.channels = 1,
1104 	.buswidth = 4,
1105 };
1106 
1107 static struct qcom_icc_node qhs_compute0_cfg = {
1108 	.name = "qhs_compute0_cfg",
1109 	.id = SA8775P_SLAVE_CDSP_CFG,
1110 	.channels = 1,
1111 	.buswidth = 4,
1112 	.num_links = 1,
1113 	.links = { SA8775P_MASTER_CDSP_NOC_CFG },
1114 };
1115 
1116 static struct qcom_icc_node qhs_compute1_cfg = {
1117 	.name = "qhs_compute1_cfg",
1118 	.id = SA8775P_SLAVE_CDSP1_CFG,
1119 	.channels = 1,
1120 	.buswidth = 4,
1121 	.num_links = 1,
1122 	.links = { SA8775P_MASTER_CDSPB_NOC_CFG },
1123 };
1124 
1125 static struct qcom_icc_node qhs_cpr_cx = {
1126 	.name = "qhs_cpr_cx",
1127 	.id = SA8775P_SLAVE_RBCPR_CX_CFG,
1128 	.channels = 1,
1129 	.buswidth = 4,
1130 };
1131 
1132 static struct qcom_icc_node qhs_cpr_mmcx = {
1133 	.name = "qhs_cpr_mmcx",
1134 	.id = SA8775P_SLAVE_RBCPR_MMCX_CFG,
1135 	.channels = 1,
1136 	.buswidth = 4,
1137 };
1138 
1139 static struct qcom_icc_node qhs_cpr_mx = {
1140 	.name = "qhs_cpr_mx",
1141 	.id = SA8775P_SLAVE_RBCPR_MX_CFG,
1142 	.channels = 1,
1143 	.buswidth = 4,
1144 };
1145 
1146 static struct qcom_icc_node qhs_cpr_nspcx = {
1147 	.name = "qhs_cpr_nspcx",
1148 	.id = SA8775P_SLAVE_CPR_NSPCX,
1149 	.channels = 1,
1150 	.buswidth = 4,
1151 };
1152 
1153 static struct qcom_icc_node qhs_crypto0_cfg = {
1154 	.name = "qhs_crypto0_cfg",
1155 	.id = SA8775P_SLAVE_CRYPTO_0_CFG,
1156 	.channels = 1,
1157 	.buswidth = 4,
1158 };
1159 
1160 static struct qcom_icc_node qhs_cx_rdpm = {
1161 	.name = "qhs_cx_rdpm",
1162 	.id = SA8775P_SLAVE_CX_RDPM,
1163 	.channels = 1,
1164 	.buswidth = 4,
1165 };
1166 
1167 static struct qcom_icc_node qhs_display0_cfg = {
1168 	.name = "qhs_display0_cfg",
1169 	.id = SA8775P_SLAVE_DISPLAY_CFG,
1170 	.channels = 1,
1171 	.buswidth = 4,
1172 };
1173 
1174 static struct qcom_icc_node qhs_display0_rt_throttle_cfg = {
1175 	.name = "qhs_display0_rt_throttle_cfg",
1176 	.id = SA8775P_SLAVE_DISPLAY_RT_THROTTLE_CFG,
1177 	.channels = 1,
1178 	.buswidth = 4,
1179 };
1180 
1181 static struct qcom_icc_node qhs_display1_cfg = {
1182 	.name = "qhs_display1_cfg",
1183 	.id = SA8775P_SLAVE_DISPLAY1_CFG,
1184 	.channels = 1,
1185 	.buswidth = 4,
1186 };
1187 
1188 static struct qcom_icc_node qhs_display1_rt_throttle_cfg = {
1189 	.name = "qhs_display1_rt_throttle_cfg",
1190 	.id = SA8775P_SLAVE_DISPLAY1_RT_THROTTLE_CFG,
1191 	.channels = 1,
1192 	.buswidth = 4,
1193 };
1194 
1195 static struct qcom_icc_node qhs_emac0_cfg = {
1196 	.name = "qhs_emac0_cfg",
1197 	.id = SA8775P_SLAVE_EMAC_CFG,
1198 	.channels = 1,
1199 	.buswidth = 4,
1200 };
1201 
1202 static struct qcom_icc_node qhs_emac1_cfg = {
1203 	.name = "qhs_emac1_cfg",
1204 	.id = SA8775P_SLAVE_EMAC1_CFG,
1205 	.channels = 1,
1206 	.buswidth = 4,
1207 };
1208 
1209 static struct qcom_icc_node qhs_gp_dsp0_cfg = {
1210 	.name = "qhs_gp_dsp0_cfg",
1211 	.id = SA8775P_SLAVE_GP_DSP0_CFG,
1212 	.channels = 1,
1213 	.buswidth = 4,
1214 };
1215 
1216 static struct qcom_icc_node qhs_gp_dsp1_cfg = {
1217 	.name = "qhs_gp_dsp1_cfg",
1218 	.id = SA8775P_SLAVE_GP_DSP1_CFG,
1219 	.channels = 1,
1220 	.buswidth = 4,
1221 };
1222 
1223 static struct qcom_icc_node qhs_gpdsp0_throttle_cfg = {
1224 	.name = "qhs_gpdsp0_throttle_cfg",
1225 	.id = SA8775P_SLAVE_GPDSP0_THROTTLE_CFG,
1226 	.channels = 1,
1227 	.buswidth = 4,
1228 };
1229 
1230 static struct qcom_icc_node qhs_gpdsp1_throttle_cfg = {
1231 	.name = "qhs_gpdsp1_throttle_cfg",
1232 	.id = SA8775P_SLAVE_GPDSP1_THROTTLE_CFG,
1233 	.channels = 1,
1234 	.buswidth = 4,
1235 };
1236 
1237 static struct qcom_icc_node qhs_gpu_tcu_throttle_cfg = {
1238 	.name = "qhs_gpu_tcu_throttle_cfg",
1239 	.id = SA8775P_SLAVE_GPU_TCU_THROTTLE_CFG,
1240 	.channels = 1,
1241 	.buswidth = 4,
1242 };
1243 
1244 static struct qcom_icc_node qhs_gpuss_cfg = {
1245 	.name = "qhs_gpuss_cfg",
1246 	.id = SA8775P_SLAVE_GFX3D_CFG,
1247 	.channels = 1,
1248 	.buswidth = 8,
1249 };
1250 
1251 static struct qcom_icc_node qhs_hwkm = {
1252 	.name = "qhs_hwkm",
1253 	.id = SA8775P_SLAVE_HWKM,
1254 	.channels = 1,
1255 	.buswidth = 4,
1256 };
1257 
1258 static struct qcom_icc_node qhs_imem_cfg = {
1259 	.name = "qhs_imem_cfg",
1260 	.id = SA8775P_SLAVE_IMEM_CFG,
1261 	.channels = 1,
1262 	.buswidth = 4,
1263 };
1264 
1265 static struct qcom_icc_node qhs_ipa = {
1266 	.name = "qhs_ipa",
1267 	.id = SA8775P_SLAVE_IPA_CFG,
1268 	.channels = 1,
1269 	.buswidth = 4,
1270 };
1271 
1272 static struct qcom_icc_node qhs_ipc_router = {
1273 	.name = "qhs_ipc_router",
1274 	.id = SA8775P_SLAVE_IPC_ROUTER_CFG,
1275 	.channels = 1,
1276 	.buswidth = 4,
1277 };
1278 
1279 static struct qcom_icc_node qhs_lpass_cfg = {
1280 	.name = "qhs_lpass_cfg",
1281 	.id = SA8775P_SLAVE_LPASS,
1282 	.channels = 1,
1283 	.buswidth = 4,
1284 	.num_links = 1,
1285 	.links = { SA8775P_MASTER_CNOC_LPASS_AG_NOC },
1286 };
1287 
1288 static struct qcom_icc_node qhs_lpass_throttle_cfg = {
1289 	.name = "qhs_lpass_throttle_cfg",
1290 	.id = SA8775P_SLAVE_LPASS_THROTTLE_CFG,
1291 	.channels = 1,
1292 	.buswidth = 4,
1293 };
1294 
1295 static struct qcom_icc_node qhs_mx_rdpm = {
1296 	.name = "qhs_mx_rdpm",
1297 	.id = SA8775P_SLAVE_MX_RDPM,
1298 	.channels = 1,
1299 	.buswidth = 4,
1300 };
1301 
1302 static struct qcom_icc_node qhs_mxc_rdpm = {
1303 	.name = "qhs_mxc_rdpm",
1304 	.id = SA8775P_SLAVE_MXC_RDPM,
1305 	.channels = 1,
1306 	.buswidth = 4,
1307 };
1308 
1309 static struct qcom_icc_node qhs_pcie0_cfg = {
1310 	.name = "qhs_pcie0_cfg",
1311 	.id = SA8775P_SLAVE_PCIE_0_CFG,
1312 	.channels = 1,
1313 	.buswidth = 4,
1314 };
1315 
1316 static struct qcom_icc_node qhs_pcie1_cfg = {
1317 	.name = "qhs_pcie1_cfg",
1318 	.id = SA8775P_SLAVE_PCIE_1_CFG,
1319 	.channels = 1,
1320 	.buswidth = 4,
1321 };
1322 
1323 static struct qcom_icc_node qhs_pcie_rsc_cfg = {
1324 	.name = "qhs_pcie_rsc_cfg",
1325 	.id = SA8775P_SLAVE_PCIE_RSC_CFG,
1326 	.channels = 1,
1327 	.buswidth = 4,
1328 };
1329 
1330 static struct qcom_icc_node qhs_pcie_tcu_throttle_cfg = {
1331 	.name = "qhs_pcie_tcu_throttle_cfg",
1332 	.id = SA8775P_SLAVE_PCIE_TCU_THROTTLE_CFG,
1333 	.channels = 1,
1334 	.buswidth = 4,
1335 };
1336 
1337 static struct qcom_icc_node qhs_pcie_throttle_cfg = {
1338 	.name = "qhs_pcie_throttle_cfg",
1339 	.id = SA8775P_SLAVE_PCIE_THROTTLE_CFG,
1340 	.channels = 1,
1341 	.buswidth = 4,
1342 };
1343 
1344 static struct qcom_icc_node qhs_pdm = {
1345 	.name = "qhs_pdm",
1346 	.id = SA8775P_SLAVE_PDM,
1347 	.channels = 1,
1348 	.buswidth = 4,
1349 };
1350 
1351 static struct qcom_icc_node qhs_pimem_cfg = {
1352 	.name = "qhs_pimem_cfg",
1353 	.id = SA8775P_SLAVE_PIMEM_CFG,
1354 	.channels = 1,
1355 	.buswidth = 4,
1356 };
1357 
1358 static struct qcom_icc_node qhs_pke_wrapper_cfg = {
1359 	.name = "qhs_pke_wrapper_cfg",
1360 	.id = SA8775P_SLAVE_PKA_WRAPPER_CFG,
1361 	.channels = 1,
1362 	.buswidth = 4,
1363 };
1364 
1365 static struct qcom_icc_node qhs_qdss_cfg = {
1366 	.name = "qhs_qdss_cfg",
1367 	.id = SA8775P_SLAVE_QDSS_CFG,
1368 	.channels = 1,
1369 	.buswidth = 4,
1370 };
1371 
1372 static struct qcom_icc_node qhs_qm_cfg = {
1373 	.name = "qhs_qm_cfg",
1374 	.id = SA8775P_SLAVE_QM_CFG,
1375 	.channels = 1,
1376 	.buswidth = 4,
1377 };
1378 
1379 static struct qcom_icc_node qhs_qm_mpu_cfg = {
1380 	.name = "qhs_qm_mpu_cfg",
1381 	.id = SA8775P_SLAVE_QM_MPU_CFG,
1382 	.channels = 1,
1383 	.buswidth = 4,
1384 };
1385 
1386 static struct qcom_icc_node qhs_qup0 = {
1387 	.name = "qhs_qup0",
1388 	.id = SA8775P_SLAVE_QUP_0,
1389 	.channels = 1,
1390 	.buswidth = 4,
1391 };
1392 
1393 static struct qcom_icc_node qhs_qup1 = {
1394 	.name = "qhs_qup1",
1395 	.id = SA8775P_SLAVE_QUP_1,
1396 	.channels = 1,
1397 	.buswidth = 4,
1398 };
1399 
1400 static struct qcom_icc_node qhs_qup2 = {
1401 	.name = "qhs_qup2",
1402 	.id = SA8775P_SLAVE_QUP_2,
1403 	.channels = 1,
1404 	.buswidth = 4,
1405 };
1406 
1407 static struct qcom_icc_node qhs_qup3 = {
1408 	.name = "qhs_qup3",
1409 	.id = SA8775P_SLAVE_QUP_3,
1410 	.channels = 1,
1411 	.buswidth = 4,
1412 };
1413 
1414 static struct qcom_icc_node qhs_sail_throttle_cfg = {
1415 	.name = "qhs_sail_throttle_cfg",
1416 	.id = SA8775P_SLAVE_SAIL_THROTTLE_CFG,
1417 	.channels = 1,
1418 	.buswidth = 4,
1419 };
1420 
1421 static struct qcom_icc_node qhs_sdc1 = {
1422 	.name = "qhs_sdc1",
1423 	.id = SA8775P_SLAVE_SDC1,
1424 	.channels = 1,
1425 	.buswidth = 4,
1426 };
1427 
1428 static struct qcom_icc_node qhs_security = {
1429 	.name = "qhs_security",
1430 	.id = SA8775P_SLAVE_SECURITY,
1431 	.channels = 1,
1432 	.buswidth = 4,
1433 };
1434 
1435 static struct qcom_icc_node qhs_snoc_throttle_cfg = {
1436 	.name = "qhs_snoc_throttle_cfg",
1437 	.id = SA8775P_SLAVE_SNOC_THROTTLE_CFG,
1438 	.channels = 1,
1439 	.buswidth = 4,
1440 };
1441 
1442 static struct qcom_icc_node qhs_tcsr = {
1443 	.name = "qhs_tcsr",
1444 	.id = SA8775P_SLAVE_TCSR,
1445 	.channels = 1,
1446 	.buswidth = 4,
1447 };
1448 
1449 static struct qcom_icc_node qhs_tlmm = {
1450 	.name = "qhs_tlmm",
1451 	.id = SA8775P_SLAVE_TLMM,
1452 	.channels = 1,
1453 	.buswidth = 4,
1454 };
1455 
1456 static struct qcom_icc_node qhs_tsc_cfg = {
1457 	.name = "qhs_tsc_cfg",
1458 	.id = SA8775P_SLAVE_TSC_CFG,
1459 	.channels = 1,
1460 	.buswidth = 4,
1461 };
1462 
1463 static struct qcom_icc_node qhs_ufs_card_cfg = {
1464 	.name = "qhs_ufs_card_cfg",
1465 	.id = SA8775P_SLAVE_UFS_CARD_CFG,
1466 	.channels = 1,
1467 	.buswidth = 4,
1468 };
1469 
1470 static struct qcom_icc_node qhs_ufs_mem_cfg = {
1471 	.name = "qhs_ufs_mem_cfg",
1472 	.id = SA8775P_SLAVE_UFS_MEM_CFG,
1473 	.channels = 1,
1474 	.buswidth = 4,
1475 };
1476 
1477 static struct qcom_icc_node qhs_usb2_0 = {
1478 	.name = "qhs_usb2_0",
1479 	.id = SA8775P_SLAVE_USB2,
1480 	.channels = 1,
1481 	.buswidth = 4,
1482 };
1483 
1484 static struct qcom_icc_node qhs_usb3_0 = {
1485 	.name = "qhs_usb3_0",
1486 	.id = SA8775P_SLAVE_USB3_0,
1487 	.channels = 1,
1488 	.buswidth = 4,
1489 };
1490 
1491 static struct qcom_icc_node qhs_usb3_1 = {
1492 	.name = "qhs_usb3_1",
1493 	.id = SA8775P_SLAVE_USB3_1,
1494 	.channels = 1,
1495 	.buswidth = 4,
1496 };
1497 
1498 static struct qcom_icc_node qhs_venus_cfg = {
1499 	.name = "qhs_venus_cfg",
1500 	.id = SA8775P_SLAVE_VENUS_CFG,
1501 	.channels = 1,
1502 	.buswidth = 4,
1503 };
1504 
1505 static struct qcom_icc_node qhs_venus_cvp_throttle_cfg = {
1506 	.name = "qhs_venus_cvp_throttle_cfg",
1507 	.id = SA8775P_SLAVE_VENUS_CVP_THROTTLE_CFG,
1508 	.channels = 1,
1509 	.buswidth = 4,
1510 };
1511 
1512 static struct qcom_icc_node qhs_venus_v_cpu_throttle_cfg = {
1513 	.name = "qhs_venus_v_cpu_throttle_cfg",
1514 	.id = SA8775P_SLAVE_VENUS_V_CPU_THROTTLE_CFG,
1515 	.channels = 1,
1516 	.buswidth = 4,
1517 };
1518 
1519 static struct qcom_icc_node qhs_venus_vcodec_throttle_cfg = {
1520 	.name = "qhs_venus_vcodec_throttle_cfg",
1521 	.id = SA8775P_SLAVE_VENUS_VCODEC_THROTTLE_CFG,
1522 	.channels = 1,
1523 	.buswidth = 4,
1524 };
1525 
1526 static struct qcom_icc_node qns_ddrss_cfg = {
1527 	.name = "qns_ddrss_cfg",
1528 	.id = SA8775P_SLAVE_DDRSS_CFG,
1529 	.channels = 1,
1530 	.buswidth = 4,
1531 	.num_links = 1,
1532 	.links = { SA8775P_MASTER_CNOC_DC_NOC },
1533 };
1534 
1535 static struct qcom_icc_node qns_gpdsp_noc_cfg = {
1536 	.name = "qns_gpdsp_noc_cfg",
1537 	.id = SA8775P_SLAVE_GPDSP_NOC_CFG,
1538 	.channels = 1,
1539 	.buswidth = 4,
1540 };
1541 
1542 static struct qcom_icc_node qns_mnoc_hf_cfg = {
1543 	.name = "qns_mnoc_hf_cfg",
1544 	.id = SA8775P_SLAVE_CNOC_MNOC_HF_CFG,
1545 	.channels = 1,
1546 	.buswidth = 4,
1547 	.num_links = 1,
1548 	.links = { SA8775P_MASTER_CNOC_MNOC_HF_CFG },
1549 };
1550 
1551 static struct qcom_icc_node qns_mnoc_sf_cfg = {
1552 	.name = "qns_mnoc_sf_cfg",
1553 	.id = SA8775P_SLAVE_CNOC_MNOC_SF_CFG,
1554 	.channels = 1,
1555 	.buswidth = 4,
1556 	.num_links = 1,
1557 	.links = { SA8775P_MASTER_CNOC_MNOC_SF_CFG },
1558 };
1559 
1560 static struct qcom_icc_node qns_pcie_anoc_cfg = {
1561 	.name = "qns_pcie_anoc_cfg",
1562 	.id = SA8775P_SLAVE_PCIE_ANOC_CFG,
1563 	.channels = 1,
1564 	.buswidth = 4,
1565 };
1566 
1567 static struct qcom_icc_node qns_snoc_cfg = {
1568 	.name = "qns_snoc_cfg",
1569 	.id = SA8775P_SLAVE_SNOC_CFG,
1570 	.channels = 1,
1571 	.buswidth = 4,
1572 	.num_links = 1,
1573 	.links = { SA8775P_MASTER_SNOC_CFG },
1574 };
1575 
1576 static struct qcom_icc_node qxs_boot_imem = {
1577 	.name = "qxs_boot_imem",
1578 	.id = SA8775P_SLAVE_BOOT_IMEM,
1579 	.channels = 1,
1580 	.buswidth = 16,
1581 };
1582 
1583 static struct qcom_icc_node qxs_imem = {
1584 	.name = "qxs_imem",
1585 	.id = SA8775P_SLAVE_IMEM,
1586 	.channels = 1,
1587 	.buswidth = 8,
1588 };
1589 
1590 static struct qcom_icc_node qxs_pimem = {
1591 	.name = "qxs_pimem",
1592 	.id = SA8775P_SLAVE_PIMEM,
1593 	.channels = 1,
1594 	.buswidth = 8,
1595 };
1596 
1597 static struct qcom_icc_node xs_pcie_0 = {
1598 	.name = "xs_pcie_0",
1599 	.id = SA8775P_SLAVE_PCIE_0,
1600 	.channels = 1,
1601 	.buswidth = 16,
1602 };
1603 
1604 static struct qcom_icc_node xs_pcie_1 = {
1605 	.name = "xs_pcie_1",
1606 	.id = SA8775P_SLAVE_PCIE_1,
1607 	.channels = 1,
1608 	.buswidth = 32,
1609 };
1610 
1611 static struct qcom_icc_node xs_qdss_stm = {
1612 	.name = "xs_qdss_stm",
1613 	.id = SA8775P_SLAVE_QDSS_STM,
1614 	.channels = 1,
1615 	.buswidth = 4,
1616 };
1617 
1618 static struct qcom_icc_node xs_sys_tcu_cfg = {
1619 	.name = "xs_sys_tcu_cfg",
1620 	.id = SA8775P_SLAVE_TCU,
1621 	.channels = 1,
1622 	.buswidth = 8,
1623 };
1624 
1625 static struct qcom_icc_node qhs_llcc = {
1626 	.name = "qhs_llcc",
1627 	.id = SA8775P_SLAVE_LLCC_CFG,
1628 	.channels = 1,
1629 	.buswidth = 4,
1630 };
1631 
1632 static struct qcom_icc_node qns_gemnoc = {
1633 	.name = "qns_gemnoc",
1634 	.id = SA8775P_SLAVE_GEM_NOC_CFG,
1635 	.channels = 1,
1636 	.buswidth = 4,
1637 	.num_links = 1,
1638 	.links = { SA8775P_MASTER_GEM_NOC_CFG },
1639 };
1640 
1641 static struct qcom_icc_node qns_gem_noc_cnoc = {
1642 	.name = "qns_gem_noc_cnoc",
1643 	.id = SA8775P_SLAVE_GEM_NOC_CNOC,
1644 	.channels = 1,
1645 	.buswidth = 16,
1646 	.num_links = 1,
1647 	.links = { SA8775P_MASTER_GEM_NOC_CNOC },
1648 };
1649 
1650 static struct qcom_icc_node qns_llcc = {
1651 	.name = "qns_llcc",
1652 	.id = SA8775P_SLAVE_LLCC,
1653 	.channels = 6,
1654 	.buswidth = 16,
1655 	.num_links = 1,
1656 	.links = { SA8775P_MASTER_LLCC },
1657 };
1658 
1659 static struct qcom_icc_node qns_pcie = {
1660 	.name = "qns_pcie",
1661 	.id = SA8775P_SLAVE_GEM_NOC_PCIE_CNOC,
1662 	.channels = 1,
1663 	.buswidth = 16,
1664 	.num_links = 1,
1665 	.links = { SA8775P_MASTER_GEM_NOC_PCIE_SNOC },
1666 };
1667 
1668 static struct qcom_icc_node srvc_even_gemnoc = {
1669 	.name = "srvc_even_gemnoc",
1670 	.id = SA8775P_SLAVE_SERVICE_GEM_NOC_1,
1671 	.channels = 1,
1672 	.buswidth = 4,
1673 };
1674 
1675 static struct qcom_icc_node srvc_odd_gemnoc = {
1676 	.name = "srvc_odd_gemnoc",
1677 	.id = SA8775P_SLAVE_SERVICE_GEM_NOC_2,
1678 	.channels = 1,
1679 	.buswidth = 4,
1680 };
1681 
1682 static struct qcom_icc_node srvc_sys_gemnoc = {
1683 	.name = "srvc_sys_gemnoc",
1684 	.id = SA8775P_SLAVE_SERVICE_GEM_NOC,
1685 	.channels = 1,
1686 	.buswidth = 4,
1687 };
1688 
1689 static struct qcom_icc_node srvc_sys_gemnoc_2 = {
1690 	.name = "srvc_sys_gemnoc_2",
1691 	.id = SA8775P_SLAVE_SERVICE_GEM_NOC2,
1692 	.channels = 1,
1693 	.buswidth = 4,
1694 };
1695 
1696 static struct qcom_icc_node qns_gp_dsp_sail_noc = {
1697 	.name = "qns_gp_dsp_sail_noc",
1698 	.id = SA8775P_SLAVE_GP_DSP_SAIL_NOC,
1699 	.channels = 1,
1700 	.buswidth = 16,
1701 	.num_links = 1,
1702 	.links = { SA8775P_MASTER_GPDSP_SAIL },
1703 };
1704 
1705 static struct qcom_icc_node qhs_lpass_core = {
1706 	.name = "qhs_lpass_core",
1707 	.id = SA8775P_SLAVE_LPASS_CORE_CFG,
1708 	.channels = 1,
1709 	.buswidth = 4,
1710 };
1711 
1712 static struct qcom_icc_node qhs_lpass_lpi = {
1713 	.name = "qhs_lpass_lpi",
1714 	.id = SA8775P_SLAVE_LPASS_LPI_CFG,
1715 	.channels = 1,
1716 	.buswidth = 4,
1717 };
1718 
1719 static struct qcom_icc_node qhs_lpass_mpu = {
1720 	.name = "qhs_lpass_mpu",
1721 	.id = SA8775P_SLAVE_LPASS_MPU_CFG,
1722 	.channels = 1,
1723 	.buswidth = 4,
1724 };
1725 
1726 static struct qcom_icc_node qhs_lpass_top = {
1727 	.name = "qhs_lpass_top",
1728 	.id = SA8775P_SLAVE_LPASS_TOP_CFG,
1729 	.channels = 1,
1730 	.buswidth = 4,
1731 };
1732 
1733 static struct qcom_icc_node qns_sysnoc = {
1734 	.name = "qns_sysnoc",
1735 	.id = SA8775P_SLAVE_LPASS_SNOC,
1736 	.channels = 1,
1737 	.buswidth = 16,
1738 	.num_links = 1,
1739 	.links = { SA8775P_MASTER_LPASS_ANOC },
1740 };
1741 
1742 static struct qcom_icc_node srvc_niu_aml_noc = {
1743 	.name = "srvc_niu_aml_noc",
1744 	.id = SA8775P_SLAVE_SERVICES_LPASS_AML_NOC,
1745 	.channels = 1,
1746 	.buswidth = 4,
1747 };
1748 
1749 static struct qcom_icc_node srvc_niu_lpass_agnoc = {
1750 	.name = "srvc_niu_lpass_agnoc",
1751 	.id = SA8775P_SLAVE_SERVICE_LPASS_AG_NOC,
1752 	.channels = 1,
1753 	.buswidth = 4,
1754 };
1755 
1756 static struct qcom_icc_node ebi = {
1757 	.name = "ebi",
1758 	.id = SA8775P_SLAVE_EBI1,
1759 	.channels = 8,
1760 	.buswidth = 4,
1761 };
1762 
1763 static struct qcom_icc_node qns_mem_noc_hf = {
1764 	.name = "qns_mem_noc_hf",
1765 	.id = SA8775P_SLAVE_MNOC_HF_MEM_NOC,
1766 	.channels = 2,
1767 	.buswidth = 32,
1768 	.num_links = 1,
1769 	.links = { SA8775P_MASTER_MNOC_HF_MEM_NOC },
1770 };
1771 
1772 static struct qcom_icc_node qns_mem_noc_sf = {
1773 	.name = "qns_mem_noc_sf",
1774 	.id = SA8775P_SLAVE_MNOC_SF_MEM_NOC,
1775 	.channels = 2,
1776 	.buswidth = 32,
1777 	.num_links = 1,
1778 	.links = { SA8775P_MASTER_MNOC_SF_MEM_NOC },
1779 };
1780 
1781 static struct qcom_icc_node srvc_mnoc_hf = {
1782 	.name = "srvc_mnoc_hf",
1783 	.id = SA8775P_SLAVE_SERVICE_MNOC_HF,
1784 	.channels = 1,
1785 	.buswidth = 4,
1786 };
1787 
1788 static struct qcom_icc_node srvc_mnoc_sf = {
1789 	.name = "srvc_mnoc_sf",
1790 	.id = SA8775P_SLAVE_SERVICE_MNOC_SF,
1791 	.channels = 1,
1792 	.buswidth = 4,
1793 };
1794 
1795 static struct qcom_icc_node qns_hcp = {
1796 	.name = "qns_hcp",
1797 	.id = SA8775P_SLAVE_HCP_A,
1798 	.channels = 2,
1799 	.buswidth = 32,
1800 };
1801 
1802 static struct qcom_icc_node qns_nsp_gemnoc = {
1803 	.name = "qns_nsp_gemnoc",
1804 	.id = SA8775P_SLAVE_CDSP_MEM_NOC,
1805 	.channels = 2,
1806 	.buswidth = 32,
1807 	.num_links = 1,
1808 	.links = { SA8775P_MASTER_COMPUTE_NOC },
1809 };
1810 
1811 static struct qcom_icc_node service_nsp_noc = {
1812 	.name = "service_nsp_noc",
1813 	.id = SA8775P_SLAVE_SERVICE_NSP_NOC,
1814 	.channels = 1,
1815 	.buswidth = 4,
1816 };
1817 
1818 static struct qcom_icc_node qns_nspb_gemnoc = {
1819 	.name = "qns_nspb_gemnoc",
1820 	.id = SA8775P_SLAVE_CDSPB_MEM_NOC,
1821 	.channels = 2,
1822 	.buswidth = 32,
1823 	.num_links = 1,
1824 	.links = { SA8775P_MASTER_COMPUTE_NOC_1 },
1825 };
1826 
1827 static struct qcom_icc_node qns_nspb_hcp = {
1828 	.name = "qns_nspb_hcp",
1829 	.id = SA8775P_SLAVE_HCP_B,
1830 	.channels = 2,
1831 	.buswidth = 32,
1832 };
1833 
1834 static struct qcom_icc_node service_nspb_noc = {
1835 	.name = "service_nspb_noc",
1836 	.id = SA8775P_SLAVE_SERVICE_NSPB_NOC,
1837 	.channels = 1,
1838 	.buswidth = 4,
1839 };
1840 
1841 static struct qcom_icc_node qns_pcie_mem_noc = {
1842 	.name = "qns_pcie_mem_noc",
1843 	.id = SA8775P_SLAVE_ANOC_PCIE_GEM_NOC,
1844 	.channels = 1,
1845 	.buswidth = 32,
1846 	.num_links = 1,
1847 	.links = { SA8775P_MASTER_ANOC_PCIE_GEM_NOC },
1848 };
1849 
1850 static struct qcom_icc_node qns_gemnoc_gc = {
1851 	.name = "qns_gemnoc_gc",
1852 	.id = SA8775P_SLAVE_SNOC_GEM_NOC_GC,
1853 	.channels = 1,
1854 	.buswidth = 8,
1855 	.num_links = 1,
1856 	.links = { SA8775P_MASTER_SNOC_GC_MEM_NOC },
1857 };
1858 
1859 static struct qcom_icc_node qns_gemnoc_sf = {
1860 	.name = "qns_gemnoc_sf",
1861 	.id = SA8775P_SLAVE_SNOC_GEM_NOC_SF,
1862 	.channels = 1,
1863 	.buswidth = 16,
1864 	.num_links = 1,
1865 	.links = { SA8775P_MASTER_SNOC_SF_MEM_NOC },
1866 };
1867 
1868 static struct qcom_icc_node srvc_snoc = {
1869 	.name = "srvc_snoc",
1870 	.id = SA8775P_SLAVE_SERVICE_SNOC,
1871 	.channels = 1,
1872 	.buswidth = 4,
1873 };
1874 
1875 static struct qcom_icc_bcm bcm_acv = {
1876 	.name = "ACV",
1877 	.enable_mask = 0x8,
1878 	.num_nodes = 1,
1879 	.nodes = { &ebi },
1880 };
1881 
1882 static struct qcom_icc_bcm bcm_ce0 = {
1883 	.name = "CE0",
1884 	.num_nodes = 2,
1885 	.nodes = { &qxm_crypto_0, &qxm_crypto_1 },
1886 };
1887 
1888 static struct qcom_icc_bcm bcm_cn0 = {
1889 	.name = "CN0",
1890 	.keepalive = true,
1891 	.num_nodes = 2,
1892 	.nodes = { &qnm_gemnoc_cnoc, &qnm_gemnoc_pcie },
1893 };
1894 
1895 static struct qcom_icc_bcm bcm_cn1 = {
1896 	.name = "CN1",
1897 	.num_nodes = 76,
1898 	.nodes = { &qhs_ahb2phy0, &qhs_ahb2phy1,
1899 		   &qhs_ahb2phy2, &qhs_ahb2phy3,
1900 		   &qhs_anoc_throttle_cfg, &qhs_aoss,
1901 		   &qhs_apss, &qhs_boot_rom,
1902 		   &qhs_camera_cfg, &qhs_camera_nrt_throttle_cfg,
1903 		   &qhs_camera_rt_throttle_cfg, &qhs_clk_ctl,
1904 		   &qhs_compute0_cfg, &qhs_compute1_cfg,
1905 		   &qhs_cpr_cx, &qhs_cpr_mmcx,
1906 		   &qhs_cpr_mx, &qhs_cpr_nspcx,
1907 		   &qhs_crypto0_cfg, &qhs_cx_rdpm,
1908 		   &qhs_display0_cfg, &qhs_display0_rt_throttle_cfg,
1909 		   &qhs_display1_cfg, &qhs_display1_rt_throttle_cfg,
1910 		   &qhs_emac0_cfg, &qhs_emac1_cfg,
1911 		   &qhs_gp_dsp0_cfg, &qhs_gp_dsp1_cfg,
1912 		   &qhs_gpdsp0_throttle_cfg, &qhs_gpdsp1_throttle_cfg,
1913 		   &qhs_gpu_tcu_throttle_cfg, &qhs_gpuss_cfg,
1914 		   &qhs_hwkm, &qhs_imem_cfg,
1915 		   &qhs_ipa, &qhs_ipc_router,
1916 		   &qhs_lpass_cfg, &qhs_lpass_throttle_cfg,
1917 		   &qhs_mx_rdpm, &qhs_mxc_rdpm,
1918 		   &qhs_pcie0_cfg, &qhs_pcie1_cfg,
1919 		   &qhs_pcie_rsc_cfg, &qhs_pcie_tcu_throttle_cfg,
1920 		   &qhs_pcie_throttle_cfg, &qhs_pdm,
1921 		   &qhs_pimem_cfg, &qhs_pke_wrapper_cfg,
1922 		   &qhs_qdss_cfg, &qhs_qm_cfg,
1923 		   &qhs_qm_mpu_cfg, &qhs_sail_throttle_cfg,
1924 		   &qhs_sdc1, &qhs_security,
1925 		   &qhs_snoc_throttle_cfg, &qhs_tcsr,
1926 		   &qhs_tlmm, &qhs_tsc_cfg,
1927 		   &qhs_ufs_card_cfg, &qhs_ufs_mem_cfg,
1928 		   &qhs_usb2_0, &qhs_usb3_0,
1929 		   &qhs_usb3_1, &qhs_venus_cfg,
1930 		   &qhs_venus_cvp_throttle_cfg, &qhs_venus_v_cpu_throttle_cfg,
1931 		   &qhs_venus_vcodec_throttle_cfg, &qns_ddrss_cfg,
1932 		   &qns_gpdsp_noc_cfg, &qns_mnoc_hf_cfg,
1933 		   &qns_mnoc_sf_cfg, &qns_pcie_anoc_cfg,
1934 		   &qns_snoc_cfg, &qxs_boot_imem,
1935 		   &qxs_imem, &xs_sys_tcu_cfg },
1936 };
1937 
1938 static struct qcom_icc_bcm bcm_cn2 = {
1939 	.name = "CN2",
1940 	.num_nodes = 4,
1941 	.nodes = { &qhs_qup0, &qhs_qup1,
1942 		   &qhs_qup2, &qhs_qup3 },
1943 };
1944 
1945 static struct qcom_icc_bcm bcm_cn3 = {
1946 	.name = "CN3",
1947 	.num_nodes = 2,
1948 	.nodes = { &xs_pcie_0, &xs_pcie_1 },
1949 };
1950 
1951 static struct qcom_icc_bcm bcm_gna0 = {
1952 	.name = "GNA0",
1953 	.num_nodes = 1,
1954 	.nodes = { &qxm_dsp0 },
1955 };
1956 
1957 static struct qcom_icc_bcm bcm_gnb0 = {
1958 	.name = "GNB0",
1959 	.num_nodes = 1,
1960 	.nodes = { &qxm_dsp1 },
1961 };
1962 
1963 static struct qcom_icc_bcm bcm_mc0 = {
1964 	.name = "MC0",
1965 	.keepalive = true,
1966 	.num_nodes = 1,
1967 	.nodes = { &ebi },
1968 };
1969 
1970 static struct qcom_icc_bcm bcm_mm0 = {
1971 	.name = "MM0",
1972 	.keepalive = true,
1973 	.num_nodes = 5,
1974 	.nodes = { &qnm_camnoc_hf, &qnm_mdp0_0,
1975 		   &qnm_mdp0_1, &qnm_mdp1_0,
1976 		   &qns_mem_noc_hf },
1977 };
1978 
1979 static struct qcom_icc_bcm bcm_mm1 = {
1980 	.name = "MM1",
1981 	.num_nodes = 7,
1982 	.nodes = { &qnm_camnoc_icp, &qnm_camnoc_sf,
1983 		   &qnm_video0, &qnm_video1,
1984 		   &qnm_video_cvp, &qnm_video_v_cpu,
1985 		   &qns_mem_noc_sf },
1986 };
1987 
1988 static struct qcom_icc_bcm bcm_nsa0 = {
1989 	.name = "NSA0",
1990 	.num_nodes = 2,
1991 	.nodes = { &qns_hcp, &qns_nsp_gemnoc },
1992 };
1993 
1994 static struct qcom_icc_bcm bcm_nsa1 = {
1995 	.name = "NSA1",
1996 	.num_nodes = 1,
1997 	.nodes = { &qxm_nsp },
1998 };
1999 
2000 static struct qcom_icc_bcm bcm_nsb0 = {
2001 	.name = "NSB0",
2002 	.num_nodes = 2,
2003 	.nodes = { &qns_nspb_gemnoc, &qns_nspb_hcp },
2004 };
2005 
2006 static struct qcom_icc_bcm bcm_nsb1 = {
2007 	.name = "NSB1",
2008 	.num_nodes = 1,
2009 	.nodes = { &qxm_nspb },
2010 };
2011 
2012 static struct qcom_icc_bcm bcm_pci0 = {
2013 	.name = "PCI0",
2014 	.num_nodes = 1,
2015 	.nodes = { &qns_pcie_mem_noc },
2016 };
2017 
2018 static struct qcom_icc_bcm bcm_qup0 = {
2019 	.name = "QUP0",
2020 	.vote_scale = 1,
2021 	.num_nodes = 1,
2022 	.nodes = { &qup0_core_slave },
2023 };
2024 
2025 static struct qcom_icc_bcm bcm_qup1 = {
2026 	.name = "QUP1",
2027 	.vote_scale = 1,
2028 	.num_nodes = 1,
2029 	.nodes = { &qup1_core_slave },
2030 };
2031 
2032 static struct qcom_icc_bcm bcm_qup2 = {
2033 	.name = "QUP2",
2034 	.vote_scale = 1,
2035 	.num_nodes = 2,
2036 	.nodes = { &qup2_core_slave, &qup3_core_slave },
2037 };
2038 
2039 static struct qcom_icc_bcm bcm_sh0 = {
2040 	.name = "SH0",
2041 	.keepalive = true,
2042 	.num_nodes = 1,
2043 	.nodes = { &qns_llcc },
2044 };
2045 
2046 static struct qcom_icc_bcm bcm_sh2 = {
2047 	.name = "SH2",
2048 	.num_nodes = 1,
2049 	.nodes = { &chm_apps },
2050 };
2051 
2052 static struct qcom_icc_bcm bcm_sn0 = {
2053 	.name = "SN0",
2054 	.keepalive = true,
2055 	.num_nodes = 1,
2056 	.nodes = { &qns_gemnoc_sf },
2057 };
2058 
2059 static struct qcom_icc_bcm bcm_sn1 = {
2060 	.name = "SN1",
2061 	.num_nodes = 1,
2062 	.nodes = { &qns_gemnoc_gc },
2063 };
2064 
2065 static struct qcom_icc_bcm bcm_sn2 = {
2066 	.name = "SN2",
2067 	.num_nodes = 1,
2068 	.nodes = { &qxs_pimem },
2069 };
2070 
2071 static struct qcom_icc_bcm bcm_sn3 = {
2072 	.name = "SN3",
2073 	.num_nodes = 2,
2074 	.nodes = { &qns_a1noc_snoc, &qnm_aggre1_noc },
2075 };
2076 
2077 static struct qcom_icc_bcm bcm_sn4 = {
2078 	.name = "SN4",
2079 	.num_nodes = 2,
2080 	.nodes = { &qns_a2noc_snoc, &qnm_aggre2_noc },
2081 };
2082 
2083 static struct qcom_icc_bcm bcm_sn9 = {
2084 	.name = "SN9",
2085 	.num_nodes = 2,
2086 	.nodes = { &qns_sysnoc, &qnm_lpass_noc },
2087 };
2088 
2089 static struct qcom_icc_bcm bcm_sn10 = {
2090 	.name = "SN10",
2091 	.num_nodes = 1,
2092 	.nodes = { &xs_qdss_stm },
2093 };
2094 
2095 static struct qcom_icc_bcm *aggre1_noc_bcms[] = {
2096 	&bcm_sn3,
2097 };
2098 
2099 static struct qcom_icc_node *aggre1_noc_nodes[] = {
2100 	[MASTER_QUP_3] = &qxm_qup3,
2101 	[MASTER_EMAC] = &xm_emac_0,
2102 	[MASTER_EMAC_1] = &xm_emac_1,
2103 	[MASTER_SDC] = &xm_sdc1,
2104 	[MASTER_UFS_MEM] = &xm_ufs_mem,
2105 	[MASTER_USB2] = &xm_usb2_2,
2106 	[MASTER_USB3_0] = &xm_usb3_0,
2107 	[MASTER_USB3_1] = &xm_usb3_1,
2108 	[SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
2109 };
2110 
2111 static const struct qcom_icc_desc sa8775p_aggre1_noc = {
2112 	.nodes = aggre1_noc_nodes,
2113 	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),
2114 	.bcms = aggre1_noc_bcms,
2115 	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),
2116 };
2117 
2118 static struct qcom_icc_bcm *aggre2_noc_bcms[] = {
2119 	&bcm_ce0,
2120 	&bcm_sn4,
2121 };
2122 
2123 static struct qcom_icc_node *aggre2_noc_nodes[] = {
2124 	[MASTER_QDSS_BAM] = &qhm_qdss_bam,
2125 	[MASTER_QUP_0] = &qhm_qup0,
2126 	[MASTER_QUP_1] = &qhm_qup1,
2127 	[MASTER_QUP_2] = &qhm_qup2,
2128 	[MASTER_CNOC_A2NOC] = &qnm_cnoc_datapath,
2129 	[MASTER_CRYPTO_CORE0] = &qxm_crypto_0,
2130 	[MASTER_CRYPTO_CORE1] = &qxm_crypto_1,
2131 	[MASTER_IPA] = &qxm_ipa,
2132 	[MASTER_QDSS_ETR_0] = &xm_qdss_etr_0,
2133 	[MASTER_QDSS_ETR_1] = &xm_qdss_etr_1,
2134 	[MASTER_UFS_CARD] = &xm_ufs_card,
2135 	[SLAVE_A2NOC_SNOC] = &qns_a2noc_snoc,
2136 };
2137 
2138 static const struct qcom_icc_desc sa8775p_aggre2_noc = {
2139 	.nodes = aggre2_noc_nodes,
2140 	.num_nodes = ARRAY_SIZE(aggre2_noc_nodes),
2141 	.bcms = aggre2_noc_bcms,
2142 	.num_bcms = ARRAY_SIZE(aggre2_noc_bcms),
2143 };
2144 
2145 static struct qcom_icc_bcm *clk_virt_bcms[] = {
2146 	&bcm_qup0,
2147 	&bcm_qup1,
2148 	&bcm_qup2,
2149 };
2150 
2151 static struct qcom_icc_node *clk_virt_nodes[] = {
2152 	[MASTER_QUP_CORE_0] = &qup0_core_master,
2153 	[MASTER_QUP_CORE_1] = &qup1_core_master,
2154 	[MASTER_QUP_CORE_2] = &qup2_core_master,
2155 	[MASTER_QUP_CORE_3] = &qup3_core_master,
2156 	[SLAVE_QUP_CORE_0] = &qup0_core_slave,
2157 	[SLAVE_QUP_CORE_1] = &qup1_core_slave,
2158 	[SLAVE_QUP_CORE_2] = &qup2_core_slave,
2159 	[SLAVE_QUP_CORE_3] = &qup3_core_slave,
2160 };
2161 
2162 static const struct qcom_icc_desc sa8775p_clk_virt = {
2163 	.nodes = clk_virt_nodes,
2164 	.num_nodes = ARRAY_SIZE(clk_virt_nodes),
2165 	.bcms = clk_virt_bcms,
2166 	.num_bcms = ARRAY_SIZE(clk_virt_bcms),
2167 };
2168 
2169 static struct qcom_icc_bcm *config_noc_bcms[] = {
2170 	&bcm_cn0,
2171 	&bcm_cn1,
2172 	&bcm_cn2,
2173 	&bcm_cn3,
2174 	&bcm_sn2,
2175 	&bcm_sn10,
2176 };
2177 
2178 static struct qcom_icc_node *config_noc_nodes[] = {
2179 	[MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
2180 	[MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
2181 	[SLAVE_AHB2PHY_0] = &qhs_ahb2phy0,
2182 	[SLAVE_AHB2PHY_1] = &qhs_ahb2phy1,
2183 	[SLAVE_AHB2PHY_2] = &qhs_ahb2phy2,
2184 	[SLAVE_AHB2PHY_3] = &qhs_ahb2phy3,
2185 	[SLAVE_ANOC_THROTTLE_CFG] = &qhs_anoc_throttle_cfg,
2186 	[SLAVE_AOSS] = &qhs_aoss,
2187 	[SLAVE_APPSS] = &qhs_apss,
2188 	[SLAVE_BOOT_ROM] = &qhs_boot_rom,
2189 	[SLAVE_CAMERA_CFG] = &qhs_camera_cfg,
2190 	[SLAVE_CAMERA_NRT_THROTTLE_CFG] = &qhs_camera_nrt_throttle_cfg,
2191 	[SLAVE_CAMERA_RT_THROTTLE_CFG] = &qhs_camera_rt_throttle_cfg,
2192 	[SLAVE_CLK_CTL] = &qhs_clk_ctl,
2193 	[SLAVE_CDSP_CFG] = &qhs_compute0_cfg,
2194 	[SLAVE_CDSP1_CFG] = &qhs_compute1_cfg,
2195 	[SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
2196 	[SLAVE_RBCPR_MMCX_CFG] = &qhs_cpr_mmcx,
2197 	[SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
2198 	[SLAVE_CPR_NSPCX] = &qhs_cpr_nspcx,
2199 	[SLAVE_CRYPTO_0_CFG] = &qhs_crypto0_cfg,
2200 	[SLAVE_CX_RDPM] = &qhs_cx_rdpm,
2201 	[SLAVE_DISPLAY_CFG] = &qhs_display0_cfg,
2202 	[SLAVE_DISPLAY_RT_THROTTLE_CFG] = &qhs_display0_rt_throttle_cfg,
2203 	[SLAVE_DISPLAY1_CFG] = &qhs_display1_cfg,
2204 	[SLAVE_DISPLAY1_RT_THROTTLE_CFG] = &qhs_display1_rt_throttle_cfg,
2205 	[SLAVE_EMAC_CFG] = &qhs_emac0_cfg,
2206 	[SLAVE_EMAC1_CFG] = &qhs_emac1_cfg,
2207 	[SLAVE_GP_DSP0_CFG] = &qhs_gp_dsp0_cfg,
2208 	[SLAVE_GP_DSP1_CFG] = &qhs_gp_dsp1_cfg,
2209 	[SLAVE_GPDSP0_THROTTLE_CFG] = &qhs_gpdsp0_throttle_cfg,
2210 	[SLAVE_GPDSP1_THROTTLE_CFG] = &qhs_gpdsp1_throttle_cfg,
2211 	[SLAVE_GPU_TCU_THROTTLE_CFG] = &qhs_gpu_tcu_throttle_cfg,
2212 	[SLAVE_GFX3D_CFG] = &qhs_gpuss_cfg,
2213 	[SLAVE_HWKM] = &qhs_hwkm,
2214 	[SLAVE_IMEM_CFG] = &qhs_imem_cfg,
2215 	[SLAVE_IPA_CFG] = &qhs_ipa,
2216 	[SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
2217 	[SLAVE_LPASS] = &qhs_lpass_cfg,
2218 	[SLAVE_LPASS_THROTTLE_CFG] = &qhs_lpass_throttle_cfg,
2219 	[SLAVE_MX_RDPM] = &qhs_mx_rdpm,
2220 	[SLAVE_MXC_RDPM] = &qhs_mxc_rdpm,
2221 	[SLAVE_PCIE_0_CFG] = &qhs_pcie0_cfg,
2222 	[SLAVE_PCIE_1_CFG] = &qhs_pcie1_cfg,
2223 	[SLAVE_PCIE_RSC_CFG] = &qhs_pcie_rsc_cfg,
2224 	[SLAVE_PCIE_TCU_THROTTLE_CFG] = &qhs_pcie_tcu_throttle_cfg,
2225 	[SLAVE_PCIE_THROTTLE_CFG] = &qhs_pcie_throttle_cfg,
2226 	[SLAVE_PDM] = &qhs_pdm,
2227 	[SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
2228 	[SLAVE_PKA_WRAPPER_CFG] = &qhs_pke_wrapper_cfg,
2229 	[SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
2230 	[SLAVE_QM_CFG] = &qhs_qm_cfg,
2231 	[SLAVE_QM_MPU_CFG] = &qhs_qm_mpu_cfg,
2232 	[SLAVE_QUP_0] = &qhs_qup0,
2233 	[SLAVE_QUP_1] = &qhs_qup1,
2234 	[SLAVE_QUP_2] = &qhs_qup2,
2235 	[SLAVE_QUP_3] = &qhs_qup3,
2236 	[SLAVE_SAIL_THROTTLE_CFG] = &qhs_sail_throttle_cfg,
2237 	[SLAVE_SDC1] = &qhs_sdc1,
2238 	[SLAVE_SECURITY] = &qhs_security,
2239 	[SLAVE_SNOC_THROTTLE_CFG] = &qhs_snoc_throttle_cfg,
2240 	[SLAVE_TCSR] = &qhs_tcsr,
2241 	[SLAVE_TLMM] = &qhs_tlmm,
2242 	[SLAVE_TSC_CFG] = &qhs_tsc_cfg,
2243 	[SLAVE_UFS_CARD_CFG] = &qhs_ufs_card_cfg,
2244 	[SLAVE_UFS_MEM_CFG] = &qhs_ufs_mem_cfg,
2245 	[SLAVE_USB2] = &qhs_usb2_0,
2246 	[SLAVE_USB3_0] = &qhs_usb3_0,
2247 	[SLAVE_USB3_1] = &qhs_usb3_1,
2248 	[SLAVE_VENUS_CFG] = &qhs_venus_cfg,
2249 	[SLAVE_VENUS_CVP_THROTTLE_CFG] = &qhs_venus_cvp_throttle_cfg,
2250 	[SLAVE_VENUS_V_CPU_THROTTLE_CFG] = &qhs_venus_v_cpu_throttle_cfg,
2251 	[SLAVE_VENUS_VCODEC_THROTTLE_CFG] = &qhs_venus_vcodec_throttle_cfg,
2252 	[SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
2253 	[SLAVE_GPDSP_NOC_CFG] = &qns_gpdsp_noc_cfg,
2254 	[SLAVE_CNOC_MNOC_HF_CFG] = &qns_mnoc_hf_cfg,
2255 	[SLAVE_CNOC_MNOC_SF_CFG] = &qns_mnoc_sf_cfg,
2256 	[SLAVE_PCIE_ANOC_CFG] = &qns_pcie_anoc_cfg,
2257 	[SLAVE_SNOC_CFG] = &qns_snoc_cfg,
2258 	[SLAVE_BOOT_IMEM] = &qxs_boot_imem,
2259 	[SLAVE_IMEM] = &qxs_imem,
2260 	[SLAVE_PIMEM] = &qxs_pimem,
2261 	[SLAVE_PCIE_0] = &xs_pcie_0,
2262 	[SLAVE_PCIE_1] = &xs_pcie_1,
2263 	[SLAVE_QDSS_STM] = &xs_qdss_stm,
2264 	[SLAVE_TCU] = &xs_sys_tcu_cfg,
2265 };
2266 
2267 static const struct qcom_icc_desc sa8775p_config_noc = {
2268 	.nodes = config_noc_nodes,
2269 	.num_nodes = ARRAY_SIZE(config_noc_nodes),
2270 	.bcms = config_noc_bcms,
2271 	.num_bcms = ARRAY_SIZE(config_noc_bcms),
2272 };
2273 
2274 static struct qcom_icc_bcm *dc_noc_bcms[] = {
2275 };
2276 
2277 static struct qcom_icc_node *dc_noc_nodes[] = {
2278 	[MASTER_CNOC_DC_NOC] = &qnm_cnoc_dc_noc,
2279 	[SLAVE_LLCC_CFG] = &qhs_llcc,
2280 	[SLAVE_GEM_NOC_CFG] = &qns_gemnoc,
2281 };
2282 
2283 static const struct qcom_icc_desc sa8775p_dc_noc = {
2284 	.nodes = dc_noc_nodes,
2285 	.num_nodes = ARRAY_SIZE(dc_noc_nodes),
2286 	.bcms = dc_noc_bcms,
2287 	.num_bcms = ARRAY_SIZE(dc_noc_bcms),
2288 };
2289 
2290 static struct qcom_icc_bcm *gem_noc_bcms[] = {
2291 	&bcm_sh0,
2292 	&bcm_sh2,
2293 };
2294 
2295 static struct qcom_icc_node *gem_noc_nodes[] = {
2296 	[MASTER_GPU_TCU] = &alm_gpu_tcu,
2297 	[MASTER_PCIE_TCU] = &alm_pcie_tcu,
2298 	[MASTER_SYS_TCU] = &alm_sys_tcu,
2299 	[MASTER_APPSS_PROC] = &chm_apps,
2300 	[MASTER_COMPUTE_NOC] = &qnm_cmpnoc0,
2301 	[MASTER_COMPUTE_NOC_1] = &qnm_cmpnoc1,
2302 	[MASTER_GEM_NOC_CFG] = &qnm_gemnoc_cfg,
2303 	[MASTER_GPDSP_SAIL] = &qnm_gpdsp_sail,
2304 	[MASTER_GFX3D] = &qnm_gpu,
2305 	[MASTER_MNOC_HF_MEM_NOC] = &qnm_mnoc_hf,
2306 	[MASTER_MNOC_SF_MEM_NOC] = &qnm_mnoc_sf,
2307 	[MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
2308 	[MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
2309 	[MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
2310 	[SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
2311 	[SLAVE_LLCC] = &qns_llcc,
2312 	[SLAVE_GEM_NOC_PCIE_CNOC] = &qns_pcie,
2313 	[SLAVE_SERVICE_GEM_NOC_1] = &srvc_even_gemnoc,
2314 	[SLAVE_SERVICE_GEM_NOC_2] = &srvc_odd_gemnoc,
2315 	[SLAVE_SERVICE_GEM_NOC] = &srvc_sys_gemnoc,
2316 	[SLAVE_SERVICE_GEM_NOC2] = &srvc_sys_gemnoc_2,
2317 };
2318 
2319 static const struct qcom_icc_desc sa8775p_gem_noc = {
2320 	.nodes = gem_noc_nodes,
2321 	.num_nodes = ARRAY_SIZE(gem_noc_nodes),
2322 	.bcms = gem_noc_bcms,
2323 	.num_bcms = ARRAY_SIZE(gem_noc_bcms),
2324 };
2325 
2326 static struct qcom_icc_bcm *gpdsp_anoc_bcms[] = {
2327 	&bcm_gna0,
2328 	&bcm_gnb0,
2329 };
2330 
2331 static struct qcom_icc_node *gpdsp_anoc_nodes[] = {
2332 	[MASTER_DSP0] = &qxm_dsp0,
2333 	[MASTER_DSP1] = &qxm_dsp1,
2334 	[SLAVE_GP_DSP_SAIL_NOC] = &qns_gp_dsp_sail_noc,
2335 };
2336 
2337 static const struct qcom_icc_desc sa8775p_gpdsp_anoc = {
2338 	.nodes = gpdsp_anoc_nodes,
2339 	.num_nodes = ARRAY_SIZE(gpdsp_anoc_nodes),
2340 	.bcms = gpdsp_anoc_bcms,
2341 	.num_bcms = ARRAY_SIZE(gpdsp_anoc_bcms),
2342 };
2343 
2344 static struct qcom_icc_bcm *lpass_ag_noc_bcms[] = {
2345 	&bcm_sn9,
2346 };
2347 
2348 static struct qcom_icc_node *lpass_ag_noc_nodes[] = {
2349 	[MASTER_CNOC_LPASS_AG_NOC] = &qhm_config_noc,
2350 	[MASTER_LPASS_PROC] = &qxm_lpass_dsp,
2351 	[SLAVE_LPASS_CORE_CFG] = &qhs_lpass_core,
2352 	[SLAVE_LPASS_LPI_CFG] = &qhs_lpass_lpi,
2353 	[SLAVE_LPASS_MPU_CFG] = &qhs_lpass_mpu,
2354 	[SLAVE_LPASS_TOP_CFG] = &qhs_lpass_top,
2355 	[SLAVE_LPASS_SNOC] = &qns_sysnoc,
2356 	[SLAVE_SERVICES_LPASS_AML_NOC] = &srvc_niu_aml_noc,
2357 	[SLAVE_SERVICE_LPASS_AG_NOC] = &srvc_niu_lpass_agnoc,
2358 };
2359 
2360 static const struct qcom_icc_desc sa8775p_lpass_ag_noc = {
2361 	.nodes = lpass_ag_noc_nodes,
2362 	.num_nodes = ARRAY_SIZE(lpass_ag_noc_nodes),
2363 	.bcms = lpass_ag_noc_bcms,
2364 	.num_bcms = ARRAY_SIZE(lpass_ag_noc_bcms),
2365 };
2366 
2367 static struct qcom_icc_bcm *mc_virt_bcms[] = {
2368 	&bcm_acv,
2369 	&bcm_mc0,
2370 };
2371 
2372 static struct qcom_icc_node *mc_virt_nodes[] = {
2373 	[MASTER_LLCC] = &llcc_mc,
2374 	[SLAVE_EBI1] = &ebi,
2375 };
2376 
2377 static const struct qcom_icc_desc sa8775p_mc_virt = {
2378 	.nodes = mc_virt_nodes,
2379 	.num_nodes = ARRAY_SIZE(mc_virt_nodes),
2380 	.bcms = mc_virt_bcms,
2381 	.num_bcms = ARRAY_SIZE(mc_virt_bcms),
2382 };
2383 
2384 static struct qcom_icc_bcm *mmss_noc_bcms[] = {
2385 	&bcm_mm0,
2386 	&bcm_mm1,
2387 };
2388 
2389 static struct qcom_icc_node *mmss_noc_nodes[] = {
2390 	[MASTER_CAMNOC_HF] = &qnm_camnoc_hf,
2391 	[MASTER_CAMNOC_ICP] = &qnm_camnoc_icp,
2392 	[MASTER_CAMNOC_SF] = &qnm_camnoc_sf,
2393 	[MASTER_MDP0] = &qnm_mdp0_0,
2394 	[MASTER_MDP1] = &qnm_mdp0_1,
2395 	[MASTER_MDP_CORE1_0] = &qnm_mdp1_0,
2396 	[MASTER_MDP_CORE1_1] = &qnm_mdp1_1,
2397 	[MASTER_CNOC_MNOC_HF_CFG] = &qnm_mnoc_hf_cfg,
2398 	[MASTER_CNOC_MNOC_SF_CFG] = &qnm_mnoc_sf_cfg,
2399 	[MASTER_VIDEO_P0] = &qnm_video0,
2400 	[MASTER_VIDEO_P1] = &qnm_video1,
2401 	[MASTER_VIDEO_PROC] = &qnm_video_cvp,
2402 	[MASTER_VIDEO_V_PROC] = &qnm_video_v_cpu,
2403 	[SLAVE_MNOC_HF_MEM_NOC] = &qns_mem_noc_hf,
2404 	[SLAVE_MNOC_SF_MEM_NOC] = &qns_mem_noc_sf,
2405 	[SLAVE_SERVICE_MNOC_HF] = &srvc_mnoc_hf,
2406 	[SLAVE_SERVICE_MNOC_SF] = &srvc_mnoc_sf,
2407 };
2408 
2409 static const struct qcom_icc_desc sa8775p_mmss_noc = {
2410 	.nodes = mmss_noc_nodes,
2411 	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),
2412 	.bcms = mmss_noc_bcms,
2413 	.num_bcms = ARRAY_SIZE(mmss_noc_bcms),
2414 };
2415 
2416 static struct qcom_icc_bcm *nspa_noc_bcms[] = {
2417 	&bcm_nsa0,
2418 	&bcm_nsa1,
2419 };
2420 
2421 static struct qcom_icc_node *nspa_noc_nodes[] = {
2422 	[MASTER_CDSP_NOC_CFG] = &qhm_nsp_noc_config,
2423 	[MASTER_CDSP_PROC] = &qxm_nsp,
2424 	[SLAVE_HCP_A] = &qns_hcp,
2425 	[SLAVE_CDSP_MEM_NOC] = &qns_nsp_gemnoc,
2426 	[SLAVE_SERVICE_NSP_NOC] = &service_nsp_noc,
2427 };
2428 
2429 static const struct qcom_icc_desc sa8775p_nspa_noc = {
2430 	.nodes = nspa_noc_nodes,
2431 	.num_nodes = ARRAY_SIZE(nspa_noc_nodes),
2432 	.bcms = nspa_noc_bcms,
2433 	.num_bcms = ARRAY_SIZE(nspa_noc_bcms),
2434 };
2435 
2436 static struct qcom_icc_bcm *nspb_noc_bcms[] = {
2437 	&bcm_nsb0,
2438 	&bcm_nsb1,
2439 };
2440 
2441 static struct qcom_icc_node *nspb_noc_nodes[] = {
2442 	[MASTER_CDSPB_NOC_CFG] = &qhm_nspb_noc_config,
2443 	[MASTER_CDSP_PROC_B] = &qxm_nspb,
2444 	[SLAVE_CDSPB_MEM_NOC] = &qns_nspb_gemnoc,
2445 	[SLAVE_HCP_B] = &qns_nspb_hcp,
2446 	[SLAVE_SERVICE_NSPB_NOC] = &service_nspb_noc,
2447 };
2448 
2449 static const struct qcom_icc_desc sa8775p_nspb_noc = {
2450 	.nodes = nspb_noc_nodes,
2451 	.num_nodes = ARRAY_SIZE(nspb_noc_nodes),
2452 	.bcms = nspb_noc_bcms,
2453 	.num_bcms = ARRAY_SIZE(nspb_noc_bcms),
2454 };
2455 
2456 static struct qcom_icc_bcm *pcie_anoc_bcms[] = {
2457 	&bcm_pci0,
2458 };
2459 
2460 static struct qcom_icc_node *pcie_anoc_nodes[] = {
2461 	[MASTER_PCIE_0] = &xm_pcie3_0,
2462 	[MASTER_PCIE_1] = &xm_pcie3_1,
2463 	[SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_mem_noc,
2464 };
2465 
2466 static const struct qcom_icc_desc sa8775p_pcie_anoc = {
2467 	.nodes = pcie_anoc_nodes,
2468 	.num_nodes = ARRAY_SIZE(pcie_anoc_nodes),
2469 	.bcms = pcie_anoc_bcms,
2470 	.num_bcms = ARRAY_SIZE(pcie_anoc_bcms),
2471 };
2472 
2473 static struct qcom_icc_bcm *system_noc_bcms[] = {
2474 	&bcm_sn0,
2475 	&bcm_sn1,
2476 	&bcm_sn3,
2477 	&bcm_sn4,
2478 	&bcm_sn9,
2479 };
2480 
2481 static struct qcom_icc_node *system_noc_nodes[] = {
2482 	[MASTER_GIC_AHB] = &qhm_gic,
2483 	[MASTER_A1NOC_SNOC] = &qnm_aggre1_noc,
2484 	[MASTER_A2NOC_SNOC] = &qnm_aggre2_noc,
2485 	[MASTER_LPASS_ANOC] = &qnm_lpass_noc,
2486 	[MASTER_SNOC_CFG] = &qnm_snoc_cfg,
2487 	[MASTER_PIMEM] = &qxm_pimem,
2488 	[MASTER_GIC] = &xm_gic,
2489 	[SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
2490 	[SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
2491 	[SLAVE_SERVICE_SNOC] = &srvc_snoc,
2492 };
2493 
2494 static const struct qcom_icc_desc sa8775p_system_noc = {
2495 	.nodes = system_noc_nodes,
2496 	.num_nodes = ARRAY_SIZE(system_noc_nodes),
2497 	.bcms = system_noc_bcms,
2498 	.num_bcms = ARRAY_SIZE(system_noc_bcms),
2499 };
2500 
2501 static const struct of_device_id qnoc_of_match[] = {
2502 	{ .compatible = "qcom,sa8775p-aggre1-noc", .data = &sa8775p_aggre1_noc, },
2503 	{ .compatible = "qcom,sa8775p-aggre2-noc", .data = &sa8775p_aggre2_noc, },
2504 	{ .compatible = "qcom,sa8775p-clk-virt", .data = &sa8775p_clk_virt, },
2505 	{ .compatible = "qcom,sa8775p-config-noc", .data = &sa8775p_config_noc, },
2506 	{ .compatible = "qcom,sa8775p-dc-noc", .data = &sa8775p_dc_noc, },
2507 	{ .compatible = "qcom,sa8775p-gem-noc", .data = &sa8775p_gem_noc, },
2508 	{ .compatible = "qcom,sa8775p-gpdsp-anoc", .data = &sa8775p_gpdsp_anoc, },
2509 	{ .compatible = "qcom,sa8775p-lpass-ag-noc", .data = &sa8775p_lpass_ag_noc, },
2510 	{ .compatible = "qcom,sa8775p-mc-virt", .data = &sa8775p_mc_virt, },
2511 	{ .compatible = "qcom,sa8775p-mmss-noc", .data = &sa8775p_mmss_noc, },
2512 	{ .compatible = "qcom,sa8775p-nspa-noc", .data = &sa8775p_nspa_noc, },
2513 	{ .compatible = "qcom,sa8775p-nspb-noc", .data = &sa8775p_nspb_noc, },
2514 	{ .compatible = "qcom,sa8775p-pcie-anoc", .data = &sa8775p_pcie_anoc, },
2515 	{ .compatible = "qcom,sa8775p-system-noc", .data = &sa8775p_system_noc, },
2516 	{ }
2517 };
2518 MODULE_DEVICE_TABLE(of, qnoc_of_match);
2519 
2520 static struct platform_driver qnoc_driver = {
2521 	.probe = qcom_icc_rpmh_probe,
2522 	.remove = qcom_icc_rpmh_remove,
2523 	.driver = {
2524 		.name = "qnoc-sa8775p",
2525 		.of_match_table = qnoc_of_match,
2526 		.sync_state = icc_sync_state,
2527 	},
2528 };
2529 
qnoc_driver_init(void)2530 static int __init qnoc_driver_init(void)
2531 {
2532 	return platform_driver_register(&qnoc_driver);
2533 }
2534 core_initcall(qnoc_driver_init);
2535 
qnoc_driver_exit(void)2536 static void __exit qnoc_driver_exit(void)
2537 {
2538 	platform_driver_unregister(&qnoc_driver);
2539 }
2540 module_exit(qnoc_driver_exit);
2541 
2542 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. SA8775P NoC driver");
2543 MODULE_LICENSE("GPL");
2544