1 /************************************************************************
2  * s2io.c: A Linux PCI-X Ethernet driver for Neterion 10GbE Server NIC
3  * Copyright(c) 2002-2010 Exar Corp.
4  *
5  * This software may be used and distributed according to the terms of
6  * the GNU General Public License (GPL), incorporated herein by reference.
7  * Drivers based on or derived from this code fall under the GPL and must
8  * retain the authorship, copyright and license notice.  This file is not
9  * a complete program and may only be used when the entire operating
10  * system is licensed under the GPL.
11  * See the file COPYING in this distribution for more information.
12  *
13  * Credits:
14  * Jeff Garzik		: For pointing out the improper error condition
15  *			  check in the s2io_xmit routine and also some
16  *			  issues in the Tx watch dog function. Also for
17  *			  patiently answering all those innumerable
18  *			  questions regaring the 2.6 porting issues.
19  * Stephen Hemminger	: Providing proper 2.6 porting mechanism for some
20  *			  macros available only in 2.6 Kernel.
21  * Francois Romieu	: For pointing out all code part that were
22  *			  deprecated and also styling related comments.
23  * Grant Grundler	: For helping me get rid of some Architecture
24  *			  dependent code.
25  * Christopher Hellwig	: Some more 2.6 specific issues in the driver.
26  *
27  * The module loadable parameters that are supported by the driver and a brief
28  * explanation of all the variables.
29  *
30  * rx_ring_num : This can be used to program the number of receive rings used
31  * in the driver.
32  * rx_ring_sz: This defines the number of receive blocks each ring can have.
33  *     This is also an array of size 8.
34  * rx_ring_mode: This defines the operation mode of all 8 rings. The valid
35  *		values are 1, 2.
36  * tx_fifo_num: This defines the number of Tx FIFOs thats used int the driver.
37  * tx_fifo_len: This too is an array of 8. Each element defines the number of
38  * Tx descriptors that can be associated with each corresponding FIFO.
39  * intr_type: This defines the type of interrupt. The values can be 0(INTA),
40  *     2(MSI_X). Default value is '2(MSI_X)'
41  * lro_max_pkts: This parameter defines maximum number of packets can be
42  *     aggregated as a single large packet
43  * napi: This parameter used to enable/disable NAPI (polling Rx)
44  *     Possible values '1' for enable and '0' for disable. Default is '1'
45  * vlan_tag_strip: This can be used to enable or disable vlan stripping.
46  *                 Possible values '1' for enable , '0' for disable.
47  *                 Default is '2' - which means disable in promisc mode
48  *                 and enable in non-promiscuous mode.
49  * multiq: This parameter used to enable/disable MULTIQUEUE support.
50  *      Possible values '1' for enable and '0' for disable. Default is '0'
51  ************************************************************************/
52 
53 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
54 
55 #include <linux/module.h>
56 #include <linux/types.h>
57 #include <linux/errno.h>
58 #include <linux/ioport.h>
59 #include <linux/pci.h>
60 #include <linux/dma-mapping.h>
61 #include <linux/kernel.h>
62 #include <linux/netdevice.h>
63 #include <linux/etherdevice.h>
64 #include <linux/mdio.h>
65 #include <linux/skbuff.h>
66 #include <linux/init.h>
67 #include <linux/delay.h>
68 #include <linux/stddef.h>
69 #include <linux/ioctl.h>
70 #include <linux/timex.h>
71 #include <linux/ethtool.h>
72 #include <linux/workqueue.h>
73 #include <linux/if_vlan.h>
74 #include <linux/ip.h>
75 #include <linux/tcp.h>
76 #include <linux/uaccess.h>
77 #include <linux/io.h>
78 #include <linux/io-64-nonatomic-lo-hi.h>
79 #include <linux/slab.h>
80 #include <linux/prefetch.h>
81 #include <net/tcp.h>
82 #include <net/checksum.h>
83 
84 #include <asm/div64.h>
85 #include <asm/irq.h>
86 
87 /* local include */
88 #include "s2io.h"
89 #include "s2io-regs.h"
90 
91 #define DRV_VERSION "2.0.26.28"
92 
93 /* S2io Driver name & version. */
94 static const char s2io_driver_name[] = "Neterion";
95 static const char s2io_driver_version[] = DRV_VERSION;
96 
97 static const int rxd_size[2] = {32, 48};
98 static const int rxd_count[2] = {127, 85};
99 
RXD_IS_UP2DT(struct RxD_t * rxdp)100 static inline int RXD_IS_UP2DT(struct RxD_t *rxdp)
101 {
102 	int ret;
103 
104 	ret = ((!(rxdp->Control_1 & RXD_OWN_XENA)) &&
105 	       (GET_RXD_MARKER(rxdp->Control_2) != THE_RXD_MARK));
106 
107 	return ret;
108 }
109 
110 /*
111  * Cards with following subsystem_id have a link state indication
112  * problem, 600B, 600C, 600D, 640B, 640C and 640D.
113  * macro below identifies these cards given the subsystem_id.
114  */
115 #define CARDS_WITH_FAULTY_LINK_INDICATORS(dev_type, subid)		\
116 	(dev_type == XFRAME_I_DEVICE) ?					\
117 	((((subid >= 0x600B) && (subid <= 0x600D)) ||			\
118 	  ((subid >= 0x640B) && (subid <= 0x640D))) ? 1 : 0) : 0
119 
120 #define LINK_IS_UP(val64) (!(val64 & (ADAPTER_STATUS_RMAC_REMOTE_FAULT | \
121 				      ADAPTER_STATUS_RMAC_LOCAL_FAULT)))
122 
is_s2io_card_up(const struct s2io_nic * sp)123 static inline int is_s2io_card_up(const struct s2io_nic *sp)
124 {
125 	return test_bit(__S2IO_STATE_CARD_UP, &sp->state);
126 }
127 
128 /* Ethtool related variables and Macros. */
129 static const char s2io_gstrings[][ETH_GSTRING_LEN] = {
130 	"Register test\t(offline)",
131 	"Eeprom test\t(offline)",
132 	"Link test\t(online)",
133 	"RLDRAM test\t(offline)",
134 	"BIST Test\t(offline)"
135 };
136 
137 static const char ethtool_xena_stats_keys[][ETH_GSTRING_LEN] = {
138 	{"tmac_frms"},
139 	{"tmac_data_octets"},
140 	{"tmac_drop_frms"},
141 	{"tmac_mcst_frms"},
142 	{"tmac_bcst_frms"},
143 	{"tmac_pause_ctrl_frms"},
144 	{"tmac_ttl_octets"},
145 	{"tmac_ucst_frms"},
146 	{"tmac_nucst_frms"},
147 	{"tmac_any_err_frms"},
148 	{"tmac_ttl_less_fb_octets"},
149 	{"tmac_vld_ip_octets"},
150 	{"tmac_vld_ip"},
151 	{"tmac_drop_ip"},
152 	{"tmac_icmp"},
153 	{"tmac_rst_tcp"},
154 	{"tmac_tcp"},
155 	{"tmac_udp"},
156 	{"rmac_vld_frms"},
157 	{"rmac_data_octets"},
158 	{"rmac_fcs_err_frms"},
159 	{"rmac_drop_frms"},
160 	{"rmac_vld_mcst_frms"},
161 	{"rmac_vld_bcst_frms"},
162 	{"rmac_in_rng_len_err_frms"},
163 	{"rmac_out_rng_len_err_frms"},
164 	{"rmac_long_frms"},
165 	{"rmac_pause_ctrl_frms"},
166 	{"rmac_unsup_ctrl_frms"},
167 	{"rmac_ttl_octets"},
168 	{"rmac_accepted_ucst_frms"},
169 	{"rmac_accepted_nucst_frms"},
170 	{"rmac_discarded_frms"},
171 	{"rmac_drop_events"},
172 	{"rmac_ttl_less_fb_octets"},
173 	{"rmac_ttl_frms"},
174 	{"rmac_usized_frms"},
175 	{"rmac_osized_frms"},
176 	{"rmac_frag_frms"},
177 	{"rmac_jabber_frms"},
178 	{"rmac_ttl_64_frms"},
179 	{"rmac_ttl_65_127_frms"},
180 	{"rmac_ttl_128_255_frms"},
181 	{"rmac_ttl_256_511_frms"},
182 	{"rmac_ttl_512_1023_frms"},
183 	{"rmac_ttl_1024_1518_frms"},
184 	{"rmac_ip"},
185 	{"rmac_ip_octets"},
186 	{"rmac_hdr_err_ip"},
187 	{"rmac_drop_ip"},
188 	{"rmac_icmp"},
189 	{"rmac_tcp"},
190 	{"rmac_udp"},
191 	{"rmac_err_drp_udp"},
192 	{"rmac_xgmii_err_sym"},
193 	{"rmac_frms_q0"},
194 	{"rmac_frms_q1"},
195 	{"rmac_frms_q2"},
196 	{"rmac_frms_q3"},
197 	{"rmac_frms_q4"},
198 	{"rmac_frms_q5"},
199 	{"rmac_frms_q6"},
200 	{"rmac_frms_q7"},
201 	{"rmac_full_q0"},
202 	{"rmac_full_q1"},
203 	{"rmac_full_q2"},
204 	{"rmac_full_q3"},
205 	{"rmac_full_q4"},
206 	{"rmac_full_q5"},
207 	{"rmac_full_q6"},
208 	{"rmac_full_q7"},
209 	{"rmac_pause_cnt"},
210 	{"rmac_xgmii_data_err_cnt"},
211 	{"rmac_xgmii_ctrl_err_cnt"},
212 	{"rmac_accepted_ip"},
213 	{"rmac_err_tcp"},
214 	{"rd_req_cnt"},
215 	{"new_rd_req_cnt"},
216 	{"new_rd_req_rtry_cnt"},
217 	{"rd_rtry_cnt"},
218 	{"wr_rtry_rd_ack_cnt"},
219 	{"wr_req_cnt"},
220 	{"new_wr_req_cnt"},
221 	{"new_wr_req_rtry_cnt"},
222 	{"wr_rtry_cnt"},
223 	{"wr_disc_cnt"},
224 	{"rd_rtry_wr_ack_cnt"},
225 	{"txp_wr_cnt"},
226 	{"txd_rd_cnt"},
227 	{"txd_wr_cnt"},
228 	{"rxd_rd_cnt"},
229 	{"rxd_wr_cnt"},
230 	{"txf_rd_cnt"},
231 	{"rxf_wr_cnt"}
232 };
233 
234 static const char ethtool_enhanced_stats_keys[][ETH_GSTRING_LEN] = {
235 	{"rmac_ttl_1519_4095_frms"},
236 	{"rmac_ttl_4096_8191_frms"},
237 	{"rmac_ttl_8192_max_frms"},
238 	{"rmac_ttl_gt_max_frms"},
239 	{"rmac_osized_alt_frms"},
240 	{"rmac_jabber_alt_frms"},
241 	{"rmac_gt_max_alt_frms"},
242 	{"rmac_vlan_frms"},
243 	{"rmac_len_discard"},
244 	{"rmac_fcs_discard"},
245 	{"rmac_pf_discard"},
246 	{"rmac_da_discard"},
247 	{"rmac_red_discard"},
248 	{"rmac_rts_discard"},
249 	{"rmac_ingm_full_discard"},
250 	{"link_fault_cnt"}
251 };
252 
253 static const char ethtool_driver_stats_keys[][ETH_GSTRING_LEN] = {
254 	{"\n DRIVER STATISTICS"},
255 	{"single_bit_ecc_errs"},
256 	{"double_bit_ecc_errs"},
257 	{"parity_err_cnt"},
258 	{"serious_err_cnt"},
259 	{"soft_reset_cnt"},
260 	{"fifo_full_cnt"},
261 	{"ring_0_full_cnt"},
262 	{"ring_1_full_cnt"},
263 	{"ring_2_full_cnt"},
264 	{"ring_3_full_cnt"},
265 	{"ring_4_full_cnt"},
266 	{"ring_5_full_cnt"},
267 	{"ring_6_full_cnt"},
268 	{"ring_7_full_cnt"},
269 	{"alarm_transceiver_temp_high"},
270 	{"alarm_transceiver_temp_low"},
271 	{"alarm_laser_bias_current_high"},
272 	{"alarm_laser_bias_current_low"},
273 	{"alarm_laser_output_power_high"},
274 	{"alarm_laser_output_power_low"},
275 	{"warn_transceiver_temp_high"},
276 	{"warn_transceiver_temp_low"},
277 	{"warn_laser_bias_current_high"},
278 	{"warn_laser_bias_current_low"},
279 	{"warn_laser_output_power_high"},
280 	{"warn_laser_output_power_low"},
281 	{"lro_aggregated_pkts"},
282 	{"lro_flush_both_count"},
283 	{"lro_out_of_sequence_pkts"},
284 	{"lro_flush_due_to_max_pkts"},
285 	{"lro_avg_aggr_pkts"},
286 	{"mem_alloc_fail_cnt"},
287 	{"pci_map_fail_cnt"},
288 	{"watchdog_timer_cnt"},
289 	{"mem_allocated"},
290 	{"mem_freed"},
291 	{"link_up_cnt"},
292 	{"link_down_cnt"},
293 	{"link_up_time"},
294 	{"link_down_time"},
295 	{"tx_tcode_buf_abort_cnt"},
296 	{"tx_tcode_desc_abort_cnt"},
297 	{"tx_tcode_parity_err_cnt"},
298 	{"tx_tcode_link_loss_cnt"},
299 	{"tx_tcode_list_proc_err_cnt"},
300 	{"rx_tcode_parity_err_cnt"},
301 	{"rx_tcode_abort_cnt"},
302 	{"rx_tcode_parity_abort_cnt"},
303 	{"rx_tcode_rda_fail_cnt"},
304 	{"rx_tcode_unkn_prot_cnt"},
305 	{"rx_tcode_fcs_err_cnt"},
306 	{"rx_tcode_buf_size_err_cnt"},
307 	{"rx_tcode_rxd_corrupt_cnt"},
308 	{"rx_tcode_unkn_err_cnt"},
309 	{"tda_err_cnt"},
310 	{"pfc_err_cnt"},
311 	{"pcc_err_cnt"},
312 	{"tti_err_cnt"},
313 	{"tpa_err_cnt"},
314 	{"sm_err_cnt"},
315 	{"lso_err_cnt"},
316 	{"mac_tmac_err_cnt"},
317 	{"mac_rmac_err_cnt"},
318 	{"xgxs_txgxs_err_cnt"},
319 	{"xgxs_rxgxs_err_cnt"},
320 	{"rc_err_cnt"},
321 	{"prc_pcix_err_cnt"},
322 	{"rpa_err_cnt"},
323 	{"rda_err_cnt"},
324 	{"rti_err_cnt"},
325 	{"mc_err_cnt"}
326 };
327 
328 #define S2IO_XENA_STAT_LEN	ARRAY_SIZE(ethtool_xena_stats_keys)
329 #define S2IO_ENHANCED_STAT_LEN	ARRAY_SIZE(ethtool_enhanced_stats_keys)
330 #define S2IO_DRIVER_STAT_LEN	ARRAY_SIZE(ethtool_driver_stats_keys)
331 
332 #define XFRAME_I_STAT_LEN (S2IO_XENA_STAT_LEN + S2IO_DRIVER_STAT_LEN)
333 #define XFRAME_II_STAT_LEN (XFRAME_I_STAT_LEN + S2IO_ENHANCED_STAT_LEN)
334 
335 #define XFRAME_I_STAT_STRINGS_LEN (XFRAME_I_STAT_LEN * ETH_GSTRING_LEN)
336 #define XFRAME_II_STAT_STRINGS_LEN (XFRAME_II_STAT_LEN * ETH_GSTRING_LEN)
337 
338 #define S2IO_TEST_LEN	ARRAY_SIZE(s2io_gstrings)
339 #define S2IO_STRINGS_LEN	(S2IO_TEST_LEN * ETH_GSTRING_LEN)
340 
341 /* copy mac addr to def_mac_addr array */
do_s2io_copy_mac_addr(struct s2io_nic * sp,int offset,u64 mac_addr)342 static void do_s2io_copy_mac_addr(struct s2io_nic *sp, int offset, u64 mac_addr)
343 {
344 	sp->def_mac_addr[offset].mac_addr[5] = (u8) (mac_addr);
345 	sp->def_mac_addr[offset].mac_addr[4] = (u8) (mac_addr >> 8);
346 	sp->def_mac_addr[offset].mac_addr[3] = (u8) (mac_addr >> 16);
347 	sp->def_mac_addr[offset].mac_addr[2] = (u8) (mac_addr >> 24);
348 	sp->def_mac_addr[offset].mac_addr[1] = (u8) (mac_addr >> 32);
349 	sp->def_mac_addr[offset].mac_addr[0] = (u8) (mac_addr >> 40);
350 }
351 
352 /*
353  * Constants to be programmed into the Xena's registers, to configure
354  * the XAUI.
355  */
356 
357 #define	END_SIGN	0x0
358 static const u64 herc_act_dtx_cfg[] = {
359 	/* Set address */
360 	0x8000051536750000ULL, 0x80000515367500E0ULL,
361 	/* Write data */
362 	0x8000051536750004ULL, 0x80000515367500E4ULL,
363 	/* Set address */
364 	0x80010515003F0000ULL, 0x80010515003F00E0ULL,
365 	/* Write data */
366 	0x80010515003F0004ULL, 0x80010515003F00E4ULL,
367 	/* Set address */
368 	0x801205150D440000ULL, 0x801205150D4400E0ULL,
369 	/* Write data */
370 	0x801205150D440004ULL, 0x801205150D4400E4ULL,
371 	/* Set address */
372 	0x80020515F2100000ULL, 0x80020515F21000E0ULL,
373 	/* Write data */
374 	0x80020515F2100004ULL, 0x80020515F21000E4ULL,
375 	/* Done */
376 	END_SIGN
377 };
378 
379 static const u64 xena_dtx_cfg[] = {
380 	/* Set address */
381 	0x8000051500000000ULL, 0x80000515000000E0ULL,
382 	/* Write data */
383 	0x80000515D9350004ULL, 0x80000515D93500E4ULL,
384 	/* Set address */
385 	0x8001051500000000ULL, 0x80010515000000E0ULL,
386 	/* Write data */
387 	0x80010515001E0004ULL, 0x80010515001E00E4ULL,
388 	/* Set address */
389 	0x8002051500000000ULL, 0x80020515000000E0ULL,
390 	/* Write data */
391 	0x80020515F2100004ULL, 0x80020515F21000E4ULL,
392 	END_SIGN
393 };
394 
395 /*
396  * Constants for Fixing the MacAddress problem seen mostly on
397  * Alpha machines.
398  */
399 static const u64 fix_mac[] = {
400 	0x0060000000000000ULL, 0x0060600000000000ULL,
401 	0x0040600000000000ULL, 0x0000600000000000ULL,
402 	0x0020600000000000ULL, 0x0060600000000000ULL,
403 	0x0020600000000000ULL, 0x0060600000000000ULL,
404 	0x0020600000000000ULL, 0x0060600000000000ULL,
405 	0x0020600000000000ULL, 0x0060600000000000ULL,
406 	0x0020600000000000ULL, 0x0060600000000000ULL,
407 	0x0020600000000000ULL, 0x0060600000000000ULL,
408 	0x0020600000000000ULL, 0x0060600000000000ULL,
409 	0x0020600000000000ULL, 0x0060600000000000ULL,
410 	0x0020600000000000ULL, 0x0060600000000000ULL,
411 	0x0020600000000000ULL, 0x0060600000000000ULL,
412 	0x0020600000000000ULL, 0x0000600000000000ULL,
413 	0x0040600000000000ULL, 0x0060600000000000ULL,
414 	END_SIGN
415 };
416 
417 MODULE_LICENSE("GPL");
418 MODULE_VERSION(DRV_VERSION);
419 
420 
421 /* Module Loadable parameters. */
422 S2IO_PARM_INT(tx_fifo_num, FIFO_DEFAULT_NUM);
423 S2IO_PARM_INT(rx_ring_num, 1);
424 S2IO_PARM_INT(multiq, 0);
425 S2IO_PARM_INT(rx_ring_mode, 1);
426 S2IO_PARM_INT(use_continuous_tx_intrs, 1);
427 S2IO_PARM_INT(rmac_pause_time, 0x100);
428 S2IO_PARM_INT(mc_pause_threshold_q0q3, 187);
429 S2IO_PARM_INT(mc_pause_threshold_q4q7, 187);
430 S2IO_PARM_INT(shared_splits, 0);
431 S2IO_PARM_INT(tmac_util_period, 5);
432 S2IO_PARM_INT(rmac_util_period, 5);
433 S2IO_PARM_INT(l3l4hdr_size, 128);
434 /* 0 is no steering, 1 is Priority steering, 2 is Default steering */
435 S2IO_PARM_INT(tx_steering_type, TX_DEFAULT_STEERING);
436 /* Frequency of Rx desc syncs expressed as power of 2 */
437 S2IO_PARM_INT(rxsync_frequency, 3);
438 /* Interrupt type. Values can be 0(INTA), 2(MSI_X) */
439 S2IO_PARM_INT(intr_type, 2);
440 /* Large receive offload feature */
441 
442 /* Max pkts to be aggregated by LRO at one time. If not specified,
443  * aggregation happens until we hit max IP pkt size(64K)
444  */
445 S2IO_PARM_INT(lro_max_pkts, 0xFFFF);
446 S2IO_PARM_INT(indicate_max_pkts, 0);
447 
448 S2IO_PARM_INT(napi, 1);
449 S2IO_PARM_INT(vlan_tag_strip, NO_STRIP_IN_PROMISC);
450 
451 static unsigned int tx_fifo_len[MAX_TX_FIFOS] =
452 {DEFAULT_FIFO_0_LEN, [1 ...(MAX_TX_FIFOS - 1)] = DEFAULT_FIFO_1_7_LEN};
453 static unsigned int rx_ring_sz[MAX_RX_RINGS] =
454 {[0 ...(MAX_RX_RINGS - 1)] = SMALL_BLK_CNT};
455 static unsigned int rts_frm_len[MAX_RX_RINGS] =
456 {[0 ...(MAX_RX_RINGS - 1)] = 0 };
457 
458 module_param_array(tx_fifo_len, uint, NULL, 0);
459 module_param_array(rx_ring_sz, uint, NULL, 0);
460 module_param_array(rts_frm_len, uint, NULL, 0);
461 
462 /*
463  * S2IO device table.
464  * This table lists all the devices that this driver supports.
465  */
466 static const struct pci_device_id s2io_tbl[] = {
467 	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_WIN,
468 	 PCI_ANY_ID, PCI_ANY_ID},
469 	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_S2IO_UNI,
470 	 PCI_ANY_ID, PCI_ANY_ID},
471 	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_WIN,
472 	 PCI_ANY_ID, PCI_ANY_ID},
473 	{PCI_VENDOR_ID_S2IO, PCI_DEVICE_ID_HERC_UNI,
474 	 PCI_ANY_ID, PCI_ANY_ID},
475 	{0,}
476 };
477 
478 MODULE_DEVICE_TABLE(pci, s2io_tbl);
479 
480 static const struct pci_error_handlers s2io_err_handler = {
481 	.error_detected = s2io_io_error_detected,
482 	.slot_reset = s2io_io_slot_reset,
483 	.resume = s2io_io_resume,
484 };
485 
486 static struct pci_driver s2io_driver = {
487 	.name = "S2IO",
488 	.id_table = s2io_tbl,
489 	.probe = s2io_init_nic,
490 	.remove = s2io_rem_nic,
491 	.err_handler = &s2io_err_handler,
492 };
493 
494 /* A simplifier macro used both by init and free shared_mem Fns(). */
495 #define TXD_MEM_PAGE_CNT(len, per_each) DIV_ROUND_UP(len, per_each)
496 
497 /* netqueue manipulation helper functions */
s2io_stop_all_tx_queue(struct s2io_nic * sp)498 static inline void s2io_stop_all_tx_queue(struct s2io_nic *sp)
499 {
500 	if (!sp->config.multiq) {
501 		int i;
502 
503 		for (i = 0; i < sp->config.tx_fifo_num; i++)
504 			sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_STOP;
505 	}
506 	netif_tx_stop_all_queues(sp->dev);
507 }
508 
s2io_stop_tx_queue(struct s2io_nic * sp,int fifo_no)509 static inline void s2io_stop_tx_queue(struct s2io_nic *sp, int fifo_no)
510 {
511 	if (!sp->config.multiq)
512 		sp->mac_control.fifos[fifo_no].queue_state =
513 			FIFO_QUEUE_STOP;
514 
515 	netif_tx_stop_all_queues(sp->dev);
516 }
517 
s2io_start_all_tx_queue(struct s2io_nic * sp)518 static inline void s2io_start_all_tx_queue(struct s2io_nic *sp)
519 {
520 	if (!sp->config.multiq) {
521 		int i;
522 
523 		for (i = 0; i < sp->config.tx_fifo_num; i++)
524 			sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
525 	}
526 	netif_tx_start_all_queues(sp->dev);
527 }
528 
s2io_wake_all_tx_queue(struct s2io_nic * sp)529 static inline void s2io_wake_all_tx_queue(struct s2io_nic *sp)
530 {
531 	if (!sp->config.multiq) {
532 		int i;
533 
534 		for (i = 0; i < sp->config.tx_fifo_num; i++)
535 			sp->mac_control.fifos[i].queue_state = FIFO_QUEUE_START;
536 	}
537 	netif_tx_wake_all_queues(sp->dev);
538 }
539 
s2io_wake_tx_queue(struct fifo_info * fifo,int cnt,u8 multiq)540 static inline void s2io_wake_tx_queue(
541 	struct fifo_info *fifo, int cnt, u8 multiq)
542 {
543 
544 	if (multiq) {
545 		if (cnt && __netif_subqueue_stopped(fifo->dev, fifo->fifo_no))
546 			netif_wake_subqueue(fifo->dev, fifo->fifo_no);
547 	} else if (cnt && (fifo->queue_state == FIFO_QUEUE_STOP)) {
548 		if (netif_queue_stopped(fifo->dev)) {
549 			fifo->queue_state = FIFO_QUEUE_START;
550 			netif_wake_queue(fifo->dev);
551 		}
552 	}
553 }
554 
555 /**
556  * init_shared_mem - Allocation and Initialization of Memory
557  * @nic: Device private variable.
558  * Description: The function allocates all the memory areas shared
559  * between the NIC and the driver. This includes Tx descriptors,
560  * Rx descriptors and the statistics block.
561  */
562 
init_shared_mem(struct s2io_nic * nic)563 static int init_shared_mem(struct s2io_nic *nic)
564 {
565 	u32 size;
566 	void *tmp_v_addr, *tmp_v_addr_next;
567 	dma_addr_t tmp_p_addr, tmp_p_addr_next;
568 	struct RxD_block *pre_rxd_blk = NULL;
569 	int i, j, blk_cnt;
570 	int lst_size, lst_per_page;
571 	struct net_device *dev = nic->dev;
572 	unsigned long tmp;
573 	struct buffAdd *ba;
574 	struct config_param *config = &nic->config;
575 	struct mac_info *mac_control = &nic->mac_control;
576 	unsigned long long mem_allocated = 0;
577 
578 	/* Allocation and initialization of TXDLs in FIFOs */
579 	size = 0;
580 	for (i = 0; i < config->tx_fifo_num; i++) {
581 		struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
582 
583 		size += tx_cfg->fifo_len;
584 	}
585 	if (size > MAX_AVAILABLE_TXDS) {
586 		DBG_PRINT(ERR_DBG,
587 			  "Too many TxDs requested: %d, max supported: %d\n",
588 			  size, MAX_AVAILABLE_TXDS);
589 		return -EINVAL;
590 	}
591 
592 	size = 0;
593 	for (i = 0; i < config->tx_fifo_num; i++) {
594 		struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
595 
596 		size = tx_cfg->fifo_len;
597 		/*
598 		 * Legal values are from 2 to 8192
599 		 */
600 		if (size < 2) {
601 			DBG_PRINT(ERR_DBG, "Fifo %d: Invalid length (%d) - "
602 				  "Valid lengths are 2 through 8192\n",
603 				  i, size);
604 			return -EINVAL;
605 		}
606 	}
607 
608 	lst_size = (sizeof(struct TxD) * config->max_txds);
609 	lst_per_page = PAGE_SIZE / lst_size;
610 
611 	for (i = 0; i < config->tx_fifo_num; i++) {
612 		struct fifo_info *fifo = &mac_control->fifos[i];
613 		struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
614 		int fifo_len = tx_cfg->fifo_len;
615 		int list_holder_size = fifo_len * sizeof(struct list_info_hold);
616 
617 		fifo->list_info = kzalloc(list_holder_size, GFP_KERNEL);
618 		if (!fifo->list_info) {
619 			DBG_PRINT(INFO_DBG, "Malloc failed for list_info\n");
620 			return -ENOMEM;
621 		}
622 		mem_allocated += list_holder_size;
623 	}
624 	for (i = 0; i < config->tx_fifo_num; i++) {
625 		int page_num = TXD_MEM_PAGE_CNT(config->tx_cfg[i].fifo_len,
626 						lst_per_page);
627 		struct fifo_info *fifo = &mac_control->fifos[i];
628 		struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
629 
630 		fifo->tx_curr_put_info.offset = 0;
631 		fifo->tx_curr_put_info.fifo_len = tx_cfg->fifo_len - 1;
632 		fifo->tx_curr_get_info.offset = 0;
633 		fifo->tx_curr_get_info.fifo_len = tx_cfg->fifo_len - 1;
634 		fifo->fifo_no = i;
635 		fifo->nic = nic;
636 		fifo->max_txds = MAX_SKB_FRAGS + 2;
637 		fifo->dev = dev;
638 
639 		for (j = 0; j < page_num; j++) {
640 			int k = 0;
641 			dma_addr_t tmp_p;
642 			void *tmp_v;
643 			tmp_v = dma_alloc_coherent(&nic->pdev->dev, PAGE_SIZE,
644 						   &tmp_p, GFP_KERNEL);
645 			if (!tmp_v) {
646 				DBG_PRINT(INFO_DBG,
647 					  "dma_alloc_coherent failed for TxDL\n");
648 				return -ENOMEM;
649 			}
650 			/* If we got a zero DMA address(can happen on
651 			 * certain platforms like PPC), reallocate.
652 			 * Store virtual address of page we don't want,
653 			 * to be freed later.
654 			 */
655 			if (!tmp_p) {
656 				mac_control->zerodma_virt_addr = tmp_v;
657 				DBG_PRINT(INIT_DBG,
658 					  "%s: Zero DMA address for TxDL. "
659 					  "Virtual address %p\n",
660 					  dev->name, tmp_v);
661 				tmp_v = dma_alloc_coherent(&nic->pdev->dev,
662 							   PAGE_SIZE, &tmp_p,
663 							   GFP_KERNEL);
664 				if (!tmp_v) {
665 					DBG_PRINT(INFO_DBG,
666 						  "dma_alloc_coherent failed for TxDL\n");
667 					return -ENOMEM;
668 				}
669 				mem_allocated += PAGE_SIZE;
670 			}
671 			while (k < lst_per_page) {
672 				int l = (j * lst_per_page) + k;
673 				if (l == tx_cfg->fifo_len)
674 					break;
675 				fifo->list_info[l].list_virt_addr =
676 					tmp_v + (k * lst_size);
677 				fifo->list_info[l].list_phy_addr =
678 					tmp_p + (k * lst_size);
679 				k++;
680 			}
681 		}
682 	}
683 
684 	for (i = 0; i < config->tx_fifo_num; i++) {
685 		struct fifo_info *fifo = &mac_control->fifos[i];
686 		struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
687 
688 		size = tx_cfg->fifo_len;
689 		fifo->ufo_in_band_v = kcalloc(size, sizeof(u64), GFP_KERNEL);
690 		if (!fifo->ufo_in_band_v)
691 			return -ENOMEM;
692 		mem_allocated += (size * sizeof(u64));
693 	}
694 
695 	/* Allocation and initialization of RXDs in Rings */
696 	size = 0;
697 	for (i = 0; i < config->rx_ring_num; i++) {
698 		struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
699 		struct ring_info *ring = &mac_control->rings[i];
700 
701 		if (rx_cfg->num_rxd % (rxd_count[nic->rxd_mode] + 1)) {
702 			DBG_PRINT(ERR_DBG, "%s: Ring%d RxD count is not a "
703 				  "multiple of RxDs per Block\n",
704 				  dev->name, i);
705 			return FAILURE;
706 		}
707 		size += rx_cfg->num_rxd;
708 		ring->block_count = rx_cfg->num_rxd /
709 			(rxd_count[nic->rxd_mode] + 1);
710 		ring->pkt_cnt = rx_cfg->num_rxd - ring->block_count;
711 	}
712 	if (nic->rxd_mode == RXD_MODE_1)
713 		size = (size * (sizeof(struct RxD1)));
714 	else
715 		size = (size * (sizeof(struct RxD3)));
716 
717 	for (i = 0; i < config->rx_ring_num; i++) {
718 		struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
719 		struct ring_info *ring = &mac_control->rings[i];
720 
721 		ring->rx_curr_get_info.block_index = 0;
722 		ring->rx_curr_get_info.offset = 0;
723 		ring->rx_curr_get_info.ring_len = rx_cfg->num_rxd - 1;
724 		ring->rx_curr_put_info.block_index = 0;
725 		ring->rx_curr_put_info.offset = 0;
726 		ring->rx_curr_put_info.ring_len = rx_cfg->num_rxd - 1;
727 		ring->nic = nic;
728 		ring->ring_no = i;
729 
730 		blk_cnt = rx_cfg->num_rxd / (rxd_count[nic->rxd_mode] + 1);
731 		/*  Allocating all the Rx blocks */
732 		for (j = 0; j < blk_cnt; j++) {
733 			struct rx_block_info *rx_blocks;
734 			int l;
735 
736 			rx_blocks = &ring->rx_blocks[j];
737 			size = SIZE_OF_BLOCK;	/* size is always page size */
738 			tmp_v_addr = dma_alloc_coherent(&nic->pdev->dev, size,
739 							&tmp_p_addr, GFP_KERNEL);
740 			if (tmp_v_addr == NULL) {
741 				/*
742 				 * In case of failure, free_shared_mem()
743 				 * is called, which should free any
744 				 * memory that was alloced till the
745 				 * failure happened.
746 				 */
747 				rx_blocks->block_virt_addr = tmp_v_addr;
748 				return -ENOMEM;
749 			}
750 			mem_allocated += size;
751 
752 			size = sizeof(struct rxd_info) *
753 				rxd_count[nic->rxd_mode];
754 			rx_blocks->block_virt_addr = tmp_v_addr;
755 			rx_blocks->block_dma_addr = tmp_p_addr;
756 			rx_blocks->rxds = kmalloc(size,  GFP_KERNEL);
757 			if (!rx_blocks->rxds)
758 				return -ENOMEM;
759 			mem_allocated += size;
760 			for (l = 0; l < rxd_count[nic->rxd_mode]; l++) {
761 				rx_blocks->rxds[l].virt_addr =
762 					rx_blocks->block_virt_addr +
763 					(rxd_size[nic->rxd_mode] * l);
764 				rx_blocks->rxds[l].dma_addr =
765 					rx_blocks->block_dma_addr +
766 					(rxd_size[nic->rxd_mode] * l);
767 			}
768 		}
769 		/* Interlinking all Rx Blocks */
770 		for (j = 0; j < blk_cnt; j++) {
771 			int next = (j + 1) % blk_cnt;
772 			tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
773 			tmp_v_addr_next = ring->rx_blocks[next].block_virt_addr;
774 			tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
775 			tmp_p_addr_next = ring->rx_blocks[next].block_dma_addr;
776 
777 			pre_rxd_blk = tmp_v_addr;
778 			pre_rxd_blk->reserved_2_pNext_RxD_block =
779 				(unsigned long)tmp_v_addr_next;
780 			pre_rxd_blk->pNext_RxD_Blk_physical =
781 				(u64)tmp_p_addr_next;
782 		}
783 	}
784 	if (nic->rxd_mode == RXD_MODE_3B) {
785 		/*
786 		 * Allocation of Storages for buffer addresses in 2BUFF mode
787 		 * and the buffers as well.
788 		 */
789 		for (i = 0; i < config->rx_ring_num; i++) {
790 			struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
791 			struct ring_info *ring = &mac_control->rings[i];
792 
793 			blk_cnt = rx_cfg->num_rxd /
794 				(rxd_count[nic->rxd_mode] + 1);
795 			size = sizeof(struct buffAdd *) * blk_cnt;
796 			ring->ba = kmalloc(size, GFP_KERNEL);
797 			if (!ring->ba)
798 				return -ENOMEM;
799 			mem_allocated += size;
800 			for (j = 0; j < blk_cnt; j++) {
801 				int k = 0;
802 
803 				size = sizeof(struct buffAdd) *
804 					(rxd_count[nic->rxd_mode] + 1);
805 				ring->ba[j] = kmalloc(size, GFP_KERNEL);
806 				if (!ring->ba[j])
807 					return -ENOMEM;
808 				mem_allocated += size;
809 				while (k != rxd_count[nic->rxd_mode]) {
810 					ba = &ring->ba[j][k];
811 					size = BUF0_LEN + ALIGN_SIZE;
812 					ba->ba_0_org = kmalloc(size, GFP_KERNEL);
813 					if (!ba->ba_0_org)
814 						return -ENOMEM;
815 					mem_allocated += size;
816 					tmp = (unsigned long)ba->ba_0_org;
817 					tmp += ALIGN_SIZE;
818 					tmp &= ~((unsigned long)ALIGN_SIZE);
819 					ba->ba_0 = (void *)tmp;
820 
821 					size = BUF1_LEN + ALIGN_SIZE;
822 					ba->ba_1_org = kmalloc(size, GFP_KERNEL);
823 					if (!ba->ba_1_org)
824 						return -ENOMEM;
825 					mem_allocated += size;
826 					tmp = (unsigned long)ba->ba_1_org;
827 					tmp += ALIGN_SIZE;
828 					tmp &= ~((unsigned long)ALIGN_SIZE);
829 					ba->ba_1 = (void *)tmp;
830 					k++;
831 				}
832 			}
833 		}
834 	}
835 
836 	/* Allocation and initialization of Statistics block */
837 	size = sizeof(struct stat_block);
838 	mac_control->stats_mem =
839 		dma_alloc_coherent(&nic->pdev->dev, size,
840 				   &mac_control->stats_mem_phy, GFP_KERNEL);
841 
842 	if (!mac_control->stats_mem) {
843 		/*
844 		 * In case of failure, free_shared_mem() is called, which
845 		 * should free any memory that was alloced till the
846 		 * failure happened.
847 		 */
848 		return -ENOMEM;
849 	}
850 	mem_allocated += size;
851 	mac_control->stats_mem_sz = size;
852 
853 	tmp_v_addr = mac_control->stats_mem;
854 	mac_control->stats_info = tmp_v_addr;
855 	memset(tmp_v_addr, 0, size);
856 	DBG_PRINT(INIT_DBG, "%s: Ring Mem PHY: 0x%llx\n",
857 		dev_name(&nic->pdev->dev), (unsigned long long)tmp_p_addr);
858 	mac_control->stats_info->sw_stat.mem_allocated += mem_allocated;
859 	return SUCCESS;
860 }
861 
862 /**
863  * free_shared_mem - Free the allocated Memory
864  * @nic:  Device private variable.
865  * Description: This function is to free all memory locations allocated by
866  * the init_shared_mem() function and return it to the kernel.
867  */
868 
free_shared_mem(struct s2io_nic * nic)869 static void free_shared_mem(struct s2io_nic *nic)
870 {
871 	int i, j, blk_cnt, size;
872 	void *tmp_v_addr;
873 	dma_addr_t tmp_p_addr;
874 	int lst_size, lst_per_page;
875 	struct net_device *dev;
876 	int page_num = 0;
877 	struct config_param *config;
878 	struct mac_info *mac_control;
879 	struct stat_block *stats;
880 	struct swStat *swstats;
881 
882 	if (!nic)
883 		return;
884 
885 	dev = nic->dev;
886 
887 	config = &nic->config;
888 	mac_control = &nic->mac_control;
889 	stats = mac_control->stats_info;
890 	swstats = &stats->sw_stat;
891 
892 	lst_size = sizeof(struct TxD) * config->max_txds;
893 	lst_per_page = PAGE_SIZE / lst_size;
894 
895 	for (i = 0; i < config->tx_fifo_num; i++) {
896 		struct fifo_info *fifo = &mac_control->fifos[i];
897 		struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
898 
899 		page_num = TXD_MEM_PAGE_CNT(tx_cfg->fifo_len, lst_per_page);
900 		for (j = 0; j < page_num; j++) {
901 			int mem_blks = (j * lst_per_page);
902 			struct list_info_hold *fli;
903 
904 			if (!fifo->list_info)
905 				return;
906 
907 			fli = &fifo->list_info[mem_blks];
908 			if (!fli->list_virt_addr)
909 				break;
910 			dma_free_coherent(&nic->pdev->dev, PAGE_SIZE,
911 					  fli->list_virt_addr,
912 					  fli->list_phy_addr);
913 			swstats->mem_freed += PAGE_SIZE;
914 		}
915 		/* If we got a zero DMA address during allocation,
916 		 * free the page now
917 		 */
918 		if (mac_control->zerodma_virt_addr) {
919 			dma_free_coherent(&nic->pdev->dev, PAGE_SIZE,
920 					  mac_control->zerodma_virt_addr,
921 					  (dma_addr_t)0);
922 			DBG_PRINT(INIT_DBG,
923 				  "%s: Freeing TxDL with zero DMA address. "
924 				  "Virtual address %p\n",
925 				  dev->name, mac_control->zerodma_virt_addr);
926 			swstats->mem_freed += PAGE_SIZE;
927 		}
928 		kfree(fifo->list_info);
929 		swstats->mem_freed += tx_cfg->fifo_len *
930 			sizeof(struct list_info_hold);
931 	}
932 
933 	size = SIZE_OF_BLOCK;
934 	for (i = 0; i < config->rx_ring_num; i++) {
935 		struct ring_info *ring = &mac_control->rings[i];
936 
937 		blk_cnt = ring->block_count;
938 		for (j = 0; j < blk_cnt; j++) {
939 			tmp_v_addr = ring->rx_blocks[j].block_virt_addr;
940 			tmp_p_addr = ring->rx_blocks[j].block_dma_addr;
941 			if (tmp_v_addr == NULL)
942 				break;
943 			dma_free_coherent(&nic->pdev->dev, size, tmp_v_addr,
944 					  tmp_p_addr);
945 			swstats->mem_freed += size;
946 			kfree(ring->rx_blocks[j].rxds);
947 			swstats->mem_freed += sizeof(struct rxd_info) *
948 				rxd_count[nic->rxd_mode];
949 		}
950 	}
951 
952 	if (nic->rxd_mode == RXD_MODE_3B) {
953 		/* Freeing buffer storage addresses in 2BUFF mode. */
954 		for (i = 0; i < config->rx_ring_num; i++) {
955 			struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
956 			struct ring_info *ring = &mac_control->rings[i];
957 
958 			blk_cnt = rx_cfg->num_rxd /
959 				(rxd_count[nic->rxd_mode] + 1);
960 			for (j = 0; j < blk_cnt; j++) {
961 				int k = 0;
962 				if (!ring->ba[j])
963 					continue;
964 				while (k != rxd_count[nic->rxd_mode]) {
965 					struct buffAdd *ba = &ring->ba[j][k];
966 					kfree(ba->ba_0_org);
967 					swstats->mem_freed +=
968 						BUF0_LEN + ALIGN_SIZE;
969 					kfree(ba->ba_1_org);
970 					swstats->mem_freed +=
971 						BUF1_LEN + ALIGN_SIZE;
972 					k++;
973 				}
974 				kfree(ring->ba[j]);
975 				swstats->mem_freed += sizeof(struct buffAdd) *
976 					(rxd_count[nic->rxd_mode] + 1);
977 			}
978 			kfree(ring->ba);
979 			swstats->mem_freed += sizeof(struct buffAdd *) *
980 				blk_cnt;
981 		}
982 	}
983 
984 	for (i = 0; i < nic->config.tx_fifo_num; i++) {
985 		struct fifo_info *fifo = &mac_control->fifos[i];
986 		struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
987 
988 		if (fifo->ufo_in_band_v) {
989 			swstats->mem_freed += tx_cfg->fifo_len *
990 				sizeof(u64);
991 			kfree(fifo->ufo_in_band_v);
992 		}
993 	}
994 
995 	if (mac_control->stats_mem) {
996 		swstats->mem_freed += mac_control->stats_mem_sz;
997 		dma_free_coherent(&nic->pdev->dev, mac_control->stats_mem_sz,
998 				  mac_control->stats_mem,
999 				  mac_control->stats_mem_phy);
1000 	}
1001 }
1002 
1003 /*
1004  * s2io_verify_pci_mode -
1005  */
1006 
s2io_verify_pci_mode(struct s2io_nic * nic)1007 static int s2io_verify_pci_mode(struct s2io_nic *nic)
1008 {
1009 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
1010 	register u64 val64 = 0;
1011 	int     mode;
1012 
1013 	val64 = readq(&bar0->pci_mode);
1014 	mode = (u8)GET_PCI_MODE(val64);
1015 
1016 	if (val64 & PCI_MODE_UNKNOWN_MODE)
1017 		return -1;      /* Unknown PCI mode */
1018 	return mode;
1019 }
1020 
1021 #define NEC_VENID   0x1033
1022 #define NEC_DEVID   0x0125
s2io_on_nec_bridge(struct pci_dev * s2io_pdev)1023 static int s2io_on_nec_bridge(struct pci_dev *s2io_pdev)
1024 {
1025 	struct pci_dev *tdev = NULL;
1026 	for_each_pci_dev(tdev) {
1027 		if (tdev->vendor == NEC_VENID && tdev->device == NEC_DEVID) {
1028 			if (tdev->bus == s2io_pdev->bus->parent) {
1029 				pci_dev_put(tdev);
1030 				return 1;
1031 			}
1032 		}
1033 	}
1034 	return 0;
1035 }
1036 
1037 static int bus_speed[8] = {33, 133, 133, 200, 266, 133, 200, 266};
1038 /*
1039  * s2io_print_pci_mode -
1040  */
s2io_print_pci_mode(struct s2io_nic * nic)1041 static int s2io_print_pci_mode(struct s2io_nic *nic)
1042 {
1043 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
1044 	register u64 val64 = 0;
1045 	int	mode;
1046 	struct config_param *config = &nic->config;
1047 	const char *pcimode;
1048 
1049 	val64 = readq(&bar0->pci_mode);
1050 	mode = (u8)GET_PCI_MODE(val64);
1051 
1052 	if (val64 & PCI_MODE_UNKNOWN_MODE)
1053 		return -1;	/* Unknown PCI mode */
1054 
1055 	config->bus_speed = bus_speed[mode];
1056 
1057 	if (s2io_on_nec_bridge(nic->pdev)) {
1058 		DBG_PRINT(ERR_DBG, "%s: Device is on PCI-E bus\n",
1059 			  nic->dev->name);
1060 		return mode;
1061 	}
1062 
1063 	switch (mode) {
1064 	case PCI_MODE_PCI_33:
1065 		pcimode = "33MHz PCI bus";
1066 		break;
1067 	case PCI_MODE_PCI_66:
1068 		pcimode = "66MHz PCI bus";
1069 		break;
1070 	case PCI_MODE_PCIX_M1_66:
1071 		pcimode = "66MHz PCIX(M1) bus";
1072 		break;
1073 	case PCI_MODE_PCIX_M1_100:
1074 		pcimode = "100MHz PCIX(M1) bus";
1075 		break;
1076 	case PCI_MODE_PCIX_M1_133:
1077 		pcimode = "133MHz PCIX(M1) bus";
1078 		break;
1079 	case PCI_MODE_PCIX_M2_66:
1080 		pcimode = "133MHz PCIX(M2) bus";
1081 		break;
1082 	case PCI_MODE_PCIX_M2_100:
1083 		pcimode = "200MHz PCIX(M2) bus";
1084 		break;
1085 	case PCI_MODE_PCIX_M2_133:
1086 		pcimode = "266MHz PCIX(M2) bus";
1087 		break;
1088 	default:
1089 		pcimode = "unsupported bus!";
1090 		mode = -1;
1091 	}
1092 
1093 	DBG_PRINT(ERR_DBG, "%s: Device is on %d bit %s\n",
1094 		  nic->dev->name, val64 & PCI_MODE_32_BITS ? 32 : 64, pcimode);
1095 
1096 	return mode;
1097 }
1098 
1099 /**
1100  *  init_tti - Initialization transmit traffic interrupt scheme
1101  *  @nic: device private variable
1102  *  @link: link status (UP/DOWN) used to enable/disable continuous
1103  *  transmit interrupts
1104  *  @may_sleep: parameter indicates if sleeping when waiting for
1105  *  command complete
1106  *  Description: The function configures transmit traffic interrupts
1107  *  Return Value:  SUCCESS on success and
1108  *  '-1' on failure
1109  */
1110 
init_tti(struct s2io_nic * nic,int link,bool may_sleep)1111 static int init_tti(struct s2io_nic *nic, int link, bool may_sleep)
1112 {
1113 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
1114 	register u64 val64 = 0;
1115 	int i;
1116 	struct config_param *config = &nic->config;
1117 
1118 	for (i = 0; i < config->tx_fifo_num; i++) {
1119 		/*
1120 		 * TTI Initialization. Default Tx timer gets us about
1121 		 * 250 interrupts per sec. Continuous interrupts are enabled
1122 		 * by default.
1123 		 */
1124 		if (nic->device_type == XFRAME_II_DEVICE) {
1125 			int count = (nic->config.bus_speed * 125)/2;
1126 			val64 = TTI_DATA1_MEM_TX_TIMER_VAL(count);
1127 		} else
1128 			val64 = TTI_DATA1_MEM_TX_TIMER_VAL(0x2078);
1129 
1130 		val64 |= TTI_DATA1_MEM_TX_URNG_A(0xA) |
1131 			TTI_DATA1_MEM_TX_URNG_B(0x10) |
1132 			TTI_DATA1_MEM_TX_URNG_C(0x30) |
1133 			TTI_DATA1_MEM_TX_TIMER_AC_EN;
1134 		if (i == 0)
1135 			if (use_continuous_tx_intrs && (link == LINK_UP))
1136 				val64 |= TTI_DATA1_MEM_TX_TIMER_CI_EN;
1137 		writeq(val64, &bar0->tti_data1_mem);
1138 
1139 		if (nic->config.intr_type == MSI_X) {
1140 			val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1141 				TTI_DATA2_MEM_TX_UFC_B(0x100) |
1142 				TTI_DATA2_MEM_TX_UFC_C(0x200) |
1143 				TTI_DATA2_MEM_TX_UFC_D(0x300);
1144 		} else {
1145 			if ((nic->config.tx_steering_type ==
1146 			     TX_DEFAULT_STEERING) &&
1147 			    (config->tx_fifo_num > 1) &&
1148 			    (i >= nic->udp_fifo_idx) &&
1149 			    (i < (nic->udp_fifo_idx +
1150 				  nic->total_udp_fifos)))
1151 				val64 = TTI_DATA2_MEM_TX_UFC_A(0x50) |
1152 					TTI_DATA2_MEM_TX_UFC_B(0x80) |
1153 					TTI_DATA2_MEM_TX_UFC_C(0x100) |
1154 					TTI_DATA2_MEM_TX_UFC_D(0x120);
1155 			else
1156 				val64 = TTI_DATA2_MEM_TX_UFC_A(0x10) |
1157 					TTI_DATA2_MEM_TX_UFC_B(0x20) |
1158 					TTI_DATA2_MEM_TX_UFC_C(0x40) |
1159 					TTI_DATA2_MEM_TX_UFC_D(0x80);
1160 		}
1161 
1162 		writeq(val64, &bar0->tti_data2_mem);
1163 
1164 		val64 = TTI_CMD_MEM_WE |
1165 			TTI_CMD_MEM_STROBE_NEW_CMD |
1166 			TTI_CMD_MEM_OFFSET(i);
1167 		writeq(val64, &bar0->tti_command_mem);
1168 
1169 		if (wait_for_cmd_complete(&bar0->tti_command_mem,
1170 					  TTI_CMD_MEM_STROBE_NEW_CMD,
1171 					  S2IO_BIT_RESET, may_sleep) != SUCCESS)
1172 			return FAILURE;
1173 	}
1174 
1175 	return SUCCESS;
1176 }
1177 
1178 /**
1179  *  init_nic - Initialization of hardware
1180  *  @nic: device private variable
1181  *  Description: The function sequentially configures every block
1182  *  of the H/W from their reset values.
1183  *  Return Value:  SUCCESS on success and
1184  *  '-1' on failure (endian settings incorrect).
1185  */
1186 
init_nic(struct s2io_nic * nic)1187 static int init_nic(struct s2io_nic *nic)
1188 {
1189 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
1190 	struct net_device *dev = nic->dev;
1191 	register u64 val64 = 0;
1192 	void __iomem *add;
1193 	u32 time;
1194 	int i, j;
1195 	int dtx_cnt = 0;
1196 	unsigned long long mem_share;
1197 	int mem_size;
1198 	struct config_param *config = &nic->config;
1199 	struct mac_info *mac_control = &nic->mac_control;
1200 
1201 	/* to set the swapper controle on the card */
1202 	if (s2io_set_swapper(nic)) {
1203 		DBG_PRINT(ERR_DBG, "ERROR: Setting Swapper failed\n");
1204 		return -EIO;
1205 	}
1206 
1207 	/*
1208 	 * Herc requires EOI to be removed from reset before XGXS, so..
1209 	 */
1210 	if (nic->device_type & XFRAME_II_DEVICE) {
1211 		val64 = 0xA500000000ULL;
1212 		writeq(val64, &bar0->sw_reset);
1213 		msleep(500);
1214 		val64 = readq(&bar0->sw_reset);
1215 	}
1216 
1217 	/* Remove XGXS from reset state */
1218 	val64 = 0;
1219 	writeq(val64, &bar0->sw_reset);
1220 	msleep(500);
1221 	val64 = readq(&bar0->sw_reset);
1222 
1223 	/* Ensure that it's safe to access registers by checking
1224 	 * RIC_RUNNING bit is reset. Check is valid only for XframeII.
1225 	 */
1226 	if (nic->device_type == XFRAME_II_DEVICE) {
1227 		for (i = 0; i < 50; i++) {
1228 			val64 = readq(&bar0->adapter_status);
1229 			if (!(val64 & ADAPTER_STATUS_RIC_RUNNING))
1230 				break;
1231 			msleep(10);
1232 		}
1233 		if (i == 50)
1234 			return -ENODEV;
1235 	}
1236 
1237 	/*  Enable Receiving broadcasts */
1238 	add = &bar0->mac_cfg;
1239 	val64 = readq(&bar0->mac_cfg);
1240 	val64 |= MAC_RMAC_BCAST_ENABLE;
1241 	writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1242 	writel((u32)val64, add);
1243 	writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1244 	writel((u32) (val64 >> 32), (add + 4));
1245 
1246 	/* Read registers in all blocks */
1247 	val64 = readq(&bar0->mac_int_mask);
1248 	val64 = readq(&bar0->mc_int_mask);
1249 	val64 = readq(&bar0->xgxs_int_mask);
1250 
1251 	/*  Set MTU */
1252 	val64 = dev->mtu;
1253 	writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
1254 
1255 	if (nic->device_type & XFRAME_II_DEVICE) {
1256 		while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
1257 			SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
1258 					  &bar0->dtx_control, UF);
1259 			if (dtx_cnt & 0x1)
1260 				msleep(1); /* Necessary!! */
1261 			dtx_cnt++;
1262 		}
1263 	} else {
1264 		while (xena_dtx_cfg[dtx_cnt] != END_SIGN) {
1265 			SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
1266 					  &bar0->dtx_control, UF);
1267 			val64 = readq(&bar0->dtx_control);
1268 			dtx_cnt++;
1269 		}
1270 	}
1271 
1272 	/*  Tx DMA Initialization */
1273 	val64 = 0;
1274 	writeq(val64, &bar0->tx_fifo_partition_0);
1275 	writeq(val64, &bar0->tx_fifo_partition_1);
1276 	writeq(val64, &bar0->tx_fifo_partition_2);
1277 	writeq(val64, &bar0->tx_fifo_partition_3);
1278 
1279 	for (i = 0, j = 0; i < config->tx_fifo_num; i++) {
1280 		struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
1281 
1282 		val64 |= vBIT(tx_cfg->fifo_len - 1, ((j * 32) + 19), 13) |
1283 			vBIT(tx_cfg->fifo_priority, ((j * 32) + 5), 3);
1284 
1285 		if (i == (config->tx_fifo_num - 1)) {
1286 			if (i % 2 == 0)
1287 				i++;
1288 		}
1289 
1290 		switch (i) {
1291 		case 1:
1292 			writeq(val64, &bar0->tx_fifo_partition_0);
1293 			val64 = 0;
1294 			j = 0;
1295 			break;
1296 		case 3:
1297 			writeq(val64, &bar0->tx_fifo_partition_1);
1298 			val64 = 0;
1299 			j = 0;
1300 			break;
1301 		case 5:
1302 			writeq(val64, &bar0->tx_fifo_partition_2);
1303 			val64 = 0;
1304 			j = 0;
1305 			break;
1306 		case 7:
1307 			writeq(val64, &bar0->tx_fifo_partition_3);
1308 			val64 = 0;
1309 			j = 0;
1310 			break;
1311 		default:
1312 			j++;
1313 			break;
1314 		}
1315 	}
1316 
1317 	/*
1318 	 * Disable 4 PCCs for Xena1, 2 and 3 as per H/W bug
1319 	 * SXE-008 TRANSMIT DMA ARBITRATION ISSUE.
1320 	 */
1321 	if ((nic->device_type == XFRAME_I_DEVICE) && (nic->pdev->revision < 4))
1322 		writeq(PCC_ENABLE_FOUR, &bar0->pcc_enable);
1323 
1324 	val64 = readq(&bar0->tx_fifo_partition_0);
1325 	DBG_PRINT(INIT_DBG, "Fifo partition at: 0x%p is: 0x%llx\n",
1326 		  &bar0->tx_fifo_partition_0, (unsigned long long)val64);
1327 
1328 	/*
1329 	 * Initialization of Tx_PA_CONFIG register to ignore packet
1330 	 * integrity checking.
1331 	 */
1332 	val64 = readq(&bar0->tx_pa_cfg);
1333 	val64 |= TX_PA_CFG_IGNORE_FRM_ERR |
1334 		TX_PA_CFG_IGNORE_SNAP_OUI |
1335 		TX_PA_CFG_IGNORE_LLC_CTRL |
1336 		TX_PA_CFG_IGNORE_L2_ERR;
1337 	writeq(val64, &bar0->tx_pa_cfg);
1338 
1339 	/* Rx DMA initialization. */
1340 	val64 = 0;
1341 	for (i = 0; i < config->rx_ring_num; i++) {
1342 		struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
1343 
1344 		val64 |= vBIT(rx_cfg->ring_priority, (5 + (i * 8)), 3);
1345 	}
1346 	writeq(val64, &bar0->rx_queue_priority);
1347 
1348 	/*
1349 	 * Allocating equal share of memory to all the
1350 	 * configured Rings.
1351 	 */
1352 	val64 = 0;
1353 	if (nic->device_type & XFRAME_II_DEVICE)
1354 		mem_size = 32;
1355 	else
1356 		mem_size = 64;
1357 
1358 	for (i = 0; i < config->rx_ring_num; i++) {
1359 		switch (i) {
1360 		case 0:
1361 			mem_share = (mem_size / config->rx_ring_num +
1362 				     mem_size % config->rx_ring_num);
1363 			val64 |= RX_QUEUE_CFG_Q0_SZ(mem_share);
1364 			continue;
1365 		case 1:
1366 			mem_share = (mem_size / config->rx_ring_num);
1367 			val64 |= RX_QUEUE_CFG_Q1_SZ(mem_share);
1368 			continue;
1369 		case 2:
1370 			mem_share = (mem_size / config->rx_ring_num);
1371 			val64 |= RX_QUEUE_CFG_Q2_SZ(mem_share);
1372 			continue;
1373 		case 3:
1374 			mem_share = (mem_size / config->rx_ring_num);
1375 			val64 |= RX_QUEUE_CFG_Q3_SZ(mem_share);
1376 			continue;
1377 		case 4:
1378 			mem_share = (mem_size / config->rx_ring_num);
1379 			val64 |= RX_QUEUE_CFG_Q4_SZ(mem_share);
1380 			continue;
1381 		case 5:
1382 			mem_share = (mem_size / config->rx_ring_num);
1383 			val64 |= RX_QUEUE_CFG_Q5_SZ(mem_share);
1384 			continue;
1385 		case 6:
1386 			mem_share = (mem_size / config->rx_ring_num);
1387 			val64 |= RX_QUEUE_CFG_Q6_SZ(mem_share);
1388 			continue;
1389 		case 7:
1390 			mem_share = (mem_size / config->rx_ring_num);
1391 			val64 |= RX_QUEUE_CFG_Q7_SZ(mem_share);
1392 			continue;
1393 		}
1394 	}
1395 	writeq(val64, &bar0->rx_queue_cfg);
1396 
1397 	/*
1398 	 * Filling Tx round robin registers
1399 	 * as per the number of FIFOs for equal scheduling priority
1400 	 */
1401 	switch (config->tx_fifo_num) {
1402 	case 1:
1403 		val64 = 0x0;
1404 		writeq(val64, &bar0->tx_w_round_robin_0);
1405 		writeq(val64, &bar0->tx_w_round_robin_1);
1406 		writeq(val64, &bar0->tx_w_round_robin_2);
1407 		writeq(val64, &bar0->tx_w_round_robin_3);
1408 		writeq(val64, &bar0->tx_w_round_robin_4);
1409 		break;
1410 	case 2:
1411 		val64 = 0x0001000100010001ULL;
1412 		writeq(val64, &bar0->tx_w_round_robin_0);
1413 		writeq(val64, &bar0->tx_w_round_robin_1);
1414 		writeq(val64, &bar0->tx_w_round_robin_2);
1415 		writeq(val64, &bar0->tx_w_round_robin_3);
1416 		val64 = 0x0001000100000000ULL;
1417 		writeq(val64, &bar0->tx_w_round_robin_4);
1418 		break;
1419 	case 3:
1420 		val64 = 0x0001020001020001ULL;
1421 		writeq(val64, &bar0->tx_w_round_robin_0);
1422 		val64 = 0x0200010200010200ULL;
1423 		writeq(val64, &bar0->tx_w_round_robin_1);
1424 		val64 = 0x0102000102000102ULL;
1425 		writeq(val64, &bar0->tx_w_round_robin_2);
1426 		val64 = 0x0001020001020001ULL;
1427 		writeq(val64, &bar0->tx_w_round_robin_3);
1428 		val64 = 0x0200010200000000ULL;
1429 		writeq(val64, &bar0->tx_w_round_robin_4);
1430 		break;
1431 	case 4:
1432 		val64 = 0x0001020300010203ULL;
1433 		writeq(val64, &bar0->tx_w_round_robin_0);
1434 		writeq(val64, &bar0->tx_w_round_robin_1);
1435 		writeq(val64, &bar0->tx_w_round_robin_2);
1436 		writeq(val64, &bar0->tx_w_round_robin_3);
1437 		val64 = 0x0001020300000000ULL;
1438 		writeq(val64, &bar0->tx_w_round_robin_4);
1439 		break;
1440 	case 5:
1441 		val64 = 0x0001020304000102ULL;
1442 		writeq(val64, &bar0->tx_w_round_robin_0);
1443 		val64 = 0x0304000102030400ULL;
1444 		writeq(val64, &bar0->tx_w_round_robin_1);
1445 		val64 = 0x0102030400010203ULL;
1446 		writeq(val64, &bar0->tx_w_round_robin_2);
1447 		val64 = 0x0400010203040001ULL;
1448 		writeq(val64, &bar0->tx_w_round_robin_3);
1449 		val64 = 0x0203040000000000ULL;
1450 		writeq(val64, &bar0->tx_w_round_robin_4);
1451 		break;
1452 	case 6:
1453 		val64 = 0x0001020304050001ULL;
1454 		writeq(val64, &bar0->tx_w_round_robin_0);
1455 		val64 = 0x0203040500010203ULL;
1456 		writeq(val64, &bar0->tx_w_round_robin_1);
1457 		val64 = 0x0405000102030405ULL;
1458 		writeq(val64, &bar0->tx_w_round_robin_2);
1459 		val64 = 0x0001020304050001ULL;
1460 		writeq(val64, &bar0->tx_w_round_robin_3);
1461 		val64 = 0x0203040500000000ULL;
1462 		writeq(val64, &bar0->tx_w_round_robin_4);
1463 		break;
1464 	case 7:
1465 		val64 = 0x0001020304050600ULL;
1466 		writeq(val64, &bar0->tx_w_round_robin_0);
1467 		val64 = 0x0102030405060001ULL;
1468 		writeq(val64, &bar0->tx_w_round_robin_1);
1469 		val64 = 0x0203040506000102ULL;
1470 		writeq(val64, &bar0->tx_w_round_robin_2);
1471 		val64 = 0x0304050600010203ULL;
1472 		writeq(val64, &bar0->tx_w_round_robin_3);
1473 		val64 = 0x0405060000000000ULL;
1474 		writeq(val64, &bar0->tx_w_round_robin_4);
1475 		break;
1476 	case 8:
1477 		val64 = 0x0001020304050607ULL;
1478 		writeq(val64, &bar0->tx_w_round_robin_0);
1479 		writeq(val64, &bar0->tx_w_round_robin_1);
1480 		writeq(val64, &bar0->tx_w_round_robin_2);
1481 		writeq(val64, &bar0->tx_w_round_robin_3);
1482 		val64 = 0x0001020300000000ULL;
1483 		writeq(val64, &bar0->tx_w_round_robin_4);
1484 		break;
1485 	}
1486 
1487 	/* Enable all configured Tx FIFO partitions */
1488 	val64 = readq(&bar0->tx_fifo_partition_0);
1489 	val64 |= (TX_FIFO_PARTITION_EN);
1490 	writeq(val64, &bar0->tx_fifo_partition_0);
1491 
1492 	/* Filling the Rx round robin registers as per the
1493 	 * number of Rings and steering based on QoS with
1494 	 * equal priority.
1495 	 */
1496 	switch (config->rx_ring_num) {
1497 	case 1:
1498 		val64 = 0x0;
1499 		writeq(val64, &bar0->rx_w_round_robin_0);
1500 		writeq(val64, &bar0->rx_w_round_robin_1);
1501 		writeq(val64, &bar0->rx_w_round_robin_2);
1502 		writeq(val64, &bar0->rx_w_round_robin_3);
1503 		writeq(val64, &bar0->rx_w_round_robin_4);
1504 
1505 		val64 = 0x8080808080808080ULL;
1506 		writeq(val64, &bar0->rts_qos_steering);
1507 		break;
1508 	case 2:
1509 		val64 = 0x0001000100010001ULL;
1510 		writeq(val64, &bar0->rx_w_round_robin_0);
1511 		writeq(val64, &bar0->rx_w_round_robin_1);
1512 		writeq(val64, &bar0->rx_w_round_robin_2);
1513 		writeq(val64, &bar0->rx_w_round_robin_3);
1514 		val64 = 0x0001000100000000ULL;
1515 		writeq(val64, &bar0->rx_w_round_robin_4);
1516 
1517 		val64 = 0x8080808040404040ULL;
1518 		writeq(val64, &bar0->rts_qos_steering);
1519 		break;
1520 	case 3:
1521 		val64 = 0x0001020001020001ULL;
1522 		writeq(val64, &bar0->rx_w_round_robin_0);
1523 		val64 = 0x0200010200010200ULL;
1524 		writeq(val64, &bar0->rx_w_round_robin_1);
1525 		val64 = 0x0102000102000102ULL;
1526 		writeq(val64, &bar0->rx_w_round_robin_2);
1527 		val64 = 0x0001020001020001ULL;
1528 		writeq(val64, &bar0->rx_w_round_robin_3);
1529 		val64 = 0x0200010200000000ULL;
1530 		writeq(val64, &bar0->rx_w_round_robin_4);
1531 
1532 		val64 = 0x8080804040402020ULL;
1533 		writeq(val64, &bar0->rts_qos_steering);
1534 		break;
1535 	case 4:
1536 		val64 = 0x0001020300010203ULL;
1537 		writeq(val64, &bar0->rx_w_round_robin_0);
1538 		writeq(val64, &bar0->rx_w_round_robin_1);
1539 		writeq(val64, &bar0->rx_w_round_robin_2);
1540 		writeq(val64, &bar0->rx_w_round_robin_3);
1541 		val64 = 0x0001020300000000ULL;
1542 		writeq(val64, &bar0->rx_w_round_robin_4);
1543 
1544 		val64 = 0x8080404020201010ULL;
1545 		writeq(val64, &bar0->rts_qos_steering);
1546 		break;
1547 	case 5:
1548 		val64 = 0x0001020304000102ULL;
1549 		writeq(val64, &bar0->rx_w_round_robin_0);
1550 		val64 = 0x0304000102030400ULL;
1551 		writeq(val64, &bar0->rx_w_round_robin_1);
1552 		val64 = 0x0102030400010203ULL;
1553 		writeq(val64, &bar0->rx_w_round_robin_2);
1554 		val64 = 0x0400010203040001ULL;
1555 		writeq(val64, &bar0->rx_w_round_robin_3);
1556 		val64 = 0x0203040000000000ULL;
1557 		writeq(val64, &bar0->rx_w_round_robin_4);
1558 
1559 		val64 = 0x8080404020201008ULL;
1560 		writeq(val64, &bar0->rts_qos_steering);
1561 		break;
1562 	case 6:
1563 		val64 = 0x0001020304050001ULL;
1564 		writeq(val64, &bar0->rx_w_round_robin_0);
1565 		val64 = 0x0203040500010203ULL;
1566 		writeq(val64, &bar0->rx_w_round_robin_1);
1567 		val64 = 0x0405000102030405ULL;
1568 		writeq(val64, &bar0->rx_w_round_robin_2);
1569 		val64 = 0x0001020304050001ULL;
1570 		writeq(val64, &bar0->rx_w_round_robin_3);
1571 		val64 = 0x0203040500000000ULL;
1572 		writeq(val64, &bar0->rx_w_round_robin_4);
1573 
1574 		val64 = 0x8080404020100804ULL;
1575 		writeq(val64, &bar0->rts_qos_steering);
1576 		break;
1577 	case 7:
1578 		val64 = 0x0001020304050600ULL;
1579 		writeq(val64, &bar0->rx_w_round_robin_0);
1580 		val64 = 0x0102030405060001ULL;
1581 		writeq(val64, &bar0->rx_w_round_robin_1);
1582 		val64 = 0x0203040506000102ULL;
1583 		writeq(val64, &bar0->rx_w_round_robin_2);
1584 		val64 = 0x0304050600010203ULL;
1585 		writeq(val64, &bar0->rx_w_round_robin_3);
1586 		val64 = 0x0405060000000000ULL;
1587 		writeq(val64, &bar0->rx_w_round_robin_4);
1588 
1589 		val64 = 0x8080402010080402ULL;
1590 		writeq(val64, &bar0->rts_qos_steering);
1591 		break;
1592 	case 8:
1593 		val64 = 0x0001020304050607ULL;
1594 		writeq(val64, &bar0->rx_w_round_robin_0);
1595 		writeq(val64, &bar0->rx_w_round_robin_1);
1596 		writeq(val64, &bar0->rx_w_round_robin_2);
1597 		writeq(val64, &bar0->rx_w_round_robin_3);
1598 		val64 = 0x0001020300000000ULL;
1599 		writeq(val64, &bar0->rx_w_round_robin_4);
1600 
1601 		val64 = 0x8040201008040201ULL;
1602 		writeq(val64, &bar0->rts_qos_steering);
1603 		break;
1604 	}
1605 
1606 	/* UDP Fix */
1607 	val64 = 0;
1608 	for (i = 0; i < 8; i++)
1609 		writeq(val64, &bar0->rts_frm_len_n[i]);
1610 
1611 	/* Set the default rts frame length for the rings configured */
1612 	val64 = MAC_RTS_FRM_LEN_SET(dev->mtu+22);
1613 	for (i = 0 ; i < config->rx_ring_num ; i++)
1614 		writeq(val64, &bar0->rts_frm_len_n[i]);
1615 
1616 	/* Set the frame length for the configured rings
1617 	 * desired by the user
1618 	 */
1619 	for (i = 0; i < config->rx_ring_num; i++) {
1620 		/* If rts_frm_len[i] == 0 then it is assumed that user not
1621 		 * specified frame length steering.
1622 		 * If the user provides the frame length then program
1623 		 * the rts_frm_len register for those values or else
1624 		 * leave it as it is.
1625 		 */
1626 		if (rts_frm_len[i] != 0) {
1627 			writeq(MAC_RTS_FRM_LEN_SET(rts_frm_len[i]),
1628 			       &bar0->rts_frm_len_n[i]);
1629 		}
1630 	}
1631 
1632 	/* Disable differentiated services steering logic */
1633 	for (i = 0; i < 64; i++) {
1634 		if (rts_ds_steer(nic, i, 0) == FAILURE) {
1635 			DBG_PRINT(ERR_DBG,
1636 				  "%s: rts_ds_steer failed on codepoint %d\n",
1637 				  dev->name, i);
1638 			return -ENODEV;
1639 		}
1640 	}
1641 
1642 	/* Program statistics memory */
1643 	writeq(mac_control->stats_mem_phy, &bar0->stat_addr);
1644 
1645 	if (nic->device_type == XFRAME_II_DEVICE) {
1646 		val64 = STAT_BC(0x320);
1647 		writeq(val64, &bar0->stat_byte_cnt);
1648 	}
1649 
1650 	/*
1651 	 * Initializing the sampling rate for the device to calculate the
1652 	 * bandwidth utilization.
1653 	 */
1654 	val64 = MAC_TX_LINK_UTIL_VAL(tmac_util_period) |
1655 		MAC_RX_LINK_UTIL_VAL(rmac_util_period);
1656 	writeq(val64, &bar0->mac_link_util);
1657 
1658 	/*
1659 	 * Initializing the Transmit and Receive Traffic Interrupt
1660 	 * Scheme.
1661 	 */
1662 
1663 	/* Initialize TTI */
1664 	if (SUCCESS != init_tti(nic, nic->last_link_state, true))
1665 		return -ENODEV;
1666 
1667 	/* RTI Initialization */
1668 	if (nic->device_type == XFRAME_II_DEVICE) {
1669 		/*
1670 		 * Programmed to generate Apprx 500 Intrs per
1671 		 * second
1672 		 */
1673 		int count = (nic->config.bus_speed * 125)/4;
1674 		val64 = RTI_DATA1_MEM_RX_TIMER_VAL(count);
1675 	} else
1676 		val64 = RTI_DATA1_MEM_RX_TIMER_VAL(0xFFF);
1677 	val64 |= RTI_DATA1_MEM_RX_URNG_A(0xA) |
1678 		RTI_DATA1_MEM_RX_URNG_B(0x10) |
1679 		RTI_DATA1_MEM_RX_URNG_C(0x30) |
1680 		RTI_DATA1_MEM_RX_TIMER_AC_EN;
1681 
1682 	writeq(val64, &bar0->rti_data1_mem);
1683 
1684 	val64 = RTI_DATA2_MEM_RX_UFC_A(0x1) |
1685 		RTI_DATA2_MEM_RX_UFC_B(0x2) ;
1686 	if (nic->config.intr_type == MSI_X)
1687 		val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x20) |
1688 			  RTI_DATA2_MEM_RX_UFC_D(0x40));
1689 	else
1690 		val64 |= (RTI_DATA2_MEM_RX_UFC_C(0x40) |
1691 			  RTI_DATA2_MEM_RX_UFC_D(0x80));
1692 	writeq(val64, &bar0->rti_data2_mem);
1693 
1694 	for (i = 0; i < config->rx_ring_num; i++) {
1695 		val64 = RTI_CMD_MEM_WE |
1696 			RTI_CMD_MEM_STROBE_NEW_CMD |
1697 			RTI_CMD_MEM_OFFSET(i);
1698 		writeq(val64, &bar0->rti_command_mem);
1699 
1700 		/*
1701 		 * Once the operation completes, the Strobe bit of the
1702 		 * command register will be reset. We poll for this
1703 		 * particular condition. We wait for a maximum of 500ms
1704 		 * for the operation to complete, if it's not complete
1705 		 * by then we return error.
1706 		 */
1707 		time = 0;
1708 		while (true) {
1709 			val64 = readq(&bar0->rti_command_mem);
1710 			if (!(val64 & RTI_CMD_MEM_STROBE_NEW_CMD))
1711 				break;
1712 
1713 			if (time > 10) {
1714 				DBG_PRINT(ERR_DBG, "%s: RTI init failed\n",
1715 					  dev->name);
1716 				return -ENODEV;
1717 			}
1718 			time++;
1719 			msleep(50);
1720 		}
1721 	}
1722 
1723 	/*
1724 	 * Initializing proper values as Pause threshold into all
1725 	 * the 8 Queues on Rx side.
1726 	 */
1727 	writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q0q3);
1728 	writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
1729 
1730 	/* Disable RMAC PAD STRIPPING */
1731 	add = &bar0->mac_cfg;
1732 	val64 = readq(&bar0->mac_cfg);
1733 	val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
1734 	writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1735 	writel((u32) (val64), add);
1736 	writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1737 	writel((u32) (val64 >> 32), (add + 4));
1738 	val64 = readq(&bar0->mac_cfg);
1739 
1740 	/* Enable FCS stripping by adapter */
1741 	add = &bar0->mac_cfg;
1742 	val64 = readq(&bar0->mac_cfg);
1743 	val64 |= MAC_CFG_RMAC_STRIP_FCS;
1744 	if (nic->device_type == XFRAME_II_DEVICE)
1745 		writeq(val64, &bar0->mac_cfg);
1746 	else {
1747 		writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1748 		writel((u32) (val64), add);
1749 		writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
1750 		writel((u32) (val64 >> 32), (add + 4));
1751 	}
1752 
1753 	/*
1754 	 * Set the time value to be inserted in the pause frame
1755 	 * generated by xena.
1756 	 */
1757 	val64 = readq(&bar0->rmac_pause_cfg);
1758 	val64 &= ~(RMAC_PAUSE_HG_PTIME(0xffff));
1759 	val64 |= RMAC_PAUSE_HG_PTIME(nic->mac_control.rmac_pause_time);
1760 	writeq(val64, &bar0->rmac_pause_cfg);
1761 
1762 	/*
1763 	 * Set the Threshold Limit for Generating the pause frame
1764 	 * If the amount of data in any Queue exceeds ratio of
1765 	 * (mac_control.mc_pause_threshold_q0q3 or q4q7)/256
1766 	 * pause frame is generated
1767 	 */
1768 	val64 = 0;
1769 	for (i = 0; i < 4; i++) {
1770 		val64 |= (((u64)0xFF00 |
1771 			   nic->mac_control.mc_pause_threshold_q0q3)
1772 			  << (i * 2 * 8));
1773 	}
1774 	writeq(val64, &bar0->mc_pause_thresh_q0q3);
1775 
1776 	val64 = 0;
1777 	for (i = 0; i < 4; i++) {
1778 		val64 |= (((u64)0xFF00 |
1779 			   nic->mac_control.mc_pause_threshold_q4q7)
1780 			  << (i * 2 * 8));
1781 	}
1782 	writeq(val64, &bar0->mc_pause_thresh_q4q7);
1783 
1784 	/*
1785 	 * TxDMA will stop Read request if the number of read split has
1786 	 * exceeded the limit pointed by shared_splits
1787 	 */
1788 	val64 = readq(&bar0->pic_control);
1789 	val64 |= PIC_CNTL_SHARED_SPLITS(shared_splits);
1790 	writeq(val64, &bar0->pic_control);
1791 
1792 	if (nic->config.bus_speed == 266) {
1793 		writeq(TXREQTO_VAL(0x7f) | TXREQTO_EN, &bar0->txreqtimeout);
1794 		writeq(0x0, &bar0->read_retry_delay);
1795 		writeq(0x0, &bar0->write_retry_delay);
1796 	}
1797 
1798 	/*
1799 	 * Programming the Herc to split every write transaction
1800 	 * that does not start on an ADB to reduce disconnects.
1801 	 */
1802 	if (nic->device_type == XFRAME_II_DEVICE) {
1803 		val64 = FAULT_BEHAVIOUR | EXT_REQ_EN |
1804 			MISC_LINK_STABILITY_PRD(3);
1805 		writeq(val64, &bar0->misc_control);
1806 		val64 = readq(&bar0->pic_control2);
1807 		val64 &= ~(s2BIT(13)|s2BIT(14)|s2BIT(15));
1808 		writeq(val64, &bar0->pic_control2);
1809 	}
1810 	if (strstr(nic->product_name, "CX4")) {
1811 		val64 = TMAC_AVG_IPG(0x17);
1812 		writeq(val64, &bar0->tmac_avg_ipg);
1813 	}
1814 
1815 	return SUCCESS;
1816 }
1817 #define LINK_UP_DOWN_INTERRUPT		1
1818 #define MAC_RMAC_ERR_TIMER		2
1819 
s2io_link_fault_indication(struct s2io_nic * nic)1820 static int s2io_link_fault_indication(struct s2io_nic *nic)
1821 {
1822 	if (nic->device_type == XFRAME_II_DEVICE)
1823 		return LINK_UP_DOWN_INTERRUPT;
1824 	else
1825 		return MAC_RMAC_ERR_TIMER;
1826 }
1827 
1828 /**
1829  *  do_s2io_write_bits -  update alarm bits in alarm register
1830  *  @value: alarm bits
1831  *  @flag: interrupt status
1832  *  @addr: address value
1833  *  Description: update alarm bits in alarm register
1834  *  Return Value:
1835  *  NONE.
1836  */
do_s2io_write_bits(u64 value,int flag,void __iomem * addr)1837 static void do_s2io_write_bits(u64 value, int flag, void __iomem *addr)
1838 {
1839 	u64 temp64;
1840 
1841 	temp64 = readq(addr);
1842 
1843 	if (flag == ENABLE_INTRS)
1844 		temp64 &= ~((u64)value);
1845 	else
1846 		temp64 |= ((u64)value);
1847 	writeq(temp64, addr);
1848 }
1849 
en_dis_err_alarms(struct s2io_nic * nic,u16 mask,int flag)1850 static void en_dis_err_alarms(struct s2io_nic *nic, u16 mask, int flag)
1851 {
1852 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
1853 	register u64 gen_int_mask = 0;
1854 	u64 interruptible;
1855 
1856 	writeq(DISABLE_ALL_INTRS, &bar0->general_int_mask);
1857 	if (mask & TX_DMA_INTR) {
1858 		gen_int_mask |= TXDMA_INT_M;
1859 
1860 		do_s2io_write_bits(TXDMA_TDA_INT | TXDMA_PFC_INT |
1861 				   TXDMA_PCC_INT | TXDMA_TTI_INT |
1862 				   TXDMA_LSO_INT | TXDMA_TPA_INT |
1863 				   TXDMA_SM_INT, flag, &bar0->txdma_int_mask);
1864 
1865 		do_s2io_write_bits(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
1866 				   PFC_MISC_0_ERR | PFC_MISC_1_ERR |
1867 				   PFC_PCIX_ERR | PFC_ECC_SG_ERR, flag,
1868 				   &bar0->pfc_err_mask);
1869 
1870 		do_s2io_write_bits(TDA_Fn_ECC_DB_ERR | TDA_SM0_ERR_ALARM |
1871 				   TDA_SM1_ERR_ALARM | TDA_Fn_ECC_SG_ERR |
1872 				   TDA_PCIX_ERR, flag, &bar0->tda_err_mask);
1873 
1874 		do_s2io_write_bits(PCC_FB_ECC_DB_ERR | PCC_TXB_ECC_DB_ERR |
1875 				   PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
1876 				   PCC_N_SERR | PCC_6_COF_OV_ERR |
1877 				   PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
1878 				   PCC_7_LSO_OV_ERR | PCC_FB_ECC_SG_ERR |
1879 				   PCC_TXB_ECC_SG_ERR,
1880 				   flag, &bar0->pcc_err_mask);
1881 
1882 		do_s2io_write_bits(TTI_SM_ERR_ALARM | TTI_ECC_SG_ERR |
1883 				   TTI_ECC_DB_ERR, flag, &bar0->tti_err_mask);
1884 
1885 		do_s2io_write_bits(LSO6_ABORT | LSO7_ABORT |
1886 				   LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM |
1887 				   LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
1888 				   flag, &bar0->lso_err_mask);
1889 
1890 		do_s2io_write_bits(TPA_SM_ERR_ALARM | TPA_TX_FRM_DROP,
1891 				   flag, &bar0->tpa_err_mask);
1892 
1893 		do_s2io_write_bits(SM_SM_ERR_ALARM, flag, &bar0->sm_err_mask);
1894 	}
1895 
1896 	if (mask & TX_MAC_INTR) {
1897 		gen_int_mask |= TXMAC_INT_M;
1898 		do_s2io_write_bits(MAC_INT_STATUS_TMAC_INT, flag,
1899 				   &bar0->mac_int_mask);
1900 		do_s2io_write_bits(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR |
1901 				   TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
1902 				   TMAC_DESC_ECC_SG_ERR | TMAC_DESC_ECC_DB_ERR,
1903 				   flag, &bar0->mac_tmac_err_mask);
1904 	}
1905 
1906 	if (mask & TX_XGXS_INTR) {
1907 		gen_int_mask |= TXXGXS_INT_M;
1908 		do_s2io_write_bits(XGXS_INT_STATUS_TXGXS, flag,
1909 				   &bar0->xgxs_int_mask);
1910 		do_s2io_write_bits(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR |
1911 				   TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
1912 				   flag, &bar0->xgxs_txgxs_err_mask);
1913 	}
1914 
1915 	if (mask & RX_DMA_INTR) {
1916 		gen_int_mask |= RXDMA_INT_M;
1917 		do_s2io_write_bits(RXDMA_INT_RC_INT_M | RXDMA_INT_RPA_INT_M |
1918 				   RXDMA_INT_RDA_INT_M | RXDMA_INT_RTI_INT_M,
1919 				   flag, &bar0->rxdma_int_mask);
1920 		do_s2io_write_bits(RC_PRCn_ECC_DB_ERR | RC_FTC_ECC_DB_ERR |
1921 				   RC_PRCn_SM_ERR_ALARM | RC_FTC_SM_ERR_ALARM |
1922 				   RC_PRCn_ECC_SG_ERR | RC_FTC_ECC_SG_ERR |
1923 				   RC_RDA_FAIL_WR_Rn, flag, &bar0->rc_err_mask);
1924 		do_s2io_write_bits(PRC_PCI_AB_RD_Rn | PRC_PCI_AB_WR_Rn |
1925 				   PRC_PCI_AB_F_WR_Rn | PRC_PCI_DP_RD_Rn |
1926 				   PRC_PCI_DP_WR_Rn | PRC_PCI_DP_F_WR_Rn, flag,
1927 				   &bar0->prc_pcix_err_mask);
1928 		do_s2io_write_bits(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR |
1929 				   RPA_ECC_SG_ERR | RPA_ECC_DB_ERR, flag,
1930 				   &bar0->rpa_err_mask);
1931 		do_s2io_write_bits(RDA_RXDn_ECC_DB_ERR | RDA_FRM_ECC_DB_N_AERR |
1932 				   RDA_SM1_ERR_ALARM | RDA_SM0_ERR_ALARM |
1933 				   RDA_RXD_ECC_DB_SERR | RDA_RXDn_ECC_SG_ERR |
1934 				   RDA_FRM_ECC_SG_ERR |
1935 				   RDA_MISC_ERR|RDA_PCIX_ERR,
1936 				   flag, &bar0->rda_err_mask);
1937 		do_s2io_write_bits(RTI_SM_ERR_ALARM |
1938 				   RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
1939 				   flag, &bar0->rti_err_mask);
1940 	}
1941 
1942 	if (mask & RX_MAC_INTR) {
1943 		gen_int_mask |= RXMAC_INT_M;
1944 		do_s2io_write_bits(MAC_INT_STATUS_RMAC_INT, flag,
1945 				   &bar0->mac_int_mask);
1946 		interruptible = (RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR |
1947 				 RMAC_UNUSED_INT | RMAC_SINGLE_ECC_ERR |
1948 				 RMAC_DOUBLE_ECC_ERR);
1949 		if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER)
1950 			interruptible |= RMAC_LINK_STATE_CHANGE_INT;
1951 		do_s2io_write_bits(interruptible,
1952 				   flag, &bar0->mac_rmac_err_mask);
1953 	}
1954 
1955 	if (mask & RX_XGXS_INTR) {
1956 		gen_int_mask |= RXXGXS_INT_M;
1957 		do_s2io_write_bits(XGXS_INT_STATUS_RXGXS, flag,
1958 				   &bar0->xgxs_int_mask);
1959 		do_s2io_write_bits(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR, flag,
1960 				   &bar0->xgxs_rxgxs_err_mask);
1961 	}
1962 
1963 	if (mask & MC_INTR) {
1964 		gen_int_mask |= MC_INT_M;
1965 		do_s2io_write_bits(MC_INT_MASK_MC_INT,
1966 				   flag, &bar0->mc_int_mask);
1967 		do_s2io_write_bits(MC_ERR_REG_SM_ERR | MC_ERR_REG_ECC_ALL_SNG |
1968 				   MC_ERR_REG_ECC_ALL_DBL | PLL_LOCK_N, flag,
1969 				   &bar0->mc_err_mask);
1970 	}
1971 	nic->general_int_mask = gen_int_mask;
1972 
1973 	/* Remove this line when alarm interrupts are enabled */
1974 	nic->general_int_mask = 0;
1975 }
1976 
1977 /**
1978  *  en_dis_able_nic_intrs - Enable or Disable the interrupts
1979  *  @nic: device private variable,
1980  *  @mask: A mask indicating which Intr block must be modified and,
1981  *  @flag: A flag indicating whether to enable or disable the Intrs.
1982  *  Description: This function will either disable or enable the interrupts
1983  *  depending on the flag argument. The mask argument can be used to
1984  *  enable/disable any Intr block.
1985  *  Return Value: NONE.
1986  */
1987 
en_dis_able_nic_intrs(struct s2io_nic * nic,u16 mask,int flag)1988 static void en_dis_able_nic_intrs(struct s2io_nic *nic, u16 mask, int flag)
1989 {
1990 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
1991 	register u64 temp64 = 0, intr_mask = 0;
1992 
1993 	intr_mask = nic->general_int_mask;
1994 
1995 	/*  Top level interrupt classification */
1996 	/*  PIC Interrupts */
1997 	if (mask & TX_PIC_INTR) {
1998 		/*  Enable PIC Intrs in the general intr mask register */
1999 		intr_mask |= TXPIC_INT_M;
2000 		if (flag == ENABLE_INTRS) {
2001 			/*
2002 			 * If Hercules adapter enable GPIO otherwise
2003 			 * disable all PCIX, Flash, MDIO, IIC and GPIO
2004 			 * interrupts for now.
2005 			 * TODO
2006 			 */
2007 			if (s2io_link_fault_indication(nic) ==
2008 			    LINK_UP_DOWN_INTERRUPT) {
2009 				do_s2io_write_bits(PIC_INT_GPIO, flag,
2010 						   &bar0->pic_int_mask);
2011 				do_s2io_write_bits(GPIO_INT_MASK_LINK_UP, flag,
2012 						   &bar0->gpio_int_mask);
2013 			} else
2014 				writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2015 		} else if (flag == DISABLE_INTRS) {
2016 			/*
2017 			 * Disable PIC Intrs in the general
2018 			 * intr mask register
2019 			 */
2020 			writeq(DISABLE_ALL_INTRS, &bar0->pic_int_mask);
2021 		}
2022 	}
2023 
2024 	/*  Tx traffic interrupts */
2025 	if (mask & TX_TRAFFIC_INTR) {
2026 		intr_mask |= TXTRAFFIC_INT_M;
2027 		if (flag == ENABLE_INTRS) {
2028 			/*
2029 			 * Enable all the Tx side interrupts
2030 			 * writing 0 Enables all 64 TX interrupt levels
2031 			 */
2032 			writeq(0x0, &bar0->tx_traffic_mask);
2033 		} else if (flag == DISABLE_INTRS) {
2034 			/*
2035 			 * Disable Tx Traffic Intrs in the general intr mask
2036 			 * register.
2037 			 */
2038 			writeq(DISABLE_ALL_INTRS, &bar0->tx_traffic_mask);
2039 		}
2040 	}
2041 
2042 	/*  Rx traffic interrupts */
2043 	if (mask & RX_TRAFFIC_INTR) {
2044 		intr_mask |= RXTRAFFIC_INT_M;
2045 		if (flag == ENABLE_INTRS) {
2046 			/* writing 0 Enables all 8 RX interrupt levels */
2047 			writeq(0x0, &bar0->rx_traffic_mask);
2048 		} else if (flag == DISABLE_INTRS) {
2049 			/*
2050 			 * Disable Rx Traffic Intrs in the general intr mask
2051 			 * register.
2052 			 */
2053 			writeq(DISABLE_ALL_INTRS, &bar0->rx_traffic_mask);
2054 		}
2055 	}
2056 
2057 	temp64 = readq(&bar0->general_int_mask);
2058 	if (flag == ENABLE_INTRS)
2059 		temp64 &= ~((u64)intr_mask);
2060 	else
2061 		temp64 = DISABLE_ALL_INTRS;
2062 	writeq(temp64, &bar0->general_int_mask);
2063 
2064 	nic->general_int_mask = readq(&bar0->general_int_mask);
2065 }
2066 
2067 /**
2068  *  verify_pcc_quiescent- Checks for PCC quiescent state
2069  *  @sp : private member of the device structure, which is a pointer to the
2070  *  s2io_nic structure.
2071  *  @flag: boolean controlling function path
2072  *  Return: 1 If PCC is quiescence
2073  *          0 If PCC is not quiescence
2074  */
verify_pcc_quiescent(struct s2io_nic * sp,int flag)2075 static int verify_pcc_quiescent(struct s2io_nic *sp, int flag)
2076 {
2077 	int ret = 0, herc;
2078 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
2079 	u64 val64 = readq(&bar0->adapter_status);
2080 
2081 	herc = (sp->device_type == XFRAME_II_DEVICE);
2082 
2083 	if (flag == false) {
2084 		if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2085 			if (!(val64 & ADAPTER_STATUS_RMAC_PCC_IDLE))
2086 				ret = 1;
2087 		} else {
2088 			if (!(val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2089 				ret = 1;
2090 		}
2091 	} else {
2092 		if ((!herc && (sp->pdev->revision >= 4)) || herc) {
2093 			if (((val64 & ADAPTER_STATUS_RMAC_PCC_IDLE) ==
2094 			     ADAPTER_STATUS_RMAC_PCC_IDLE))
2095 				ret = 1;
2096 		} else {
2097 			if (((val64 & ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE) ==
2098 			     ADAPTER_STATUS_RMAC_PCC_FOUR_IDLE))
2099 				ret = 1;
2100 		}
2101 	}
2102 
2103 	return ret;
2104 }
2105 /**
2106  *  verify_xena_quiescence - Checks whether the H/W is ready
2107  *  @sp : private member of the device structure, which is a pointer to the
2108  *  s2io_nic structure.
2109  *  Description: Returns whether the H/W is ready to go or not. Depending
2110  *  on whether adapter enable bit was written or not the comparison
2111  *  differs and the calling function passes the input argument flag to
2112  *  indicate this.
2113  *  Return: 1 If xena is quiescence
2114  *          0 If Xena is not quiescence
2115  */
2116 
verify_xena_quiescence(struct s2io_nic * sp)2117 static int verify_xena_quiescence(struct s2io_nic *sp)
2118 {
2119 	int  mode;
2120 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
2121 	u64 val64 = readq(&bar0->adapter_status);
2122 	mode = s2io_verify_pci_mode(sp);
2123 
2124 	if (!(val64 & ADAPTER_STATUS_TDMA_READY)) {
2125 		DBG_PRINT(ERR_DBG, "TDMA is not ready!\n");
2126 		return 0;
2127 	}
2128 	if (!(val64 & ADAPTER_STATUS_RDMA_READY)) {
2129 		DBG_PRINT(ERR_DBG, "RDMA is not ready!\n");
2130 		return 0;
2131 	}
2132 	if (!(val64 & ADAPTER_STATUS_PFC_READY)) {
2133 		DBG_PRINT(ERR_DBG, "PFC is not ready!\n");
2134 		return 0;
2135 	}
2136 	if (!(val64 & ADAPTER_STATUS_TMAC_BUF_EMPTY)) {
2137 		DBG_PRINT(ERR_DBG, "TMAC BUF is not empty!\n");
2138 		return 0;
2139 	}
2140 	if (!(val64 & ADAPTER_STATUS_PIC_QUIESCENT)) {
2141 		DBG_PRINT(ERR_DBG, "PIC is not QUIESCENT!\n");
2142 		return 0;
2143 	}
2144 	if (!(val64 & ADAPTER_STATUS_MC_DRAM_READY)) {
2145 		DBG_PRINT(ERR_DBG, "MC_DRAM is not ready!\n");
2146 		return 0;
2147 	}
2148 	if (!(val64 & ADAPTER_STATUS_MC_QUEUES_READY)) {
2149 		DBG_PRINT(ERR_DBG, "MC_QUEUES is not ready!\n");
2150 		return 0;
2151 	}
2152 	if (!(val64 & ADAPTER_STATUS_M_PLL_LOCK)) {
2153 		DBG_PRINT(ERR_DBG, "M_PLL is not locked!\n");
2154 		return 0;
2155 	}
2156 
2157 	/*
2158 	 * In PCI 33 mode, the P_PLL is not used, and therefore,
2159 	 * the P_PLL_LOCK bit in the adapter_status register will
2160 	 * not be asserted.
2161 	 */
2162 	if (!(val64 & ADAPTER_STATUS_P_PLL_LOCK) &&
2163 	    sp->device_type == XFRAME_II_DEVICE &&
2164 	    mode != PCI_MODE_PCI_33) {
2165 		DBG_PRINT(ERR_DBG, "P_PLL is not locked!\n");
2166 		return 0;
2167 	}
2168 	if (!((val64 & ADAPTER_STATUS_RC_PRC_QUIESCENT) ==
2169 	      ADAPTER_STATUS_RC_PRC_QUIESCENT)) {
2170 		DBG_PRINT(ERR_DBG, "RC_PRC is not QUIESCENT!\n");
2171 		return 0;
2172 	}
2173 	return 1;
2174 }
2175 
2176 /**
2177  * fix_mac_address -  Fix for Mac addr problem on Alpha platforms
2178  * @sp: Pointer to device specifc structure
2179  * Description :
2180  * New procedure to clear mac address reading  problems on Alpha platforms
2181  *
2182  */
2183 
fix_mac_address(struct s2io_nic * sp)2184 static void fix_mac_address(struct s2io_nic *sp)
2185 {
2186 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
2187 	int i = 0;
2188 
2189 	while (fix_mac[i] != END_SIGN) {
2190 		writeq(fix_mac[i++], &bar0->gpio_control);
2191 		udelay(10);
2192 		(void) readq(&bar0->gpio_control);
2193 	}
2194 }
2195 
2196 /**
2197  *  start_nic - Turns the device on
2198  *  @nic : device private variable.
2199  *  Description:
2200  *  This function actually turns the device on. Before this  function is
2201  *  called,all Registers are configured from their reset states
2202  *  and shared memory is allocated but the NIC is still quiescent. On
2203  *  calling this function, the device interrupts are cleared and the NIC is
2204  *  literally switched on by writing into the adapter control register.
2205  *  Return Value:
2206  *  SUCCESS on success and -1 on failure.
2207  */
2208 
start_nic(struct s2io_nic * nic)2209 static int start_nic(struct s2io_nic *nic)
2210 {
2211 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
2212 	struct net_device *dev = nic->dev;
2213 	register u64 val64 = 0;
2214 	u16 subid, i;
2215 	struct config_param *config = &nic->config;
2216 	struct mac_info *mac_control = &nic->mac_control;
2217 
2218 	/*  PRC Initialization and configuration */
2219 	for (i = 0; i < config->rx_ring_num; i++) {
2220 		struct ring_info *ring = &mac_control->rings[i];
2221 
2222 		writeq((u64)ring->rx_blocks[0].block_dma_addr,
2223 		       &bar0->prc_rxd0_n[i]);
2224 
2225 		val64 = readq(&bar0->prc_ctrl_n[i]);
2226 		if (nic->rxd_mode == RXD_MODE_1)
2227 			val64 |= PRC_CTRL_RC_ENABLED;
2228 		else
2229 			val64 |= PRC_CTRL_RC_ENABLED | PRC_CTRL_RING_MODE_3;
2230 		if (nic->device_type == XFRAME_II_DEVICE)
2231 			val64 |= PRC_CTRL_GROUP_READS;
2232 		val64 &= ~PRC_CTRL_RXD_BACKOFF_INTERVAL(0xFFFFFF);
2233 		val64 |= PRC_CTRL_RXD_BACKOFF_INTERVAL(0x1000);
2234 		writeq(val64, &bar0->prc_ctrl_n[i]);
2235 	}
2236 
2237 	if (nic->rxd_mode == RXD_MODE_3B) {
2238 		/* Enabling 2 buffer mode by writing into Rx_pa_cfg reg. */
2239 		val64 = readq(&bar0->rx_pa_cfg);
2240 		val64 |= RX_PA_CFG_IGNORE_L2_ERR;
2241 		writeq(val64, &bar0->rx_pa_cfg);
2242 	}
2243 
2244 	if (vlan_tag_strip == 0) {
2245 		val64 = readq(&bar0->rx_pa_cfg);
2246 		val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
2247 		writeq(val64, &bar0->rx_pa_cfg);
2248 		nic->vlan_strip_flag = 0;
2249 	}
2250 
2251 	/*
2252 	 * Enabling MC-RLDRAM. After enabling the device, we timeout
2253 	 * for around 100ms, which is approximately the time required
2254 	 * for the device to be ready for operation.
2255 	 */
2256 	val64 = readq(&bar0->mc_rldram_mrs);
2257 	val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE | MC_RLDRAM_MRS_ENABLE;
2258 	SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
2259 	val64 = readq(&bar0->mc_rldram_mrs);
2260 
2261 	msleep(100);	/* Delay by around 100 ms. */
2262 
2263 	/* Enabling ECC Protection. */
2264 	val64 = readq(&bar0->adapter_control);
2265 	val64 &= ~ADAPTER_ECC_EN;
2266 	writeq(val64, &bar0->adapter_control);
2267 
2268 	/*
2269 	 * Verify if the device is ready to be enabled, if so enable
2270 	 * it.
2271 	 */
2272 	val64 = readq(&bar0->adapter_status);
2273 	if (!verify_xena_quiescence(nic)) {
2274 		DBG_PRINT(ERR_DBG, "%s: device is not ready, "
2275 			  "Adapter status reads: 0x%llx\n",
2276 			  dev->name, (unsigned long long)val64);
2277 		return FAILURE;
2278 	}
2279 
2280 	/*
2281 	 * With some switches, link might be already up at this point.
2282 	 * Because of this weird behavior, when we enable laser,
2283 	 * we may not get link. We need to handle this. We cannot
2284 	 * figure out which switch is misbehaving. So we are forced to
2285 	 * make a global change.
2286 	 */
2287 
2288 	/* Enabling Laser. */
2289 	val64 = readq(&bar0->adapter_control);
2290 	val64 |= ADAPTER_EOI_TX_ON;
2291 	writeq(val64, &bar0->adapter_control);
2292 
2293 	if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
2294 		/*
2295 		 * Dont see link state interrupts initially on some switches,
2296 		 * so directly scheduling the link state task here.
2297 		 */
2298 		schedule_work(&nic->set_link_task);
2299 	}
2300 	/* SXE-002: Initialize link and activity LED */
2301 	subid = nic->pdev->subsystem_device;
2302 	if (((subid & 0xFF) >= 0x07) &&
2303 	    (nic->device_type == XFRAME_I_DEVICE)) {
2304 		val64 = readq(&bar0->gpio_control);
2305 		val64 |= 0x0000800000000000ULL;
2306 		writeq(val64, &bar0->gpio_control);
2307 		val64 = 0x0411040400000000ULL;
2308 		writeq(val64, (void __iomem *)bar0 + 0x2700);
2309 	}
2310 
2311 	return SUCCESS;
2312 }
2313 /**
2314  * s2io_txdl_getskb - Get the skb from txdl, unmap and return skb
2315  * @fifo_data: fifo data pointer
2316  * @txdlp: descriptor
2317  * @get_off: unused
2318  */
s2io_txdl_getskb(struct fifo_info * fifo_data,struct TxD * txdlp,int get_off)2319 static struct sk_buff *s2io_txdl_getskb(struct fifo_info *fifo_data,
2320 					struct TxD *txdlp, int get_off)
2321 {
2322 	struct s2io_nic *nic = fifo_data->nic;
2323 	struct sk_buff *skb;
2324 	struct TxD *txds;
2325 	u16 j, frg_cnt;
2326 
2327 	txds = txdlp;
2328 	if (txds->Host_Control == (u64)(long)fifo_data->ufo_in_band_v) {
2329 		dma_unmap_single(&nic->pdev->dev,
2330 				 (dma_addr_t)txds->Buffer_Pointer,
2331 				 sizeof(u64), DMA_TO_DEVICE);
2332 		txds++;
2333 	}
2334 
2335 	skb = (struct sk_buff *)((unsigned long)txds->Host_Control);
2336 	if (!skb) {
2337 		memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2338 		return NULL;
2339 	}
2340 	dma_unmap_single(&nic->pdev->dev, (dma_addr_t)txds->Buffer_Pointer,
2341 			 skb_headlen(skb), DMA_TO_DEVICE);
2342 	frg_cnt = skb_shinfo(skb)->nr_frags;
2343 	if (frg_cnt) {
2344 		txds++;
2345 		for (j = 0; j < frg_cnt; j++, txds++) {
2346 			const skb_frag_t *frag = &skb_shinfo(skb)->frags[j];
2347 			if (!txds->Buffer_Pointer)
2348 				break;
2349 			dma_unmap_page(&nic->pdev->dev,
2350 				       (dma_addr_t)txds->Buffer_Pointer,
2351 				       skb_frag_size(frag), DMA_TO_DEVICE);
2352 		}
2353 	}
2354 	memset(txdlp, 0, (sizeof(struct TxD) * fifo_data->max_txds));
2355 	return skb;
2356 }
2357 
2358 /**
2359  *  free_tx_buffers - Free all queued Tx buffers
2360  *  @nic : device private variable.
2361  *  Description:
2362  *  Free all queued Tx buffers.
2363  *  Return Value: void
2364  */
2365 
free_tx_buffers(struct s2io_nic * nic)2366 static void free_tx_buffers(struct s2io_nic *nic)
2367 {
2368 	struct net_device *dev = nic->dev;
2369 	struct sk_buff *skb;
2370 	struct TxD *txdp;
2371 	int i, j;
2372 	int cnt = 0;
2373 	struct config_param *config = &nic->config;
2374 	struct mac_info *mac_control = &nic->mac_control;
2375 	struct stat_block *stats = mac_control->stats_info;
2376 	struct swStat *swstats = &stats->sw_stat;
2377 
2378 	for (i = 0; i < config->tx_fifo_num; i++) {
2379 		struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
2380 		struct fifo_info *fifo = &mac_control->fifos[i];
2381 		unsigned long flags;
2382 
2383 		spin_lock_irqsave(&fifo->tx_lock, flags);
2384 		for (j = 0; j < tx_cfg->fifo_len; j++) {
2385 			txdp = fifo->list_info[j].list_virt_addr;
2386 			skb = s2io_txdl_getskb(&mac_control->fifos[i], txdp, j);
2387 			if (skb) {
2388 				swstats->mem_freed += skb->truesize;
2389 				dev_kfree_skb_irq(skb);
2390 				cnt++;
2391 			}
2392 		}
2393 		DBG_PRINT(INTR_DBG,
2394 			  "%s: forcibly freeing %d skbs on FIFO%d\n",
2395 			  dev->name, cnt, i);
2396 		fifo->tx_curr_get_info.offset = 0;
2397 		fifo->tx_curr_put_info.offset = 0;
2398 		spin_unlock_irqrestore(&fifo->tx_lock, flags);
2399 	}
2400 }
2401 
2402 /**
2403  *   stop_nic -  To stop the nic
2404  *   @nic : device private variable.
2405  *   Description:
2406  *   This function does exactly the opposite of what the start_nic()
2407  *   function does. This function is called to stop the device.
2408  *   Return Value:
2409  *   void.
2410  */
2411 
stop_nic(struct s2io_nic * nic)2412 static void stop_nic(struct s2io_nic *nic)
2413 {
2414 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
2415 	register u64 val64 = 0;
2416 	u16 interruptible;
2417 
2418 	/*  Disable all interrupts */
2419 	en_dis_err_alarms(nic, ENA_ALL_INTRS, DISABLE_INTRS);
2420 	interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
2421 	interruptible |= TX_PIC_INTR;
2422 	en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
2423 
2424 	/* Clearing Adapter_En bit of ADAPTER_CONTROL Register */
2425 	val64 = readq(&bar0->adapter_control);
2426 	val64 &= ~(ADAPTER_CNTL_EN);
2427 	writeq(val64, &bar0->adapter_control);
2428 }
2429 
2430 /**
2431  *  fill_rx_buffers - Allocates the Rx side skbs
2432  *  @nic : device private variable.
2433  *  @ring: per ring structure
2434  *  @from_card_up: If this is true, we will map the buffer to get
2435  *     the dma address for buf0 and buf1 to give it to the card.
2436  *     Else we will sync the already mapped buffer to give it to the card.
2437  *  Description:
2438  *  The function allocates Rx side skbs and puts the physical
2439  *  address of these buffers into the RxD buffer pointers, so that the NIC
2440  *  can DMA the received frame into these locations.
2441  *  The NIC supports 3 receive modes, viz
2442  *  1. single buffer,
2443  *  2. three buffer and
2444  *  3. Five buffer modes.
2445  *  Each mode defines how many fragments the received frame will be split
2446  *  up into by the NIC. The frame is split into L3 header, L4 Header,
2447  *  L4 payload in three buffer mode and in 5 buffer mode, L4 payload itself
2448  *  is split into 3 fragments. As of now only single buffer mode is
2449  *  supported.
2450  *   Return Value:
2451  *  SUCCESS on success or an appropriate -ve value on failure.
2452  */
fill_rx_buffers(struct s2io_nic * nic,struct ring_info * ring,int from_card_up)2453 static int fill_rx_buffers(struct s2io_nic *nic, struct ring_info *ring,
2454 			   int from_card_up)
2455 {
2456 	struct sk_buff *skb;
2457 	struct RxD_t *rxdp;
2458 	int off, size, block_no, block_no1;
2459 	u32 alloc_tab = 0;
2460 	u32 alloc_cnt;
2461 	u64 tmp;
2462 	struct buffAdd *ba;
2463 	struct RxD_t *first_rxdp = NULL;
2464 	u64 Buffer0_ptr = 0, Buffer1_ptr = 0;
2465 	struct RxD1 *rxdp1;
2466 	struct RxD3 *rxdp3;
2467 	struct swStat *swstats = &ring->nic->mac_control.stats_info->sw_stat;
2468 
2469 	alloc_cnt = ring->pkt_cnt - ring->rx_bufs_left;
2470 
2471 	block_no1 = ring->rx_curr_get_info.block_index;
2472 	while (alloc_tab < alloc_cnt) {
2473 		block_no = ring->rx_curr_put_info.block_index;
2474 
2475 		off = ring->rx_curr_put_info.offset;
2476 
2477 		rxdp = ring->rx_blocks[block_no].rxds[off].virt_addr;
2478 
2479 		if ((block_no == block_no1) &&
2480 		    (off == ring->rx_curr_get_info.offset) &&
2481 		    (rxdp->Host_Control)) {
2482 			DBG_PRINT(INTR_DBG, "%s: Get and Put info equated\n",
2483 				  ring->dev->name);
2484 			goto end;
2485 		}
2486 		if (off && (off == ring->rxd_count)) {
2487 			ring->rx_curr_put_info.block_index++;
2488 			if (ring->rx_curr_put_info.block_index ==
2489 			    ring->block_count)
2490 				ring->rx_curr_put_info.block_index = 0;
2491 			block_no = ring->rx_curr_put_info.block_index;
2492 			off = 0;
2493 			ring->rx_curr_put_info.offset = off;
2494 			rxdp = ring->rx_blocks[block_no].block_virt_addr;
2495 			DBG_PRINT(INTR_DBG, "%s: Next block at: %p\n",
2496 				  ring->dev->name, rxdp);
2497 
2498 		}
2499 
2500 		if ((rxdp->Control_1 & RXD_OWN_XENA) &&
2501 		    ((ring->rxd_mode == RXD_MODE_3B) &&
2502 		     (rxdp->Control_2 & s2BIT(0)))) {
2503 			ring->rx_curr_put_info.offset = off;
2504 			goto end;
2505 		}
2506 		/* calculate size of skb based on ring mode */
2507 		size = ring->mtu +
2508 			HEADER_ETHERNET_II_802_3_SIZE +
2509 			HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
2510 		if (ring->rxd_mode == RXD_MODE_1)
2511 			size += NET_IP_ALIGN;
2512 		else
2513 			size = ring->mtu + ALIGN_SIZE + BUF0_LEN + 4;
2514 
2515 		/* allocate skb */
2516 		skb = netdev_alloc_skb(nic->dev, size);
2517 		if (!skb) {
2518 			DBG_PRINT(INFO_DBG, "%s: Could not allocate skb\n",
2519 				  ring->dev->name);
2520 			if (first_rxdp) {
2521 				dma_wmb();
2522 				first_rxdp->Control_1 |= RXD_OWN_XENA;
2523 			}
2524 			swstats->mem_alloc_fail_cnt++;
2525 
2526 			return -ENOMEM ;
2527 		}
2528 		swstats->mem_allocated += skb->truesize;
2529 
2530 		if (ring->rxd_mode == RXD_MODE_1) {
2531 			/* 1 buffer mode - normal operation mode */
2532 			rxdp1 = (struct RxD1 *)rxdp;
2533 			memset(rxdp, 0, sizeof(struct RxD1));
2534 			skb_reserve(skb, NET_IP_ALIGN);
2535 			rxdp1->Buffer0_ptr =
2536 				dma_map_single(&ring->pdev->dev, skb->data,
2537 					       size - NET_IP_ALIGN,
2538 					       DMA_FROM_DEVICE);
2539 			if (dma_mapping_error(&nic->pdev->dev, rxdp1->Buffer0_ptr))
2540 				goto pci_map_failed;
2541 
2542 			rxdp->Control_2 =
2543 				SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
2544 			rxdp->Host_Control = (unsigned long)skb;
2545 		} else if (ring->rxd_mode == RXD_MODE_3B) {
2546 			/*
2547 			 * 2 buffer mode -
2548 			 * 2 buffer mode provides 128
2549 			 * byte aligned receive buffers.
2550 			 */
2551 
2552 			rxdp3 = (struct RxD3 *)rxdp;
2553 			/* save buffer pointers to avoid frequent dma mapping */
2554 			Buffer0_ptr = rxdp3->Buffer0_ptr;
2555 			Buffer1_ptr = rxdp3->Buffer1_ptr;
2556 			memset(rxdp, 0, sizeof(struct RxD3));
2557 			/* restore the buffer pointers for dma sync*/
2558 			rxdp3->Buffer0_ptr = Buffer0_ptr;
2559 			rxdp3->Buffer1_ptr = Buffer1_ptr;
2560 
2561 			ba = &ring->ba[block_no][off];
2562 			skb_reserve(skb, BUF0_LEN);
2563 			tmp = (u64)(unsigned long)skb->data;
2564 			tmp += ALIGN_SIZE;
2565 			tmp &= ~ALIGN_SIZE;
2566 			skb->data = (void *) (unsigned long)tmp;
2567 			skb_reset_tail_pointer(skb);
2568 
2569 			if (from_card_up) {
2570 				rxdp3->Buffer0_ptr =
2571 					dma_map_single(&ring->pdev->dev,
2572 						       ba->ba_0, BUF0_LEN,
2573 						       DMA_FROM_DEVICE);
2574 				if (dma_mapping_error(&nic->pdev->dev, rxdp3->Buffer0_ptr))
2575 					goto pci_map_failed;
2576 			} else
2577 				dma_sync_single_for_device(&ring->pdev->dev,
2578 							   (dma_addr_t)rxdp3->Buffer0_ptr,
2579 							   BUF0_LEN,
2580 							   DMA_FROM_DEVICE);
2581 
2582 			rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
2583 			if (ring->rxd_mode == RXD_MODE_3B) {
2584 				/* Two buffer mode */
2585 
2586 				/*
2587 				 * Buffer2 will have L3/L4 header plus
2588 				 * L4 payload
2589 				 */
2590 				rxdp3->Buffer2_ptr = dma_map_single(&ring->pdev->dev,
2591 								    skb->data,
2592 								    ring->mtu + 4,
2593 								    DMA_FROM_DEVICE);
2594 
2595 				if (dma_mapping_error(&nic->pdev->dev, rxdp3->Buffer2_ptr))
2596 					goto pci_map_failed;
2597 
2598 				if (from_card_up) {
2599 					rxdp3->Buffer1_ptr =
2600 						dma_map_single(&ring->pdev->dev,
2601 							       ba->ba_1,
2602 							       BUF1_LEN,
2603 							       DMA_FROM_DEVICE);
2604 
2605 					if (dma_mapping_error(&nic->pdev->dev,
2606 							      rxdp3->Buffer1_ptr)) {
2607 						dma_unmap_single(&ring->pdev->dev,
2608 								 (dma_addr_t)(unsigned long)
2609 								 skb->data,
2610 								 ring->mtu + 4,
2611 								 DMA_FROM_DEVICE);
2612 						goto pci_map_failed;
2613 					}
2614 				}
2615 				rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
2616 				rxdp->Control_2 |= SET_BUFFER2_SIZE_3
2617 					(ring->mtu + 4);
2618 			}
2619 			rxdp->Control_2 |= s2BIT(0);
2620 			rxdp->Host_Control = (unsigned long) (skb);
2621 		}
2622 		if (alloc_tab & ((1 << rxsync_frequency) - 1))
2623 			rxdp->Control_1 |= RXD_OWN_XENA;
2624 		off++;
2625 		if (off == (ring->rxd_count + 1))
2626 			off = 0;
2627 		ring->rx_curr_put_info.offset = off;
2628 
2629 		rxdp->Control_2 |= SET_RXD_MARKER;
2630 		if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
2631 			if (first_rxdp) {
2632 				dma_wmb();
2633 				first_rxdp->Control_1 |= RXD_OWN_XENA;
2634 			}
2635 			first_rxdp = rxdp;
2636 		}
2637 		ring->rx_bufs_left += 1;
2638 		alloc_tab++;
2639 	}
2640 
2641 end:
2642 	/* Transfer ownership of first descriptor to adapter just before
2643 	 * exiting. Before that, use memory barrier so that ownership
2644 	 * and other fields are seen by adapter correctly.
2645 	 */
2646 	if (first_rxdp) {
2647 		dma_wmb();
2648 		first_rxdp->Control_1 |= RXD_OWN_XENA;
2649 	}
2650 
2651 	return SUCCESS;
2652 
2653 pci_map_failed:
2654 	swstats->pci_map_fail_cnt++;
2655 	swstats->mem_freed += skb->truesize;
2656 	dev_kfree_skb_irq(skb);
2657 	return -ENOMEM;
2658 }
2659 
free_rxd_blk(struct s2io_nic * sp,int ring_no,int blk)2660 static void free_rxd_blk(struct s2io_nic *sp, int ring_no, int blk)
2661 {
2662 	struct net_device *dev = sp->dev;
2663 	int j;
2664 	struct sk_buff *skb;
2665 	struct RxD_t *rxdp;
2666 	struct RxD1 *rxdp1;
2667 	struct RxD3 *rxdp3;
2668 	struct mac_info *mac_control = &sp->mac_control;
2669 	struct stat_block *stats = mac_control->stats_info;
2670 	struct swStat *swstats = &stats->sw_stat;
2671 
2672 	for (j = 0 ; j < rxd_count[sp->rxd_mode]; j++) {
2673 		rxdp = mac_control->rings[ring_no].
2674 			rx_blocks[blk].rxds[j].virt_addr;
2675 		skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2676 		if (!skb)
2677 			continue;
2678 		if (sp->rxd_mode == RXD_MODE_1) {
2679 			rxdp1 = (struct RxD1 *)rxdp;
2680 			dma_unmap_single(&sp->pdev->dev,
2681 					 (dma_addr_t)rxdp1->Buffer0_ptr,
2682 					 dev->mtu +
2683 					 HEADER_ETHERNET_II_802_3_SIZE +
2684 					 HEADER_802_2_SIZE + HEADER_SNAP_SIZE,
2685 					 DMA_FROM_DEVICE);
2686 			memset(rxdp, 0, sizeof(struct RxD1));
2687 		} else if (sp->rxd_mode == RXD_MODE_3B) {
2688 			rxdp3 = (struct RxD3 *)rxdp;
2689 			dma_unmap_single(&sp->pdev->dev,
2690 					 (dma_addr_t)rxdp3->Buffer0_ptr,
2691 					 BUF0_LEN, DMA_FROM_DEVICE);
2692 			dma_unmap_single(&sp->pdev->dev,
2693 					 (dma_addr_t)rxdp3->Buffer1_ptr,
2694 					 BUF1_LEN, DMA_FROM_DEVICE);
2695 			dma_unmap_single(&sp->pdev->dev,
2696 					 (dma_addr_t)rxdp3->Buffer2_ptr,
2697 					 dev->mtu + 4, DMA_FROM_DEVICE);
2698 			memset(rxdp, 0, sizeof(struct RxD3));
2699 		}
2700 		swstats->mem_freed += skb->truesize;
2701 		dev_kfree_skb(skb);
2702 		mac_control->rings[ring_no].rx_bufs_left -= 1;
2703 	}
2704 }
2705 
2706 /**
2707  *  free_rx_buffers - Frees all Rx buffers
2708  *  @sp: device private variable.
2709  *  Description:
2710  *  This function will free all Rx buffers allocated by host.
2711  *  Return Value:
2712  *  NONE.
2713  */
2714 
free_rx_buffers(struct s2io_nic * sp)2715 static void free_rx_buffers(struct s2io_nic *sp)
2716 {
2717 	struct net_device *dev = sp->dev;
2718 	int i, blk = 0, buf_cnt = 0;
2719 	struct config_param *config = &sp->config;
2720 	struct mac_info *mac_control = &sp->mac_control;
2721 
2722 	for (i = 0; i < config->rx_ring_num; i++) {
2723 		struct ring_info *ring = &mac_control->rings[i];
2724 
2725 		for (blk = 0; blk < rx_ring_sz[i]; blk++)
2726 			free_rxd_blk(sp, i, blk);
2727 
2728 		ring->rx_curr_put_info.block_index = 0;
2729 		ring->rx_curr_get_info.block_index = 0;
2730 		ring->rx_curr_put_info.offset = 0;
2731 		ring->rx_curr_get_info.offset = 0;
2732 		ring->rx_bufs_left = 0;
2733 		DBG_PRINT(INIT_DBG, "%s: Freed 0x%x Rx Buffers on ring%d\n",
2734 			  dev->name, buf_cnt, i);
2735 	}
2736 }
2737 
s2io_chk_rx_buffers(struct s2io_nic * nic,struct ring_info * ring)2738 static int s2io_chk_rx_buffers(struct s2io_nic *nic, struct ring_info *ring)
2739 {
2740 	if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2741 		DBG_PRINT(INFO_DBG, "%s: Out of memory in Rx Intr!!\n",
2742 			  ring->dev->name);
2743 	}
2744 	return 0;
2745 }
2746 
2747 /**
2748  * s2io_poll_msix - Rx interrupt handler for NAPI support
2749  * @napi : pointer to the napi structure.
2750  * @budget : The number of packets that were budgeted to be processed
2751  * during  one pass through the 'Poll" function.
2752  * Description:
2753  * Comes into picture only if NAPI support has been incorporated. It does
2754  * the same thing that rx_intr_handler does, but not in a interrupt context
2755  * also It will process only a given number of packets.
2756  * Return value:
2757  * 0 on success and 1 if there are No Rx packets to be processed.
2758  */
2759 
s2io_poll_msix(struct napi_struct * napi,int budget)2760 static int s2io_poll_msix(struct napi_struct *napi, int budget)
2761 {
2762 	struct ring_info *ring = container_of(napi, struct ring_info, napi);
2763 	struct net_device *dev = ring->dev;
2764 	int pkts_processed = 0;
2765 	u8 __iomem *addr = NULL;
2766 	u8 val8 = 0;
2767 	struct s2io_nic *nic = netdev_priv(dev);
2768 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
2769 	int budget_org = budget;
2770 
2771 	if (unlikely(!is_s2io_card_up(nic)))
2772 		return 0;
2773 
2774 	pkts_processed = rx_intr_handler(ring, budget);
2775 	s2io_chk_rx_buffers(nic, ring);
2776 
2777 	if (pkts_processed < budget_org) {
2778 		napi_complete_done(napi, pkts_processed);
2779 		/*Re Enable MSI-Rx Vector*/
2780 		addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
2781 		addr += 7 - ring->ring_no;
2782 		val8 = (ring->ring_no == 0) ? 0x3f : 0xbf;
2783 		writeb(val8, addr);
2784 		val8 = readb(addr);
2785 	}
2786 	return pkts_processed;
2787 }
2788 
s2io_poll_inta(struct napi_struct * napi,int budget)2789 static int s2io_poll_inta(struct napi_struct *napi, int budget)
2790 {
2791 	struct s2io_nic *nic = container_of(napi, struct s2io_nic, napi);
2792 	int pkts_processed = 0;
2793 	int ring_pkts_processed, i;
2794 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
2795 	int budget_org = budget;
2796 	struct config_param *config = &nic->config;
2797 	struct mac_info *mac_control = &nic->mac_control;
2798 
2799 	if (unlikely(!is_s2io_card_up(nic)))
2800 		return 0;
2801 
2802 	for (i = 0; i < config->rx_ring_num; i++) {
2803 		struct ring_info *ring = &mac_control->rings[i];
2804 		ring_pkts_processed = rx_intr_handler(ring, budget);
2805 		s2io_chk_rx_buffers(nic, ring);
2806 		pkts_processed += ring_pkts_processed;
2807 		budget -= ring_pkts_processed;
2808 		if (budget <= 0)
2809 			break;
2810 	}
2811 	if (pkts_processed < budget_org) {
2812 		napi_complete_done(napi, pkts_processed);
2813 		/* Re enable the Rx interrupts for the ring */
2814 		writeq(0, &bar0->rx_traffic_mask);
2815 		readl(&bar0->rx_traffic_mask);
2816 	}
2817 	return pkts_processed;
2818 }
2819 
2820 #ifdef CONFIG_NET_POLL_CONTROLLER
2821 /**
2822  * s2io_netpoll - netpoll event handler entry point
2823  * @dev : pointer to the device structure.
2824  * Description:
2825  * 	This function will be called by upper layer to check for events on the
2826  * interface in situations where interrupts are disabled. It is used for
2827  * specific in-kernel networking tasks, such as remote consoles and kernel
2828  * debugging over the network (example netdump in RedHat).
2829  */
s2io_netpoll(struct net_device * dev)2830 static void s2io_netpoll(struct net_device *dev)
2831 {
2832 	struct s2io_nic *nic = netdev_priv(dev);
2833 	const int irq = nic->pdev->irq;
2834 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
2835 	u64 val64 = 0xFFFFFFFFFFFFFFFFULL;
2836 	int i;
2837 	struct config_param *config = &nic->config;
2838 	struct mac_info *mac_control = &nic->mac_control;
2839 
2840 	if (pci_channel_offline(nic->pdev))
2841 		return;
2842 
2843 	disable_irq(irq);
2844 
2845 	writeq(val64, &bar0->rx_traffic_int);
2846 	writeq(val64, &bar0->tx_traffic_int);
2847 
2848 	/* we need to free up the transmitted skbufs or else netpoll will
2849 	 * run out of skbs and will fail and eventually netpoll application such
2850 	 * as netdump will fail.
2851 	 */
2852 	for (i = 0; i < config->tx_fifo_num; i++)
2853 		tx_intr_handler(&mac_control->fifos[i]);
2854 
2855 	/* check for received packet and indicate up to network */
2856 	for (i = 0; i < config->rx_ring_num; i++) {
2857 		struct ring_info *ring = &mac_control->rings[i];
2858 
2859 		rx_intr_handler(ring, 0);
2860 	}
2861 
2862 	for (i = 0; i < config->rx_ring_num; i++) {
2863 		struct ring_info *ring = &mac_control->rings[i];
2864 
2865 		if (fill_rx_buffers(nic, ring, 0) == -ENOMEM) {
2866 			DBG_PRINT(INFO_DBG,
2867 				  "%s: Out of memory in Rx Netpoll!!\n",
2868 				  dev->name);
2869 			break;
2870 		}
2871 	}
2872 	enable_irq(irq);
2873 }
2874 #endif
2875 
2876 /**
2877  *  rx_intr_handler - Rx interrupt handler
2878  *  @ring_data: per ring structure.
2879  *  @budget: budget for napi processing.
2880  *  Description:
2881  *  If the interrupt is because of a received frame or if the
2882  *  receive ring contains fresh as yet un-processed frames,this function is
2883  *  called. It picks out the RxD at which place the last Rx processing had
2884  *  stopped and sends the skb to the OSM's Rx handler and then increments
2885  *  the offset.
2886  *  Return Value:
2887  *  No. of napi packets processed.
2888  */
rx_intr_handler(struct ring_info * ring_data,int budget)2889 static int rx_intr_handler(struct ring_info *ring_data, int budget)
2890 {
2891 	int get_block, put_block;
2892 	struct rx_curr_get_info get_info, put_info;
2893 	struct RxD_t *rxdp;
2894 	struct sk_buff *skb;
2895 	int pkt_cnt = 0, napi_pkts = 0;
2896 	int i;
2897 	struct RxD1 *rxdp1;
2898 	struct RxD3 *rxdp3;
2899 
2900 	if (budget <= 0)
2901 		return napi_pkts;
2902 
2903 	get_info = ring_data->rx_curr_get_info;
2904 	get_block = get_info.block_index;
2905 	memcpy(&put_info, &ring_data->rx_curr_put_info, sizeof(put_info));
2906 	put_block = put_info.block_index;
2907 	rxdp = ring_data->rx_blocks[get_block].rxds[get_info.offset].virt_addr;
2908 
2909 	while (RXD_IS_UP2DT(rxdp)) {
2910 		/*
2911 		 * If your are next to put index then it's
2912 		 * FIFO full condition
2913 		 */
2914 		if ((get_block == put_block) &&
2915 		    (get_info.offset + 1) == put_info.offset) {
2916 			DBG_PRINT(INTR_DBG, "%s: Ring Full\n",
2917 				  ring_data->dev->name);
2918 			break;
2919 		}
2920 		skb = (struct sk_buff *)((unsigned long)rxdp->Host_Control);
2921 		if (skb == NULL) {
2922 			DBG_PRINT(ERR_DBG, "%s: NULL skb in Rx Intr\n",
2923 				  ring_data->dev->name);
2924 			return 0;
2925 		}
2926 		if (ring_data->rxd_mode == RXD_MODE_1) {
2927 			rxdp1 = (struct RxD1 *)rxdp;
2928 			dma_unmap_single(&ring_data->pdev->dev,
2929 					 (dma_addr_t)rxdp1->Buffer0_ptr,
2930 					 ring_data->mtu +
2931 					 HEADER_ETHERNET_II_802_3_SIZE +
2932 					 HEADER_802_2_SIZE +
2933 					 HEADER_SNAP_SIZE,
2934 					 DMA_FROM_DEVICE);
2935 		} else if (ring_data->rxd_mode == RXD_MODE_3B) {
2936 			rxdp3 = (struct RxD3 *)rxdp;
2937 			dma_sync_single_for_cpu(&ring_data->pdev->dev,
2938 						(dma_addr_t)rxdp3->Buffer0_ptr,
2939 						BUF0_LEN, DMA_FROM_DEVICE);
2940 			dma_unmap_single(&ring_data->pdev->dev,
2941 					 (dma_addr_t)rxdp3->Buffer2_ptr,
2942 					 ring_data->mtu + 4, DMA_FROM_DEVICE);
2943 		}
2944 		prefetch(skb->data);
2945 		rx_osm_handler(ring_data, rxdp);
2946 		get_info.offset++;
2947 		ring_data->rx_curr_get_info.offset = get_info.offset;
2948 		rxdp = ring_data->rx_blocks[get_block].
2949 			rxds[get_info.offset].virt_addr;
2950 		if (get_info.offset == rxd_count[ring_data->rxd_mode]) {
2951 			get_info.offset = 0;
2952 			ring_data->rx_curr_get_info.offset = get_info.offset;
2953 			get_block++;
2954 			if (get_block == ring_data->block_count)
2955 				get_block = 0;
2956 			ring_data->rx_curr_get_info.block_index = get_block;
2957 			rxdp = ring_data->rx_blocks[get_block].block_virt_addr;
2958 		}
2959 
2960 		if (ring_data->nic->config.napi) {
2961 			budget--;
2962 			napi_pkts++;
2963 			if (!budget)
2964 				break;
2965 		}
2966 		pkt_cnt++;
2967 		if ((indicate_max_pkts) && (pkt_cnt > indicate_max_pkts))
2968 			break;
2969 	}
2970 	if (ring_data->lro) {
2971 		/* Clear all LRO sessions before exiting */
2972 		for (i = 0; i < MAX_LRO_SESSIONS; i++) {
2973 			struct lro *lro = &ring_data->lro0_n[i];
2974 			if (lro->in_use) {
2975 				update_L3L4_header(ring_data->nic, lro);
2976 				queue_rx_frame(lro->parent, lro->vlan_tag);
2977 				clear_lro_session(lro);
2978 			}
2979 		}
2980 	}
2981 	return napi_pkts;
2982 }
2983 
2984 /**
2985  *  tx_intr_handler - Transmit interrupt handler
2986  *  @fifo_data : fifo data pointer
2987  *  Description:
2988  *  If an interrupt was raised to indicate DMA complete of the
2989  *  Tx packet, this function is called. It identifies the last TxD
2990  *  whose buffer was freed and frees all skbs whose data have already
2991  *  DMA'ed into the NICs internal memory.
2992  *  Return Value:
2993  *  NONE
2994  */
2995 
tx_intr_handler(struct fifo_info * fifo_data)2996 static void tx_intr_handler(struct fifo_info *fifo_data)
2997 {
2998 	struct s2io_nic *nic = fifo_data->nic;
2999 	struct tx_curr_get_info get_info, put_info;
3000 	struct sk_buff *skb = NULL;
3001 	struct TxD *txdlp;
3002 	int pkt_cnt = 0;
3003 	unsigned long flags = 0;
3004 	u8 err_mask;
3005 	struct stat_block *stats = nic->mac_control.stats_info;
3006 	struct swStat *swstats = &stats->sw_stat;
3007 
3008 	if (!spin_trylock_irqsave(&fifo_data->tx_lock, flags))
3009 		return;
3010 
3011 	get_info = fifo_data->tx_curr_get_info;
3012 	memcpy(&put_info, &fifo_data->tx_curr_put_info, sizeof(put_info));
3013 	txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3014 	while ((!(txdlp->Control_1 & TXD_LIST_OWN_XENA)) &&
3015 	       (get_info.offset != put_info.offset) &&
3016 	       (txdlp->Host_Control)) {
3017 		/* Check for TxD errors */
3018 		if (txdlp->Control_1 & TXD_T_CODE) {
3019 			unsigned long long err;
3020 			err = txdlp->Control_1 & TXD_T_CODE;
3021 			if (err & 0x1) {
3022 				swstats->parity_err_cnt++;
3023 			}
3024 
3025 			/* update t_code statistics */
3026 			err_mask = err >> 48;
3027 			switch (err_mask) {
3028 			case 2:
3029 				swstats->tx_buf_abort_cnt++;
3030 				break;
3031 
3032 			case 3:
3033 				swstats->tx_desc_abort_cnt++;
3034 				break;
3035 
3036 			case 7:
3037 				swstats->tx_parity_err_cnt++;
3038 				break;
3039 
3040 			case 10:
3041 				swstats->tx_link_loss_cnt++;
3042 				break;
3043 
3044 			case 15:
3045 				swstats->tx_list_proc_err_cnt++;
3046 				break;
3047 			}
3048 		}
3049 
3050 		skb = s2io_txdl_getskb(fifo_data, txdlp, get_info.offset);
3051 		if (skb == NULL) {
3052 			spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3053 			DBG_PRINT(ERR_DBG, "%s: NULL skb in Tx Free Intr\n",
3054 				  __func__);
3055 			return;
3056 		}
3057 		pkt_cnt++;
3058 
3059 		/* Updating the statistics block */
3060 		swstats->mem_freed += skb->truesize;
3061 		dev_consume_skb_irq(skb);
3062 
3063 		get_info.offset++;
3064 		if (get_info.offset == get_info.fifo_len + 1)
3065 			get_info.offset = 0;
3066 		txdlp = fifo_data->list_info[get_info.offset].list_virt_addr;
3067 		fifo_data->tx_curr_get_info.offset = get_info.offset;
3068 	}
3069 
3070 	s2io_wake_tx_queue(fifo_data, pkt_cnt, nic->config.multiq);
3071 
3072 	spin_unlock_irqrestore(&fifo_data->tx_lock, flags);
3073 }
3074 
3075 /**
3076  *  s2io_mdio_write - Function to write in to MDIO registers
3077  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3078  *  @addr     : address value
3079  *  @value    : data value
3080  *  @dev      : pointer to net_device structure
3081  *  Description:
3082  *  This function is used to write values to the MDIO registers
3083  *  NONE
3084  */
s2io_mdio_write(u32 mmd_type,u64 addr,u16 value,struct net_device * dev)3085 static void s2io_mdio_write(u32 mmd_type, u64 addr, u16 value,
3086 			    struct net_device *dev)
3087 {
3088 	u64 val64;
3089 	struct s2io_nic *sp = netdev_priv(dev);
3090 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
3091 
3092 	/* address transaction */
3093 	val64 = MDIO_MMD_INDX_ADDR(addr) |
3094 		MDIO_MMD_DEV_ADDR(mmd_type) |
3095 		MDIO_MMS_PRT_ADDR(0x0);
3096 	writeq(val64, &bar0->mdio_control);
3097 	val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3098 	writeq(val64, &bar0->mdio_control);
3099 	udelay(100);
3100 
3101 	/* Data transaction */
3102 	val64 = MDIO_MMD_INDX_ADDR(addr) |
3103 		MDIO_MMD_DEV_ADDR(mmd_type) |
3104 		MDIO_MMS_PRT_ADDR(0x0) |
3105 		MDIO_MDIO_DATA(value) |
3106 		MDIO_OP(MDIO_OP_WRITE_TRANS);
3107 	writeq(val64, &bar0->mdio_control);
3108 	val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3109 	writeq(val64, &bar0->mdio_control);
3110 	udelay(100);
3111 
3112 	val64 = MDIO_MMD_INDX_ADDR(addr) |
3113 		MDIO_MMD_DEV_ADDR(mmd_type) |
3114 		MDIO_MMS_PRT_ADDR(0x0) |
3115 		MDIO_OP(MDIO_OP_READ_TRANS);
3116 	writeq(val64, &bar0->mdio_control);
3117 	val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3118 	writeq(val64, &bar0->mdio_control);
3119 	udelay(100);
3120 }
3121 
3122 /**
3123  *  s2io_mdio_read - Function to write in to MDIO registers
3124  *  @mmd_type : MMD type value (PMA/PMD/WIS/PCS/PHYXS)
3125  *  @addr     : address value
3126  *  @dev      : pointer to net_device structure
3127  *  Description:
3128  *  This function is used to read values to the MDIO registers
3129  *  NONE
3130  */
s2io_mdio_read(u32 mmd_type,u64 addr,struct net_device * dev)3131 static u64 s2io_mdio_read(u32 mmd_type, u64 addr, struct net_device *dev)
3132 {
3133 	u64 val64 = 0x0;
3134 	u64 rval64 = 0x0;
3135 	struct s2io_nic *sp = netdev_priv(dev);
3136 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
3137 
3138 	/* address transaction */
3139 	val64 = val64 | (MDIO_MMD_INDX_ADDR(addr)
3140 			 | MDIO_MMD_DEV_ADDR(mmd_type)
3141 			 | MDIO_MMS_PRT_ADDR(0x0));
3142 	writeq(val64, &bar0->mdio_control);
3143 	val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3144 	writeq(val64, &bar0->mdio_control);
3145 	udelay(100);
3146 
3147 	/* Data transaction */
3148 	val64 = MDIO_MMD_INDX_ADDR(addr) |
3149 		MDIO_MMD_DEV_ADDR(mmd_type) |
3150 		MDIO_MMS_PRT_ADDR(0x0) |
3151 		MDIO_OP(MDIO_OP_READ_TRANS);
3152 	writeq(val64, &bar0->mdio_control);
3153 	val64 = val64 | MDIO_CTRL_START_TRANS(0xE);
3154 	writeq(val64, &bar0->mdio_control);
3155 	udelay(100);
3156 
3157 	/* Read the value from regs */
3158 	rval64 = readq(&bar0->mdio_control);
3159 	rval64 = rval64 & 0xFFFF0000;
3160 	rval64 = rval64 >> 16;
3161 	return rval64;
3162 }
3163 
3164 /**
3165  *  s2io_chk_xpak_counter - Function to check the status of the xpak counters
3166  *  @counter      : counter value to be updated
3167  *  @regs_stat    : registers status
3168  *  @index        : index
3169  *  @flag         : flag to indicate the status
3170  *  @type         : counter type
3171  *  Description:
3172  *  This function is to check the status of the xpak counters value
3173  *  NONE
3174  */
3175 
s2io_chk_xpak_counter(u64 * counter,u64 * regs_stat,u32 index,u16 flag,u16 type)3176 static void s2io_chk_xpak_counter(u64 *counter, u64 * regs_stat, u32 index,
3177 				  u16 flag, u16 type)
3178 {
3179 	u64 mask = 0x3;
3180 	u64 val64;
3181 	int i;
3182 	for (i = 0; i < index; i++)
3183 		mask = mask << 0x2;
3184 
3185 	if (flag > 0) {
3186 		*counter = *counter + 1;
3187 		val64 = *regs_stat & mask;
3188 		val64 = val64 >> (index * 0x2);
3189 		val64 = val64 + 1;
3190 		if (val64 == 3) {
3191 			switch (type) {
3192 			case 1:
3193 				DBG_PRINT(ERR_DBG,
3194 					  "Take Xframe NIC out of service.\n");
3195 				DBG_PRINT(ERR_DBG,
3196 "Excessive temperatures may result in premature transceiver failure.\n");
3197 				break;
3198 			case 2:
3199 				DBG_PRINT(ERR_DBG,
3200 					  "Take Xframe NIC out of service.\n");
3201 				DBG_PRINT(ERR_DBG,
3202 "Excessive bias currents may indicate imminent laser diode failure.\n");
3203 				break;
3204 			case 3:
3205 				DBG_PRINT(ERR_DBG,
3206 					  "Take Xframe NIC out of service.\n");
3207 				DBG_PRINT(ERR_DBG,
3208 "Excessive laser output power may saturate far-end receiver.\n");
3209 				break;
3210 			default:
3211 				DBG_PRINT(ERR_DBG,
3212 					  "Incorrect XPAK Alarm type\n");
3213 			}
3214 			val64 = 0x0;
3215 		}
3216 		val64 = val64 << (index * 0x2);
3217 		*regs_stat = (*regs_stat & (~mask)) | (val64);
3218 
3219 	} else {
3220 		*regs_stat = *regs_stat & (~mask);
3221 	}
3222 }
3223 
3224 /**
3225  *  s2io_updt_xpak_counter - Function to update the xpak counters
3226  *  @dev         : pointer to net_device struct
3227  *  Description:
3228  *  This function is to upate the status of the xpak counters value
3229  *  NONE
3230  */
s2io_updt_xpak_counter(struct net_device * dev)3231 static void s2io_updt_xpak_counter(struct net_device *dev)
3232 {
3233 	u16 flag  = 0x0;
3234 	u16 type  = 0x0;
3235 	u16 val16 = 0x0;
3236 	u64 val64 = 0x0;
3237 	u64 addr  = 0x0;
3238 
3239 	struct s2io_nic *sp = netdev_priv(dev);
3240 	struct stat_block *stats = sp->mac_control.stats_info;
3241 	struct xpakStat *xstats = &stats->xpak_stat;
3242 
3243 	/* Check the communication with the MDIO slave */
3244 	addr = MDIO_CTRL1;
3245 	val64 = 0x0;
3246 	val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3247 	if ((val64 == 0xFFFF) || (val64 == 0x0000)) {
3248 		DBG_PRINT(ERR_DBG,
3249 			  "ERR: MDIO slave access failed - Returned %llx\n",
3250 			  (unsigned long long)val64);
3251 		return;
3252 	}
3253 
3254 	/* Check for the expected value of control reg 1 */
3255 	if (val64 != MDIO_CTRL1_SPEED10G) {
3256 		DBG_PRINT(ERR_DBG, "Incorrect value at PMA address 0x0000 - "
3257 			  "Returned: %llx- Expected: 0x%x\n",
3258 			  (unsigned long long)val64, MDIO_CTRL1_SPEED10G);
3259 		return;
3260 	}
3261 
3262 	/* Loading the DOM register to MDIO register */
3263 	addr = 0xA100;
3264 	s2io_mdio_write(MDIO_MMD_PMAPMD, addr, val16, dev);
3265 	val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3266 
3267 	/* Reading the Alarm flags */
3268 	addr = 0xA070;
3269 	val64 = 0x0;
3270 	val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3271 
3272 	flag = CHECKBIT(val64, 0x7);
3273 	type = 1;
3274 	s2io_chk_xpak_counter(&xstats->alarm_transceiver_temp_high,
3275 			      &xstats->xpak_regs_stat,
3276 			      0x0, flag, type);
3277 
3278 	if (CHECKBIT(val64, 0x6))
3279 		xstats->alarm_transceiver_temp_low++;
3280 
3281 	flag = CHECKBIT(val64, 0x3);
3282 	type = 2;
3283 	s2io_chk_xpak_counter(&xstats->alarm_laser_bias_current_high,
3284 			      &xstats->xpak_regs_stat,
3285 			      0x2, flag, type);
3286 
3287 	if (CHECKBIT(val64, 0x2))
3288 		xstats->alarm_laser_bias_current_low++;
3289 
3290 	flag = CHECKBIT(val64, 0x1);
3291 	type = 3;
3292 	s2io_chk_xpak_counter(&xstats->alarm_laser_output_power_high,
3293 			      &xstats->xpak_regs_stat,
3294 			      0x4, flag, type);
3295 
3296 	if (CHECKBIT(val64, 0x0))
3297 		xstats->alarm_laser_output_power_low++;
3298 
3299 	/* Reading the Warning flags */
3300 	addr = 0xA074;
3301 	val64 = 0x0;
3302 	val64 = s2io_mdio_read(MDIO_MMD_PMAPMD, addr, dev);
3303 
3304 	if (CHECKBIT(val64, 0x7))
3305 		xstats->warn_transceiver_temp_high++;
3306 
3307 	if (CHECKBIT(val64, 0x6))
3308 		xstats->warn_transceiver_temp_low++;
3309 
3310 	if (CHECKBIT(val64, 0x3))
3311 		xstats->warn_laser_bias_current_high++;
3312 
3313 	if (CHECKBIT(val64, 0x2))
3314 		xstats->warn_laser_bias_current_low++;
3315 
3316 	if (CHECKBIT(val64, 0x1))
3317 		xstats->warn_laser_output_power_high++;
3318 
3319 	if (CHECKBIT(val64, 0x0))
3320 		xstats->warn_laser_output_power_low++;
3321 }
3322 
3323 /**
3324  *  wait_for_cmd_complete - waits for a command to complete.
3325  *  @addr: address
3326  *  @busy_bit: bit to check for busy
3327  *  @bit_state: state to check
3328  *  @may_sleep: parameter indicates if sleeping when waiting for
3329  *  command complete
3330  *  Description: Function that waits for a command to Write into RMAC
3331  *  ADDR DATA registers to be completed and returns either success or
3332  *  error depending on whether the command was complete or not.
3333  *  Return value:
3334  *   SUCCESS on success and FAILURE on failure.
3335  */
3336 
wait_for_cmd_complete(void __iomem * addr,u64 busy_bit,int bit_state,bool may_sleep)3337 static int wait_for_cmd_complete(void __iomem *addr, u64 busy_bit,
3338 				 int bit_state, bool may_sleep)
3339 {
3340 	int ret = FAILURE, cnt = 0, delay = 1;
3341 	u64 val64;
3342 
3343 	if ((bit_state != S2IO_BIT_RESET) && (bit_state != S2IO_BIT_SET))
3344 		return FAILURE;
3345 
3346 	do {
3347 		val64 = readq(addr);
3348 		if (bit_state == S2IO_BIT_RESET) {
3349 			if (!(val64 & busy_bit)) {
3350 				ret = SUCCESS;
3351 				break;
3352 			}
3353 		} else {
3354 			if (val64 & busy_bit) {
3355 				ret = SUCCESS;
3356 				break;
3357 			}
3358 		}
3359 
3360 		if (!may_sleep)
3361 			mdelay(delay);
3362 		else
3363 			msleep(delay);
3364 
3365 		if (++cnt >= 10)
3366 			delay = 50;
3367 	} while (cnt < 20);
3368 	return ret;
3369 }
3370 /**
3371  * check_pci_device_id - Checks if the device id is supported
3372  * @id : device id
3373  * Description: Function to check if the pci device id is supported by driver.
3374  * Return value: Actual device id if supported else PCI_ANY_ID
3375  */
check_pci_device_id(u16 id)3376 static u16 check_pci_device_id(u16 id)
3377 {
3378 	switch (id) {
3379 	case PCI_DEVICE_ID_HERC_WIN:
3380 	case PCI_DEVICE_ID_HERC_UNI:
3381 		return XFRAME_II_DEVICE;
3382 	case PCI_DEVICE_ID_S2IO_UNI:
3383 	case PCI_DEVICE_ID_S2IO_WIN:
3384 		return XFRAME_I_DEVICE;
3385 	default:
3386 		return PCI_ANY_ID;
3387 	}
3388 }
3389 
3390 /**
3391  *  s2io_reset - Resets the card.
3392  *  @sp : private member of the device structure.
3393  *  Description: Function to Reset the card. This function then also
3394  *  restores the previously saved PCI configuration space registers as
3395  *  the card reset also resets the configuration space.
3396  *  Return value:
3397  *  void.
3398  */
3399 
s2io_reset(struct s2io_nic * sp)3400 static void s2io_reset(struct s2io_nic *sp)
3401 {
3402 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
3403 	u64 val64;
3404 	u16 subid, pci_cmd;
3405 	int i;
3406 	u16 val16;
3407 	unsigned long long up_cnt, down_cnt, up_time, down_time, reset_cnt;
3408 	unsigned long long mem_alloc_cnt, mem_free_cnt, watchdog_cnt;
3409 	struct stat_block *stats;
3410 	struct swStat *swstats;
3411 
3412 	DBG_PRINT(INIT_DBG, "%s: Resetting XFrame card %s\n",
3413 		  __func__, pci_name(sp->pdev));
3414 
3415 	/* Back up  the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
3416 	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
3417 
3418 	val64 = SW_RESET_ALL;
3419 	writeq(val64, &bar0->sw_reset);
3420 	if (strstr(sp->product_name, "CX4"))
3421 		msleep(750);
3422 	msleep(250);
3423 	for (i = 0; i < S2IO_MAX_PCI_CONFIG_SPACE_REINIT; i++) {
3424 
3425 		/* Restore the PCI state saved during initialization. */
3426 		pci_restore_state(sp->pdev);
3427 		pci_save_state(sp->pdev);
3428 		pci_read_config_word(sp->pdev, 0x2, &val16);
3429 		if (check_pci_device_id(val16) != (u16)PCI_ANY_ID)
3430 			break;
3431 		msleep(200);
3432 	}
3433 
3434 	if (check_pci_device_id(val16) == (u16)PCI_ANY_ID)
3435 		DBG_PRINT(ERR_DBG, "%s SW_Reset failed!\n", __func__);
3436 
3437 	pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER, pci_cmd);
3438 
3439 	s2io_init_pci(sp);
3440 
3441 	/* Set swapper to enable I/O register access */
3442 	s2io_set_swapper(sp);
3443 
3444 	/* restore mac_addr entries */
3445 	do_s2io_restore_unicast_mc(sp);
3446 
3447 	/* Restore the MSIX table entries from local variables */
3448 	restore_xmsi_data(sp);
3449 
3450 	/* Clear certain PCI/PCI-X fields after reset */
3451 	if (sp->device_type == XFRAME_II_DEVICE) {
3452 		/* Clear "detected parity error" bit */
3453 		pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
3454 
3455 		/* Clearing PCIX Ecc status register */
3456 		pci_write_config_dword(sp->pdev, 0x68, 0x7C);
3457 
3458 		/* Clearing PCI_STATUS error reflected here */
3459 		writeq(s2BIT(62), &bar0->txpic_int_reg);
3460 	}
3461 
3462 	/* Reset device statistics maintained by OS */
3463 	memset(&sp->stats, 0, sizeof(struct net_device_stats));
3464 
3465 	stats = sp->mac_control.stats_info;
3466 	swstats = &stats->sw_stat;
3467 
3468 	/* save link up/down time/cnt, reset/memory/watchdog cnt */
3469 	up_cnt = swstats->link_up_cnt;
3470 	down_cnt = swstats->link_down_cnt;
3471 	up_time = swstats->link_up_time;
3472 	down_time = swstats->link_down_time;
3473 	reset_cnt = swstats->soft_reset_cnt;
3474 	mem_alloc_cnt = swstats->mem_allocated;
3475 	mem_free_cnt = swstats->mem_freed;
3476 	watchdog_cnt = swstats->watchdog_timer_cnt;
3477 
3478 	memset(stats, 0, sizeof(struct stat_block));
3479 
3480 	/* restore link up/down time/cnt, reset/memory/watchdog cnt */
3481 	swstats->link_up_cnt = up_cnt;
3482 	swstats->link_down_cnt = down_cnt;
3483 	swstats->link_up_time = up_time;
3484 	swstats->link_down_time = down_time;
3485 	swstats->soft_reset_cnt = reset_cnt;
3486 	swstats->mem_allocated = mem_alloc_cnt;
3487 	swstats->mem_freed = mem_free_cnt;
3488 	swstats->watchdog_timer_cnt = watchdog_cnt;
3489 
3490 	/* SXE-002: Configure link and activity LED to turn it off */
3491 	subid = sp->pdev->subsystem_device;
3492 	if (((subid & 0xFF) >= 0x07) &&
3493 	    (sp->device_type == XFRAME_I_DEVICE)) {
3494 		val64 = readq(&bar0->gpio_control);
3495 		val64 |= 0x0000800000000000ULL;
3496 		writeq(val64, &bar0->gpio_control);
3497 		val64 = 0x0411040400000000ULL;
3498 		writeq(val64, (void __iomem *)bar0 + 0x2700);
3499 	}
3500 
3501 	/*
3502 	 * Clear spurious ECC interrupts that would have occurred on
3503 	 * XFRAME II cards after reset.
3504 	 */
3505 	if (sp->device_type == XFRAME_II_DEVICE) {
3506 		val64 = readq(&bar0->pcc_err_reg);
3507 		writeq(val64, &bar0->pcc_err_reg);
3508 	}
3509 
3510 	sp->device_enabled_once = false;
3511 }
3512 
3513 /**
3514  *  s2io_set_swapper - to set the swapper controle on the card
3515  *  @sp : private member of the device structure,
3516  *  pointer to the s2io_nic structure.
3517  *  Description: Function to set the swapper control on the card
3518  *  correctly depending on the 'endianness' of the system.
3519  *  Return value:
3520  *  SUCCESS on success and FAILURE on failure.
3521  */
3522 
s2io_set_swapper(struct s2io_nic * sp)3523 static int s2io_set_swapper(struct s2io_nic *sp)
3524 {
3525 	struct net_device *dev = sp->dev;
3526 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
3527 	u64 val64, valt, valr;
3528 
3529 	/*
3530 	 * Set proper endian settings and verify the same by reading
3531 	 * the PIF Feed-back register.
3532 	 */
3533 
3534 	val64 = readq(&bar0->pif_rd_swapper_fb);
3535 	if (val64 != 0x0123456789ABCDEFULL) {
3536 		int i = 0;
3537 		static const u64 value[] = {
3538 			0xC30000C3C30000C3ULL,	/* FE=1, SE=1 */
3539 			0x8100008181000081ULL,	/* FE=1, SE=0 */
3540 			0x4200004242000042ULL,	/* FE=0, SE=1 */
3541 			0			/* FE=0, SE=0 */
3542 		};
3543 
3544 		while (i < 4) {
3545 			writeq(value[i], &bar0->swapper_ctrl);
3546 			val64 = readq(&bar0->pif_rd_swapper_fb);
3547 			if (val64 == 0x0123456789ABCDEFULL)
3548 				break;
3549 			i++;
3550 		}
3551 		if (i == 4) {
3552 			DBG_PRINT(ERR_DBG, "%s: Endian settings are wrong, "
3553 				  "feedback read %llx\n",
3554 				  dev->name, (unsigned long long)val64);
3555 			return FAILURE;
3556 		}
3557 		valr = value[i];
3558 	} else {
3559 		valr = readq(&bar0->swapper_ctrl);
3560 	}
3561 
3562 	valt = 0x0123456789ABCDEFULL;
3563 	writeq(valt, &bar0->xmsi_address);
3564 	val64 = readq(&bar0->xmsi_address);
3565 
3566 	if (val64 != valt) {
3567 		int i = 0;
3568 		static const u64 value[] = {
3569 			0x00C3C30000C3C300ULL,	/* FE=1, SE=1 */
3570 			0x0081810000818100ULL,	/* FE=1, SE=0 */
3571 			0x0042420000424200ULL,	/* FE=0, SE=1 */
3572 			0			/* FE=0, SE=0 */
3573 		};
3574 
3575 		while (i < 4) {
3576 			writeq((value[i] | valr), &bar0->swapper_ctrl);
3577 			writeq(valt, &bar0->xmsi_address);
3578 			val64 = readq(&bar0->xmsi_address);
3579 			if (val64 == valt)
3580 				break;
3581 			i++;
3582 		}
3583 		if (i == 4) {
3584 			unsigned long long x = val64;
3585 			DBG_PRINT(ERR_DBG,
3586 				  "Write failed, Xmsi_addr reads:0x%llx\n", x);
3587 			return FAILURE;
3588 		}
3589 	}
3590 	val64 = readq(&bar0->swapper_ctrl);
3591 	val64 &= 0xFFFF000000000000ULL;
3592 
3593 #ifdef __BIG_ENDIAN
3594 	/*
3595 	 * The device by default set to a big endian format, so a
3596 	 * big endian driver need not set anything.
3597 	 */
3598 	val64 |= (SWAPPER_CTRL_TXP_FE |
3599 		  SWAPPER_CTRL_TXP_SE |
3600 		  SWAPPER_CTRL_TXD_R_FE |
3601 		  SWAPPER_CTRL_TXD_W_FE |
3602 		  SWAPPER_CTRL_TXF_R_FE |
3603 		  SWAPPER_CTRL_RXD_R_FE |
3604 		  SWAPPER_CTRL_RXD_W_FE |
3605 		  SWAPPER_CTRL_RXF_W_FE |
3606 		  SWAPPER_CTRL_XMSI_FE |
3607 		  SWAPPER_CTRL_STATS_FE |
3608 		  SWAPPER_CTRL_STATS_SE);
3609 	if (sp->config.intr_type == INTA)
3610 		val64 |= SWAPPER_CTRL_XMSI_SE;
3611 	writeq(val64, &bar0->swapper_ctrl);
3612 #else
3613 	/*
3614 	 * Initially we enable all bits to make it accessible by the
3615 	 * driver, then we selectively enable only those bits that
3616 	 * we want to set.
3617 	 */
3618 	val64 |= (SWAPPER_CTRL_TXP_FE |
3619 		  SWAPPER_CTRL_TXP_SE |
3620 		  SWAPPER_CTRL_TXD_R_FE |
3621 		  SWAPPER_CTRL_TXD_R_SE |
3622 		  SWAPPER_CTRL_TXD_W_FE |
3623 		  SWAPPER_CTRL_TXD_W_SE |
3624 		  SWAPPER_CTRL_TXF_R_FE |
3625 		  SWAPPER_CTRL_RXD_R_FE |
3626 		  SWAPPER_CTRL_RXD_R_SE |
3627 		  SWAPPER_CTRL_RXD_W_FE |
3628 		  SWAPPER_CTRL_RXD_W_SE |
3629 		  SWAPPER_CTRL_RXF_W_FE |
3630 		  SWAPPER_CTRL_XMSI_FE |
3631 		  SWAPPER_CTRL_STATS_FE |
3632 		  SWAPPER_CTRL_STATS_SE);
3633 	if (sp->config.intr_type == INTA)
3634 		val64 |= SWAPPER_CTRL_XMSI_SE;
3635 	writeq(val64, &bar0->swapper_ctrl);
3636 #endif
3637 	val64 = readq(&bar0->swapper_ctrl);
3638 
3639 	/*
3640 	 * Verifying if endian settings are accurate by reading a
3641 	 * feedback register.
3642 	 */
3643 	val64 = readq(&bar0->pif_rd_swapper_fb);
3644 	if (val64 != 0x0123456789ABCDEFULL) {
3645 		/* Endian settings are incorrect, calls for another dekko. */
3646 		DBG_PRINT(ERR_DBG,
3647 			  "%s: Endian settings are wrong, feedback read %llx\n",
3648 			  dev->name, (unsigned long long)val64);
3649 		return FAILURE;
3650 	}
3651 
3652 	return SUCCESS;
3653 }
3654 
wait_for_msix_trans(struct s2io_nic * nic,int i)3655 static int wait_for_msix_trans(struct s2io_nic *nic, int i)
3656 {
3657 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
3658 	u64 val64;
3659 	int ret = 0, cnt = 0;
3660 
3661 	do {
3662 		val64 = readq(&bar0->xmsi_access);
3663 		if (!(val64 & s2BIT(15)))
3664 			break;
3665 		mdelay(1);
3666 		cnt++;
3667 	} while (cnt < 5);
3668 	if (cnt == 5) {
3669 		DBG_PRINT(ERR_DBG, "XMSI # %d Access failed\n", i);
3670 		ret = 1;
3671 	}
3672 
3673 	return ret;
3674 }
3675 
restore_xmsi_data(struct s2io_nic * nic)3676 static void restore_xmsi_data(struct s2io_nic *nic)
3677 {
3678 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
3679 	u64 val64;
3680 	int i, msix_index;
3681 
3682 	if (nic->device_type == XFRAME_I_DEVICE)
3683 		return;
3684 
3685 	for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3686 		msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3687 		writeq(nic->msix_info[i].addr, &bar0->xmsi_address);
3688 		writeq(nic->msix_info[i].data, &bar0->xmsi_data);
3689 		val64 = (s2BIT(7) | s2BIT(15) | vBIT(msix_index, 26, 6));
3690 		writeq(val64, &bar0->xmsi_access);
3691 		if (wait_for_msix_trans(nic, msix_index))
3692 			DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3693 				  __func__, msix_index);
3694 	}
3695 }
3696 
store_xmsi_data(struct s2io_nic * nic)3697 static void store_xmsi_data(struct s2io_nic *nic)
3698 {
3699 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
3700 	u64 val64, addr, data;
3701 	int i, msix_index;
3702 
3703 	if (nic->device_type == XFRAME_I_DEVICE)
3704 		return;
3705 
3706 	/* Store and display */
3707 	for (i = 0; i < MAX_REQUESTED_MSI_X; i++) {
3708 		msix_index = (i) ? ((i-1) * 8 + 1) : 0;
3709 		val64 = (s2BIT(15) | vBIT(msix_index, 26, 6));
3710 		writeq(val64, &bar0->xmsi_access);
3711 		if (wait_for_msix_trans(nic, msix_index)) {
3712 			DBG_PRINT(ERR_DBG, "%s: index: %d failed\n",
3713 				  __func__, msix_index);
3714 			continue;
3715 		}
3716 		addr = readq(&bar0->xmsi_address);
3717 		data = readq(&bar0->xmsi_data);
3718 		if (addr && data) {
3719 			nic->msix_info[i].addr = addr;
3720 			nic->msix_info[i].data = data;
3721 		}
3722 	}
3723 }
3724 
s2io_enable_msi_x(struct s2io_nic * nic)3725 static int s2io_enable_msi_x(struct s2io_nic *nic)
3726 {
3727 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
3728 	u64 rx_mat;
3729 	u16 msi_control; /* Temp variable */
3730 	int ret, i, j, msix_indx = 1;
3731 	int size;
3732 	struct stat_block *stats = nic->mac_control.stats_info;
3733 	struct swStat *swstats = &stats->sw_stat;
3734 
3735 	size = nic->num_entries * sizeof(struct msix_entry);
3736 	nic->entries = kzalloc(size, GFP_KERNEL);
3737 	if (!nic->entries) {
3738 		DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3739 			  __func__);
3740 		swstats->mem_alloc_fail_cnt++;
3741 		return -ENOMEM;
3742 	}
3743 	swstats->mem_allocated += size;
3744 
3745 	size = nic->num_entries * sizeof(struct s2io_msix_entry);
3746 	nic->s2io_entries = kzalloc(size, GFP_KERNEL);
3747 	if (!nic->s2io_entries) {
3748 		DBG_PRINT(INFO_DBG, "%s: Memory allocation failed\n",
3749 			  __func__);
3750 		swstats->mem_alloc_fail_cnt++;
3751 		kfree(nic->entries);
3752 		swstats->mem_freed
3753 			+= (nic->num_entries * sizeof(struct msix_entry));
3754 		return -ENOMEM;
3755 	}
3756 	swstats->mem_allocated += size;
3757 
3758 	nic->entries[0].entry = 0;
3759 	nic->s2io_entries[0].entry = 0;
3760 	nic->s2io_entries[0].in_use = MSIX_FLG;
3761 	nic->s2io_entries[0].type = MSIX_ALARM_TYPE;
3762 	nic->s2io_entries[0].arg = &nic->mac_control.fifos;
3763 
3764 	for (i = 1; i < nic->num_entries; i++) {
3765 		nic->entries[i].entry = ((i - 1) * 8) + 1;
3766 		nic->s2io_entries[i].entry = ((i - 1) * 8) + 1;
3767 		nic->s2io_entries[i].arg = NULL;
3768 		nic->s2io_entries[i].in_use = 0;
3769 	}
3770 
3771 	rx_mat = readq(&bar0->rx_mat);
3772 	for (j = 0; j < nic->config.rx_ring_num; j++) {
3773 		rx_mat |= RX_MAT_SET(j, msix_indx);
3774 		nic->s2io_entries[j+1].arg = &nic->mac_control.rings[j];
3775 		nic->s2io_entries[j+1].type = MSIX_RING_TYPE;
3776 		nic->s2io_entries[j+1].in_use = MSIX_FLG;
3777 		msix_indx += 8;
3778 	}
3779 	writeq(rx_mat, &bar0->rx_mat);
3780 	readq(&bar0->rx_mat);
3781 
3782 	ret = pci_enable_msix_range(nic->pdev, nic->entries,
3783 				    nic->num_entries, nic->num_entries);
3784 	/* We fail init if error or we get less vectors than min required */
3785 	if (ret < 0) {
3786 		DBG_PRINT(ERR_DBG, "Enabling MSI-X failed\n");
3787 		kfree(nic->entries);
3788 		swstats->mem_freed += nic->num_entries *
3789 			sizeof(struct msix_entry);
3790 		kfree(nic->s2io_entries);
3791 		swstats->mem_freed += nic->num_entries *
3792 			sizeof(struct s2io_msix_entry);
3793 		nic->entries = NULL;
3794 		nic->s2io_entries = NULL;
3795 		return -ENOMEM;
3796 	}
3797 
3798 	/*
3799 	 * To enable MSI-X, MSI also needs to be enabled, due to a bug
3800 	 * in the herc NIC. (Temp change, needs to be removed later)
3801 	 */
3802 	pci_read_config_word(nic->pdev, 0x42, &msi_control);
3803 	msi_control |= 0x1; /* Enable MSI */
3804 	pci_write_config_word(nic->pdev, 0x42, msi_control);
3805 
3806 	return 0;
3807 }
3808 
3809 /* Handle software interrupt used during MSI(X) test */
s2io_test_intr(int irq,void * dev_id)3810 static irqreturn_t s2io_test_intr(int irq, void *dev_id)
3811 {
3812 	struct s2io_nic *sp = dev_id;
3813 
3814 	sp->msi_detected = 1;
3815 	wake_up(&sp->msi_wait);
3816 
3817 	return IRQ_HANDLED;
3818 }
3819 
3820 /* Test interrupt path by forcing a software IRQ */
s2io_test_msi(struct s2io_nic * sp)3821 static int s2io_test_msi(struct s2io_nic *sp)
3822 {
3823 	struct pci_dev *pdev = sp->pdev;
3824 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
3825 	int err;
3826 	u64 val64, saved64;
3827 
3828 	err = request_irq(sp->entries[1].vector, s2io_test_intr, 0,
3829 			  sp->name, sp);
3830 	if (err) {
3831 		DBG_PRINT(ERR_DBG, "%s: PCI %s: cannot assign irq %d\n",
3832 			  sp->dev->name, pci_name(pdev), pdev->irq);
3833 		return err;
3834 	}
3835 
3836 	init_waitqueue_head(&sp->msi_wait);
3837 	sp->msi_detected = 0;
3838 
3839 	saved64 = val64 = readq(&bar0->scheduled_int_ctrl);
3840 	val64 |= SCHED_INT_CTRL_ONE_SHOT;
3841 	val64 |= SCHED_INT_CTRL_TIMER_EN;
3842 	val64 |= SCHED_INT_CTRL_INT2MSI(1);
3843 	writeq(val64, &bar0->scheduled_int_ctrl);
3844 
3845 	wait_event_timeout(sp->msi_wait, sp->msi_detected, HZ/10);
3846 
3847 	if (!sp->msi_detected) {
3848 		/* MSI(X) test failed, go back to INTx mode */
3849 		DBG_PRINT(ERR_DBG, "%s: PCI %s: No interrupt was generated "
3850 			  "using MSI(X) during test\n",
3851 			  sp->dev->name, pci_name(pdev));
3852 
3853 		err = -EOPNOTSUPP;
3854 	}
3855 
3856 	free_irq(sp->entries[1].vector, sp);
3857 
3858 	writeq(saved64, &bar0->scheduled_int_ctrl);
3859 
3860 	return err;
3861 }
3862 
remove_msix_isr(struct s2io_nic * sp)3863 static void remove_msix_isr(struct s2io_nic *sp)
3864 {
3865 	int i;
3866 	u16 msi_control;
3867 
3868 	for (i = 0; i < sp->num_entries; i++) {
3869 		if (sp->s2io_entries[i].in_use == MSIX_REGISTERED_SUCCESS) {
3870 			int vector = sp->entries[i].vector;
3871 			void *arg = sp->s2io_entries[i].arg;
3872 			free_irq(vector, arg);
3873 		}
3874 	}
3875 
3876 	kfree(sp->entries);
3877 	kfree(sp->s2io_entries);
3878 	sp->entries = NULL;
3879 	sp->s2io_entries = NULL;
3880 
3881 	pci_read_config_word(sp->pdev, 0x42, &msi_control);
3882 	msi_control &= 0xFFFE; /* Disable MSI */
3883 	pci_write_config_word(sp->pdev, 0x42, msi_control);
3884 
3885 	pci_disable_msix(sp->pdev);
3886 }
3887 
remove_inta_isr(struct s2io_nic * sp)3888 static void remove_inta_isr(struct s2io_nic *sp)
3889 {
3890 	free_irq(sp->pdev->irq, sp->dev);
3891 }
3892 
3893 /* ********************************************************* *
3894  * Functions defined below concern the OS part of the driver *
3895  * ********************************************************* */
3896 
3897 /**
3898  *  s2io_open - open entry point of the driver
3899  *  @dev : pointer to the device structure.
3900  *  Description:
3901  *  This function is the open entry point of the driver. It mainly calls a
3902  *  function to allocate Rx buffers and inserts them into the buffer
3903  *  descriptors and then enables the Rx part of the NIC.
3904  *  Return value:
3905  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3906  *   file on failure.
3907  */
3908 
s2io_open(struct net_device * dev)3909 static int s2io_open(struct net_device *dev)
3910 {
3911 	struct s2io_nic *sp = netdev_priv(dev);
3912 	struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
3913 	int err = 0;
3914 
3915 	/*
3916 	 * Make sure you have link off by default every time
3917 	 * Nic is initialized
3918 	 */
3919 	netif_carrier_off(dev);
3920 	sp->last_link_state = 0;
3921 
3922 	/* Initialize H/W and enable interrupts */
3923 	err = s2io_card_up(sp);
3924 	if (err) {
3925 		DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
3926 			  dev->name);
3927 		goto hw_init_failed;
3928 	}
3929 
3930 	if (do_s2io_prog_unicast(dev, dev->dev_addr) == FAILURE) {
3931 		DBG_PRINT(ERR_DBG, "Set Mac Address Failed\n");
3932 		s2io_card_down(sp);
3933 		err = -ENODEV;
3934 		goto hw_init_failed;
3935 	}
3936 	s2io_start_all_tx_queue(sp);
3937 	return 0;
3938 
3939 hw_init_failed:
3940 	if (sp->config.intr_type == MSI_X) {
3941 		if (sp->entries) {
3942 			kfree(sp->entries);
3943 			swstats->mem_freed += sp->num_entries *
3944 				sizeof(struct msix_entry);
3945 		}
3946 		if (sp->s2io_entries) {
3947 			kfree(sp->s2io_entries);
3948 			swstats->mem_freed += sp->num_entries *
3949 				sizeof(struct s2io_msix_entry);
3950 		}
3951 	}
3952 	return err;
3953 }
3954 
3955 /**
3956  *  s2io_close -close entry point of the driver
3957  *  @dev : device pointer.
3958  *  Description:
3959  *  This is the stop entry point of the driver. It needs to undo exactly
3960  *  whatever was done by the open entry point,thus it's usually referred to
3961  *  as the close function.Among other things this function mainly stops the
3962  *  Rx side of the NIC and frees all the Rx buffers in the Rx rings.
3963  *  Return value:
3964  *  0 on success and an appropriate (-)ve integer as defined in errno.h
3965  *  file on failure.
3966  */
3967 
s2io_close(struct net_device * dev)3968 static int s2io_close(struct net_device *dev)
3969 {
3970 	struct s2io_nic *sp = netdev_priv(dev);
3971 	struct config_param *config = &sp->config;
3972 	u64 tmp64;
3973 	int offset;
3974 
3975 	/* Return if the device is already closed               *
3976 	 *  Can happen when s2io_card_up failed in change_mtu    *
3977 	 */
3978 	if (!is_s2io_card_up(sp))
3979 		return 0;
3980 
3981 	s2io_stop_all_tx_queue(sp);
3982 	/* delete all populated mac entries */
3983 	for (offset = 1; offset < config->max_mc_addr; offset++) {
3984 		tmp64 = do_s2io_read_unicast_mc(sp, offset);
3985 		if (tmp64 != S2IO_DISABLE_MAC_ENTRY)
3986 			do_s2io_delete_unicast_mc(sp, tmp64);
3987 	}
3988 
3989 	s2io_card_down(sp);
3990 
3991 	return 0;
3992 }
3993 
3994 /**
3995  *  s2io_xmit - Tx entry point of te driver
3996  *  @skb : the socket buffer containing the Tx data.
3997  *  @dev : device pointer.
3998  *  Description :
3999  *  This function is the Tx entry point of the driver. S2IO NIC supports
4000  *  certain protocol assist features on Tx side, namely  CSO, S/G, LSO.
4001  *  NOTE: when device can't queue the pkt,just the trans_start variable will
4002  *  not be upadted.
4003  *  Return value:
4004  *  0 on success & 1 on failure.
4005  */
4006 
s2io_xmit(struct sk_buff * skb,struct net_device * dev)4007 static netdev_tx_t s2io_xmit(struct sk_buff *skb, struct net_device *dev)
4008 {
4009 	struct s2io_nic *sp = netdev_priv(dev);
4010 	u16 frg_cnt, frg_len, i, queue, queue_len, put_off, get_off;
4011 	register u64 val64;
4012 	struct TxD *txdp;
4013 	struct TxFIFO_element __iomem *tx_fifo;
4014 	unsigned long flags = 0;
4015 	u16 vlan_tag = 0;
4016 	struct fifo_info *fifo = NULL;
4017 	int offload_type;
4018 	int enable_per_list_interrupt = 0;
4019 	struct config_param *config = &sp->config;
4020 	struct mac_info *mac_control = &sp->mac_control;
4021 	struct stat_block *stats = mac_control->stats_info;
4022 	struct swStat *swstats = &stats->sw_stat;
4023 
4024 	DBG_PRINT(TX_DBG, "%s: In Neterion Tx routine\n", dev->name);
4025 
4026 	if (unlikely(skb->len <= 0)) {
4027 		DBG_PRINT(TX_DBG, "%s: Buffer has no data..\n", dev->name);
4028 		dev_kfree_skb_any(skb);
4029 		return NETDEV_TX_OK;
4030 	}
4031 
4032 	if (!is_s2io_card_up(sp)) {
4033 		DBG_PRINT(TX_DBG, "%s: Card going down for reset\n",
4034 			  dev->name);
4035 		dev_kfree_skb_any(skb);
4036 		return NETDEV_TX_OK;
4037 	}
4038 
4039 	queue = 0;
4040 	if (skb_vlan_tag_present(skb))
4041 		vlan_tag = skb_vlan_tag_get(skb);
4042 	if (sp->config.tx_steering_type == TX_DEFAULT_STEERING) {
4043 		if (skb->protocol == htons(ETH_P_IP)) {
4044 			struct iphdr *ip;
4045 			struct tcphdr *th;
4046 			ip = ip_hdr(skb);
4047 
4048 			if (!ip_is_fragment(ip)) {
4049 				th = (struct tcphdr *)(((unsigned char *)ip) +
4050 						       ip->ihl*4);
4051 
4052 				if (ip->protocol == IPPROTO_TCP) {
4053 					queue_len = sp->total_tcp_fifos;
4054 					queue = (ntohs(th->source) +
4055 						 ntohs(th->dest)) &
4056 						sp->fifo_selector[queue_len - 1];
4057 					if (queue >= queue_len)
4058 						queue = queue_len - 1;
4059 				} else if (ip->protocol == IPPROTO_UDP) {
4060 					queue_len = sp->total_udp_fifos;
4061 					queue = (ntohs(th->source) +
4062 						 ntohs(th->dest)) &
4063 						sp->fifo_selector[queue_len - 1];
4064 					if (queue >= queue_len)
4065 						queue = queue_len - 1;
4066 					queue += sp->udp_fifo_idx;
4067 					if (skb->len > 1024)
4068 						enable_per_list_interrupt = 1;
4069 				}
4070 			}
4071 		}
4072 	} else if (sp->config.tx_steering_type == TX_PRIORITY_STEERING)
4073 		/* get fifo number based on skb->priority value */
4074 		queue = config->fifo_mapping
4075 			[skb->priority & (MAX_TX_FIFOS - 1)];
4076 	fifo = &mac_control->fifos[queue];
4077 
4078 	spin_lock_irqsave(&fifo->tx_lock, flags);
4079 
4080 	if (sp->config.multiq) {
4081 		if (__netif_subqueue_stopped(dev, fifo->fifo_no)) {
4082 			spin_unlock_irqrestore(&fifo->tx_lock, flags);
4083 			return NETDEV_TX_BUSY;
4084 		}
4085 	} else if (unlikely(fifo->queue_state == FIFO_QUEUE_STOP)) {
4086 		if (netif_queue_stopped(dev)) {
4087 			spin_unlock_irqrestore(&fifo->tx_lock, flags);
4088 			return NETDEV_TX_BUSY;
4089 		}
4090 	}
4091 
4092 	put_off = (u16)fifo->tx_curr_put_info.offset;
4093 	get_off = (u16)fifo->tx_curr_get_info.offset;
4094 	txdp = fifo->list_info[put_off].list_virt_addr;
4095 
4096 	queue_len = fifo->tx_curr_put_info.fifo_len + 1;
4097 	/* Avoid "put" pointer going beyond "get" pointer */
4098 	if (txdp->Host_Control ||
4099 	    ((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4100 		DBG_PRINT(TX_DBG, "Error in xmit, No free TXDs.\n");
4101 		s2io_stop_tx_queue(sp, fifo->fifo_no);
4102 		dev_kfree_skb_any(skb);
4103 		spin_unlock_irqrestore(&fifo->tx_lock, flags);
4104 		return NETDEV_TX_OK;
4105 	}
4106 
4107 	offload_type = s2io_offload_type(skb);
4108 	if (offload_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
4109 		txdp->Control_1 |= TXD_TCP_LSO_EN;
4110 		txdp->Control_1 |= TXD_TCP_LSO_MSS(s2io_tcp_mss(skb));
4111 	}
4112 	if (skb->ip_summed == CHECKSUM_PARTIAL) {
4113 		txdp->Control_2 |= (TXD_TX_CKO_IPV4_EN |
4114 				    TXD_TX_CKO_TCP_EN |
4115 				    TXD_TX_CKO_UDP_EN);
4116 	}
4117 	txdp->Control_1 |= TXD_GATHER_CODE_FIRST;
4118 	txdp->Control_1 |= TXD_LIST_OWN_XENA;
4119 	txdp->Control_2 |= TXD_INT_NUMBER(fifo->fifo_no);
4120 	if (enable_per_list_interrupt)
4121 		if (put_off & (queue_len >> 5))
4122 			txdp->Control_2 |= TXD_INT_TYPE_PER_LIST;
4123 	if (vlan_tag) {
4124 		txdp->Control_2 |= TXD_VLAN_ENABLE;
4125 		txdp->Control_2 |= TXD_VLAN_TAG(vlan_tag);
4126 	}
4127 
4128 	frg_len = skb_headlen(skb);
4129 	txdp->Buffer_Pointer = dma_map_single(&sp->pdev->dev, skb->data,
4130 					      frg_len, DMA_TO_DEVICE);
4131 	if (dma_mapping_error(&sp->pdev->dev, txdp->Buffer_Pointer))
4132 		goto pci_map_failed;
4133 
4134 	txdp->Host_Control = (unsigned long)skb;
4135 	txdp->Control_1 |= TXD_BUFFER0_SIZE(frg_len);
4136 
4137 	frg_cnt = skb_shinfo(skb)->nr_frags;
4138 	/* For fragmented SKB. */
4139 	for (i = 0; i < frg_cnt; i++) {
4140 		const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4141 		/* A '0' length fragment will be ignored */
4142 		if (!skb_frag_size(frag))
4143 			continue;
4144 		txdp++;
4145 		txdp->Buffer_Pointer = (u64)skb_frag_dma_map(&sp->pdev->dev,
4146 							     frag, 0,
4147 							     skb_frag_size(frag),
4148 							     DMA_TO_DEVICE);
4149 		txdp->Control_1 = TXD_BUFFER0_SIZE(skb_frag_size(frag));
4150 	}
4151 	txdp->Control_1 |= TXD_GATHER_CODE_LAST;
4152 
4153 	tx_fifo = mac_control->tx_FIFO_start[queue];
4154 	val64 = fifo->list_info[put_off].list_phy_addr;
4155 	writeq(val64, &tx_fifo->TxDL_Pointer);
4156 
4157 	val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
4158 		 TX_FIFO_LAST_LIST);
4159 	if (offload_type)
4160 		val64 |= TX_FIFO_SPECIAL_FUNC;
4161 
4162 	writeq(val64, &tx_fifo->List_Control);
4163 
4164 	put_off++;
4165 	if (put_off == fifo->tx_curr_put_info.fifo_len + 1)
4166 		put_off = 0;
4167 	fifo->tx_curr_put_info.offset = put_off;
4168 
4169 	/* Avoid "put" pointer going beyond "get" pointer */
4170 	if (((put_off+1) == queue_len ? 0 : (put_off+1)) == get_off) {
4171 		swstats->fifo_full_cnt++;
4172 		DBG_PRINT(TX_DBG,
4173 			  "No free TxDs for xmit, Put: 0x%x Get:0x%x\n",
4174 			  put_off, get_off);
4175 		s2io_stop_tx_queue(sp, fifo->fifo_no);
4176 	}
4177 	swstats->mem_allocated += skb->truesize;
4178 	spin_unlock_irqrestore(&fifo->tx_lock, flags);
4179 
4180 	if (sp->config.intr_type == MSI_X)
4181 		tx_intr_handler(fifo);
4182 
4183 	return NETDEV_TX_OK;
4184 
4185 pci_map_failed:
4186 	swstats->pci_map_fail_cnt++;
4187 	s2io_stop_tx_queue(sp, fifo->fifo_no);
4188 	swstats->mem_freed += skb->truesize;
4189 	dev_kfree_skb_any(skb);
4190 	spin_unlock_irqrestore(&fifo->tx_lock, flags);
4191 	return NETDEV_TX_OK;
4192 }
4193 
4194 static void
s2io_alarm_handle(struct timer_list * t)4195 s2io_alarm_handle(struct timer_list *t)
4196 {
4197 	struct s2io_nic *sp = from_timer(sp, t, alarm_timer);
4198 	struct net_device *dev = sp->dev;
4199 
4200 	s2io_handle_errors(dev);
4201 	mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
4202 }
4203 
s2io_msix_ring_handle(int irq,void * dev_id)4204 static irqreturn_t s2io_msix_ring_handle(int irq, void *dev_id)
4205 {
4206 	struct ring_info *ring = (struct ring_info *)dev_id;
4207 	struct s2io_nic *sp = ring->nic;
4208 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
4209 
4210 	if (unlikely(!is_s2io_card_up(sp)))
4211 		return IRQ_HANDLED;
4212 
4213 	if (sp->config.napi) {
4214 		u8 __iomem *addr = NULL;
4215 		u8 val8 = 0;
4216 
4217 		addr = (u8 __iomem *)&bar0->xmsi_mask_reg;
4218 		addr += (7 - ring->ring_no);
4219 		val8 = (ring->ring_no == 0) ? 0x7f : 0xff;
4220 		writeb(val8, addr);
4221 		val8 = readb(addr);
4222 		napi_schedule(&ring->napi);
4223 	} else {
4224 		rx_intr_handler(ring, 0);
4225 		s2io_chk_rx_buffers(sp, ring);
4226 	}
4227 
4228 	return IRQ_HANDLED;
4229 }
4230 
s2io_msix_fifo_handle(int irq,void * dev_id)4231 static irqreturn_t s2io_msix_fifo_handle(int irq, void *dev_id)
4232 {
4233 	int i;
4234 	struct fifo_info *fifos = (struct fifo_info *)dev_id;
4235 	struct s2io_nic *sp = fifos->nic;
4236 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
4237 	struct config_param *config  = &sp->config;
4238 	u64 reason;
4239 
4240 	if (unlikely(!is_s2io_card_up(sp)))
4241 		return IRQ_NONE;
4242 
4243 	reason = readq(&bar0->general_int_status);
4244 	if (unlikely(reason == S2IO_MINUS_ONE))
4245 		/* Nothing much can be done. Get out */
4246 		return IRQ_HANDLED;
4247 
4248 	if (reason & (GEN_INTR_TXPIC | GEN_INTR_TXTRAFFIC)) {
4249 		writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4250 
4251 		if (reason & GEN_INTR_TXPIC)
4252 			s2io_txpic_intr_handle(sp);
4253 
4254 		if (reason & GEN_INTR_TXTRAFFIC)
4255 			writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4256 
4257 		for (i = 0; i < config->tx_fifo_num; i++)
4258 			tx_intr_handler(&fifos[i]);
4259 
4260 		writeq(sp->general_int_mask, &bar0->general_int_mask);
4261 		readl(&bar0->general_int_status);
4262 		return IRQ_HANDLED;
4263 	}
4264 	/* The interrupt was not raised by us */
4265 	return IRQ_NONE;
4266 }
4267 
s2io_txpic_intr_handle(struct s2io_nic * sp)4268 static void s2io_txpic_intr_handle(struct s2io_nic *sp)
4269 {
4270 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
4271 	u64 val64;
4272 
4273 	val64 = readq(&bar0->pic_int_status);
4274 	if (val64 & PIC_INT_GPIO) {
4275 		val64 = readq(&bar0->gpio_int_reg);
4276 		if ((val64 & GPIO_INT_REG_LINK_DOWN) &&
4277 		    (val64 & GPIO_INT_REG_LINK_UP)) {
4278 			/*
4279 			 * This is unstable state so clear both up/down
4280 			 * interrupt and adapter to re-evaluate the link state.
4281 			 */
4282 			val64 |= GPIO_INT_REG_LINK_DOWN;
4283 			val64 |= GPIO_INT_REG_LINK_UP;
4284 			writeq(val64, &bar0->gpio_int_reg);
4285 			val64 = readq(&bar0->gpio_int_mask);
4286 			val64 &= ~(GPIO_INT_MASK_LINK_UP |
4287 				   GPIO_INT_MASK_LINK_DOWN);
4288 			writeq(val64, &bar0->gpio_int_mask);
4289 		} else if (val64 & GPIO_INT_REG_LINK_UP) {
4290 			val64 = readq(&bar0->adapter_status);
4291 			/* Enable Adapter */
4292 			val64 = readq(&bar0->adapter_control);
4293 			val64 |= ADAPTER_CNTL_EN;
4294 			writeq(val64, &bar0->adapter_control);
4295 			val64 |= ADAPTER_LED_ON;
4296 			writeq(val64, &bar0->adapter_control);
4297 			if (!sp->device_enabled_once)
4298 				sp->device_enabled_once = 1;
4299 
4300 			s2io_link(sp, LINK_UP);
4301 			/*
4302 			 * unmask link down interrupt and mask link-up
4303 			 * intr
4304 			 */
4305 			val64 = readq(&bar0->gpio_int_mask);
4306 			val64 &= ~GPIO_INT_MASK_LINK_DOWN;
4307 			val64 |= GPIO_INT_MASK_LINK_UP;
4308 			writeq(val64, &bar0->gpio_int_mask);
4309 
4310 		} else if (val64 & GPIO_INT_REG_LINK_DOWN) {
4311 			val64 = readq(&bar0->adapter_status);
4312 			s2io_link(sp, LINK_DOWN);
4313 			/* Link is down so unmaks link up interrupt */
4314 			val64 = readq(&bar0->gpio_int_mask);
4315 			val64 &= ~GPIO_INT_MASK_LINK_UP;
4316 			val64 |= GPIO_INT_MASK_LINK_DOWN;
4317 			writeq(val64, &bar0->gpio_int_mask);
4318 
4319 			/* turn off LED */
4320 			val64 = readq(&bar0->adapter_control);
4321 			val64 = val64 & (~ADAPTER_LED_ON);
4322 			writeq(val64, &bar0->adapter_control);
4323 		}
4324 	}
4325 	val64 = readq(&bar0->gpio_int_mask);
4326 }
4327 
4328 /**
4329  *  do_s2io_chk_alarm_bit - Check for alarm and incrment the counter
4330  *  @value: alarm bits
4331  *  @addr: address value
4332  *  @cnt: counter variable
4333  *  Description: Check for alarm and increment the counter
4334  *  Return Value:
4335  *  1 - if alarm bit set
4336  *  0 - if alarm bit is not set
4337  */
do_s2io_chk_alarm_bit(u64 value,void __iomem * addr,unsigned long long * cnt)4338 static int do_s2io_chk_alarm_bit(u64 value, void __iomem *addr,
4339 				 unsigned long long *cnt)
4340 {
4341 	u64 val64;
4342 	val64 = readq(addr);
4343 	if (val64 & value) {
4344 		writeq(val64, addr);
4345 		(*cnt)++;
4346 		return 1;
4347 	}
4348 	return 0;
4349 
4350 }
4351 
4352 /**
4353  *  s2io_handle_errors - Xframe error indication handler
4354  *  @dev_id: opaque handle to dev
4355  *  Description: Handle alarms such as loss of link, single or
4356  *  double ECC errors, critical and serious errors.
4357  *  Return Value:
4358  *  NONE
4359  */
s2io_handle_errors(void * dev_id)4360 static void s2io_handle_errors(void *dev_id)
4361 {
4362 	struct net_device *dev = (struct net_device *)dev_id;
4363 	struct s2io_nic *sp = netdev_priv(dev);
4364 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
4365 	u64 temp64 = 0, val64 = 0;
4366 	int i = 0;
4367 
4368 	struct swStat *sw_stat = &sp->mac_control.stats_info->sw_stat;
4369 	struct xpakStat *stats = &sp->mac_control.stats_info->xpak_stat;
4370 
4371 	if (!is_s2io_card_up(sp))
4372 		return;
4373 
4374 	if (pci_channel_offline(sp->pdev))
4375 		return;
4376 
4377 	memset(&sw_stat->ring_full_cnt, 0,
4378 	       sizeof(sw_stat->ring_full_cnt));
4379 
4380 	/* Handling the XPAK counters update */
4381 	if (stats->xpak_timer_count < 72000) {
4382 		/* waiting for an hour */
4383 		stats->xpak_timer_count++;
4384 	} else {
4385 		s2io_updt_xpak_counter(dev);
4386 		/* reset the count to zero */
4387 		stats->xpak_timer_count = 0;
4388 	}
4389 
4390 	/* Handling link status change error Intr */
4391 	if (s2io_link_fault_indication(sp) == MAC_RMAC_ERR_TIMER) {
4392 		val64 = readq(&bar0->mac_rmac_err_reg);
4393 		writeq(val64, &bar0->mac_rmac_err_reg);
4394 		if (val64 & RMAC_LINK_STATE_CHANGE_INT)
4395 			schedule_work(&sp->set_link_task);
4396 	}
4397 
4398 	/* In case of a serious error, the device will be Reset. */
4399 	if (do_s2io_chk_alarm_bit(SERR_SOURCE_ANY, &bar0->serr_source,
4400 				  &sw_stat->serious_err_cnt))
4401 		goto reset;
4402 
4403 	/* Check for data parity error */
4404 	if (do_s2io_chk_alarm_bit(GPIO_INT_REG_DP_ERR_INT, &bar0->gpio_int_reg,
4405 				  &sw_stat->parity_err_cnt))
4406 		goto reset;
4407 
4408 	/* Check for ring full counter */
4409 	if (sp->device_type == XFRAME_II_DEVICE) {
4410 		val64 = readq(&bar0->ring_bump_counter1);
4411 		for (i = 0; i < 4; i++) {
4412 			temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4413 			temp64 >>= 64 - ((i+1)*16);
4414 			sw_stat->ring_full_cnt[i] += temp64;
4415 		}
4416 
4417 		val64 = readq(&bar0->ring_bump_counter2);
4418 		for (i = 0; i < 4; i++) {
4419 			temp64 = (val64 & vBIT(0xFFFF, (i*16), 16));
4420 			temp64 >>= 64 - ((i+1)*16);
4421 			sw_stat->ring_full_cnt[i+4] += temp64;
4422 		}
4423 	}
4424 
4425 	val64 = readq(&bar0->txdma_int_status);
4426 	/*check for pfc_err*/
4427 	if (val64 & TXDMA_PFC_INT) {
4428 		if (do_s2io_chk_alarm_bit(PFC_ECC_DB_ERR | PFC_SM_ERR_ALARM |
4429 					  PFC_MISC_0_ERR | PFC_MISC_1_ERR |
4430 					  PFC_PCIX_ERR,
4431 					  &bar0->pfc_err_reg,
4432 					  &sw_stat->pfc_err_cnt))
4433 			goto reset;
4434 		do_s2io_chk_alarm_bit(PFC_ECC_SG_ERR,
4435 				      &bar0->pfc_err_reg,
4436 				      &sw_stat->pfc_err_cnt);
4437 	}
4438 
4439 	/*check for tda_err*/
4440 	if (val64 & TXDMA_TDA_INT) {
4441 		if (do_s2io_chk_alarm_bit(TDA_Fn_ECC_DB_ERR |
4442 					  TDA_SM0_ERR_ALARM |
4443 					  TDA_SM1_ERR_ALARM,
4444 					  &bar0->tda_err_reg,
4445 					  &sw_stat->tda_err_cnt))
4446 			goto reset;
4447 		do_s2io_chk_alarm_bit(TDA_Fn_ECC_SG_ERR | TDA_PCIX_ERR,
4448 				      &bar0->tda_err_reg,
4449 				      &sw_stat->tda_err_cnt);
4450 	}
4451 	/*check for pcc_err*/
4452 	if (val64 & TXDMA_PCC_INT) {
4453 		if (do_s2io_chk_alarm_bit(PCC_SM_ERR_ALARM | PCC_WR_ERR_ALARM |
4454 					  PCC_N_SERR | PCC_6_COF_OV_ERR |
4455 					  PCC_7_COF_OV_ERR | PCC_6_LSO_OV_ERR |
4456 					  PCC_7_LSO_OV_ERR | PCC_FB_ECC_DB_ERR |
4457 					  PCC_TXB_ECC_DB_ERR,
4458 					  &bar0->pcc_err_reg,
4459 					  &sw_stat->pcc_err_cnt))
4460 			goto reset;
4461 		do_s2io_chk_alarm_bit(PCC_FB_ECC_SG_ERR | PCC_TXB_ECC_SG_ERR,
4462 				      &bar0->pcc_err_reg,
4463 				      &sw_stat->pcc_err_cnt);
4464 	}
4465 
4466 	/*check for tti_err*/
4467 	if (val64 & TXDMA_TTI_INT) {
4468 		if (do_s2io_chk_alarm_bit(TTI_SM_ERR_ALARM,
4469 					  &bar0->tti_err_reg,
4470 					  &sw_stat->tti_err_cnt))
4471 			goto reset;
4472 		do_s2io_chk_alarm_bit(TTI_ECC_SG_ERR | TTI_ECC_DB_ERR,
4473 				      &bar0->tti_err_reg,
4474 				      &sw_stat->tti_err_cnt);
4475 	}
4476 
4477 	/*check for lso_err*/
4478 	if (val64 & TXDMA_LSO_INT) {
4479 		if (do_s2io_chk_alarm_bit(LSO6_ABORT | LSO7_ABORT |
4480 					  LSO6_SM_ERR_ALARM | LSO7_SM_ERR_ALARM,
4481 					  &bar0->lso_err_reg,
4482 					  &sw_stat->lso_err_cnt))
4483 			goto reset;
4484 		do_s2io_chk_alarm_bit(LSO6_SEND_OFLOW | LSO7_SEND_OFLOW,
4485 				      &bar0->lso_err_reg,
4486 				      &sw_stat->lso_err_cnt);
4487 	}
4488 
4489 	/*check for tpa_err*/
4490 	if (val64 & TXDMA_TPA_INT) {
4491 		if (do_s2io_chk_alarm_bit(TPA_SM_ERR_ALARM,
4492 					  &bar0->tpa_err_reg,
4493 					  &sw_stat->tpa_err_cnt))
4494 			goto reset;
4495 		do_s2io_chk_alarm_bit(TPA_TX_FRM_DROP,
4496 				      &bar0->tpa_err_reg,
4497 				      &sw_stat->tpa_err_cnt);
4498 	}
4499 
4500 	/*check for sm_err*/
4501 	if (val64 & TXDMA_SM_INT) {
4502 		if (do_s2io_chk_alarm_bit(SM_SM_ERR_ALARM,
4503 					  &bar0->sm_err_reg,
4504 					  &sw_stat->sm_err_cnt))
4505 			goto reset;
4506 	}
4507 
4508 	val64 = readq(&bar0->mac_int_status);
4509 	if (val64 & MAC_INT_STATUS_TMAC_INT) {
4510 		if (do_s2io_chk_alarm_bit(TMAC_TX_BUF_OVRN | TMAC_TX_SM_ERR,
4511 					  &bar0->mac_tmac_err_reg,
4512 					  &sw_stat->mac_tmac_err_cnt))
4513 			goto reset;
4514 		do_s2io_chk_alarm_bit(TMAC_ECC_SG_ERR | TMAC_ECC_DB_ERR |
4515 				      TMAC_DESC_ECC_SG_ERR |
4516 				      TMAC_DESC_ECC_DB_ERR,
4517 				      &bar0->mac_tmac_err_reg,
4518 				      &sw_stat->mac_tmac_err_cnt);
4519 	}
4520 
4521 	val64 = readq(&bar0->xgxs_int_status);
4522 	if (val64 & XGXS_INT_STATUS_TXGXS) {
4523 		if (do_s2io_chk_alarm_bit(TXGXS_ESTORE_UFLOW | TXGXS_TX_SM_ERR,
4524 					  &bar0->xgxs_txgxs_err_reg,
4525 					  &sw_stat->xgxs_txgxs_err_cnt))
4526 			goto reset;
4527 		do_s2io_chk_alarm_bit(TXGXS_ECC_SG_ERR | TXGXS_ECC_DB_ERR,
4528 				      &bar0->xgxs_txgxs_err_reg,
4529 				      &sw_stat->xgxs_txgxs_err_cnt);
4530 	}
4531 
4532 	val64 = readq(&bar0->rxdma_int_status);
4533 	if (val64 & RXDMA_INT_RC_INT_M) {
4534 		if (do_s2io_chk_alarm_bit(RC_PRCn_ECC_DB_ERR |
4535 					  RC_FTC_ECC_DB_ERR |
4536 					  RC_PRCn_SM_ERR_ALARM |
4537 					  RC_FTC_SM_ERR_ALARM,
4538 					  &bar0->rc_err_reg,
4539 					  &sw_stat->rc_err_cnt))
4540 			goto reset;
4541 		do_s2io_chk_alarm_bit(RC_PRCn_ECC_SG_ERR |
4542 				      RC_FTC_ECC_SG_ERR |
4543 				      RC_RDA_FAIL_WR_Rn, &bar0->rc_err_reg,
4544 				      &sw_stat->rc_err_cnt);
4545 		if (do_s2io_chk_alarm_bit(PRC_PCI_AB_RD_Rn |
4546 					  PRC_PCI_AB_WR_Rn |
4547 					  PRC_PCI_AB_F_WR_Rn,
4548 					  &bar0->prc_pcix_err_reg,
4549 					  &sw_stat->prc_pcix_err_cnt))
4550 			goto reset;
4551 		do_s2io_chk_alarm_bit(PRC_PCI_DP_RD_Rn |
4552 				      PRC_PCI_DP_WR_Rn |
4553 				      PRC_PCI_DP_F_WR_Rn,
4554 				      &bar0->prc_pcix_err_reg,
4555 				      &sw_stat->prc_pcix_err_cnt);
4556 	}
4557 
4558 	if (val64 & RXDMA_INT_RPA_INT_M) {
4559 		if (do_s2io_chk_alarm_bit(RPA_SM_ERR_ALARM | RPA_CREDIT_ERR,
4560 					  &bar0->rpa_err_reg,
4561 					  &sw_stat->rpa_err_cnt))
4562 			goto reset;
4563 		do_s2io_chk_alarm_bit(RPA_ECC_SG_ERR | RPA_ECC_DB_ERR,
4564 				      &bar0->rpa_err_reg,
4565 				      &sw_stat->rpa_err_cnt);
4566 	}
4567 
4568 	if (val64 & RXDMA_INT_RDA_INT_M) {
4569 		if (do_s2io_chk_alarm_bit(RDA_RXDn_ECC_DB_ERR |
4570 					  RDA_FRM_ECC_DB_N_AERR |
4571 					  RDA_SM1_ERR_ALARM |
4572 					  RDA_SM0_ERR_ALARM |
4573 					  RDA_RXD_ECC_DB_SERR,
4574 					  &bar0->rda_err_reg,
4575 					  &sw_stat->rda_err_cnt))
4576 			goto reset;
4577 		do_s2io_chk_alarm_bit(RDA_RXDn_ECC_SG_ERR |
4578 				      RDA_FRM_ECC_SG_ERR |
4579 				      RDA_MISC_ERR |
4580 				      RDA_PCIX_ERR,
4581 				      &bar0->rda_err_reg,
4582 				      &sw_stat->rda_err_cnt);
4583 	}
4584 
4585 	if (val64 & RXDMA_INT_RTI_INT_M) {
4586 		if (do_s2io_chk_alarm_bit(RTI_SM_ERR_ALARM,
4587 					  &bar0->rti_err_reg,
4588 					  &sw_stat->rti_err_cnt))
4589 			goto reset;
4590 		do_s2io_chk_alarm_bit(RTI_ECC_SG_ERR | RTI_ECC_DB_ERR,
4591 				      &bar0->rti_err_reg,
4592 				      &sw_stat->rti_err_cnt);
4593 	}
4594 
4595 	val64 = readq(&bar0->mac_int_status);
4596 	if (val64 & MAC_INT_STATUS_RMAC_INT) {
4597 		if (do_s2io_chk_alarm_bit(RMAC_RX_BUFF_OVRN | RMAC_RX_SM_ERR,
4598 					  &bar0->mac_rmac_err_reg,
4599 					  &sw_stat->mac_rmac_err_cnt))
4600 			goto reset;
4601 		do_s2io_chk_alarm_bit(RMAC_UNUSED_INT |
4602 				      RMAC_SINGLE_ECC_ERR |
4603 				      RMAC_DOUBLE_ECC_ERR,
4604 				      &bar0->mac_rmac_err_reg,
4605 				      &sw_stat->mac_rmac_err_cnt);
4606 	}
4607 
4608 	val64 = readq(&bar0->xgxs_int_status);
4609 	if (val64 & XGXS_INT_STATUS_RXGXS) {
4610 		if (do_s2io_chk_alarm_bit(RXGXS_ESTORE_OFLOW | RXGXS_RX_SM_ERR,
4611 					  &bar0->xgxs_rxgxs_err_reg,
4612 					  &sw_stat->xgxs_rxgxs_err_cnt))
4613 			goto reset;
4614 	}
4615 
4616 	val64 = readq(&bar0->mc_int_status);
4617 	if (val64 & MC_INT_STATUS_MC_INT) {
4618 		if (do_s2io_chk_alarm_bit(MC_ERR_REG_SM_ERR,
4619 					  &bar0->mc_err_reg,
4620 					  &sw_stat->mc_err_cnt))
4621 			goto reset;
4622 
4623 		/* Handling Ecc errors */
4624 		if (val64 & (MC_ERR_REG_ECC_ALL_SNG | MC_ERR_REG_ECC_ALL_DBL)) {
4625 			writeq(val64, &bar0->mc_err_reg);
4626 			if (val64 & MC_ERR_REG_ECC_ALL_DBL) {
4627 				sw_stat->double_ecc_errs++;
4628 				if (sp->device_type != XFRAME_II_DEVICE) {
4629 					/*
4630 					 * Reset XframeI only if critical error
4631 					 */
4632 					if (val64 &
4633 					    (MC_ERR_REG_MIRI_ECC_DB_ERR_0 |
4634 					     MC_ERR_REG_MIRI_ECC_DB_ERR_1))
4635 						goto reset;
4636 				}
4637 			} else
4638 				sw_stat->single_ecc_errs++;
4639 		}
4640 	}
4641 	return;
4642 
4643 reset:
4644 	s2io_stop_all_tx_queue(sp);
4645 	schedule_work(&sp->rst_timer_task);
4646 	sw_stat->soft_reset_cnt++;
4647 }
4648 
4649 /**
4650  *  s2io_isr - ISR handler of the device .
4651  *  @irq: the irq of the device.
4652  *  @dev_id: a void pointer to the dev structure of the NIC.
4653  *  Description:  This function is the ISR handler of the device. It
4654  *  identifies the reason for the interrupt and calls the relevant
4655  *  service routines. As a contongency measure, this ISR allocates the
4656  *  recv buffers, if their numbers are below the panic value which is
4657  *  presently set to 25% of the original number of rcv buffers allocated.
4658  *  Return value:
4659  *   IRQ_HANDLED: will be returned if IRQ was handled by this routine
4660  *   IRQ_NONE: will be returned if interrupt is not from our device
4661  */
s2io_isr(int irq,void * dev_id)4662 static irqreturn_t s2io_isr(int irq, void *dev_id)
4663 {
4664 	struct net_device *dev = (struct net_device *)dev_id;
4665 	struct s2io_nic *sp = netdev_priv(dev);
4666 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
4667 	int i;
4668 	u64 reason = 0;
4669 	struct mac_info *mac_control;
4670 	struct config_param *config;
4671 
4672 	/* Pretend we handled any irq's from a disconnected card */
4673 	if (pci_channel_offline(sp->pdev))
4674 		return IRQ_NONE;
4675 
4676 	if (!is_s2io_card_up(sp))
4677 		return IRQ_NONE;
4678 
4679 	config = &sp->config;
4680 	mac_control = &sp->mac_control;
4681 
4682 	/*
4683 	 * Identify the cause for interrupt and call the appropriate
4684 	 * interrupt handler. Causes for the interrupt could be;
4685 	 * 1. Rx of packet.
4686 	 * 2. Tx complete.
4687 	 * 3. Link down.
4688 	 */
4689 	reason = readq(&bar0->general_int_status);
4690 
4691 	if (unlikely(reason == S2IO_MINUS_ONE))
4692 		return IRQ_HANDLED;	/* Nothing much can be done. Get out */
4693 
4694 	if (reason &
4695 	    (GEN_INTR_RXTRAFFIC | GEN_INTR_TXTRAFFIC | GEN_INTR_TXPIC)) {
4696 		writeq(S2IO_MINUS_ONE, &bar0->general_int_mask);
4697 
4698 		if (config->napi) {
4699 			if (reason & GEN_INTR_RXTRAFFIC) {
4700 				napi_schedule(&sp->napi);
4701 				writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_mask);
4702 				writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4703 				readl(&bar0->rx_traffic_int);
4704 			}
4705 		} else {
4706 			/*
4707 			 * rx_traffic_int reg is an R1 register, writing all 1's
4708 			 * will ensure that the actual interrupt causing bit
4709 			 * get's cleared and hence a read can be avoided.
4710 			 */
4711 			if (reason & GEN_INTR_RXTRAFFIC)
4712 				writeq(S2IO_MINUS_ONE, &bar0->rx_traffic_int);
4713 
4714 			for (i = 0; i < config->rx_ring_num; i++) {
4715 				struct ring_info *ring = &mac_control->rings[i];
4716 
4717 				rx_intr_handler(ring, 0);
4718 			}
4719 		}
4720 
4721 		/*
4722 		 * tx_traffic_int reg is an R1 register, writing all 1's
4723 		 * will ensure that the actual interrupt causing bit get's
4724 		 * cleared and hence a read can be avoided.
4725 		 */
4726 		if (reason & GEN_INTR_TXTRAFFIC)
4727 			writeq(S2IO_MINUS_ONE, &bar0->tx_traffic_int);
4728 
4729 		for (i = 0; i < config->tx_fifo_num; i++)
4730 			tx_intr_handler(&mac_control->fifos[i]);
4731 
4732 		if (reason & GEN_INTR_TXPIC)
4733 			s2io_txpic_intr_handle(sp);
4734 
4735 		/*
4736 		 * Reallocate the buffers from the interrupt handler itself.
4737 		 */
4738 		if (!config->napi) {
4739 			for (i = 0; i < config->rx_ring_num; i++) {
4740 				struct ring_info *ring = &mac_control->rings[i];
4741 
4742 				s2io_chk_rx_buffers(sp, ring);
4743 			}
4744 		}
4745 		writeq(sp->general_int_mask, &bar0->general_int_mask);
4746 		readl(&bar0->general_int_status);
4747 
4748 		return IRQ_HANDLED;
4749 
4750 	} else if (!reason) {
4751 		/* The interrupt was not raised by us */
4752 		return IRQ_NONE;
4753 	}
4754 
4755 	return IRQ_HANDLED;
4756 }
4757 
4758 /*
4759  * s2io_updt_stats -
4760  */
s2io_updt_stats(struct s2io_nic * sp)4761 static void s2io_updt_stats(struct s2io_nic *sp)
4762 {
4763 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
4764 	u64 val64;
4765 	int cnt = 0;
4766 
4767 	if (is_s2io_card_up(sp)) {
4768 		/* Apprx 30us on a 133 MHz bus */
4769 		val64 = SET_UPDT_CLICKS(10) |
4770 			STAT_CFG_ONE_SHOT_EN | STAT_CFG_STAT_EN;
4771 		writeq(val64, &bar0->stat_cfg);
4772 		do {
4773 			udelay(100);
4774 			val64 = readq(&bar0->stat_cfg);
4775 			if (!(val64 & s2BIT(0)))
4776 				break;
4777 			cnt++;
4778 			if (cnt == 5)
4779 				break; /* Updt failed */
4780 		} while (1);
4781 	}
4782 }
4783 
4784 /**
4785  *  s2io_get_stats - Updates the device statistics structure.
4786  *  @dev : pointer to the device structure.
4787  *  Description:
4788  *  This function updates the device statistics structure in the s2io_nic
4789  *  structure and returns a pointer to the same.
4790  *  Return value:
4791  *  pointer to the updated net_device_stats structure.
4792  */
s2io_get_stats(struct net_device * dev)4793 static struct net_device_stats *s2io_get_stats(struct net_device *dev)
4794 {
4795 	struct s2io_nic *sp = netdev_priv(dev);
4796 	struct mac_info *mac_control = &sp->mac_control;
4797 	struct stat_block *stats = mac_control->stats_info;
4798 	u64 delta;
4799 
4800 	/* Configure Stats for immediate updt */
4801 	s2io_updt_stats(sp);
4802 
4803 	/* A device reset will cause the on-adapter statistics to be zero'ed.
4804 	 * This can be done while running by changing the MTU.  To prevent the
4805 	 * system from having the stats zero'ed, the driver keeps a copy of the
4806 	 * last update to the system (which is also zero'ed on reset).  This
4807 	 * enables the driver to accurately know the delta between the last
4808 	 * update and the current update.
4809 	 */
4810 	delta = ((u64) le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
4811 		le32_to_cpu(stats->rmac_vld_frms)) - sp->stats.rx_packets;
4812 	sp->stats.rx_packets += delta;
4813 	dev->stats.rx_packets += delta;
4814 
4815 	delta = ((u64) le32_to_cpu(stats->tmac_frms_oflow) << 32 |
4816 		le32_to_cpu(stats->tmac_frms)) - sp->stats.tx_packets;
4817 	sp->stats.tx_packets += delta;
4818 	dev->stats.tx_packets += delta;
4819 
4820 	delta = ((u64) le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
4821 		le32_to_cpu(stats->rmac_data_octets)) - sp->stats.rx_bytes;
4822 	sp->stats.rx_bytes += delta;
4823 	dev->stats.rx_bytes += delta;
4824 
4825 	delta = ((u64) le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
4826 		le32_to_cpu(stats->tmac_data_octets)) - sp->stats.tx_bytes;
4827 	sp->stats.tx_bytes += delta;
4828 	dev->stats.tx_bytes += delta;
4829 
4830 	delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_errors;
4831 	sp->stats.rx_errors += delta;
4832 	dev->stats.rx_errors += delta;
4833 
4834 	delta = ((u64) le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
4835 		le32_to_cpu(stats->tmac_any_err_frms)) - sp->stats.tx_errors;
4836 	sp->stats.tx_errors += delta;
4837 	dev->stats.tx_errors += delta;
4838 
4839 	delta = le64_to_cpu(stats->rmac_drop_frms) - sp->stats.rx_dropped;
4840 	sp->stats.rx_dropped += delta;
4841 	dev->stats.rx_dropped += delta;
4842 
4843 	delta = le64_to_cpu(stats->tmac_drop_frms) - sp->stats.tx_dropped;
4844 	sp->stats.tx_dropped += delta;
4845 	dev->stats.tx_dropped += delta;
4846 
4847 	/* The adapter MAC interprets pause frames as multicast packets, but
4848 	 * does not pass them up.  This erroneously increases the multicast
4849 	 * packet count and needs to be deducted when the multicast frame count
4850 	 * is queried.
4851 	 */
4852 	delta = (u64) le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
4853 		le32_to_cpu(stats->rmac_vld_mcst_frms);
4854 	delta -= le64_to_cpu(stats->rmac_pause_ctrl_frms);
4855 	delta -= sp->stats.multicast;
4856 	sp->stats.multicast += delta;
4857 	dev->stats.multicast += delta;
4858 
4859 	delta = ((u64) le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
4860 		le32_to_cpu(stats->rmac_usized_frms)) +
4861 		le64_to_cpu(stats->rmac_long_frms) - sp->stats.rx_length_errors;
4862 	sp->stats.rx_length_errors += delta;
4863 	dev->stats.rx_length_errors += delta;
4864 
4865 	delta = le64_to_cpu(stats->rmac_fcs_err_frms) - sp->stats.rx_crc_errors;
4866 	sp->stats.rx_crc_errors += delta;
4867 	dev->stats.rx_crc_errors += delta;
4868 
4869 	return &dev->stats;
4870 }
4871 
4872 /**
4873  *  s2io_set_multicast - entry point for multicast address enable/disable.
4874  *  @dev : pointer to the device structure
4875  *  @may_sleep: parameter indicates if sleeping when waiting for command
4876  *  complete
4877  *  Description:
4878  *  This function is a driver entry point which gets called by the kernel
4879  *  whenever multicast addresses must be enabled/disabled. This also gets
4880  *  called to set/reset promiscuous mode. Depending on the deivce flag, we
4881  *  determine, if multicast address must be enabled or if promiscuous mode
4882  *  is to be disabled etc.
4883  *  Return value:
4884  *  void.
4885  */
s2io_set_multicast(struct net_device * dev,bool may_sleep)4886 static void s2io_set_multicast(struct net_device *dev, bool may_sleep)
4887 {
4888 	int i, j, prev_cnt;
4889 	struct netdev_hw_addr *ha;
4890 	struct s2io_nic *sp = netdev_priv(dev);
4891 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
4892 	u64 val64 = 0, multi_mac = 0x010203040506ULL, mask =
4893 		0xfeffffffffffULL;
4894 	u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, mac_addr = 0;
4895 	void __iomem *add;
4896 	struct config_param *config = &sp->config;
4897 
4898 	if ((dev->flags & IFF_ALLMULTI) && (!sp->m_cast_flg)) {
4899 		/*  Enable all Multicast addresses */
4900 		writeq(RMAC_ADDR_DATA0_MEM_ADDR(multi_mac),
4901 		       &bar0->rmac_addr_data0_mem);
4902 		writeq(RMAC_ADDR_DATA1_MEM_MASK(mask),
4903 		       &bar0->rmac_addr_data1_mem);
4904 		val64 = RMAC_ADDR_CMD_MEM_WE |
4905 			RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4906 			RMAC_ADDR_CMD_MEM_OFFSET(config->max_mc_addr - 1);
4907 		writeq(val64, &bar0->rmac_addr_cmd_mem);
4908 		/* Wait till command completes */
4909 		wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4910 				      RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4911 				      S2IO_BIT_RESET, may_sleep);
4912 
4913 		sp->m_cast_flg = 1;
4914 		sp->all_multi_pos = config->max_mc_addr - 1;
4915 	} else if ((dev->flags & IFF_ALLMULTI) && (sp->m_cast_flg)) {
4916 		/*  Disable all Multicast addresses */
4917 		writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4918 		       &bar0->rmac_addr_data0_mem);
4919 		writeq(RMAC_ADDR_DATA1_MEM_MASK(0x0),
4920 		       &bar0->rmac_addr_data1_mem);
4921 		val64 = RMAC_ADDR_CMD_MEM_WE |
4922 			RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
4923 			RMAC_ADDR_CMD_MEM_OFFSET(sp->all_multi_pos);
4924 		writeq(val64, &bar0->rmac_addr_cmd_mem);
4925 		/* Wait till command completes */
4926 		wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
4927 				      RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
4928 				      S2IO_BIT_RESET, may_sleep);
4929 
4930 		sp->m_cast_flg = 0;
4931 		sp->all_multi_pos = 0;
4932 	}
4933 
4934 	if ((dev->flags & IFF_PROMISC) && (!sp->promisc_flg)) {
4935 		/*  Put the NIC into promiscuous mode */
4936 		add = &bar0->mac_cfg;
4937 		val64 = readq(&bar0->mac_cfg);
4938 		val64 |= MAC_CFG_RMAC_PROM_ENABLE;
4939 
4940 		writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4941 		writel((u32)val64, add);
4942 		writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4943 		writel((u32) (val64 >> 32), (add + 4));
4944 
4945 		if (vlan_tag_strip != 1) {
4946 			val64 = readq(&bar0->rx_pa_cfg);
4947 			val64 &= ~RX_PA_CFG_STRIP_VLAN_TAG;
4948 			writeq(val64, &bar0->rx_pa_cfg);
4949 			sp->vlan_strip_flag = 0;
4950 		}
4951 
4952 		val64 = readq(&bar0->mac_cfg);
4953 		sp->promisc_flg = 1;
4954 		DBG_PRINT(INFO_DBG, "%s: entered promiscuous mode\n",
4955 			  dev->name);
4956 	} else if (!(dev->flags & IFF_PROMISC) && (sp->promisc_flg)) {
4957 		/*  Remove the NIC from promiscuous mode */
4958 		add = &bar0->mac_cfg;
4959 		val64 = readq(&bar0->mac_cfg);
4960 		val64 &= ~MAC_CFG_RMAC_PROM_ENABLE;
4961 
4962 		writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4963 		writel((u32)val64, add);
4964 		writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
4965 		writel((u32) (val64 >> 32), (add + 4));
4966 
4967 		if (vlan_tag_strip != 0) {
4968 			val64 = readq(&bar0->rx_pa_cfg);
4969 			val64 |= RX_PA_CFG_STRIP_VLAN_TAG;
4970 			writeq(val64, &bar0->rx_pa_cfg);
4971 			sp->vlan_strip_flag = 1;
4972 		}
4973 
4974 		val64 = readq(&bar0->mac_cfg);
4975 		sp->promisc_flg = 0;
4976 		DBG_PRINT(INFO_DBG, "%s: left promiscuous mode\n", dev->name);
4977 	}
4978 
4979 	/*  Update individual M_CAST address list */
4980 	if ((!sp->m_cast_flg) && netdev_mc_count(dev)) {
4981 		if (netdev_mc_count(dev) >
4982 		    (config->max_mc_addr - config->max_mac_addr)) {
4983 			DBG_PRINT(ERR_DBG,
4984 				  "%s: No more Rx filters can be added - "
4985 				  "please enable ALL_MULTI instead\n",
4986 				  dev->name);
4987 			return;
4988 		}
4989 
4990 		prev_cnt = sp->mc_addr_count;
4991 		sp->mc_addr_count = netdev_mc_count(dev);
4992 
4993 		/* Clear out the previous list of Mc in the H/W. */
4994 		for (i = 0; i < prev_cnt; i++) {
4995 			writeq(RMAC_ADDR_DATA0_MEM_ADDR(dis_addr),
4996 			       &bar0->rmac_addr_data0_mem);
4997 			writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
4998 			       &bar0->rmac_addr_data1_mem);
4999 			val64 = RMAC_ADDR_CMD_MEM_WE |
5000 				RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5001 				RMAC_ADDR_CMD_MEM_OFFSET
5002 				(config->mc_start_offset + i);
5003 			writeq(val64, &bar0->rmac_addr_cmd_mem);
5004 
5005 			/* Wait for command completes */
5006 			if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5007 						  RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5008 						  S2IO_BIT_RESET, may_sleep)) {
5009 				DBG_PRINT(ERR_DBG,
5010 					  "%s: Adding Multicasts failed\n",
5011 					  dev->name);
5012 				return;
5013 			}
5014 		}
5015 
5016 		/* Create the new Rx filter list and update the same in H/W. */
5017 		i = 0;
5018 		netdev_for_each_mc_addr(ha, dev) {
5019 			mac_addr = 0;
5020 			for (j = 0; j < ETH_ALEN; j++) {
5021 				mac_addr |= ha->addr[j];
5022 				mac_addr <<= 8;
5023 			}
5024 			mac_addr >>= 8;
5025 			writeq(RMAC_ADDR_DATA0_MEM_ADDR(mac_addr),
5026 			       &bar0->rmac_addr_data0_mem);
5027 			writeq(RMAC_ADDR_DATA1_MEM_MASK(0ULL),
5028 			       &bar0->rmac_addr_data1_mem);
5029 			val64 = RMAC_ADDR_CMD_MEM_WE |
5030 				RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5031 				RMAC_ADDR_CMD_MEM_OFFSET
5032 				(i + config->mc_start_offset);
5033 			writeq(val64, &bar0->rmac_addr_cmd_mem);
5034 
5035 			/* Wait for command completes */
5036 			if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5037 						  RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5038 						  S2IO_BIT_RESET, may_sleep)) {
5039 				DBG_PRINT(ERR_DBG,
5040 					  "%s: Adding Multicasts failed\n",
5041 					  dev->name);
5042 				return;
5043 			}
5044 			i++;
5045 		}
5046 	}
5047 }
5048 
5049 /* NDO wrapper for s2io_set_multicast */
s2io_ndo_set_multicast(struct net_device * dev)5050 static void s2io_ndo_set_multicast(struct net_device *dev)
5051 {
5052 	s2io_set_multicast(dev, false);
5053 }
5054 
5055 /* read from CAM unicast & multicast addresses and store it in
5056  * def_mac_addr structure
5057  */
do_s2io_store_unicast_mc(struct s2io_nic * sp)5058 static void do_s2io_store_unicast_mc(struct s2io_nic *sp)
5059 {
5060 	int offset;
5061 	u64 mac_addr = 0x0;
5062 	struct config_param *config = &sp->config;
5063 
5064 	/* store unicast & multicast mac addresses */
5065 	for (offset = 0; offset < config->max_mc_addr; offset++) {
5066 		mac_addr = do_s2io_read_unicast_mc(sp, offset);
5067 		/* if read fails disable the entry */
5068 		if (mac_addr == FAILURE)
5069 			mac_addr = S2IO_DISABLE_MAC_ENTRY;
5070 		do_s2io_copy_mac_addr(sp, offset, mac_addr);
5071 	}
5072 }
5073 
5074 /* restore unicast & multicast MAC to CAM from def_mac_addr structure */
do_s2io_restore_unicast_mc(struct s2io_nic * sp)5075 static void do_s2io_restore_unicast_mc(struct s2io_nic *sp)
5076 {
5077 	int offset;
5078 	struct config_param *config = &sp->config;
5079 	/* restore unicast mac address */
5080 	for (offset = 0; offset < config->max_mac_addr; offset++)
5081 		do_s2io_prog_unicast(sp->dev,
5082 				     sp->def_mac_addr[offset].mac_addr);
5083 
5084 	/* restore multicast mac address */
5085 	for (offset = config->mc_start_offset;
5086 	     offset < config->max_mc_addr; offset++)
5087 		do_s2io_add_mc(sp, sp->def_mac_addr[offset].mac_addr);
5088 }
5089 
5090 /* add a multicast MAC address to CAM */
do_s2io_add_mc(struct s2io_nic * sp,u8 * addr)5091 static int do_s2io_add_mc(struct s2io_nic *sp, u8 *addr)
5092 {
5093 	int i;
5094 	u64 mac_addr;
5095 	struct config_param *config = &sp->config;
5096 
5097 	mac_addr = ether_addr_to_u64(addr);
5098 	if ((0ULL == mac_addr) || (mac_addr == S2IO_DISABLE_MAC_ENTRY))
5099 		return SUCCESS;
5100 
5101 	/* check if the multicast mac already preset in CAM */
5102 	for (i = config->mc_start_offset; i < config->max_mc_addr; i++) {
5103 		u64 tmp64;
5104 		tmp64 = do_s2io_read_unicast_mc(sp, i);
5105 		if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5106 			break;
5107 
5108 		if (tmp64 == mac_addr)
5109 			return SUCCESS;
5110 	}
5111 	if (i == config->max_mc_addr) {
5112 		DBG_PRINT(ERR_DBG,
5113 			  "CAM full no space left for multicast MAC\n");
5114 		return FAILURE;
5115 	}
5116 	/* Update the internal structure with this new mac address */
5117 	do_s2io_copy_mac_addr(sp, i, mac_addr);
5118 
5119 	return do_s2io_add_mac(sp, mac_addr, i);
5120 }
5121 
5122 /* add MAC address to CAM */
do_s2io_add_mac(struct s2io_nic * sp,u64 addr,int off)5123 static int do_s2io_add_mac(struct s2io_nic *sp, u64 addr, int off)
5124 {
5125 	u64 val64;
5126 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
5127 
5128 	writeq(RMAC_ADDR_DATA0_MEM_ADDR(addr),
5129 	       &bar0->rmac_addr_data0_mem);
5130 
5131 	val64 =	RMAC_ADDR_CMD_MEM_WE | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5132 		RMAC_ADDR_CMD_MEM_OFFSET(off);
5133 	writeq(val64, &bar0->rmac_addr_cmd_mem);
5134 
5135 	/* Wait till command completes */
5136 	if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5137 				  RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5138 				  S2IO_BIT_RESET, true)) {
5139 		DBG_PRINT(INFO_DBG, "do_s2io_add_mac failed\n");
5140 		return FAILURE;
5141 	}
5142 	return SUCCESS;
5143 }
5144 /* deletes a specified unicast/multicast mac entry from CAM */
do_s2io_delete_unicast_mc(struct s2io_nic * sp,u64 addr)5145 static int do_s2io_delete_unicast_mc(struct s2io_nic *sp, u64 addr)
5146 {
5147 	int offset;
5148 	u64 dis_addr = S2IO_DISABLE_MAC_ENTRY, tmp64;
5149 	struct config_param *config = &sp->config;
5150 
5151 	for (offset = 1;
5152 	     offset < config->max_mc_addr; offset++) {
5153 		tmp64 = do_s2io_read_unicast_mc(sp, offset);
5154 		if (tmp64 == addr) {
5155 			/* disable the entry by writing  0xffffffffffffULL */
5156 			if (do_s2io_add_mac(sp, dis_addr, offset) ==  FAILURE)
5157 				return FAILURE;
5158 			/* store the new mac list from CAM */
5159 			do_s2io_store_unicast_mc(sp);
5160 			return SUCCESS;
5161 		}
5162 	}
5163 	DBG_PRINT(ERR_DBG, "MAC address 0x%llx not found in CAM\n",
5164 		  (unsigned long long)addr);
5165 	return FAILURE;
5166 }
5167 
5168 /* read mac entries from CAM */
do_s2io_read_unicast_mc(struct s2io_nic * sp,int offset)5169 static u64 do_s2io_read_unicast_mc(struct s2io_nic *sp, int offset)
5170 {
5171 	u64 tmp64, val64;
5172 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
5173 
5174 	/* read mac addr */
5175 	val64 =	RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
5176 		RMAC_ADDR_CMD_MEM_OFFSET(offset);
5177 	writeq(val64, &bar0->rmac_addr_cmd_mem);
5178 
5179 	/* Wait till command completes */
5180 	if (wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
5181 				  RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
5182 				  S2IO_BIT_RESET, true)) {
5183 		DBG_PRINT(INFO_DBG, "do_s2io_read_unicast_mc failed\n");
5184 		return FAILURE;
5185 	}
5186 	tmp64 = readq(&bar0->rmac_addr_data0_mem);
5187 
5188 	return tmp64 >> 16;
5189 }
5190 
5191 /*
5192  * s2io_set_mac_addr - driver entry point
5193  */
5194 
s2io_set_mac_addr(struct net_device * dev,void * p)5195 static int s2io_set_mac_addr(struct net_device *dev, void *p)
5196 {
5197 	struct sockaddr *addr = p;
5198 
5199 	if (!is_valid_ether_addr(addr->sa_data))
5200 		return -EADDRNOTAVAIL;
5201 
5202 	eth_hw_addr_set(dev, addr->sa_data);
5203 
5204 	/* store the MAC address in CAM */
5205 	return do_s2io_prog_unicast(dev, dev->dev_addr);
5206 }
5207 /**
5208  *  do_s2io_prog_unicast - Programs the Xframe mac address
5209  *  @dev : pointer to the device structure.
5210  *  @addr: a uchar pointer to the new mac address which is to be set.
5211  *  Description : This procedure will program the Xframe to receive
5212  *  frames with new Mac Address
5213  *  Return value: SUCCESS on success and an appropriate (-)ve integer
5214  *  as defined in errno.h file on failure.
5215  */
5216 
do_s2io_prog_unicast(struct net_device * dev,const u8 * addr)5217 static int do_s2io_prog_unicast(struct net_device *dev, const u8 *addr)
5218 {
5219 	struct s2io_nic *sp = netdev_priv(dev);
5220 	register u64 mac_addr, perm_addr;
5221 	int i;
5222 	u64 tmp64;
5223 	struct config_param *config = &sp->config;
5224 
5225 	/*
5226 	 * Set the new MAC address as the new unicast filter and reflect this
5227 	 * change on the device address registered with the OS. It will be
5228 	 * at offset 0.
5229 	 */
5230 	mac_addr = ether_addr_to_u64(addr);
5231 	perm_addr = ether_addr_to_u64(sp->def_mac_addr[0].mac_addr);
5232 
5233 	/* check if the dev_addr is different than perm_addr */
5234 	if (mac_addr == perm_addr)
5235 		return SUCCESS;
5236 
5237 	/* check if the mac already preset in CAM */
5238 	for (i = 1; i < config->max_mac_addr; i++) {
5239 		tmp64 = do_s2io_read_unicast_mc(sp, i);
5240 		if (tmp64 == S2IO_DISABLE_MAC_ENTRY) /* CAM entry is empty */
5241 			break;
5242 
5243 		if (tmp64 == mac_addr) {
5244 			DBG_PRINT(INFO_DBG,
5245 				  "MAC addr:0x%llx already present in CAM\n",
5246 				  (unsigned long long)mac_addr);
5247 			return SUCCESS;
5248 		}
5249 	}
5250 	if (i == config->max_mac_addr) {
5251 		DBG_PRINT(ERR_DBG, "CAM full no space left for Unicast MAC\n");
5252 		return FAILURE;
5253 	}
5254 	/* Update the internal structure with this new mac address */
5255 	do_s2io_copy_mac_addr(sp, i, mac_addr);
5256 
5257 	return do_s2io_add_mac(sp, mac_addr, i);
5258 }
5259 
5260 /**
5261  * s2io_ethtool_set_link_ksettings - Sets different link parameters.
5262  * @dev : pointer to netdev
5263  * @cmd: pointer to the structure with parameters given by ethtool to set
5264  * link information.
5265  * Description:
5266  * The function sets different link parameters provided by the user onto
5267  * the NIC.
5268  * Return value:
5269  * 0 on success.
5270  */
5271 
5272 static int
s2io_ethtool_set_link_ksettings(struct net_device * dev,const struct ethtool_link_ksettings * cmd)5273 s2io_ethtool_set_link_ksettings(struct net_device *dev,
5274 				const struct ethtool_link_ksettings *cmd)
5275 {
5276 	struct s2io_nic *sp = netdev_priv(dev);
5277 	if ((cmd->base.autoneg == AUTONEG_ENABLE) ||
5278 	    (cmd->base.speed != SPEED_10000) ||
5279 	    (cmd->base.duplex != DUPLEX_FULL))
5280 		return -EINVAL;
5281 	else {
5282 		s2io_close(sp->dev);
5283 		s2io_open(sp->dev);
5284 	}
5285 
5286 	return 0;
5287 }
5288 
5289 /**
5290  * s2io_ethtool_get_link_ksettings - Return link specific information.
5291  * @dev: pointer to netdev
5292  * @cmd : pointer to the structure with parameters given by ethtool
5293  * to return link information.
5294  * Description:
5295  * Returns link specific information like speed, duplex etc.. to ethtool.
5296  * Return value :
5297  * return 0 on success.
5298  */
5299 
5300 static int
s2io_ethtool_get_link_ksettings(struct net_device * dev,struct ethtool_link_ksettings * cmd)5301 s2io_ethtool_get_link_ksettings(struct net_device *dev,
5302 				struct ethtool_link_ksettings *cmd)
5303 {
5304 	struct s2io_nic *sp = netdev_priv(dev);
5305 
5306 	ethtool_link_ksettings_zero_link_mode(cmd, supported);
5307 	ethtool_link_ksettings_add_link_mode(cmd, supported, 10000baseT_Full);
5308 	ethtool_link_ksettings_add_link_mode(cmd, supported, FIBRE);
5309 
5310 	ethtool_link_ksettings_zero_link_mode(cmd, advertising);
5311 	ethtool_link_ksettings_add_link_mode(cmd, advertising, 10000baseT_Full);
5312 	ethtool_link_ksettings_add_link_mode(cmd, advertising, FIBRE);
5313 
5314 	cmd->base.port = PORT_FIBRE;
5315 
5316 	if (netif_carrier_ok(sp->dev)) {
5317 		cmd->base.speed = SPEED_10000;
5318 		cmd->base.duplex = DUPLEX_FULL;
5319 	} else {
5320 		cmd->base.speed = SPEED_UNKNOWN;
5321 		cmd->base.duplex = DUPLEX_UNKNOWN;
5322 	}
5323 
5324 	cmd->base.autoneg = AUTONEG_DISABLE;
5325 	return 0;
5326 }
5327 
5328 /**
5329  * s2io_ethtool_gdrvinfo - Returns driver specific information.
5330  * @dev: pointer to netdev
5331  * @info : pointer to the structure with parameters given by ethtool to
5332  * return driver information.
5333  * Description:
5334  * Returns driver specefic information like name, version etc.. to ethtool.
5335  * Return value:
5336  *  void
5337  */
5338 
s2io_ethtool_gdrvinfo(struct net_device * dev,struct ethtool_drvinfo * info)5339 static void s2io_ethtool_gdrvinfo(struct net_device *dev,
5340 				  struct ethtool_drvinfo *info)
5341 {
5342 	struct s2io_nic *sp = netdev_priv(dev);
5343 
5344 	strscpy(info->driver, s2io_driver_name, sizeof(info->driver));
5345 	strscpy(info->version, s2io_driver_version, sizeof(info->version));
5346 	strscpy(info->bus_info, pci_name(sp->pdev), sizeof(info->bus_info));
5347 }
5348 
5349 /**
5350  *  s2io_ethtool_gregs - dumps the entire space of Xfame into the buffer.
5351  *  @dev: pointer to netdev
5352  *  @regs : pointer to the structure with parameters given by ethtool for
5353  *          dumping the registers.
5354  *  @space: The input argument into which all the registers are dumped.
5355  *  Description:
5356  *  Dumps the entire register space of xFrame NIC into the user given
5357  *  buffer area.
5358  * Return value :
5359  * void .
5360  */
5361 
s2io_ethtool_gregs(struct net_device * dev,struct ethtool_regs * regs,void * space)5362 static void s2io_ethtool_gregs(struct net_device *dev,
5363 			       struct ethtool_regs *regs, void *space)
5364 {
5365 	int i;
5366 	u64 reg;
5367 	u8 *reg_space = (u8 *)space;
5368 	struct s2io_nic *sp = netdev_priv(dev);
5369 
5370 	regs->len = XENA_REG_SPACE;
5371 	regs->version = sp->pdev->subsystem_device;
5372 
5373 	for (i = 0; i < regs->len; i += 8) {
5374 		reg = readq(sp->bar0 + i);
5375 		memcpy((reg_space + i), &reg, 8);
5376 	}
5377 }
5378 
5379 /*
5380  *  s2io_set_led - control NIC led
5381  */
s2io_set_led(struct s2io_nic * sp,bool on)5382 static void s2io_set_led(struct s2io_nic *sp, bool on)
5383 {
5384 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
5385 	u16 subid = sp->pdev->subsystem_device;
5386 	u64 val64;
5387 
5388 	if ((sp->device_type == XFRAME_II_DEVICE) ||
5389 	    ((subid & 0xFF) >= 0x07)) {
5390 		val64 = readq(&bar0->gpio_control);
5391 		if (on)
5392 			val64 |= GPIO_CTRL_GPIO_0;
5393 		else
5394 			val64 &= ~GPIO_CTRL_GPIO_0;
5395 
5396 		writeq(val64, &bar0->gpio_control);
5397 	} else {
5398 		val64 = readq(&bar0->adapter_control);
5399 		if (on)
5400 			val64 |= ADAPTER_LED_ON;
5401 		else
5402 			val64 &= ~ADAPTER_LED_ON;
5403 
5404 		writeq(val64, &bar0->adapter_control);
5405 	}
5406 
5407 }
5408 
5409 /**
5410  * s2io_ethtool_set_led - To physically identify the nic on the system.
5411  * @dev : network device
5412  * @state: led setting
5413  *
5414  * Description: Used to physically identify the NIC on the system.
5415  * The Link LED will blink for a time specified by the user for
5416  * identification.
5417  * NOTE: The Link has to be Up to be able to blink the LED. Hence
5418  * identification is possible only if it's link is up.
5419  */
5420 
s2io_ethtool_set_led(struct net_device * dev,enum ethtool_phys_id_state state)5421 static int s2io_ethtool_set_led(struct net_device *dev,
5422 				enum ethtool_phys_id_state state)
5423 {
5424 	struct s2io_nic *sp = netdev_priv(dev);
5425 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
5426 	u16 subid = sp->pdev->subsystem_device;
5427 
5428 	if ((sp->device_type == XFRAME_I_DEVICE) && ((subid & 0xFF) < 0x07)) {
5429 		u64 val64 = readq(&bar0->adapter_control);
5430 		if (!(val64 & ADAPTER_CNTL_EN)) {
5431 			pr_err("Adapter Link down, cannot blink LED\n");
5432 			return -EAGAIN;
5433 		}
5434 	}
5435 
5436 	switch (state) {
5437 	case ETHTOOL_ID_ACTIVE:
5438 		sp->adapt_ctrl_org = readq(&bar0->gpio_control);
5439 		return 1;	/* cycle on/off once per second */
5440 
5441 	case ETHTOOL_ID_ON:
5442 		s2io_set_led(sp, true);
5443 		break;
5444 
5445 	case ETHTOOL_ID_OFF:
5446 		s2io_set_led(sp, false);
5447 		break;
5448 
5449 	case ETHTOOL_ID_INACTIVE:
5450 		if (CARDS_WITH_FAULTY_LINK_INDICATORS(sp->device_type, subid))
5451 			writeq(sp->adapt_ctrl_org, &bar0->gpio_control);
5452 	}
5453 
5454 	return 0;
5455 }
5456 
5457 static void
s2io_ethtool_gringparam(struct net_device * dev,struct ethtool_ringparam * ering,struct kernel_ethtool_ringparam * kernel_ering,struct netlink_ext_ack * extack)5458 s2io_ethtool_gringparam(struct net_device *dev,
5459 			struct ethtool_ringparam *ering,
5460 			struct kernel_ethtool_ringparam *kernel_ering,
5461 			struct netlink_ext_ack *extack)
5462 {
5463 	struct s2io_nic *sp = netdev_priv(dev);
5464 	int i, tx_desc_count = 0, rx_desc_count = 0;
5465 
5466 	if (sp->rxd_mode == RXD_MODE_1) {
5467 		ering->rx_max_pending = MAX_RX_DESC_1;
5468 		ering->rx_jumbo_max_pending = MAX_RX_DESC_1;
5469 	} else {
5470 		ering->rx_max_pending = MAX_RX_DESC_2;
5471 		ering->rx_jumbo_max_pending = MAX_RX_DESC_2;
5472 	}
5473 
5474 	ering->tx_max_pending = MAX_TX_DESC;
5475 
5476 	for (i = 0; i < sp->config.rx_ring_num; i++)
5477 		rx_desc_count += sp->config.rx_cfg[i].num_rxd;
5478 	ering->rx_pending = rx_desc_count;
5479 	ering->rx_jumbo_pending = rx_desc_count;
5480 
5481 	for (i = 0; i < sp->config.tx_fifo_num; i++)
5482 		tx_desc_count += sp->config.tx_cfg[i].fifo_len;
5483 	ering->tx_pending = tx_desc_count;
5484 	DBG_PRINT(INFO_DBG, "max txds: %d\n", sp->config.max_txds);
5485 }
5486 
5487 /**
5488  * s2io_ethtool_getpause_data -Pause frame generation and reception.
5489  * @dev: pointer to netdev
5490  * @ep : pointer to the structure with pause parameters given by ethtool.
5491  * Description:
5492  * Returns the Pause frame generation and reception capability of the NIC.
5493  * Return value:
5494  *  void
5495  */
s2io_ethtool_getpause_data(struct net_device * dev,struct ethtool_pauseparam * ep)5496 static void s2io_ethtool_getpause_data(struct net_device *dev,
5497 				       struct ethtool_pauseparam *ep)
5498 {
5499 	u64 val64;
5500 	struct s2io_nic *sp = netdev_priv(dev);
5501 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
5502 
5503 	val64 = readq(&bar0->rmac_pause_cfg);
5504 	if (val64 & RMAC_PAUSE_GEN_ENABLE)
5505 		ep->tx_pause = true;
5506 	if (val64 & RMAC_PAUSE_RX_ENABLE)
5507 		ep->rx_pause = true;
5508 	ep->autoneg = false;
5509 }
5510 
5511 /**
5512  * s2io_ethtool_setpause_data -  set/reset pause frame generation.
5513  * @dev: pointer to netdev
5514  * @ep : pointer to the structure with pause parameters given by ethtool.
5515  * Description:
5516  * It can be used to set or reset Pause frame generation or reception
5517  * support of the NIC.
5518  * Return value:
5519  * int, returns 0 on Success
5520  */
5521 
s2io_ethtool_setpause_data(struct net_device * dev,struct ethtool_pauseparam * ep)5522 static int s2io_ethtool_setpause_data(struct net_device *dev,
5523 				      struct ethtool_pauseparam *ep)
5524 {
5525 	u64 val64;
5526 	struct s2io_nic *sp = netdev_priv(dev);
5527 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
5528 
5529 	val64 = readq(&bar0->rmac_pause_cfg);
5530 	if (ep->tx_pause)
5531 		val64 |= RMAC_PAUSE_GEN_ENABLE;
5532 	else
5533 		val64 &= ~RMAC_PAUSE_GEN_ENABLE;
5534 	if (ep->rx_pause)
5535 		val64 |= RMAC_PAUSE_RX_ENABLE;
5536 	else
5537 		val64 &= ~RMAC_PAUSE_RX_ENABLE;
5538 	writeq(val64, &bar0->rmac_pause_cfg);
5539 	return 0;
5540 }
5541 
5542 #define S2IO_DEV_ID		5
5543 /**
5544  * read_eeprom - reads 4 bytes of data from user given offset.
5545  * @sp : private member of the device structure, which is a pointer to the
5546  *      s2io_nic structure.
5547  * @off : offset at which the data must be written
5548  * @data : Its an output parameter where the data read at the given
5549  *	offset is stored.
5550  * Description:
5551  * Will read 4 bytes of data from the user given offset and return the
5552  * read data.
5553  * NOTE: Will allow to read only part of the EEPROM visible through the
5554  *   I2C bus.
5555  * Return value:
5556  *  -1 on failure and 0 on success.
5557  */
read_eeprom(struct s2io_nic * sp,int off,u64 * data)5558 static int read_eeprom(struct s2io_nic *sp, int off, u64 *data)
5559 {
5560 	int ret = -1;
5561 	u32 exit_cnt = 0;
5562 	u64 val64;
5563 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
5564 
5565 	if (sp->device_type == XFRAME_I_DEVICE) {
5566 		val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5567 			I2C_CONTROL_ADDR(off) |
5568 			I2C_CONTROL_BYTE_CNT(0x3) |
5569 			I2C_CONTROL_READ |
5570 			I2C_CONTROL_CNTL_START;
5571 		SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5572 
5573 		while (exit_cnt < 5) {
5574 			val64 = readq(&bar0->i2c_control);
5575 			if (I2C_CONTROL_CNTL_END(val64)) {
5576 				*data = I2C_CONTROL_GET_DATA(val64);
5577 				ret = 0;
5578 				break;
5579 			}
5580 			msleep(50);
5581 			exit_cnt++;
5582 		}
5583 	}
5584 
5585 	if (sp->device_type == XFRAME_II_DEVICE) {
5586 		val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5587 			SPI_CONTROL_BYTECNT(0x3) |
5588 			SPI_CONTROL_CMD(0x3) | SPI_CONTROL_ADDR(off);
5589 		SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5590 		val64 |= SPI_CONTROL_REQ;
5591 		SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5592 		while (exit_cnt < 5) {
5593 			val64 = readq(&bar0->spi_control);
5594 			if (val64 & SPI_CONTROL_NACK) {
5595 				ret = 1;
5596 				break;
5597 			} else if (val64 & SPI_CONTROL_DONE) {
5598 				*data = readq(&bar0->spi_data);
5599 				*data &= 0xffffff;
5600 				ret = 0;
5601 				break;
5602 			}
5603 			msleep(50);
5604 			exit_cnt++;
5605 		}
5606 	}
5607 	return ret;
5608 }
5609 
5610 /**
5611  *  write_eeprom - actually writes the relevant part of the data value.
5612  *  @sp : private member of the device structure, which is a pointer to the
5613  *       s2io_nic structure.
5614  *  @off : offset at which the data must be written
5615  *  @data : The data that is to be written
5616  *  @cnt : Number of bytes of the data that are actually to be written into
5617  *  the Eeprom. (max of 3)
5618  * Description:
5619  *  Actually writes the relevant part of the data value into the Eeprom
5620  *  through the I2C bus.
5621  * Return value:
5622  *  0 on success, -1 on failure.
5623  */
5624 
write_eeprom(struct s2io_nic * sp,int off,u64 data,int cnt)5625 static int write_eeprom(struct s2io_nic *sp, int off, u64 data, int cnt)
5626 {
5627 	int exit_cnt = 0, ret = -1;
5628 	u64 val64;
5629 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
5630 
5631 	if (sp->device_type == XFRAME_I_DEVICE) {
5632 		val64 = I2C_CONTROL_DEV_ID(S2IO_DEV_ID) |
5633 			I2C_CONTROL_ADDR(off) |
5634 			I2C_CONTROL_BYTE_CNT(cnt) |
5635 			I2C_CONTROL_SET_DATA((u32)data) |
5636 			I2C_CONTROL_CNTL_START;
5637 		SPECIAL_REG_WRITE(val64, &bar0->i2c_control, LF);
5638 
5639 		while (exit_cnt < 5) {
5640 			val64 = readq(&bar0->i2c_control);
5641 			if (I2C_CONTROL_CNTL_END(val64)) {
5642 				if (!(val64 & I2C_CONTROL_NACK))
5643 					ret = 0;
5644 				break;
5645 			}
5646 			msleep(50);
5647 			exit_cnt++;
5648 		}
5649 	}
5650 
5651 	if (sp->device_type == XFRAME_II_DEVICE) {
5652 		int write_cnt = (cnt == 8) ? 0 : cnt;
5653 		writeq(SPI_DATA_WRITE(data, (cnt << 3)), &bar0->spi_data);
5654 
5655 		val64 = SPI_CONTROL_KEY(0x9) | SPI_CONTROL_SEL1 |
5656 			SPI_CONTROL_BYTECNT(write_cnt) |
5657 			SPI_CONTROL_CMD(0x2) | SPI_CONTROL_ADDR(off);
5658 		SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5659 		val64 |= SPI_CONTROL_REQ;
5660 		SPECIAL_REG_WRITE(val64, &bar0->spi_control, LF);
5661 		while (exit_cnt < 5) {
5662 			val64 = readq(&bar0->spi_control);
5663 			if (val64 & SPI_CONTROL_NACK) {
5664 				ret = 1;
5665 				break;
5666 			} else if (val64 & SPI_CONTROL_DONE) {
5667 				ret = 0;
5668 				break;
5669 			}
5670 			msleep(50);
5671 			exit_cnt++;
5672 		}
5673 	}
5674 	return ret;
5675 }
s2io_vpd_read(struct s2io_nic * nic)5676 static void s2io_vpd_read(struct s2io_nic *nic)
5677 {
5678 	u8 *vpd_data;
5679 	u8 data;
5680 	int i = 0, cnt, len, fail = 0;
5681 	int vpd_addr = 0x80;
5682 	struct swStat *swstats = &nic->mac_control.stats_info->sw_stat;
5683 
5684 	if (nic->device_type == XFRAME_II_DEVICE) {
5685 		strcpy(nic->product_name, "Xframe II 10GbE network adapter");
5686 		vpd_addr = 0x80;
5687 	} else {
5688 		strcpy(nic->product_name, "Xframe I 10GbE network adapter");
5689 		vpd_addr = 0x50;
5690 	}
5691 	strcpy(nic->serial_num, "NOT AVAILABLE");
5692 
5693 	vpd_data = kmalloc(256, GFP_KERNEL);
5694 	if (!vpd_data) {
5695 		swstats->mem_alloc_fail_cnt++;
5696 		return;
5697 	}
5698 	swstats->mem_allocated += 256;
5699 
5700 	for (i = 0; i < 256; i += 4) {
5701 		pci_write_config_byte(nic->pdev, (vpd_addr + 2), i);
5702 		pci_read_config_byte(nic->pdev,  (vpd_addr + 2), &data);
5703 		pci_write_config_byte(nic->pdev, (vpd_addr + 3), 0);
5704 		for (cnt = 0; cnt < 5; cnt++) {
5705 			msleep(2);
5706 			pci_read_config_byte(nic->pdev, (vpd_addr + 3), &data);
5707 			if (data == 0x80)
5708 				break;
5709 		}
5710 		if (cnt >= 5) {
5711 			DBG_PRINT(ERR_DBG, "Read of VPD data failed\n");
5712 			fail = 1;
5713 			break;
5714 		}
5715 		pci_read_config_dword(nic->pdev,  (vpd_addr + 4),
5716 				      (u32 *)&vpd_data[i]);
5717 	}
5718 
5719 	if (!fail) {
5720 		/* read serial number of adapter */
5721 		for (cnt = 0; cnt < 252; cnt++) {
5722 			if ((vpd_data[cnt] == 'S') &&
5723 			    (vpd_data[cnt+1] == 'N')) {
5724 				len = vpd_data[cnt+2];
5725 				if (len < min(VPD_STRING_LEN, 256-cnt-2)) {
5726 					memcpy(nic->serial_num,
5727 					       &vpd_data[cnt + 3],
5728 					       len);
5729 					memset(nic->serial_num+len,
5730 					       0,
5731 					       VPD_STRING_LEN-len);
5732 					break;
5733 				}
5734 			}
5735 		}
5736 	}
5737 
5738 	if ((!fail) && (vpd_data[1] < VPD_STRING_LEN)) {
5739 		len = vpd_data[1];
5740 		memcpy(nic->product_name, &vpd_data[3], len);
5741 		nic->product_name[len] = 0;
5742 	}
5743 	kfree(vpd_data);
5744 	swstats->mem_freed += 256;
5745 }
5746 
5747 /**
5748  *  s2io_ethtool_geeprom  - reads the value stored in the Eeprom.
5749  *  @dev: pointer to netdev
5750  *  @eeprom : pointer to the user level structure provided by ethtool,
5751  *  containing all relevant information.
5752  *  @data_buf : user defined value to be written into Eeprom.
5753  *  Description: Reads the values stored in the Eeprom at given offset
5754  *  for a given length. Stores these values int the input argument data
5755  *  buffer 'data_buf' and returns these to the caller (ethtool.)
5756  *  Return value:
5757  *  int  0 on success
5758  */
5759 
s2io_ethtool_geeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data_buf)5760 static int s2io_ethtool_geeprom(struct net_device *dev,
5761 				struct ethtool_eeprom *eeprom, u8 * data_buf)
5762 {
5763 	u32 i, valid;
5764 	u64 data;
5765 	struct s2io_nic *sp = netdev_priv(dev);
5766 
5767 	eeprom->magic = sp->pdev->vendor | (sp->pdev->device << 16);
5768 
5769 	if ((eeprom->offset + eeprom->len) > (XENA_EEPROM_SPACE))
5770 		eeprom->len = XENA_EEPROM_SPACE - eeprom->offset;
5771 
5772 	for (i = 0; i < eeprom->len; i += 4) {
5773 		if (read_eeprom(sp, (eeprom->offset + i), &data)) {
5774 			DBG_PRINT(ERR_DBG, "Read of EEPROM failed\n");
5775 			return -EFAULT;
5776 		}
5777 		valid = INV(data);
5778 		memcpy((data_buf + i), &valid, 4);
5779 	}
5780 	return 0;
5781 }
5782 
5783 /**
5784  *  s2io_ethtool_seeprom - tries to write the user provided value in Eeprom
5785  *  @dev: pointer to netdev
5786  *  @eeprom : pointer to the user level structure provided by ethtool,
5787  *  containing all relevant information.
5788  *  @data_buf : user defined value to be written into Eeprom.
5789  *  Description:
5790  *  Tries to write the user provided value in the Eeprom, at the offset
5791  *  given by the user.
5792  *  Return value:
5793  *  0 on success, -EFAULT on failure.
5794  */
5795 
s2io_ethtool_seeprom(struct net_device * dev,struct ethtool_eeprom * eeprom,u8 * data_buf)5796 static int s2io_ethtool_seeprom(struct net_device *dev,
5797 				struct ethtool_eeprom *eeprom,
5798 				u8 *data_buf)
5799 {
5800 	int len = eeprom->len, cnt = 0;
5801 	u64 valid = 0, data;
5802 	struct s2io_nic *sp = netdev_priv(dev);
5803 
5804 	if (eeprom->magic != (sp->pdev->vendor | (sp->pdev->device << 16))) {
5805 		DBG_PRINT(ERR_DBG,
5806 			  "ETHTOOL_WRITE_EEPROM Err: "
5807 			  "Magic value is wrong, it is 0x%x should be 0x%x\n",
5808 			  (sp->pdev->vendor | (sp->pdev->device << 16)),
5809 			  eeprom->magic);
5810 		return -EFAULT;
5811 	}
5812 
5813 	while (len) {
5814 		data = (u32)data_buf[cnt] & 0x000000FF;
5815 		if (data)
5816 			valid = (u32)(data << 24);
5817 		else
5818 			valid = data;
5819 
5820 		if (write_eeprom(sp, (eeprom->offset + cnt), valid, 0)) {
5821 			DBG_PRINT(ERR_DBG,
5822 				  "ETHTOOL_WRITE_EEPROM Err: "
5823 				  "Cannot write into the specified offset\n");
5824 			return -EFAULT;
5825 		}
5826 		cnt++;
5827 		len--;
5828 	}
5829 
5830 	return 0;
5831 }
5832 
5833 /**
5834  * s2io_register_test - reads and writes into all clock domains.
5835  * @sp : private member of the device structure, which is a pointer to the
5836  * s2io_nic structure.
5837  * @data : variable that returns the result of each of the test conducted b
5838  * by the driver.
5839  * Description:
5840  * Read and write into all clock domains. The NIC has 3 clock domains,
5841  * see that registers in all the three regions are accessible.
5842  * Return value:
5843  * 0 on success.
5844  */
5845 
s2io_register_test(struct s2io_nic * sp,uint64_t * data)5846 static int s2io_register_test(struct s2io_nic *sp, uint64_t *data)
5847 {
5848 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
5849 	u64 val64 = 0, exp_val;
5850 	int fail = 0;
5851 
5852 	val64 = readq(&bar0->pif_rd_swapper_fb);
5853 	if (val64 != 0x123456789abcdefULL) {
5854 		fail = 1;
5855 		DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 1);
5856 	}
5857 
5858 	val64 = readq(&bar0->rmac_pause_cfg);
5859 	if (val64 != 0xc000ffff00000000ULL) {
5860 		fail = 1;
5861 		DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 2);
5862 	}
5863 
5864 	val64 = readq(&bar0->rx_queue_cfg);
5865 	if (sp->device_type == XFRAME_II_DEVICE)
5866 		exp_val = 0x0404040404040404ULL;
5867 	else
5868 		exp_val = 0x0808080808080808ULL;
5869 	if (val64 != exp_val) {
5870 		fail = 1;
5871 		DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 3);
5872 	}
5873 
5874 	val64 = readq(&bar0->xgxs_efifo_cfg);
5875 	if (val64 != 0x000000001923141EULL) {
5876 		fail = 1;
5877 		DBG_PRINT(INFO_DBG, "Read Test level %d fails\n", 4);
5878 	}
5879 
5880 	val64 = 0x5A5A5A5A5A5A5A5AULL;
5881 	writeq(val64, &bar0->xmsi_data);
5882 	val64 = readq(&bar0->xmsi_data);
5883 	if (val64 != 0x5A5A5A5A5A5A5A5AULL) {
5884 		fail = 1;
5885 		DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 1);
5886 	}
5887 
5888 	val64 = 0xA5A5A5A5A5A5A5A5ULL;
5889 	writeq(val64, &bar0->xmsi_data);
5890 	val64 = readq(&bar0->xmsi_data);
5891 	if (val64 != 0xA5A5A5A5A5A5A5A5ULL) {
5892 		fail = 1;
5893 		DBG_PRINT(ERR_DBG, "Write Test level %d fails\n", 2);
5894 	}
5895 
5896 	*data = fail;
5897 	return fail;
5898 }
5899 
5900 /**
5901  * s2io_eeprom_test - to verify that EEprom in the xena can be programmed.
5902  * @sp : private member of the device structure, which is a pointer to the
5903  * s2io_nic structure.
5904  * @data:variable that returns the result of each of the test conducted by
5905  * the driver.
5906  * Description:
5907  * Verify that EEPROM in the xena can be programmed using I2C_CONTROL
5908  * register.
5909  * Return value:
5910  * 0 on success.
5911  */
5912 
s2io_eeprom_test(struct s2io_nic * sp,uint64_t * data)5913 static int s2io_eeprom_test(struct s2io_nic *sp, uint64_t *data)
5914 {
5915 	int fail = 0;
5916 	u64 ret_data, org_4F0, org_7F0;
5917 	u8 saved_4F0 = 0, saved_7F0 = 0;
5918 	struct net_device *dev = sp->dev;
5919 
5920 	/* Test Write Error at offset 0 */
5921 	/* Note that SPI interface allows write access to all areas
5922 	 * of EEPROM. Hence doing all negative testing only for Xframe I.
5923 	 */
5924 	if (sp->device_type == XFRAME_I_DEVICE)
5925 		if (!write_eeprom(sp, 0, 0, 3))
5926 			fail = 1;
5927 
5928 	/* Save current values at offsets 0x4F0 and 0x7F0 */
5929 	if (!read_eeprom(sp, 0x4F0, &org_4F0))
5930 		saved_4F0 = 1;
5931 	if (!read_eeprom(sp, 0x7F0, &org_7F0))
5932 		saved_7F0 = 1;
5933 
5934 	/* Test Write at offset 4f0 */
5935 	if (write_eeprom(sp, 0x4F0, 0x012345, 3))
5936 		fail = 1;
5937 	if (read_eeprom(sp, 0x4F0, &ret_data))
5938 		fail = 1;
5939 
5940 	if (ret_data != 0x012345) {
5941 		DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x4F0. "
5942 			  "Data written %llx Data read %llx\n",
5943 			  dev->name, (unsigned long long)0x12345,
5944 			  (unsigned long long)ret_data);
5945 		fail = 1;
5946 	}
5947 
5948 	/* Reset the EEPROM data go FFFF */
5949 	write_eeprom(sp, 0x4F0, 0xFFFFFF, 3);
5950 
5951 	/* Test Write Request Error at offset 0x7c */
5952 	if (sp->device_type == XFRAME_I_DEVICE)
5953 		if (!write_eeprom(sp, 0x07C, 0, 3))
5954 			fail = 1;
5955 
5956 	/* Test Write Request at offset 0x7f0 */
5957 	if (write_eeprom(sp, 0x7F0, 0x012345, 3))
5958 		fail = 1;
5959 	if (read_eeprom(sp, 0x7F0, &ret_data))
5960 		fail = 1;
5961 
5962 	if (ret_data != 0x012345) {
5963 		DBG_PRINT(ERR_DBG, "%s: eeprom test error at offset 0x7F0. "
5964 			  "Data written %llx Data read %llx\n",
5965 			  dev->name, (unsigned long long)0x12345,
5966 			  (unsigned long long)ret_data);
5967 		fail = 1;
5968 	}
5969 
5970 	/* Reset the EEPROM data go FFFF */
5971 	write_eeprom(sp, 0x7F0, 0xFFFFFF, 3);
5972 
5973 	if (sp->device_type == XFRAME_I_DEVICE) {
5974 		/* Test Write Error at offset 0x80 */
5975 		if (!write_eeprom(sp, 0x080, 0, 3))
5976 			fail = 1;
5977 
5978 		/* Test Write Error at offset 0xfc */
5979 		if (!write_eeprom(sp, 0x0FC, 0, 3))
5980 			fail = 1;
5981 
5982 		/* Test Write Error at offset 0x100 */
5983 		if (!write_eeprom(sp, 0x100, 0, 3))
5984 			fail = 1;
5985 
5986 		/* Test Write Error at offset 4ec */
5987 		if (!write_eeprom(sp, 0x4EC, 0, 3))
5988 			fail = 1;
5989 	}
5990 
5991 	/* Restore values at offsets 0x4F0 and 0x7F0 */
5992 	if (saved_4F0)
5993 		write_eeprom(sp, 0x4F0, org_4F0, 3);
5994 	if (saved_7F0)
5995 		write_eeprom(sp, 0x7F0, org_7F0, 3);
5996 
5997 	*data = fail;
5998 	return fail;
5999 }
6000 
6001 /**
6002  * s2io_bist_test - invokes the MemBist test of the card .
6003  * @sp : private member of the device structure, which is a pointer to the
6004  * s2io_nic structure.
6005  * @data:variable that returns the result of each of the test conducted by
6006  * the driver.
6007  * Description:
6008  * This invokes the MemBist test of the card. We give around
6009  * 2 secs time for the Test to complete. If it's still not complete
6010  * within this peiod, we consider that the test failed.
6011  * Return value:
6012  * 0 on success and -1 on failure.
6013  */
6014 
s2io_bist_test(struct s2io_nic * sp,uint64_t * data)6015 static int s2io_bist_test(struct s2io_nic *sp, uint64_t *data)
6016 {
6017 	u8 bist = 0;
6018 	int cnt = 0, ret = -1;
6019 
6020 	pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6021 	bist |= PCI_BIST_START;
6022 	pci_write_config_word(sp->pdev, PCI_BIST, bist);
6023 
6024 	while (cnt < 20) {
6025 		pci_read_config_byte(sp->pdev, PCI_BIST, &bist);
6026 		if (!(bist & PCI_BIST_START)) {
6027 			*data = (bist & PCI_BIST_CODE_MASK);
6028 			ret = 0;
6029 			break;
6030 		}
6031 		msleep(100);
6032 		cnt++;
6033 	}
6034 
6035 	return ret;
6036 }
6037 
6038 /**
6039  * s2io_link_test - verifies the link state of the nic
6040  * @sp: private member of the device structure, which is a pointer to the
6041  * s2io_nic structure.
6042  * @data: variable that returns the result of each of the test conducted by
6043  * the driver.
6044  * Description:
6045  * The function verifies the link state of the NIC and updates the input
6046  * argument 'data' appropriately.
6047  * Return value:
6048  * 0 on success.
6049  */
6050 
s2io_link_test(struct s2io_nic * sp,uint64_t * data)6051 static int s2io_link_test(struct s2io_nic *sp, uint64_t *data)
6052 {
6053 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
6054 	u64 val64;
6055 
6056 	val64 = readq(&bar0->adapter_status);
6057 	if (!(LINK_IS_UP(val64)))
6058 		*data = 1;
6059 	else
6060 		*data = 0;
6061 
6062 	return *data;
6063 }
6064 
6065 /**
6066  * s2io_rldram_test - offline test for access to the RldRam chip on the NIC
6067  * @sp: private member of the device structure, which is a pointer to the
6068  * s2io_nic structure.
6069  * @data: variable that returns the result of each of the test
6070  * conducted by the driver.
6071  * Description:
6072  *  This is one of the offline test that tests the read and write
6073  *  access to the RldRam chip on the NIC.
6074  * Return value:
6075  *  0 on success.
6076  */
6077 
s2io_rldram_test(struct s2io_nic * sp,uint64_t * data)6078 static int s2io_rldram_test(struct s2io_nic *sp, uint64_t *data)
6079 {
6080 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
6081 	u64 val64;
6082 	int cnt, iteration = 0, test_fail = 0;
6083 
6084 	val64 = readq(&bar0->adapter_control);
6085 	val64 &= ~ADAPTER_ECC_EN;
6086 	writeq(val64, &bar0->adapter_control);
6087 
6088 	val64 = readq(&bar0->mc_rldram_test_ctrl);
6089 	val64 |= MC_RLDRAM_TEST_MODE;
6090 	SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6091 
6092 	val64 = readq(&bar0->mc_rldram_mrs);
6093 	val64 |= MC_RLDRAM_QUEUE_SIZE_ENABLE;
6094 	SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6095 
6096 	val64 |= MC_RLDRAM_MRS_ENABLE;
6097 	SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_mrs, UF);
6098 
6099 	while (iteration < 2) {
6100 		val64 = 0x55555555aaaa0000ULL;
6101 		if (iteration == 1)
6102 			val64 ^= 0xFFFFFFFFFFFF0000ULL;
6103 		writeq(val64, &bar0->mc_rldram_test_d0);
6104 
6105 		val64 = 0xaaaa5a5555550000ULL;
6106 		if (iteration == 1)
6107 			val64 ^= 0xFFFFFFFFFFFF0000ULL;
6108 		writeq(val64, &bar0->mc_rldram_test_d1);
6109 
6110 		val64 = 0x55aaaaaaaa5a0000ULL;
6111 		if (iteration == 1)
6112 			val64 ^= 0xFFFFFFFFFFFF0000ULL;
6113 		writeq(val64, &bar0->mc_rldram_test_d2);
6114 
6115 		val64 = (u64) (0x0000003ffffe0100ULL);
6116 		writeq(val64, &bar0->mc_rldram_test_add);
6117 
6118 		val64 = MC_RLDRAM_TEST_MODE |
6119 			MC_RLDRAM_TEST_WRITE |
6120 			MC_RLDRAM_TEST_GO;
6121 		SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6122 
6123 		for (cnt = 0; cnt < 5; cnt++) {
6124 			val64 = readq(&bar0->mc_rldram_test_ctrl);
6125 			if (val64 & MC_RLDRAM_TEST_DONE)
6126 				break;
6127 			msleep(200);
6128 		}
6129 
6130 		if (cnt == 5)
6131 			break;
6132 
6133 		val64 = MC_RLDRAM_TEST_MODE | MC_RLDRAM_TEST_GO;
6134 		SPECIAL_REG_WRITE(val64, &bar0->mc_rldram_test_ctrl, LF);
6135 
6136 		for (cnt = 0; cnt < 5; cnt++) {
6137 			val64 = readq(&bar0->mc_rldram_test_ctrl);
6138 			if (val64 & MC_RLDRAM_TEST_DONE)
6139 				break;
6140 			msleep(500);
6141 		}
6142 
6143 		if (cnt == 5)
6144 			break;
6145 
6146 		val64 = readq(&bar0->mc_rldram_test_ctrl);
6147 		if (!(val64 & MC_RLDRAM_TEST_PASS))
6148 			test_fail = 1;
6149 
6150 		iteration++;
6151 	}
6152 
6153 	*data = test_fail;
6154 
6155 	/* Bring the adapter out of test mode */
6156 	SPECIAL_REG_WRITE(0, &bar0->mc_rldram_test_ctrl, LF);
6157 
6158 	return test_fail;
6159 }
6160 
6161 /**
6162  *  s2io_ethtool_test - conducts 6 tsets to determine the health of card.
6163  *  @dev: pointer to netdev
6164  *  @ethtest : pointer to a ethtool command specific structure that will be
6165  *  returned to the user.
6166  *  @data : variable that returns the result of each of the test
6167  * conducted by the driver.
6168  * Description:
6169  *  This function conducts 6 tests ( 4 offline and 2 online) to determine
6170  *  the health of the card.
6171  * Return value:
6172  *  void
6173  */
6174 
s2io_ethtool_test(struct net_device * dev,struct ethtool_test * ethtest,uint64_t * data)6175 static void s2io_ethtool_test(struct net_device *dev,
6176 			      struct ethtool_test *ethtest,
6177 			      uint64_t *data)
6178 {
6179 	struct s2io_nic *sp = netdev_priv(dev);
6180 	int orig_state = netif_running(sp->dev);
6181 
6182 	if (ethtest->flags == ETH_TEST_FL_OFFLINE) {
6183 		/* Offline Tests. */
6184 		if (orig_state)
6185 			s2io_close(sp->dev);
6186 
6187 		if (s2io_register_test(sp, &data[0]))
6188 			ethtest->flags |= ETH_TEST_FL_FAILED;
6189 
6190 		s2io_reset(sp);
6191 
6192 		if (s2io_rldram_test(sp, &data[3]))
6193 			ethtest->flags |= ETH_TEST_FL_FAILED;
6194 
6195 		s2io_reset(sp);
6196 
6197 		if (s2io_eeprom_test(sp, &data[1]))
6198 			ethtest->flags |= ETH_TEST_FL_FAILED;
6199 
6200 		if (s2io_bist_test(sp, &data[4]))
6201 			ethtest->flags |= ETH_TEST_FL_FAILED;
6202 
6203 		if (orig_state)
6204 			s2io_open(sp->dev);
6205 
6206 		data[2] = 0;
6207 	} else {
6208 		/* Online Tests. */
6209 		if (!orig_state) {
6210 			DBG_PRINT(ERR_DBG, "%s: is not up, cannot run test\n",
6211 				  dev->name);
6212 			data[0] = -1;
6213 			data[1] = -1;
6214 			data[2] = -1;
6215 			data[3] = -1;
6216 			data[4] = -1;
6217 		}
6218 
6219 		if (s2io_link_test(sp, &data[2]))
6220 			ethtest->flags |= ETH_TEST_FL_FAILED;
6221 
6222 		data[0] = 0;
6223 		data[1] = 0;
6224 		data[3] = 0;
6225 		data[4] = 0;
6226 	}
6227 }
6228 
s2io_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * estats,u64 * tmp_stats)6229 static void s2io_get_ethtool_stats(struct net_device *dev,
6230 				   struct ethtool_stats *estats,
6231 				   u64 *tmp_stats)
6232 {
6233 	int i = 0, k;
6234 	struct s2io_nic *sp = netdev_priv(dev);
6235 	struct stat_block *stats = sp->mac_control.stats_info;
6236 	struct swStat *swstats = &stats->sw_stat;
6237 	struct xpakStat *xstats = &stats->xpak_stat;
6238 
6239 	s2io_updt_stats(sp);
6240 	tmp_stats[i++] =
6241 		(u64)le32_to_cpu(stats->tmac_frms_oflow) << 32  |
6242 		le32_to_cpu(stats->tmac_frms);
6243 	tmp_stats[i++] =
6244 		(u64)le32_to_cpu(stats->tmac_data_octets_oflow) << 32 |
6245 		le32_to_cpu(stats->tmac_data_octets);
6246 	tmp_stats[i++] = le64_to_cpu(stats->tmac_drop_frms);
6247 	tmp_stats[i++] =
6248 		(u64)le32_to_cpu(stats->tmac_mcst_frms_oflow) << 32 |
6249 		le32_to_cpu(stats->tmac_mcst_frms);
6250 	tmp_stats[i++] =
6251 		(u64)le32_to_cpu(stats->tmac_bcst_frms_oflow) << 32 |
6252 		le32_to_cpu(stats->tmac_bcst_frms);
6253 	tmp_stats[i++] = le64_to_cpu(stats->tmac_pause_ctrl_frms);
6254 	tmp_stats[i++] =
6255 		(u64)le32_to_cpu(stats->tmac_ttl_octets_oflow) << 32 |
6256 		le32_to_cpu(stats->tmac_ttl_octets);
6257 	tmp_stats[i++] =
6258 		(u64)le32_to_cpu(stats->tmac_ucst_frms_oflow) << 32 |
6259 		le32_to_cpu(stats->tmac_ucst_frms);
6260 	tmp_stats[i++] =
6261 		(u64)le32_to_cpu(stats->tmac_nucst_frms_oflow) << 32 |
6262 		le32_to_cpu(stats->tmac_nucst_frms);
6263 	tmp_stats[i++] =
6264 		(u64)le32_to_cpu(stats->tmac_any_err_frms_oflow) << 32 |
6265 		le32_to_cpu(stats->tmac_any_err_frms);
6266 	tmp_stats[i++] = le64_to_cpu(stats->tmac_ttl_less_fb_octets);
6267 	tmp_stats[i++] = le64_to_cpu(stats->tmac_vld_ip_octets);
6268 	tmp_stats[i++] =
6269 		(u64)le32_to_cpu(stats->tmac_vld_ip_oflow) << 32 |
6270 		le32_to_cpu(stats->tmac_vld_ip);
6271 	tmp_stats[i++] =
6272 		(u64)le32_to_cpu(stats->tmac_drop_ip_oflow) << 32 |
6273 		le32_to_cpu(stats->tmac_drop_ip);
6274 	tmp_stats[i++] =
6275 		(u64)le32_to_cpu(stats->tmac_icmp_oflow) << 32 |
6276 		le32_to_cpu(stats->tmac_icmp);
6277 	tmp_stats[i++] =
6278 		(u64)le32_to_cpu(stats->tmac_rst_tcp_oflow) << 32 |
6279 		le32_to_cpu(stats->tmac_rst_tcp);
6280 	tmp_stats[i++] = le64_to_cpu(stats->tmac_tcp);
6281 	tmp_stats[i++] = (u64)le32_to_cpu(stats->tmac_udp_oflow) << 32 |
6282 		le32_to_cpu(stats->tmac_udp);
6283 	tmp_stats[i++] =
6284 		(u64)le32_to_cpu(stats->rmac_vld_frms_oflow) << 32 |
6285 		le32_to_cpu(stats->rmac_vld_frms);
6286 	tmp_stats[i++] =
6287 		(u64)le32_to_cpu(stats->rmac_data_octets_oflow) << 32 |
6288 		le32_to_cpu(stats->rmac_data_octets);
6289 	tmp_stats[i++] = le64_to_cpu(stats->rmac_fcs_err_frms);
6290 	tmp_stats[i++] = le64_to_cpu(stats->rmac_drop_frms);
6291 	tmp_stats[i++] =
6292 		(u64)le32_to_cpu(stats->rmac_vld_mcst_frms_oflow) << 32 |
6293 		le32_to_cpu(stats->rmac_vld_mcst_frms);
6294 	tmp_stats[i++] =
6295 		(u64)le32_to_cpu(stats->rmac_vld_bcst_frms_oflow) << 32 |
6296 		le32_to_cpu(stats->rmac_vld_bcst_frms);
6297 	tmp_stats[i++] = le32_to_cpu(stats->rmac_in_rng_len_err_frms);
6298 	tmp_stats[i++] = le32_to_cpu(stats->rmac_out_rng_len_err_frms);
6299 	tmp_stats[i++] = le64_to_cpu(stats->rmac_long_frms);
6300 	tmp_stats[i++] = le64_to_cpu(stats->rmac_pause_ctrl_frms);
6301 	tmp_stats[i++] = le64_to_cpu(stats->rmac_unsup_ctrl_frms);
6302 	tmp_stats[i++] =
6303 		(u64)le32_to_cpu(stats->rmac_ttl_octets_oflow) << 32 |
6304 		le32_to_cpu(stats->rmac_ttl_octets);
6305 	tmp_stats[i++] =
6306 		(u64)le32_to_cpu(stats->rmac_accepted_ucst_frms_oflow) << 32
6307 		| le32_to_cpu(stats->rmac_accepted_ucst_frms);
6308 	tmp_stats[i++] =
6309 		(u64)le32_to_cpu(stats->rmac_accepted_nucst_frms_oflow)
6310 		<< 32 | le32_to_cpu(stats->rmac_accepted_nucst_frms);
6311 	tmp_stats[i++] =
6312 		(u64)le32_to_cpu(stats->rmac_discarded_frms_oflow) << 32 |
6313 		le32_to_cpu(stats->rmac_discarded_frms);
6314 	tmp_stats[i++] =
6315 		(u64)le32_to_cpu(stats->rmac_drop_events_oflow)
6316 		<< 32 | le32_to_cpu(stats->rmac_drop_events);
6317 	tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_less_fb_octets);
6318 	tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_frms);
6319 	tmp_stats[i++] =
6320 		(u64)le32_to_cpu(stats->rmac_usized_frms_oflow) << 32 |
6321 		le32_to_cpu(stats->rmac_usized_frms);
6322 	tmp_stats[i++] =
6323 		(u64)le32_to_cpu(stats->rmac_osized_frms_oflow) << 32 |
6324 		le32_to_cpu(stats->rmac_osized_frms);
6325 	tmp_stats[i++] =
6326 		(u64)le32_to_cpu(stats->rmac_frag_frms_oflow) << 32 |
6327 		le32_to_cpu(stats->rmac_frag_frms);
6328 	tmp_stats[i++] =
6329 		(u64)le32_to_cpu(stats->rmac_jabber_frms_oflow) << 32 |
6330 		le32_to_cpu(stats->rmac_jabber_frms);
6331 	tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_64_frms);
6332 	tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_65_127_frms);
6333 	tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_128_255_frms);
6334 	tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_256_511_frms);
6335 	tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_512_1023_frms);
6336 	tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_1024_1518_frms);
6337 	tmp_stats[i++] =
6338 		(u64)le32_to_cpu(stats->rmac_ip_oflow) << 32 |
6339 		le32_to_cpu(stats->rmac_ip);
6340 	tmp_stats[i++] = le64_to_cpu(stats->rmac_ip_octets);
6341 	tmp_stats[i++] = le32_to_cpu(stats->rmac_hdr_err_ip);
6342 	tmp_stats[i++] =
6343 		(u64)le32_to_cpu(stats->rmac_drop_ip_oflow) << 32 |
6344 		le32_to_cpu(stats->rmac_drop_ip);
6345 	tmp_stats[i++] =
6346 		(u64)le32_to_cpu(stats->rmac_icmp_oflow) << 32 |
6347 		le32_to_cpu(stats->rmac_icmp);
6348 	tmp_stats[i++] = le64_to_cpu(stats->rmac_tcp);
6349 	tmp_stats[i++] =
6350 		(u64)le32_to_cpu(stats->rmac_udp_oflow) << 32 |
6351 		le32_to_cpu(stats->rmac_udp);
6352 	tmp_stats[i++] =
6353 		(u64)le32_to_cpu(stats->rmac_err_drp_udp_oflow) << 32 |
6354 		le32_to_cpu(stats->rmac_err_drp_udp);
6355 	tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_err_sym);
6356 	tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q0);
6357 	tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q1);
6358 	tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q2);
6359 	tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q3);
6360 	tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q4);
6361 	tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q5);
6362 	tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q6);
6363 	tmp_stats[i++] = le64_to_cpu(stats->rmac_frms_q7);
6364 	tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q0);
6365 	tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q1);
6366 	tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q2);
6367 	tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q3);
6368 	tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q4);
6369 	tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q5);
6370 	tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q6);
6371 	tmp_stats[i++] = le16_to_cpu(stats->rmac_full_q7);
6372 	tmp_stats[i++] =
6373 		(u64)le32_to_cpu(stats->rmac_pause_cnt_oflow) << 32 |
6374 		le32_to_cpu(stats->rmac_pause_cnt);
6375 	tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_data_err_cnt);
6376 	tmp_stats[i++] = le64_to_cpu(stats->rmac_xgmii_ctrl_err_cnt);
6377 	tmp_stats[i++] =
6378 		(u64)le32_to_cpu(stats->rmac_accepted_ip_oflow) << 32 |
6379 		le32_to_cpu(stats->rmac_accepted_ip);
6380 	tmp_stats[i++] = le32_to_cpu(stats->rmac_err_tcp);
6381 	tmp_stats[i++] = le32_to_cpu(stats->rd_req_cnt);
6382 	tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_cnt);
6383 	tmp_stats[i++] = le32_to_cpu(stats->new_rd_req_rtry_cnt);
6384 	tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_cnt);
6385 	tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_rd_ack_cnt);
6386 	tmp_stats[i++] = le32_to_cpu(stats->wr_req_cnt);
6387 	tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_cnt);
6388 	tmp_stats[i++] = le32_to_cpu(stats->new_wr_req_rtry_cnt);
6389 	tmp_stats[i++] = le32_to_cpu(stats->wr_rtry_cnt);
6390 	tmp_stats[i++] = le32_to_cpu(stats->wr_disc_cnt);
6391 	tmp_stats[i++] = le32_to_cpu(stats->rd_rtry_wr_ack_cnt);
6392 	tmp_stats[i++] = le32_to_cpu(stats->txp_wr_cnt);
6393 	tmp_stats[i++] = le32_to_cpu(stats->txd_rd_cnt);
6394 	tmp_stats[i++] = le32_to_cpu(stats->txd_wr_cnt);
6395 	tmp_stats[i++] = le32_to_cpu(stats->rxd_rd_cnt);
6396 	tmp_stats[i++] = le32_to_cpu(stats->rxd_wr_cnt);
6397 	tmp_stats[i++] = le32_to_cpu(stats->txf_rd_cnt);
6398 	tmp_stats[i++] = le32_to_cpu(stats->rxf_wr_cnt);
6399 
6400 	/* Enhanced statistics exist only for Hercules */
6401 	if (sp->device_type == XFRAME_II_DEVICE) {
6402 		tmp_stats[i++] =
6403 			le64_to_cpu(stats->rmac_ttl_1519_4095_frms);
6404 		tmp_stats[i++] =
6405 			le64_to_cpu(stats->rmac_ttl_4096_8191_frms);
6406 		tmp_stats[i++] =
6407 			le64_to_cpu(stats->rmac_ttl_8192_max_frms);
6408 		tmp_stats[i++] = le64_to_cpu(stats->rmac_ttl_gt_max_frms);
6409 		tmp_stats[i++] = le64_to_cpu(stats->rmac_osized_alt_frms);
6410 		tmp_stats[i++] = le64_to_cpu(stats->rmac_jabber_alt_frms);
6411 		tmp_stats[i++] = le64_to_cpu(stats->rmac_gt_max_alt_frms);
6412 		tmp_stats[i++] = le64_to_cpu(stats->rmac_vlan_frms);
6413 		tmp_stats[i++] = le32_to_cpu(stats->rmac_len_discard);
6414 		tmp_stats[i++] = le32_to_cpu(stats->rmac_fcs_discard);
6415 		tmp_stats[i++] = le32_to_cpu(stats->rmac_pf_discard);
6416 		tmp_stats[i++] = le32_to_cpu(stats->rmac_da_discard);
6417 		tmp_stats[i++] = le32_to_cpu(stats->rmac_red_discard);
6418 		tmp_stats[i++] = le32_to_cpu(stats->rmac_rts_discard);
6419 		tmp_stats[i++] = le32_to_cpu(stats->rmac_ingm_full_discard);
6420 		tmp_stats[i++] = le32_to_cpu(stats->link_fault_cnt);
6421 	}
6422 
6423 	tmp_stats[i++] = 0;
6424 	tmp_stats[i++] = swstats->single_ecc_errs;
6425 	tmp_stats[i++] = swstats->double_ecc_errs;
6426 	tmp_stats[i++] = swstats->parity_err_cnt;
6427 	tmp_stats[i++] = swstats->serious_err_cnt;
6428 	tmp_stats[i++] = swstats->soft_reset_cnt;
6429 	tmp_stats[i++] = swstats->fifo_full_cnt;
6430 	for (k = 0; k < MAX_RX_RINGS; k++)
6431 		tmp_stats[i++] = swstats->ring_full_cnt[k];
6432 	tmp_stats[i++] = xstats->alarm_transceiver_temp_high;
6433 	tmp_stats[i++] = xstats->alarm_transceiver_temp_low;
6434 	tmp_stats[i++] = xstats->alarm_laser_bias_current_high;
6435 	tmp_stats[i++] = xstats->alarm_laser_bias_current_low;
6436 	tmp_stats[i++] = xstats->alarm_laser_output_power_high;
6437 	tmp_stats[i++] = xstats->alarm_laser_output_power_low;
6438 	tmp_stats[i++] = xstats->warn_transceiver_temp_high;
6439 	tmp_stats[i++] = xstats->warn_transceiver_temp_low;
6440 	tmp_stats[i++] = xstats->warn_laser_bias_current_high;
6441 	tmp_stats[i++] = xstats->warn_laser_bias_current_low;
6442 	tmp_stats[i++] = xstats->warn_laser_output_power_high;
6443 	tmp_stats[i++] = xstats->warn_laser_output_power_low;
6444 	tmp_stats[i++] = swstats->clubbed_frms_cnt;
6445 	tmp_stats[i++] = swstats->sending_both;
6446 	tmp_stats[i++] = swstats->outof_sequence_pkts;
6447 	tmp_stats[i++] = swstats->flush_max_pkts;
6448 	if (swstats->num_aggregations) {
6449 		u64 tmp = swstats->sum_avg_pkts_aggregated;
6450 		int count = 0;
6451 		/*
6452 		 * Since 64-bit divide does not work on all platforms,
6453 		 * do repeated subtraction.
6454 		 */
6455 		while (tmp >= swstats->num_aggregations) {
6456 			tmp -= swstats->num_aggregations;
6457 			count++;
6458 		}
6459 		tmp_stats[i++] = count;
6460 	} else
6461 		tmp_stats[i++] = 0;
6462 	tmp_stats[i++] = swstats->mem_alloc_fail_cnt;
6463 	tmp_stats[i++] = swstats->pci_map_fail_cnt;
6464 	tmp_stats[i++] = swstats->watchdog_timer_cnt;
6465 	tmp_stats[i++] = swstats->mem_allocated;
6466 	tmp_stats[i++] = swstats->mem_freed;
6467 	tmp_stats[i++] = swstats->link_up_cnt;
6468 	tmp_stats[i++] = swstats->link_down_cnt;
6469 	tmp_stats[i++] = swstats->link_up_time;
6470 	tmp_stats[i++] = swstats->link_down_time;
6471 
6472 	tmp_stats[i++] = swstats->tx_buf_abort_cnt;
6473 	tmp_stats[i++] = swstats->tx_desc_abort_cnt;
6474 	tmp_stats[i++] = swstats->tx_parity_err_cnt;
6475 	tmp_stats[i++] = swstats->tx_link_loss_cnt;
6476 	tmp_stats[i++] = swstats->tx_list_proc_err_cnt;
6477 
6478 	tmp_stats[i++] = swstats->rx_parity_err_cnt;
6479 	tmp_stats[i++] = swstats->rx_abort_cnt;
6480 	tmp_stats[i++] = swstats->rx_parity_abort_cnt;
6481 	tmp_stats[i++] = swstats->rx_rda_fail_cnt;
6482 	tmp_stats[i++] = swstats->rx_unkn_prot_cnt;
6483 	tmp_stats[i++] = swstats->rx_fcs_err_cnt;
6484 	tmp_stats[i++] = swstats->rx_buf_size_err_cnt;
6485 	tmp_stats[i++] = swstats->rx_rxd_corrupt_cnt;
6486 	tmp_stats[i++] = swstats->rx_unkn_err_cnt;
6487 	tmp_stats[i++] = swstats->tda_err_cnt;
6488 	tmp_stats[i++] = swstats->pfc_err_cnt;
6489 	tmp_stats[i++] = swstats->pcc_err_cnt;
6490 	tmp_stats[i++] = swstats->tti_err_cnt;
6491 	tmp_stats[i++] = swstats->tpa_err_cnt;
6492 	tmp_stats[i++] = swstats->sm_err_cnt;
6493 	tmp_stats[i++] = swstats->lso_err_cnt;
6494 	tmp_stats[i++] = swstats->mac_tmac_err_cnt;
6495 	tmp_stats[i++] = swstats->mac_rmac_err_cnt;
6496 	tmp_stats[i++] = swstats->xgxs_txgxs_err_cnt;
6497 	tmp_stats[i++] = swstats->xgxs_rxgxs_err_cnt;
6498 	tmp_stats[i++] = swstats->rc_err_cnt;
6499 	tmp_stats[i++] = swstats->prc_pcix_err_cnt;
6500 	tmp_stats[i++] = swstats->rpa_err_cnt;
6501 	tmp_stats[i++] = swstats->rda_err_cnt;
6502 	tmp_stats[i++] = swstats->rti_err_cnt;
6503 	tmp_stats[i++] = swstats->mc_err_cnt;
6504 }
6505 
s2io_ethtool_get_regs_len(struct net_device * dev)6506 static int s2io_ethtool_get_regs_len(struct net_device *dev)
6507 {
6508 	return XENA_REG_SPACE;
6509 }
6510 
6511 
s2io_get_eeprom_len(struct net_device * dev)6512 static int s2io_get_eeprom_len(struct net_device *dev)
6513 {
6514 	return XENA_EEPROM_SPACE;
6515 }
6516 
s2io_get_sset_count(struct net_device * dev,int sset)6517 static int s2io_get_sset_count(struct net_device *dev, int sset)
6518 {
6519 	struct s2io_nic *sp = netdev_priv(dev);
6520 
6521 	switch (sset) {
6522 	case ETH_SS_TEST:
6523 		return S2IO_TEST_LEN;
6524 	case ETH_SS_STATS:
6525 		switch (sp->device_type) {
6526 		case XFRAME_I_DEVICE:
6527 			return XFRAME_I_STAT_LEN;
6528 		case XFRAME_II_DEVICE:
6529 			return XFRAME_II_STAT_LEN;
6530 		default:
6531 			return 0;
6532 		}
6533 	default:
6534 		return -EOPNOTSUPP;
6535 	}
6536 }
6537 
s2io_ethtool_get_strings(struct net_device * dev,u32 stringset,u8 * data)6538 static void s2io_ethtool_get_strings(struct net_device *dev,
6539 				     u32 stringset, u8 *data)
6540 {
6541 	int stat_size = 0;
6542 	struct s2io_nic *sp = netdev_priv(dev);
6543 
6544 	switch (stringset) {
6545 	case ETH_SS_TEST:
6546 		memcpy(data, s2io_gstrings, S2IO_STRINGS_LEN);
6547 		break;
6548 	case ETH_SS_STATS:
6549 		stat_size = sizeof(ethtool_xena_stats_keys);
6550 		memcpy(data, &ethtool_xena_stats_keys, stat_size);
6551 		if (sp->device_type == XFRAME_II_DEVICE) {
6552 			memcpy(data + stat_size,
6553 			       &ethtool_enhanced_stats_keys,
6554 			       sizeof(ethtool_enhanced_stats_keys));
6555 			stat_size += sizeof(ethtool_enhanced_stats_keys);
6556 		}
6557 
6558 		memcpy(data + stat_size, &ethtool_driver_stats_keys,
6559 		       sizeof(ethtool_driver_stats_keys));
6560 	}
6561 }
6562 
s2io_set_features(struct net_device * dev,netdev_features_t features)6563 static int s2io_set_features(struct net_device *dev, netdev_features_t features)
6564 {
6565 	struct s2io_nic *sp = netdev_priv(dev);
6566 	netdev_features_t changed = (features ^ dev->features) & NETIF_F_LRO;
6567 
6568 	if (changed && netif_running(dev)) {
6569 		int rc;
6570 
6571 		s2io_stop_all_tx_queue(sp);
6572 		s2io_card_down(sp);
6573 		dev->features = features;
6574 		rc = s2io_card_up(sp);
6575 		if (rc)
6576 			s2io_reset(sp);
6577 		else
6578 			s2io_start_all_tx_queue(sp);
6579 
6580 		return rc ? rc : 1;
6581 	}
6582 
6583 	return 0;
6584 }
6585 
6586 static const struct ethtool_ops netdev_ethtool_ops = {
6587 	.get_drvinfo = s2io_ethtool_gdrvinfo,
6588 	.get_regs_len = s2io_ethtool_get_regs_len,
6589 	.get_regs = s2io_ethtool_gregs,
6590 	.get_link = ethtool_op_get_link,
6591 	.get_eeprom_len = s2io_get_eeprom_len,
6592 	.get_eeprom = s2io_ethtool_geeprom,
6593 	.set_eeprom = s2io_ethtool_seeprom,
6594 	.get_ringparam = s2io_ethtool_gringparam,
6595 	.get_pauseparam = s2io_ethtool_getpause_data,
6596 	.set_pauseparam = s2io_ethtool_setpause_data,
6597 	.self_test = s2io_ethtool_test,
6598 	.get_strings = s2io_ethtool_get_strings,
6599 	.set_phys_id = s2io_ethtool_set_led,
6600 	.get_ethtool_stats = s2io_get_ethtool_stats,
6601 	.get_sset_count = s2io_get_sset_count,
6602 	.get_link_ksettings = s2io_ethtool_get_link_ksettings,
6603 	.set_link_ksettings = s2io_ethtool_set_link_ksettings,
6604 };
6605 
6606 /**
6607  *  s2io_ioctl - Entry point for the Ioctl
6608  *  @dev :  Device pointer.
6609  *  @rq :  An IOCTL specefic structure, that can contain a pointer to
6610  *  a proprietary structure used to pass information to the driver.
6611  *  @cmd :  This is used to distinguish between the different commands that
6612  *  can be passed to the IOCTL functions.
6613  *  Description:
6614  *  Currently there are no special functionality supported in IOCTL, hence
6615  *  function always return EOPNOTSUPPORTED
6616  */
6617 
s2io_ioctl(struct net_device * dev,struct ifreq * rq,int cmd)6618 static int s2io_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
6619 {
6620 	return -EOPNOTSUPP;
6621 }
6622 
6623 /**
6624  *  s2io_change_mtu - entry point to change MTU size for the device.
6625  *   @dev : device pointer.
6626  *   @new_mtu : the new MTU size for the device.
6627  *   Description: A driver entry point to change MTU size for the device.
6628  *   Before changing the MTU the device must be stopped.
6629  *  Return value:
6630  *   0 on success and an appropriate (-)ve integer as defined in errno.h
6631  *   file on failure.
6632  */
6633 
s2io_change_mtu(struct net_device * dev,int new_mtu)6634 static int s2io_change_mtu(struct net_device *dev, int new_mtu)
6635 {
6636 	struct s2io_nic *sp = netdev_priv(dev);
6637 	int ret = 0;
6638 
6639 	dev->mtu = new_mtu;
6640 	if (netif_running(dev)) {
6641 		s2io_stop_all_tx_queue(sp);
6642 		s2io_card_down(sp);
6643 		ret = s2io_card_up(sp);
6644 		if (ret) {
6645 			DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n",
6646 				  __func__);
6647 			return ret;
6648 		}
6649 		s2io_wake_all_tx_queue(sp);
6650 	} else { /* Device is down */
6651 		struct XENA_dev_config __iomem *bar0 = sp->bar0;
6652 		u64 val64 = new_mtu;
6653 
6654 		writeq(vBIT(val64, 2, 14), &bar0->rmac_max_pyld_len);
6655 	}
6656 
6657 	return ret;
6658 }
6659 
6660 /**
6661  * s2io_set_link - Set the LInk status
6662  * @work: work struct containing a pointer to device private structure
6663  * Description: Sets the link status for the adapter
6664  */
6665 
s2io_set_link(struct work_struct * work)6666 static void s2io_set_link(struct work_struct *work)
6667 {
6668 	struct s2io_nic *nic = container_of(work, struct s2io_nic,
6669 					    set_link_task);
6670 	struct net_device *dev = nic->dev;
6671 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
6672 	register u64 val64;
6673 	u16 subid;
6674 
6675 	rtnl_lock();
6676 
6677 	if (!netif_running(dev))
6678 		goto out_unlock;
6679 
6680 	if (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(nic->state))) {
6681 		/* The card is being reset, no point doing anything */
6682 		goto out_unlock;
6683 	}
6684 
6685 	subid = nic->pdev->subsystem_device;
6686 	if (s2io_link_fault_indication(nic) == MAC_RMAC_ERR_TIMER) {
6687 		/*
6688 		 * Allow a small delay for the NICs self initiated
6689 		 * cleanup to complete.
6690 		 */
6691 		msleep(100);
6692 	}
6693 
6694 	val64 = readq(&bar0->adapter_status);
6695 	if (LINK_IS_UP(val64)) {
6696 		if (!(readq(&bar0->adapter_control) & ADAPTER_CNTL_EN)) {
6697 			if (verify_xena_quiescence(nic)) {
6698 				val64 = readq(&bar0->adapter_control);
6699 				val64 |= ADAPTER_CNTL_EN;
6700 				writeq(val64, &bar0->adapter_control);
6701 				if (CARDS_WITH_FAULTY_LINK_INDICATORS(
6702 					    nic->device_type, subid)) {
6703 					val64 = readq(&bar0->gpio_control);
6704 					val64 |= GPIO_CTRL_GPIO_0;
6705 					writeq(val64, &bar0->gpio_control);
6706 					val64 = readq(&bar0->gpio_control);
6707 				} else {
6708 					val64 |= ADAPTER_LED_ON;
6709 					writeq(val64, &bar0->adapter_control);
6710 				}
6711 				nic->device_enabled_once = true;
6712 			} else {
6713 				DBG_PRINT(ERR_DBG,
6714 					  "%s: Error: device is not Quiescent\n",
6715 					  dev->name);
6716 				s2io_stop_all_tx_queue(nic);
6717 			}
6718 		}
6719 		val64 = readq(&bar0->adapter_control);
6720 		val64 |= ADAPTER_LED_ON;
6721 		writeq(val64, &bar0->adapter_control);
6722 		s2io_link(nic, LINK_UP);
6723 	} else {
6724 		if (CARDS_WITH_FAULTY_LINK_INDICATORS(nic->device_type,
6725 						      subid)) {
6726 			val64 = readq(&bar0->gpio_control);
6727 			val64 &= ~GPIO_CTRL_GPIO_0;
6728 			writeq(val64, &bar0->gpio_control);
6729 			val64 = readq(&bar0->gpio_control);
6730 		}
6731 		/* turn off LED */
6732 		val64 = readq(&bar0->adapter_control);
6733 		val64 = val64 & (~ADAPTER_LED_ON);
6734 		writeq(val64, &bar0->adapter_control);
6735 		s2io_link(nic, LINK_DOWN);
6736 	}
6737 	clear_bit(__S2IO_STATE_LINK_TASK, &(nic->state));
6738 
6739 out_unlock:
6740 	rtnl_unlock();
6741 }
6742 
set_rxd_buffer_pointer(struct s2io_nic * sp,struct RxD_t * rxdp,struct buffAdd * ba,struct sk_buff ** skb,u64 * temp0,u64 * temp1,u64 * temp2,int size)6743 static int set_rxd_buffer_pointer(struct s2io_nic *sp, struct RxD_t *rxdp,
6744 				  struct buffAdd *ba,
6745 				  struct sk_buff **skb, u64 *temp0, u64 *temp1,
6746 				  u64 *temp2, int size)
6747 {
6748 	struct net_device *dev = sp->dev;
6749 	struct swStat *stats = &sp->mac_control.stats_info->sw_stat;
6750 
6751 	if ((sp->rxd_mode == RXD_MODE_1) && (rxdp->Host_Control == 0)) {
6752 		struct RxD1 *rxdp1 = (struct RxD1 *)rxdp;
6753 		/* allocate skb */
6754 		if (*skb) {
6755 			DBG_PRINT(INFO_DBG, "SKB is not NULL\n");
6756 			/*
6757 			 * As Rx frame are not going to be processed,
6758 			 * using same mapped address for the Rxd
6759 			 * buffer pointer
6760 			 */
6761 			rxdp1->Buffer0_ptr = *temp0;
6762 		} else {
6763 			*skb = netdev_alloc_skb(dev, size);
6764 			if (!(*skb)) {
6765 				DBG_PRINT(INFO_DBG,
6766 					  "%s: Out of memory to allocate %s\n",
6767 					  dev->name, "1 buf mode SKBs");
6768 				stats->mem_alloc_fail_cnt++;
6769 				return -ENOMEM ;
6770 			}
6771 			stats->mem_allocated += (*skb)->truesize;
6772 			/* storing the mapped addr in a temp variable
6773 			 * such it will be used for next rxd whose
6774 			 * Host Control is NULL
6775 			 */
6776 			rxdp1->Buffer0_ptr = *temp0 =
6777 				dma_map_single(&sp->pdev->dev, (*skb)->data,
6778 					       size - NET_IP_ALIGN,
6779 					       DMA_FROM_DEVICE);
6780 			if (dma_mapping_error(&sp->pdev->dev, rxdp1->Buffer0_ptr))
6781 				goto memalloc_failed;
6782 			rxdp->Host_Control = (unsigned long) (*skb);
6783 		}
6784 	} else if ((sp->rxd_mode == RXD_MODE_3B) && (rxdp->Host_Control == 0)) {
6785 		struct RxD3 *rxdp3 = (struct RxD3 *)rxdp;
6786 		/* Two buffer Mode */
6787 		if (*skb) {
6788 			rxdp3->Buffer2_ptr = *temp2;
6789 			rxdp3->Buffer0_ptr = *temp0;
6790 			rxdp3->Buffer1_ptr = *temp1;
6791 		} else {
6792 			*skb = netdev_alloc_skb(dev, size);
6793 			if (!(*skb)) {
6794 				DBG_PRINT(INFO_DBG,
6795 					  "%s: Out of memory to allocate %s\n",
6796 					  dev->name,
6797 					  "2 buf mode SKBs");
6798 				stats->mem_alloc_fail_cnt++;
6799 				return -ENOMEM;
6800 			}
6801 			stats->mem_allocated += (*skb)->truesize;
6802 			rxdp3->Buffer2_ptr = *temp2 =
6803 				dma_map_single(&sp->pdev->dev, (*skb)->data,
6804 					       dev->mtu + 4, DMA_FROM_DEVICE);
6805 			if (dma_mapping_error(&sp->pdev->dev, rxdp3->Buffer2_ptr))
6806 				goto memalloc_failed;
6807 			rxdp3->Buffer0_ptr = *temp0 =
6808 				dma_map_single(&sp->pdev->dev, ba->ba_0,
6809 					       BUF0_LEN, DMA_FROM_DEVICE);
6810 			if (dma_mapping_error(&sp->pdev->dev, rxdp3->Buffer0_ptr)) {
6811 				dma_unmap_single(&sp->pdev->dev,
6812 						 (dma_addr_t)rxdp3->Buffer2_ptr,
6813 						 dev->mtu + 4,
6814 						 DMA_FROM_DEVICE);
6815 				goto memalloc_failed;
6816 			}
6817 			rxdp->Host_Control = (unsigned long) (*skb);
6818 
6819 			/* Buffer-1 will be dummy buffer not used */
6820 			rxdp3->Buffer1_ptr = *temp1 =
6821 				dma_map_single(&sp->pdev->dev, ba->ba_1,
6822 					       BUF1_LEN, DMA_FROM_DEVICE);
6823 			if (dma_mapping_error(&sp->pdev->dev, rxdp3->Buffer1_ptr)) {
6824 				dma_unmap_single(&sp->pdev->dev,
6825 						 (dma_addr_t)rxdp3->Buffer0_ptr,
6826 						 BUF0_LEN, DMA_FROM_DEVICE);
6827 				dma_unmap_single(&sp->pdev->dev,
6828 						 (dma_addr_t)rxdp3->Buffer2_ptr,
6829 						 dev->mtu + 4,
6830 						 DMA_FROM_DEVICE);
6831 				goto memalloc_failed;
6832 			}
6833 		}
6834 	}
6835 	return 0;
6836 
6837 memalloc_failed:
6838 	stats->pci_map_fail_cnt++;
6839 	stats->mem_freed += (*skb)->truesize;
6840 	dev_kfree_skb(*skb);
6841 	return -ENOMEM;
6842 }
6843 
set_rxd_buffer_size(struct s2io_nic * sp,struct RxD_t * rxdp,int size)6844 static void set_rxd_buffer_size(struct s2io_nic *sp, struct RxD_t *rxdp,
6845 				int size)
6846 {
6847 	struct net_device *dev = sp->dev;
6848 	if (sp->rxd_mode == RXD_MODE_1) {
6849 		rxdp->Control_2 = SET_BUFFER0_SIZE_1(size - NET_IP_ALIGN);
6850 	} else if (sp->rxd_mode == RXD_MODE_3B) {
6851 		rxdp->Control_2 = SET_BUFFER0_SIZE_3(BUF0_LEN);
6852 		rxdp->Control_2 |= SET_BUFFER1_SIZE_3(1);
6853 		rxdp->Control_2 |= SET_BUFFER2_SIZE_3(dev->mtu + 4);
6854 	}
6855 }
6856 
rxd_owner_bit_reset(struct s2io_nic * sp)6857 static  int rxd_owner_bit_reset(struct s2io_nic *sp)
6858 {
6859 	int i, j, k, blk_cnt = 0, size;
6860 	struct config_param *config = &sp->config;
6861 	struct mac_info *mac_control = &sp->mac_control;
6862 	struct net_device *dev = sp->dev;
6863 	struct RxD_t *rxdp = NULL;
6864 	struct sk_buff *skb = NULL;
6865 	struct buffAdd *ba = NULL;
6866 	u64 temp0_64 = 0, temp1_64 = 0, temp2_64 = 0;
6867 
6868 	/* Calculate the size based on ring mode */
6869 	size = dev->mtu + HEADER_ETHERNET_II_802_3_SIZE +
6870 		HEADER_802_2_SIZE + HEADER_SNAP_SIZE;
6871 	if (sp->rxd_mode == RXD_MODE_1)
6872 		size += NET_IP_ALIGN;
6873 	else if (sp->rxd_mode == RXD_MODE_3B)
6874 		size = dev->mtu + ALIGN_SIZE + BUF0_LEN + 4;
6875 
6876 	for (i = 0; i < config->rx_ring_num; i++) {
6877 		struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
6878 		struct ring_info *ring = &mac_control->rings[i];
6879 
6880 		blk_cnt = rx_cfg->num_rxd / (rxd_count[sp->rxd_mode] + 1);
6881 
6882 		for (j = 0; j < blk_cnt; j++) {
6883 			for (k = 0; k < rxd_count[sp->rxd_mode]; k++) {
6884 				rxdp = ring->rx_blocks[j].rxds[k].virt_addr;
6885 				if (sp->rxd_mode == RXD_MODE_3B)
6886 					ba = &ring->ba[j][k];
6887 				if (set_rxd_buffer_pointer(sp, rxdp, ba, &skb,
6888 							   &temp0_64,
6889 							   &temp1_64,
6890 							   &temp2_64,
6891 							   size) == -ENOMEM) {
6892 					return 0;
6893 				}
6894 
6895 				set_rxd_buffer_size(sp, rxdp, size);
6896 				dma_wmb();
6897 				/* flip the Ownership bit to Hardware */
6898 				rxdp->Control_1 |= RXD_OWN_XENA;
6899 			}
6900 		}
6901 	}
6902 	return 0;
6903 
6904 }
6905 
s2io_add_isr(struct s2io_nic * sp)6906 static int s2io_add_isr(struct s2io_nic *sp)
6907 {
6908 	int ret = 0;
6909 	struct net_device *dev = sp->dev;
6910 	int err = 0;
6911 
6912 	if (sp->config.intr_type == MSI_X)
6913 		ret = s2io_enable_msi_x(sp);
6914 	if (ret) {
6915 		DBG_PRINT(ERR_DBG, "%s: Defaulting to INTA\n", dev->name);
6916 		sp->config.intr_type = INTA;
6917 	}
6918 
6919 	/*
6920 	 * Store the values of the MSIX table in
6921 	 * the struct s2io_nic structure
6922 	 */
6923 	store_xmsi_data(sp);
6924 
6925 	/* After proper initialization of H/W, register ISR */
6926 	if (sp->config.intr_type == MSI_X) {
6927 		int i, msix_rx_cnt = 0;
6928 
6929 		for (i = 0; i < sp->num_entries; i++) {
6930 			if (sp->s2io_entries[i].in_use == MSIX_FLG) {
6931 				if (sp->s2io_entries[i].type ==
6932 				    MSIX_RING_TYPE) {
6933 					snprintf(sp->desc[i],
6934 						sizeof(sp->desc[i]),
6935 						"%s:MSI-X-%d-RX",
6936 						dev->name, i);
6937 					err = request_irq(sp->entries[i].vector,
6938 							  s2io_msix_ring_handle,
6939 							  0,
6940 							  sp->desc[i],
6941 							  sp->s2io_entries[i].arg);
6942 				} else if (sp->s2io_entries[i].type ==
6943 					   MSIX_ALARM_TYPE) {
6944 					snprintf(sp->desc[i],
6945 						sizeof(sp->desc[i]),
6946 						"%s:MSI-X-%d-TX",
6947 						dev->name, i);
6948 					err = request_irq(sp->entries[i].vector,
6949 							  s2io_msix_fifo_handle,
6950 							  0,
6951 							  sp->desc[i],
6952 							  sp->s2io_entries[i].arg);
6953 
6954 				}
6955 				/* if either data or addr is zero print it. */
6956 				if (!(sp->msix_info[i].addr &&
6957 				      sp->msix_info[i].data)) {
6958 					DBG_PRINT(ERR_DBG,
6959 						  "%s @Addr:0x%llx Data:0x%llx\n",
6960 						  sp->desc[i],
6961 						  (unsigned long long)
6962 						  sp->msix_info[i].addr,
6963 						  (unsigned long long)
6964 						  ntohl(sp->msix_info[i].data));
6965 				} else
6966 					msix_rx_cnt++;
6967 				if (err) {
6968 					remove_msix_isr(sp);
6969 
6970 					DBG_PRINT(ERR_DBG,
6971 						  "%s:MSI-X-%d registration "
6972 						  "failed\n", dev->name, i);
6973 
6974 					DBG_PRINT(ERR_DBG,
6975 						  "%s: Defaulting to INTA\n",
6976 						  dev->name);
6977 					sp->config.intr_type = INTA;
6978 					break;
6979 				}
6980 				sp->s2io_entries[i].in_use =
6981 					MSIX_REGISTERED_SUCCESS;
6982 			}
6983 		}
6984 		if (!err) {
6985 			pr_info("MSI-X-RX %d entries enabled\n", --msix_rx_cnt);
6986 			DBG_PRINT(INFO_DBG,
6987 				  "MSI-X-TX entries enabled through alarm vector\n");
6988 		}
6989 	}
6990 	if (sp->config.intr_type == INTA) {
6991 		err = request_irq(sp->pdev->irq, s2io_isr, IRQF_SHARED,
6992 				  sp->name, dev);
6993 		if (err) {
6994 			DBG_PRINT(ERR_DBG, "%s: ISR registration failed\n",
6995 				  dev->name);
6996 			return -1;
6997 		}
6998 	}
6999 	return 0;
7000 }
7001 
s2io_rem_isr(struct s2io_nic * sp)7002 static void s2io_rem_isr(struct s2io_nic *sp)
7003 {
7004 	if (sp->config.intr_type == MSI_X)
7005 		remove_msix_isr(sp);
7006 	else
7007 		remove_inta_isr(sp);
7008 }
7009 
do_s2io_card_down(struct s2io_nic * sp,int do_io)7010 static void do_s2io_card_down(struct s2io_nic *sp, int do_io)
7011 {
7012 	int cnt = 0;
7013 	struct XENA_dev_config __iomem *bar0 = sp->bar0;
7014 	register u64 val64 = 0;
7015 	struct config_param *config;
7016 	config = &sp->config;
7017 
7018 	if (!is_s2io_card_up(sp))
7019 		return;
7020 
7021 	del_timer_sync(&sp->alarm_timer);
7022 	/* If s2io_set_link task is executing, wait till it completes. */
7023 	while (test_and_set_bit(__S2IO_STATE_LINK_TASK, &(sp->state)))
7024 		msleep(50);
7025 	clear_bit(__S2IO_STATE_CARD_UP, &sp->state);
7026 
7027 	/* Disable napi */
7028 	if (sp->config.napi) {
7029 		int off = 0;
7030 		if (config->intr_type ==  MSI_X) {
7031 			for (; off < sp->config.rx_ring_num; off++)
7032 				napi_disable(&sp->mac_control.rings[off].napi);
7033 		}
7034 		else
7035 			napi_disable(&sp->napi);
7036 	}
7037 
7038 	/* disable Tx and Rx traffic on the NIC */
7039 	if (do_io)
7040 		stop_nic(sp);
7041 
7042 	s2io_rem_isr(sp);
7043 
7044 	/* stop the tx queue, indicate link down */
7045 	s2io_link(sp, LINK_DOWN);
7046 
7047 	/* Check if the device is Quiescent and then Reset the NIC */
7048 	while (do_io) {
7049 		/* As per the HW requirement we need to replenish the
7050 		 * receive buffer to avoid the ring bump. Since there is
7051 		 * no intention of processing the Rx frame at this pointwe are
7052 		 * just setting the ownership bit of rxd in Each Rx
7053 		 * ring to HW and set the appropriate buffer size
7054 		 * based on the ring mode
7055 		 */
7056 		rxd_owner_bit_reset(sp);
7057 
7058 		val64 = readq(&bar0->adapter_status);
7059 		if (verify_xena_quiescence(sp)) {
7060 			if (verify_pcc_quiescent(sp, sp->device_enabled_once))
7061 				break;
7062 		}
7063 
7064 		msleep(50);
7065 		cnt++;
7066 		if (cnt == 10) {
7067 			DBG_PRINT(ERR_DBG, "Device not Quiescent - "
7068 				  "adapter status reads 0x%llx\n",
7069 				  (unsigned long long)val64);
7070 			break;
7071 		}
7072 	}
7073 	if (do_io)
7074 		s2io_reset(sp);
7075 
7076 	/* Free all Tx buffers */
7077 	free_tx_buffers(sp);
7078 
7079 	/* Free all Rx buffers */
7080 	free_rx_buffers(sp);
7081 
7082 	clear_bit(__S2IO_STATE_LINK_TASK, &(sp->state));
7083 }
7084 
s2io_card_down(struct s2io_nic * sp)7085 static void s2io_card_down(struct s2io_nic *sp)
7086 {
7087 	do_s2io_card_down(sp, 1);
7088 }
7089 
s2io_card_up(struct s2io_nic * sp)7090 static int s2io_card_up(struct s2io_nic *sp)
7091 {
7092 	int i, ret = 0;
7093 	struct config_param *config;
7094 	struct mac_info *mac_control;
7095 	struct net_device *dev = sp->dev;
7096 	u16 interruptible;
7097 
7098 	/* Initialize the H/W I/O registers */
7099 	ret = init_nic(sp);
7100 	if (ret != 0) {
7101 		DBG_PRINT(ERR_DBG, "%s: H/W initialization failed\n",
7102 			  dev->name);
7103 		if (ret != -EIO)
7104 			s2io_reset(sp);
7105 		return ret;
7106 	}
7107 
7108 	/*
7109 	 * Initializing the Rx buffers. For now we are considering only 1
7110 	 * Rx ring and initializing buffers into 30 Rx blocks
7111 	 */
7112 	config = &sp->config;
7113 	mac_control = &sp->mac_control;
7114 
7115 	for (i = 0; i < config->rx_ring_num; i++) {
7116 		struct ring_info *ring = &mac_control->rings[i];
7117 
7118 		ring->mtu = dev->mtu;
7119 		ring->lro = !!(dev->features & NETIF_F_LRO);
7120 		ret = fill_rx_buffers(sp, ring, 1);
7121 		if (ret) {
7122 			DBG_PRINT(ERR_DBG, "%s: Out of memory in Open\n",
7123 				  dev->name);
7124 			ret = -ENOMEM;
7125 			goto err_fill_buff;
7126 		}
7127 		DBG_PRINT(INFO_DBG, "Buf in ring:%d is %d:\n", i,
7128 			  ring->rx_bufs_left);
7129 	}
7130 
7131 	/* Initialise napi */
7132 	if (config->napi) {
7133 		if (config->intr_type ==  MSI_X) {
7134 			for (i = 0; i < sp->config.rx_ring_num; i++)
7135 				napi_enable(&sp->mac_control.rings[i].napi);
7136 		} else {
7137 			napi_enable(&sp->napi);
7138 		}
7139 	}
7140 
7141 	/* Maintain the state prior to the open */
7142 	if (sp->promisc_flg)
7143 		sp->promisc_flg = 0;
7144 	if (sp->m_cast_flg) {
7145 		sp->m_cast_flg = 0;
7146 		sp->all_multi_pos = 0;
7147 	}
7148 
7149 	/* Setting its receive mode */
7150 	s2io_set_multicast(dev, true);
7151 
7152 	if (dev->features & NETIF_F_LRO) {
7153 		/* Initialize max aggregatable pkts per session based on MTU */
7154 		sp->lro_max_aggr_per_sess = ((1<<16) - 1) / dev->mtu;
7155 		/* Check if we can use (if specified) user provided value */
7156 		if (lro_max_pkts < sp->lro_max_aggr_per_sess)
7157 			sp->lro_max_aggr_per_sess = lro_max_pkts;
7158 	}
7159 
7160 	/* Enable Rx Traffic and interrupts on the NIC */
7161 	if (start_nic(sp)) {
7162 		DBG_PRINT(ERR_DBG, "%s: Starting NIC failed\n", dev->name);
7163 		ret = -ENODEV;
7164 		goto err_out;
7165 	}
7166 
7167 	/* Add interrupt service routine */
7168 	if (s2io_add_isr(sp) != 0) {
7169 		if (sp->config.intr_type == MSI_X)
7170 			s2io_rem_isr(sp);
7171 		ret = -ENODEV;
7172 		goto err_out;
7173 	}
7174 
7175 	timer_setup(&sp->alarm_timer, s2io_alarm_handle, 0);
7176 	mod_timer(&sp->alarm_timer, jiffies + HZ / 2);
7177 
7178 	set_bit(__S2IO_STATE_CARD_UP, &sp->state);
7179 
7180 	/*  Enable select interrupts */
7181 	en_dis_err_alarms(sp, ENA_ALL_INTRS, ENABLE_INTRS);
7182 	if (sp->config.intr_type != INTA) {
7183 		interruptible = TX_TRAFFIC_INTR | TX_PIC_INTR;
7184 		en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7185 	} else {
7186 		interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
7187 		interruptible |= TX_PIC_INTR;
7188 		en_dis_able_nic_intrs(sp, interruptible, ENABLE_INTRS);
7189 	}
7190 
7191 	return 0;
7192 
7193 err_out:
7194 	if (config->napi) {
7195 		if (config->intr_type == MSI_X) {
7196 			for (i = 0; i < sp->config.rx_ring_num; i++)
7197 				napi_disable(&sp->mac_control.rings[i].napi);
7198 		} else {
7199 			napi_disable(&sp->napi);
7200 		}
7201 	}
7202 err_fill_buff:
7203 	s2io_reset(sp);
7204 	free_rx_buffers(sp);
7205 	return ret;
7206 }
7207 
7208 /**
7209  * s2io_restart_nic - Resets the NIC.
7210  * @work : work struct containing a pointer to the device private structure
7211  * Description:
7212  * This function is scheduled to be run by the s2io_tx_watchdog
7213  * function after 0.5 secs to reset the NIC. The idea is to reduce
7214  * the run time of the watch dog routine which is run holding a
7215  * spin lock.
7216  */
7217 
s2io_restart_nic(struct work_struct * work)7218 static void s2io_restart_nic(struct work_struct *work)
7219 {
7220 	struct s2io_nic *sp = container_of(work, struct s2io_nic, rst_timer_task);
7221 	struct net_device *dev = sp->dev;
7222 
7223 	rtnl_lock();
7224 
7225 	if (!netif_running(dev))
7226 		goto out_unlock;
7227 
7228 	s2io_card_down(sp);
7229 	if (s2io_card_up(sp)) {
7230 		DBG_PRINT(ERR_DBG, "%s: Device bring up failed\n", dev->name);
7231 	}
7232 	s2io_wake_all_tx_queue(sp);
7233 	DBG_PRINT(ERR_DBG, "%s: was reset by Tx watchdog timer\n", dev->name);
7234 out_unlock:
7235 	rtnl_unlock();
7236 }
7237 
7238 /**
7239  *  s2io_tx_watchdog - Watchdog for transmit side.
7240  *  @dev : Pointer to net device structure
7241  *  @txqueue: index of the hanging queue
7242  *  Description:
7243  *  This function is triggered if the Tx Queue is stopped
7244  *  for a pre-defined amount of time when the Interface is still up.
7245  *  If the Interface is jammed in such a situation, the hardware is
7246  *  reset (by s2io_close) and restarted again (by s2io_open) to
7247  *  overcome any problem that might have been caused in the hardware.
7248  *  Return value:
7249  *  void
7250  */
7251 
s2io_tx_watchdog(struct net_device * dev,unsigned int txqueue)7252 static void s2io_tx_watchdog(struct net_device *dev, unsigned int txqueue)
7253 {
7254 	struct s2io_nic *sp = netdev_priv(dev);
7255 	struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7256 
7257 	if (netif_carrier_ok(dev)) {
7258 		swstats->watchdog_timer_cnt++;
7259 		schedule_work(&sp->rst_timer_task);
7260 		swstats->soft_reset_cnt++;
7261 	}
7262 }
7263 
7264 /**
7265  *   rx_osm_handler - To perform some OS related operations on SKB.
7266  *   @ring_data : the ring from which this RxD was extracted.
7267  *   @rxdp: descriptor
7268  *   Description:
7269  *   This function is called by the Rx interrupt serivce routine to perform
7270  *   some OS related operations on the SKB before passing it to the upper
7271  *   layers. It mainly checks if the checksum is OK, if so adds it to the
7272  *   SKBs cksum variable, increments the Rx packet count and passes the SKB
7273  *   to the upper layer. If the checksum is wrong, it increments the Rx
7274  *   packet error count, frees the SKB and returns error.
7275  *   Return value:
7276  *   SUCCESS on success and -1 on failure.
7277  */
rx_osm_handler(struct ring_info * ring_data,struct RxD_t * rxdp)7278 static int rx_osm_handler(struct ring_info *ring_data, struct RxD_t * rxdp)
7279 {
7280 	struct s2io_nic *sp = ring_data->nic;
7281 	struct net_device *dev = ring_data->dev;
7282 	struct sk_buff *skb = (struct sk_buff *)
7283 		((unsigned long)rxdp->Host_Control);
7284 	int ring_no = ring_data->ring_no;
7285 	u16 l3_csum, l4_csum;
7286 	unsigned long long err = rxdp->Control_1 & RXD_T_CODE;
7287 	struct lro *lro;
7288 	u8 err_mask;
7289 	struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7290 
7291 	skb->dev = dev;
7292 
7293 	if (err) {
7294 		/* Check for parity error */
7295 		if (err & 0x1)
7296 			swstats->parity_err_cnt++;
7297 
7298 		err_mask = err >> 48;
7299 		switch (err_mask) {
7300 		case 1:
7301 			swstats->rx_parity_err_cnt++;
7302 			break;
7303 
7304 		case 2:
7305 			swstats->rx_abort_cnt++;
7306 			break;
7307 
7308 		case 3:
7309 			swstats->rx_parity_abort_cnt++;
7310 			break;
7311 
7312 		case 4:
7313 			swstats->rx_rda_fail_cnt++;
7314 			break;
7315 
7316 		case 5:
7317 			swstats->rx_unkn_prot_cnt++;
7318 			break;
7319 
7320 		case 6:
7321 			swstats->rx_fcs_err_cnt++;
7322 			break;
7323 
7324 		case 7:
7325 			swstats->rx_buf_size_err_cnt++;
7326 			break;
7327 
7328 		case 8:
7329 			swstats->rx_rxd_corrupt_cnt++;
7330 			break;
7331 
7332 		case 15:
7333 			swstats->rx_unkn_err_cnt++;
7334 			break;
7335 		}
7336 		/*
7337 		 * Drop the packet if bad transfer code. Exception being
7338 		 * 0x5, which could be due to unsupported IPv6 extension header.
7339 		 * In this case, we let stack handle the packet.
7340 		 * Note that in this case, since checksum will be incorrect,
7341 		 * stack will validate the same.
7342 		 */
7343 		if (err_mask != 0x5) {
7344 			DBG_PRINT(ERR_DBG, "%s: Rx error Value: 0x%x\n",
7345 				  dev->name, err_mask);
7346 			dev->stats.rx_crc_errors++;
7347 			swstats->mem_freed
7348 				+= skb->truesize;
7349 			dev_kfree_skb(skb);
7350 			ring_data->rx_bufs_left -= 1;
7351 			rxdp->Host_Control = 0;
7352 			return 0;
7353 		}
7354 	}
7355 
7356 	rxdp->Host_Control = 0;
7357 	if (sp->rxd_mode == RXD_MODE_1) {
7358 		int len = RXD_GET_BUFFER0_SIZE_1(rxdp->Control_2);
7359 
7360 		skb_put(skb, len);
7361 	} else if (sp->rxd_mode == RXD_MODE_3B) {
7362 		int get_block = ring_data->rx_curr_get_info.block_index;
7363 		int get_off = ring_data->rx_curr_get_info.offset;
7364 		int buf0_len = RXD_GET_BUFFER0_SIZE_3(rxdp->Control_2);
7365 		int buf2_len = RXD_GET_BUFFER2_SIZE_3(rxdp->Control_2);
7366 
7367 		struct buffAdd *ba = &ring_data->ba[get_block][get_off];
7368 		skb_put_data(skb, ba->ba_0, buf0_len);
7369 		skb_put(skb, buf2_len);
7370 	}
7371 
7372 	if ((rxdp->Control_1 & TCP_OR_UDP_FRAME) &&
7373 	    ((!ring_data->lro) ||
7374 	     (!(rxdp->Control_1 & RXD_FRAME_IP_FRAG))) &&
7375 	    (dev->features & NETIF_F_RXCSUM)) {
7376 		l3_csum = RXD_GET_L3_CKSUM(rxdp->Control_1);
7377 		l4_csum = RXD_GET_L4_CKSUM(rxdp->Control_1);
7378 		if ((l3_csum == L3_CKSUM_OK) && (l4_csum == L4_CKSUM_OK)) {
7379 			/*
7380 			 * NIC verifies if the Checksum of the received
7381 			 * frame is Ok or not and accordingly returns
7382 			 * a flag in the RxD.
7383 			 */
7384 			skb->ip_summed = CHECKSUM_UNNECESSARY;
7385 			if (ring_data->lro) {
7386 				u32 tcp_len = 0;
7387 				u8 *tcp;
7388 				int ret = 0;
7389 
7390 				ret = s2io_club_tcp_session(ring_data,
7391 							    skb->data, &tcp,
7392 							    &tcp_len, &lro,
7393 							    rxdp, sp);
7394 				switch (ret) {
7395 				case 3: /* Begin anew */
7396 					lro->parent = skb;
7397 					goto aggregate;
7398 				case 1: /* Aggregate */
7399 					lro_append_pkt(sp, lro, skb, tcp_len);
7400 					goto aggregate;
7401 				case 4: /* Flush session */
7402 					lro_append_pkt(sp, lro, skb, tcp_len);
7403 					queue_rx_frame(lro->parent,
7404 						       lro->vlan_tag);
7405 					clear_lro_session(lro);
7406 					swstats->flush_max_pkts++;
7407 					goto aggregate;
7408 				case 2: /* Flush both */
7409 					lro->parent->data_len = lro->frags_len;
7410 					swstats->sending_both++;
7411 					queue_rx_frame(lro->parent,
7412 						       lro->vlan_tag);
7413 					clear_lro_session(lro);
7414 					goto send_up;
7415 				case 0: /* sessions exceeded */
7416 				case -1: /* non-TCP or not L2 aggregatable */
7417 				case 5: /*
7418 					 * First pkt in session not
7419 					 * L3/L4 aggregatable
7420 					 */
7421 					break;
7422 				default:
7423 					DBG_PRINT(ERR_DBG,
7424 						  "%s: Samadhana!!\n",
7425 						  __func__);
7426 					BUG();
7427 				}
7428 			}
7429 		} else {
7430 			/*
7431 			 * Packet with erroneous checksum, let the
7432 			 * upper layers deal with it.
7433 			 */
7434 			skb_checksum_none_assert(skb);
7435 		}
7436 	} else
7437 		skb_checksum_none_assert(skb);
7438 
7439 	swstats->mem_freed += skb->truesize;
7440 send_up:
7441 	skb_record_rx_queue(skb, ring_no);
7442 	queue_rx_frame(skb, RXD_GET_VLAN_TAG(rxdp->Control_2));
7443 aggregate:
7444 	sp->mac_control.rings[ring_no].rx_bufs_left -= 1;
7445 	return SUCCESS;
7446 }
7447 
7448 /**
7449  *  s2io_link - stops/starts the Tx queue.
7450  *  @sp : private member of the device structure, which is a pointer to the
7451  *  s2io_nic structure.
7452  *  @link : inidicates whether link is UP/DOWN.
7453  *  Description:
7454  *  This function stops/starts the Tx queue depending on whether the link
7455  *  status of the NIC is down or up. This is called by the Alarm
7456  *  interrupt handler whenever a link change interrupt comes up.
7457  *  Return value:
7458  *  void.
7459  */
7460 
s2io_link(struct s2io_nic * sp,int link)7461 static void s2io_link(struct s2io_nic *sp, int link)
7462 {
7463 	struct net_device *dev = sp->dev;
7464 	struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
7465 
7466 	if (link != sp->last_link_state) {
7467 		init_tti(sp, link, false);
7468 		if (link == LINK_DOWN) {
7469 			DBG_PRINT(ERR_DBG, "%s: Link down\n", dev->name);
7470 			s2io_stop_all_tx_queue(sp);
7471 			netif_carrier_off(dev);
7472 			if (swstats->link_up_cnt)
7473 				swstats->link_up_time =
7474 					jiffies - sp->start_time;
7475 			swstats->link_down_cnt++;
7476 		} else {
7477 			DBG_PRINT(ERR_DBG, "%s: Link Up\n", dev->name);
7478 			if (swstats->link_down_cnt)
7479 				swstats->link_down_time =
7480 					jiffies - sp->start_time;
7481 			swstats->link_up_cnt++;
7482 			netif_carrier_on(dev);
7483 			s2io_wake_all_tx_queue(sp);
7484 		}
7485 	}
7486 	sp->last_link_state = link;
7487 	sp->start_time = jiffies;
7488 }
7489 
7490 /**
7491  *  s2io_init_pci -Initialization of PCI and PCI-X configuration registers .
7492  *  @sp : private member of the device structure, which is a pointer to the
7493  *  s2io_nic structure.
7494  *  Description:
7495  *  This function initializes a few of the PCI and PCI-X configuration registers
7496  *  with recommended values.
7497  *  Return value:
7498  *  void
7499  */
7500 
s2io_init_pci(struct s2io_nic * sp)7501 static void s2io_init_pci(struct s2io_nic *sp)
7502 {
7503 	u16 pci_cmd = 0, pcix_cmd = 0;
7504 
7505 	/* Enable Data Parity Error Recovery in PCI-X command register. */
7506 	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7507 			     &(pcix_cmd));
7508 	pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7509 			      (pcix_cmd | 1));
7510 	pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
7511 			     &(pcix_cmd));
7512 
7513 	/* Set the PErr Response bit in PCI command register. */
7514 	pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7515 	pci_write_config_word(sp->pdev, PCI_COMMAND,
7516 			      (pci_cmd | PCI_COMMAND_PARITY));
7517 	pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
7518 }
7519 
s2io_verify_parm(struct pci_dev * pdev,u8 * dev_intr_type,u8 * dev_multiq)7520 static int s2io_verify_parm(struct pci_dev *pdev, u8 *dev_intr_type,
7521 			    u8 *dev_multiq)
7522 {
7523 	int i;
7524 
7525 	if ((tx_fifo_num > MAX_TX_FIFOS) || (tx_fifo_num < 1)) {
7526 		DBG_PRINT(ERR_DBG, "Requested number of tx fifos "
7527 			  "(%d) not supported\n", tx_fifo_num);
7528 
7529 		if (tx_fifo_num < 1)
7530 			tx_fifo_num = 1;
7531 		else
7532 			tx_fifo_num = MAX_TX_FIFOS;
7533 
7534 		DBG_PRINT(ERR_DBG, "Default to %d tx fifos\n", tx_fifo_num);
7535 	}
7536 
7537 	if (multiq)
7538 		*dev_multiq = multiq;
7539 
7540 	if (tx_steering_type && (1 == tx_fifo_num)) {
7541 		if (tx_steering_type != TX_DEFAULT_STEERING)
7542 			DBG_PRINT(ERR_DBG,
7543 				  "Tx steering is not supported with "
7544 				  "one fifo. Disabling Tx steering.\n");
7545 		tx_steering_type = NO_STEERING;
7546 	}
7547 
7548 	if ((tx_steering_type < NO_STEERING) ||
7549 	    (tx_steering_type > TX_DEFAULT_STEERING)) {
7550 		DBG_PRINT(ERR_DBG,
7551 			  "Requested transmit steering not supported\n");
7552 		DBG_PRINT(ERR_DBG, "Disabling transmit steering\n");
7553 		tx_steering_type = NO_STEERING;
7554 	}
7555 
7556 	if (rx_ring_num > MAX_RX_RINGS) {
7557 		DBG_PRINT(ERR_DBG,
7558 			  "Requested number of rx rings not supported\n");
7559 		DBG_PRINT(ERR_DBG, "Default to %d rx rings\n",
7560 			  MAX_RX_RINGS);
7561 		rx_ring_num = MAX_RX_RINGS;
7562 	}
7563 
7564 	if ((*dev_intr_type != INTA) && (*dev_intr_type != MSI_X)) {
7565 		DBG_PRINT(ERR_DBG, "Wrong intr_type requested. "
7566 			  "Defaulting to INTA\n");
7567 		*dev_intr_type = INTA;
7568 	}
7569 
7570 	if ((*dev_intr_type == MSI_X) &&
7571 	    ((pdev->device != PCI_DEVICE_ID_HERC_WIN) &&
7572 	     (pdev->device != PCI_DEVICE_ID_HERC_UNI))) {
7573 		DBG_PRINT(ERR_DBG, "Xframe I does not support MSI_X. "
7574 			  "Defaulting to INTA\n");
7575 		*dev_intr_type = INTA;
7576 	}
7577 
7578 	if ((rx_ring_mode != 1) && (rx_ring_mode != 2)) {
7579 		DBG_PRINT(ERR_DBG, "Requested ring mode not supported\n");
7580 		DBG_PRINT(ERR_DBG, "Defaulting to 1-buffer mode\n");
7581 		rx_ring_mode = 1;
7582 	}
7583 
7584 	for (i = 0; i < MAX_RX_RINGS; i++)
7585 		if (rx_ring_sz[i] > MAX_RX_BLOCKS_PER_RING) {
7586 			DBG_PRINT(ERR_DBG, "Requested rx ring size not "
7587 				  "supported\nDefaulting to %d\n",
7588 				  MAX_RX_BLOCKS_PER_RING);
7589 			rx_ring_sz[i] = MAX_RX_BLOCKS_PER_RING;
7590 		}
7591 
7592 	return SUCCESS;
7593 }
7594 
7595 /**
7596  * rts_ds_steer - Receive traffic steering based on IPv4 or IPv6 TOS or Traffic class respectively.
7597  * @nic: device private variable
7598  * @ds_codepoint: data
7599  * @ring: ring index
7600  * Description: The function configures the receive steering to
7601  * desired receive ring.
7602  * Return Value:  SUCCESS on success and
7603  * '-1' on failure (endian settings incorrect).
7604  */
rts_ds_steer(struct s2io_nic * nic,u8 ds_codepoint,u8 ring)7605 static int rts_ds_steer(struct s2io_nic *nic, u8 ds_codepoint, u8 ring)
7606 {
7607 	struct XENA_dev_config __iomem *bar0 = nic->bar0;
7608 	register u64 val64 = 0;
7609 
7610 	if (ds_codepoint > 63)
7611 		return FAILURE;
7612 
7613 	val64 = RTS_DS_MEM_DATA(ring);
7614 	writeq(val64, &bar0->rts_ds_mem_data);
7615 
7616 	val64 = RTS_DS_MEM_CTRL_WE |
7617 		RTS_DS_MEM_CTRL_STROBE_NEW_CMD |
7618 		RTS_DS_MEM_CTRL_OFFSET(ds_codepoint);
7619 
7620 	writeq(val64, &bar0->rts_ds_mem_ctrl);
7621 
7622 	return wait_for_cmd_complete(&bar0->rts_ds_mem_ctrl,
7623 				     RTS_DS_MEM_CTRL_STROBE_CMD_BEING_EXECUTED,
7624 				     S2IO_BIT_RESET, true);
7625 }
7626 
7627 static const struct net_device_ops s2io_netdev_ops = {
7628 	.ndo_open	        = s2io_open,
7629 	.ndo_stop	        = s2io_close,
7630 	.ndo_get_stats	        = s2io_get_stats,
7631 	.ndo_start_xmit    	= s2io_xmit,
7632 	.ndo_validate_addr	= eth_validate_addr,
7633 	.ndo_set_rx_mode	= s2io_ndo_set_multicast,
7634 	.ndo_eth_ioctl		= s2io_ioctl,
7635 	.ndo_set_mac_address    = s2io_set_mac_addr,
7636 	.ndo_change_mtu	   	= s2io_change_mtu,
7637 	.ndo_set_features	= s2io_set_features,
7638 	.ndo_tx_timeout	   	= s2io_tx_watchdog,
7639 #ifdef CONFIG_NET_POLL_CONTROLLER
7640 	.ndo_poll_controller    = s2io_netpoll,
7641 #endif
7642 };
7643 
7644 /**
7645  *  s2io_init_nic - Initialization of the adapter .
7646  *  @pdev : structure containing the PCI related information of the device.
7647  *  @pre: List of PCI devices supported by the driver listed in s2io_tbl.
7648  *  Description:
7649  *  The function initializes an adapter identified by the pci_dec structure.
7650  *  All OS related initialization including memory and device structure and
7651  *  initlaization of the device private variable is done. Also the swapper
7652  *  control register is initialized to enable read and write into the I/O
7653  *  registers of the device.
7654  *  Return value:
7655  *  returns 0 on success and negative on failure.
7656  */
7657 
7658 static int
s2io_init_nic(struct pci_dev * pdev,const struct pci_device_id * pre)7659 s2io_init_nic(struct pci_dev *pdev, const struct pci_device_id *pre)
7660 {
7661 	struct s2io_nic *sp;
7662 	struct net_device *dev;
7663 	int i, j, ret;
7664 	u32 mac_up, mac_down;
7665 	u64 val64 = 0, tmp64 = 0;
7666 	struct XENA_dev_config __iomem *bar0 = NULL;
7667 	u16 subid;
7668 	struct config_param *config;
7669 	struct mac_info *mac_control;
7670 	int mode;
7671 	u8 dev_intr_type = intr_type;
7672 	u8 dev_multiq = 0;
7673 
7674 	ret = s2io_verify_parm(pdev, &dev_intr_type, &dev_multiq);
7675 	if (ret)
7676 		return ret;
7677 
7678 	ret = pci_enable_device(pdev);
7679 	if (ret) {
7680 		DBG_PRINT(ERR_DBG,
7681 			  "%s: pci_enable_device failed\n", __func__);
7682 		return ret;
7683 	}
7684 
7685 	if (!dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64))) {
7686 		DBG_PRINT(INIT_DBG, "%s: Using 64bit DMA\n", __func__);
7687 	} else {
7688 		pci_disable_device(pdev);
7689 		return -ENOMEM;
7690 	}
7691 	ret = pci_request_regions(pdev, s2io_driver_name);
7692 	if (ret) {
7693 		DBG_PRINT(ERR_DBG, "%s: Request Regions failed - %x\n",
7694 			  __func__, ret);
7695 		pci_disable_device(pdev);
7696 		return -ENODEV;
7697 	}
7698 	if (dev_multiq)
7699 		dev = alloc_etherdev_mq(sizeof(struct s2io_nic), tx_fifo_num);
7700 	else
7701 		dev = alloc_etherdev(sizeof(struct s2io_nic));
7702 	if (dev == NULL) {
7703 		pci_disable_device(pdev);
7704 		pci_release_regions(pdev);
7705 		return -ENODEV;
7706 	}
7707 
7708 	pci_set_master(pdev);
7709 	pci_set_drvdata(pdev, dev);
7710 	SET_NETDEV_DEV(dev, &pdev->dev);
7711 
7712 	/*  Private member variable initialized to s2io NIC structure */
7713 	sp = netdev_priv(dev);
7714 	sp->dev = dev;
7715 	sp->pdev = pdev;
7716 	sp->device_enabled_once = false;
7717 	if (rx_ring_mode == 1)
7718 		sp->rxd_mode = RXD_MODE_1;
7719 	if (rx_ring_mode == 2)
7720 		sp->rxd_mode = RXD_MODE_3B;
7721 
7722 	sp->config.intr_type = dev_intr_type;
7723 
7724 	if ((pdev->device == PCI_DEVICE_ID_HERC_WIN) ||
7725 	    (pdev->device == PCI_DEVICE_ID_HERC_UNI))
7726 		sp->device_type = XFRAME_II_DEVICE;
7727 	else
7728 		sp->device_type = XFRAME_I_DEVICE;
7729 
7730 
7731 	/* Initialize some PCI/PCI-X fields of the NIC. */
7732 	s2io_init_pci(sp);
7733 
7734 	/*
7735 	 * Setting the device configuration parameters.
7736 	 * Most of these parameters can be specified by the user during
7737 	 * module insertion as they are module loadable parameters. If
7738 	 * these parameters are not specified during load time, they
7739 	 * are initialized with default values.
7740 	 */
7741 	config = &sp->config;
7742 	mac_control = &sp->mac_control;
7743 
7744 	config->napi = napi;
7745 	config->tx_steering_type = tx_steering_type;
7746 
7747 	/* Tx side parameters. */
7748 	if (config->tx_steering_type == TX_PRIORITY_STEERING)
7749 		config->tx_fifo_num = MAX_TX_FIFOS;
7750 	else
7751 		config->tx_fifo_num = tx_fifo_num;
7752 
7753 	/* Initialize the fifos used for tx steering */
7754 	if (config->tx_fifo_num < 5) {
7755 		if (config->tx_fifo_num  == 1)
7756 			sp->total_tcp_fifos = 1;
7757 		else
7758 			sp->total_tcp_fifos = config->tx_fifo_num - 1;
7759 		sp->udp_fifo_idx = config->tx_fifo_num - 1;
7760 		sp->total_udp_fifos = 1;
7761 		sp->other_fifo_idx = sp->total_tcp_fifos - 1;
7762 	} else {
7763 		sp->total_tcp_fifos = (tx_fifo_num - FIFO_UDP_MAX_NUM -
7764 				       FIFO_OTHER_MAX_NUM);
7765 		sp->udp_fifo_idx = sp->total_tcp_fifos;
7766 		sp->total_udp_fifos = FIFO_UDP_MAX_NUM;
7767 		sp->other_fifo_idx = sp->udp_fifo_idx + FIFO_UDP_MAX_NUM;
7768 	}
7769 
7770 	config->multiq = dev_multiq;
7771 	for (i = 0; i < config->tx_fifo_num; i++) {
7772 		struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7773 
7774 		tx_cfg->fifo_len = tx_fifo_len[i];
7775 		tx_cfg->fifo_priority = i;
7776 	}
7777 
7778 	/* mapping the QoS priority to the configured fifos */
7779 	for (i = 0; i < MAX_TX_FIFOS; i++)
7780 		config->fifo_mapping[i] = fifo_map[config->tx_fifo_num - 1][i];
7781 
7782 	/* map the hashing selector table to the configured fifos */
7783 	for (i = 0; i < config->tx_fifo_num; i++)
7784 		sp->fifo_selector[i] = fifo_selector[i];
7785 
7786 
7787 	config->tx_intr_type = TXD_INT_TYPE_UTILZ;
7788 	for (i = 0; i < config->tx_fifo_num; i++) {
7789 		struct tx_fifo_config *tx_cfg = &config->tx_cfg[i];
7790 
7791 		tx_cfg->f_no_snoop = (NO_SNOOP_TXD | NO_SNOOP_TXD_BUFFER);
7792 		if (tx_cfg->fifo_len < 65) {
7793 			config->tx_intr_type = TXD_INT_TYPE_PER_LIST;
7794 			break;
7795 		}
7796 	}
7797 	/* + 2 because one Txd for skb->data and one Txd for UFO */
7798 	config->max_txds = MAX_SKB_FRAGS + 2;
7799 
7800 	/* Rx side parameters. */
7801 	config->rx_ring_num = rx_ring_num;
7802 	for (i = 0; i < config->rx_ring_num; i++) {
7803 		struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7804 		struct ring_info *ring = &mac_control->rings[i];
7805 
7806 		rx_cfg->num_rxd = rx_ring_sz[i] * (rxd_count[sp->rxd_mode] + 1);
7807 		rx_cfg->ring_priority = i;
7808 		ring->rx_bufs_left = 0;
7809 		ring->rxd_mode = sp->rxd_mode;
7810 		ring->rxd_count = rxd_count[sp->rxd_mode];
7811 		ring->pdev = sp->pdev;
7812 		ring->dev = sp->dev;
7813 	}
7814 
7815 	for (i = 0; i < rx_ring_num; i++) {
7816 		struct rx_ring_config *rx_cfg = &config->rx_cfg[i];
7817 
7818 		rx_cfg->ring_org = RING_ORG_BUFF1;
7819 		rx_cfg->f_no_snoop = (NO_SNOOP_RXD | NO_SNOOP_RXD_BUFFER);
7820 	}
7821 
7822 	/*  Setting Mac Control parameters */
7823 	mac_control->rmac_pause_time = rmac_pause_time;
7824 	mac_control->mc_pause_threshold_q0q3 = mc_pause_threshold_q0q3;
7825 	mac_control->mc_pause_threshold_q4q7 = mc_pause_threshold_q4q7;
7826 
7827 
7828 	/*  initialize the shared memory used by the NIC and the host */
7829 	if (init_shared_mem(sp)) {
7830 		DBG_PRINT(ERR_DBG, "%s: Memory allocation failed\n", dev->name);
7831 		ret = -ENOMEM;
7832 		goto mem_alloc_failed;
7833 	}
7834 
7835 	sp->bar0 = pci_ioremap_bar(pdev, 0);
7836 	if (!sp->bar0) {
7837 		DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem1\n",
7838 			  dev->name);
7839 		ret = -ENOMEM;
7840 		goto bar0_remap_failed;
7841 	}
7842 
7843 	sp->bar1 = pci_ioremap_bar(pdev, 2);
7844 	if (!sp->bar1) {
7845 		DBG_PRINT(ERR_DBG, "%s: Neterion: cannot remap io mem2\n",
7846 			  dev->name);
7847 		ret = -ENOMEM;
7848 		goto bar1_remap_failed;
7849 	}
7850 
7851 	/* Initializing the BAR1 address as the start of the FIFO pointer. */
7852 	for (j = 0; j < MAX_TX_FIFOS; j++) {
7853 		mac_control->tx_FIFO_start[j] = sp->bar1 + (j * 0x00020000);
7854 	}
7855 
7856 	/*  Driver entry points */
7857 	dev->netdev_ops = &s2io_netdev_ops;
7858 	dev->ethtool_ops = &netdev_ethtool_ops;
7859 	dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM |
7860 		NETIF_F_TSO | NETIF_F_TSO6 |
7861 		NETIF_F_RXCSUM | NETIF_F_LRO;
7862 	dev->features |= dev->hw_features |
7863 		NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX |
7864 		NETIF_F_HIGHDMA;
7865 	dev->watchdog_timeo = WATCH_DOG_TIMEOUT;
7866 	INIT_WORK(&sp->rst_timer_task, s2io_restart_nic);
7867 	INIT_WORK(&sp->set_link_task, s2io_set_link);
7868 
7869 	pci_save_state(sp->pdev);
7870 
7871 	/* Setting swapper control on the NIC, for proper reset operation */
7872 	if (s2io_set_swapper(sp)) {
7873 		DBG_PRINT(ERR_DBG, "%s: swapper settings are wrong\n",
7874 			  dev->name);
7875 		ret = -EAGAIN;
7876 		goto set_swap_failed;
7877 	}
7878 
7879 	/* Verify if the Herc works on the slot its placed into */
7880 	if (sp->device_type & XFRAME_II_DEVICE) {
7881 		mode = s2io_verify_pci_mode(sp);
7882 		if (mode < 0) {
7883 			DBG_PRINT(ERR_DBG, "%s: Unsupported PCI bus mode\n",
7884 				  __func__);
7885 			ret = -EBADSLT;
7886 			goto set_swap_failed;
7887 		}
7888 	}
7889 
7890 	if (sp->config.intr_type == MSI_X) {
7891 		sp->num_entries = config->rx_ring_num + 1;
7892 		ret = s2io_enable_msi_x(sp);
7893 
7894 		if (!ret) {
7895 			ret = s2io_test_msi(sp);
7896 			/* rollback MSI-X, will re-enable during add_isr() */
7897 			remove_msix_isr(sp);
7898 		}
7899 		if (ret) {
7900 
7901 			DBG_PRINT(ERR_DBG,
7902 				  "MSI-X requested but failed to enable\n");
7903 			sp->config.intr_type = INTA;
7904 		}
7905 	}
7906 
7907 	if (config->intr_type ==  MSI_X) {
7908 		for (i = 0; i < config->rx_ring_num ; i++) {
7909 			struct ring_info *ring = &mac_control->rings[i];
7910 
7911 			netif_napi_add(dev, &ring->napi, s2io_poll_msix);
7912 		}
7913 	} else {
7914 		netif_napi_add(dev, &sp->napi, s2io_poll_inta);
7915 	}
7916 
7917 	/* Not needed for Herc */
7918 	if (sp->device_type & XFRAME_I_DEVICE) {
7919 		/*
7920 		 * Fix for all "FFs" MAC address problems observed on
7921 		 * Alpha platforms
7922 		 */
7923 		fix_mac_address(sp);
7924 		s2io_reset(sp);
7925 	}
7926 
7927 	/*
7928 	 * MAC address initialization.
7929 	 * For now only one mac address will be read and used.
7930 	 */
7931 	bar0 = sp->bar0;
7932 	val64 = RMAC_ADDR_CMD_MEM_RD | RMAC_ADDR_CMD_MEM_STROBE_NEW_CMD |
7933 		RMAC_ADDR_CMD_MEM_OFFSET(0 + S2IO_MAC_ADDR_START_OFFSET);
7934 	writeq(val64, &bar0->rmac_addr_cmd_mem);
7935 	wait_for_cmd_complete(&bar0->rmac_addr_cmd_mem,
7936 			      RMAC_ADDR_CMD_MEM_STROBE_CMD_EXECUTING,
7937 			      S2IO_BIT_RESET, true);
7938 	tmp64 = readq(&bar0->rmac_addr_data0_mem);
7939 	mac_down = (u32)tmp64;
7940 	mac_up = (u32) (tmp64 >> 32);
7941 
7942 	sp->def_mac_addr[0].mac_addr[3] = (u8) (mac_up);
7943 	sp->def_mac_addr[0].mac_addr[2] = (u8) (mac_up >> 8);
7944 	sp->def_mac_addr[0].mac_addr[1] = (u8) (mac_up >> 16);
7945 	sp->def_mac_addr[0].mac_addr[0] = (u8) (mac_up >> 24);
7946 	sp->def_mac_addr[0].mac_addr[5] = (u8) (mac_down >> 16);
7947 	sp->def_mac_addr[0].mac_addr[4] = (u8) (mac_down >> 24);
7948 
7949 	/*  Set the factory defined MAC address initially   */
7950 	dev->addr_len = ETH_ALEN;
7951 	eth_hw_addr_set(dev, sp->def_mac_addr[0].mac_addr);
7952 
7953 	/* initialize number of multicast & unicast MAC entries variables */
7954 	if (sp->device_type == XFRAME_I_DEVICE) {
7955 		config->max_mc_addr = S2IO_XENA_MAX_MC_ADDRESSES;
7956 		config->max_mac_addr = S2IO_XENA_MAX_MAC_ADDRESSES;
7957 		config->mc_start_offset = S2IO_XENA_MC_ADDR_START_OFFSET;
7958 	} else if (sp->device_type == XFRAME_II_DEVICE) {
7959 		config->max_mc_addr = S2IO_HERC_MAX_MC_ADDRESSES;
7960 		config->max_mac_addr = S2IO_HERC_MAX_MAC_ADDRESSES;
7961 		config->mc_start_offset = S2IO_HERC_MC_ADDR_START_OFFSET;
7962 	}
7963 
7964 	/* MTU range: 46 - 9600 */
7965 	dev->min_mtu = MIN_MTU;
7966 	dev->max_mtu = S2IO_JUMBO_SIZE;
7967 
7968 	/* store mac addresses from CAM to s2io_nic structure */
7969 	do_s2io_store_unicast_mc(sp);
7970 
7971 	/* Configure MSIX vector for number of rings configured plus one */
7972 	if ((sp->device_type == XFRAME_II_DEVICE) &&
7973 	    (config->intr_type == MSI_X))
7974 		sp->num_entries = config->rx_ring_num + 1;
7975 
7976 	/* Store the values of the MSIX table in the s2io_nic structure */
7977 	store_xmsi_data(sp);
7978 	/* reset Nic and bring it to known state */
7979 	s2io_reset(sp);
7980 
7981 	/*
7982 	 * Initialize link state flags
7983 	 * and the card state parameter
7984 	 */
7985 	sp->state = 0;
7986 
7987 	/* Initialize spinlocks */
7988 	for (i = 0; i < sp->config.tx_fifo_num; i++) {
7989 		struct fifo_info *fifo = &mac_control->fifos[i];
7990 
7991 		spin_lock_init(&fifo->tx_lock);
7992 	}
7993 
7994 	/*
7995 	 * SXE-002: Configure link and activity LED to init state
7996 	 * on driver load.
7997 	 */
7998 	subid = sp->pdev->subsystem_device;
7999 	if ((subid & 0xFF) >= 0x07) {
8000 		val64 = readq(&bar0->gpio_control);
8001 		val64 |= 0x0000800000000000ULL;
8002 		writeq(val64, &bar0->gpio_control);
8003 		val64 = 0x0411040400000000ULL;
8004 		writeq(val64, (void __iomem *)bar0 + 0x2700);
8005 		val64 = readq(&bar0->gpio_control);
8006 	}
8007 
8008 	sp->rx_csum = 1;	/* Rx chksum verify enabled by default */
8009 
8010 	if (register_netdev(dev)) {
8011 		DBG_PRINT(ERR_DBG, "Device registration failed\n");
8012 		ret = -ENODEV;
8013 		goto register_failed;
8014 	}
8015 	s2io_vpd_read(sp);
8016 	DBG_PRINT(ERR_DBG, "Copyright(c) 2002-2010 Exar Corp.\n");
8017 	DBG_PRINT(ERR_DBG, "%s: Neterion %s (rev %d)\n", dev->name,
8018 		  sp->product_name, pdev->revision);
8019 	DBG_PRINT(ERR_DBG, "%s: Driver version %s\n", dev->name,
8020 		  s2io_driver_version);
8021 	DBG_PRINT(ERR_DBG, "%s: MAC Address: %pM\n", dev->name, dev->dev_addr);
8022 	DBG_PRINT(ERR_DBG, "Serial number: %s\n", sp->serial_num);
8023 	if (sp->device_type & XFRAME_II_DEVICE) {
8024 		mode = s2io_print_pci_mode(sp);
8025 		if (mode < 0) {
8026 			ret = -EBADSLT;
8027 			unregister_netdev(dev);
8028 			goto set_swap_failed;
8029 		}
8030 	}
8031 	switch (sp->rxd_mode) {
8032 	case RXD_MODE_1:
8033 		DBG_PRINT(ERR_DBG, "%s: 1-Buffer receive mode enabled\n",
8034 			  dev->name);
8035 		break;
8036 	case RXD_MODE_3B:
8037 		DBG_PRINT(ERR_DBG, "%s: 2-Buffer receive mode enabled\n",
8038 			  dev->name);
8039 		break;
8040 	}
8041 
8042 	switch (sp->config.napi) {
8043 	case 0:
8044 		DBG_PRINT(ERR_DBG, "%s: NAPI disabled\n", dev->name);
8045 		break;
8046 	case 1:
8047 		DBG_PRINT(ERR_DBG, "%s: NAPI enabled\n", dev->name);
8048 		break;
8049 	}
8050 
8051 	DBG_PRINT(ERR_DBG, "%s: Using %d Tx fifo(s)\n", dev->name,
8052 		  sp->config.tx_fifo_num);
8053 
8054 	DBG_PRINT(ERR_DBG, "%s: Using %d Rx ring(s)\n", dev->name,
8055 		  sp->config.rx_ring_num);
8056 
8057 	switch (sp->config.intr_type) {
8058 	case INTA:
8059 		DBG_PRINT(ERR_DBG, "%s: Interrupt type INTA\n", dev->name);
8060 		break;
8061 	case MSI_X:
8062 		DBG_PRINT(ERR_DBG, "%s: Interrupt type MSI-X\n", dev->name);
8063 		break;
8064 	}
8065 	if (sp->config.multiq) {
8066 		for (i = 0; i < sp->config.tx_fifo_num; i++) {
8067 			struct fifo_info *fifo = &mac_control->fifos[i];
8068 
8069 			fifo->multiq = config->multiq;
8070 		}
8071 		DBG_PRINT(ERR_DBG, "%s: Multiqueue support enabled\n",
8072 			  dev->name);
8073 	} else
8074 		DBG_PRINT(ERR_DBG, "%s: Multiqueue support disabled\n",
8075 			  dev->name);
8076 
8077 	switch (sp->config.tx_steering_type) {
8078 	case NO_STEERING:
8079 		DBG_PRINT(ERR_DBG, "%s: No steering enabled for transmit\n",
8080 			  dev->name);
8081 		break;
8082 	case TX_PRIORITY_STEERING:
8083 		DBG_PRINT(ERR_DBG,
8084 			  "%s: Priority steering enabled for transmit\n",
8085 			  dev->name);
8086 		break;
8087 	case TX_DEFAULT_STEERING:
8088 		DBG_PRINT(ERR_DBG,
8089 			  "%s: Default steering enabled for transmit\n",
8090 			  dev->name);
8091 	}
8092 
8093 	DBG_PRINT(ERR_DBG, "%s: Large receive offload enabled\n",
8094 		  dev->name);
8095 	/* Initialize device name */
8096 	snprintf(sp->name, sizeof(sp->name), "%s Neterion %s", dev->name,
8097 		 sp->product_name);
8098 
8099 	if (vlan_tag_strip)
8100 		sp->vlan_strip_flag = 1;
8101 	else
8102 		sp->vlan_strip_flag = 0;
8103 
8104 	/*
8105 	 * Make Link state as off at this point, when the Link change
8106 	 * interrupt comes the state will be automatically changed to
8107 	 * the right state.
8108 	 */
8109 	netif_carrier_off(dev);
8110 
8111 	return 0;
8112 
8113 register_failed:
8114 set_swap_failed:
8115 	iounmap(sp->bar1);
8116 bar1_remap_failed:
8117 	iounmap(sp->bar0);
8118 bar0_remap_failed:
8119 mem_alloc_failed:
8120 	free_shared_mem(sp);
8121 	pci_disable_device(pdev);
8122 	pci_release_regions(pdev);
8123 	free_netdev(dev);
8124 
8125 	return ret;
8126 }
8127 
8128 /**
8129  * s2io_rem_nic - Free the PCI device
8130  * @pdev: structure containing the PCI related information of the device.
8131  * Description: This function is called by the Pci subsystem to release a
8132  * PCI device and free up all resource held up by the device. This could
8133  * be in response to a Hot plug event or when the driver is to be removed
8134  * from memory.
8135  */
8136 
s2io_rem_nic(struct pci_dev * pdev)8137 static void s2io_rem_nic(struct pci_dev *pdev)
8138 {
8139 	struct net_device *dev = pci_get_drvdata(pdev);
8140 	struct s2io_nic *sp;
8141 
8142 	if (dev == NULL) {
8143 		DBG_PRINT(ERR_DBG, "Driver Data is NULL!!\n");
8144 		return;
8145 	}
8146 
8147 	sp = netdev_priv(dev);
8148 
8149 	cancel_work_sync(&sp->rst_timer_task);
8150 	cancel_work_sync(&sp->set_link_task);
8151 
8152 	unregister_netdev(dev);
8153 
8154 	free_shared_mem(sp);
8155 	iounmap(sp->bar0);
8156 	iounmap(sp->bar1);
8157 	pci_release_regions(pdev);
8158 	free_netdev(dev);
8159 	pci_disable_device(pdev);
8160 }
8161 
8162 module_pci_driver(s2io_driver);
8163 
check_L2_lro_capable(u8 * buffer,struct iphdr ** ip,struct tcphdr ** tcp,struct RxD_t * rxdp,struct s2io_nic * sp)8164 static int check_L2_lro_capable(u8 *buffer, struct iphdr **ip,
8165 				struct tcphdr **tcp, struct RxD_t *rxdp,
8166 				struct s2io_nic *sp)
8167 {
8168 	int ip_off;
8169 	u8 l2_type = (u8)((rxdp->Control_1 >> 37) & 0x7), ip_len;
8170 
8171 	if (!(rxdp->Control_1 & RXD_FRAME_PROTO_TCP)) {
8172 		DBG_PRINT(INIT_DBG,
8173 			  "%s: Non-TCP frames not supported for LRO\n",
8174 			  __func__);
8175 		return -1;
8176 	}
8177 
8178 	/* Checking for DIX type or DIX type with VLAN */
8179 	if ((l2_type == 0) || (l2_type == 4)) {
8180 		ip_off = HEADER_ETHERNET_II_802_3_SIZE;
8181 		/*
8182 		 * If vlan stripping is disabled and the frame is VLAN tagged,
8183 		 * shift the offset by the VLAN header size bytes.
8184 		 */
8185 		if ((!sp->vlan_strip_flag) &&
8186 		    (rxdp->Control_1 & RXD_FRAME_VLAN_TAG))
8187 			ip_off += HEADER_VLAN_SIZE;
8188 	} else {
8189 		/* LLC, SNAP etc are considered non-mergeable */
8190 		return -1;
8191 	}
8192 
8193 	*ip = (struct iphdr *)(buffer + ip_off);
8194 	ip_len = (u8)((*ip)->ihl);
8195 	ip_len <<= 2;
8196 	*tcp = (struct tcphdr *)((unsigned long)*ip + ip_len);
8197 
8198 	return 0;
8199 }
8200 
check_for_socket_match(struct lro * lro,struct iphdr * ip,struct tcphdr * tcp)8201 static int check_for_socket_match(struct lro *lro, struct iphdr *ip,
8202 				  struct tcphdr *tcp)
8203 {
8204 	DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8205 	if ((lro->iph->saddr != ip->saddr) ||
8206 	    (lro->iph->daddr != ip->daddr) ||
8207 	    (lro->tcph->source != tcp->source) ||
8208 	    (lro->tcph->dest != tcp->dest))
8209 		return -1;
8210 	return 0;
8211 }
8212 
get_l4_pyld_length(struct iphdr * ip,struct tcphdr * tcp)8213 static inline int get_l4_pyld_length(struct iphdr *ip, struct tcphdr *tcp)
8214 {
8215 	return ntohs(ip->tot_len) - (ip->ihl << 2) - (tcp->doff << 2);
8216 }
8217 
initiate_new_session(struct lro * lro,u8 * l2h,struct iphdr * ip,struct tcphdr * tcp,u32 tcp_pyld_len,u16 vlan_tag)8218 static void initiate_new_session(struct lro *lro, u8 *l2h,
8219 				 struct iphdr *ip, struct tcphdr *tcp,
8220 				 u32 tcp_pyld_len, u16 vlan_tag)
8221 {
8222 	DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8223 	lro->l2h = l2h;
8224 	lro->iph = ip;
8225 	lro->tcph = tcp;
8226 	lro->tcp_next_seq = tcp_pyld_len + ntohl(tcp->seq);
8227 	lro->tcp_ack = tcp->ack_seq;
8228 	lro->sg_num = 1;
8229 	lro->total_len = ntohs(ip->tot_len);
8230 	lro->frags_len = 0;
8231 	lro->vlan_tag = vlan_tag;
8232 	/*
8233 	 * Check if we saw TCP timestamp.
8234 	 * Other consistency checks have already been done.
8235 	 */
8236 	if (tcp->doff == 8) {
8237 		__be32 *ptr;
8238 		ptr = (__be32 *)(tcp+1);
8239 		lro->saw_ts = 1;
8240 		lro->cur_tsval = ntohl(*(ptr+1));
8241 		lro->cur_tsecr = *(ptr+2);
8242 	}
8243 	lro->in_use = 1;
8244 }
8245 
update_L3L4_header(struct s2io_nic * sp,struct lro * lro)8246 static void update_L3L4_header(struct s2io_nic *sp, struct lro *lro)
8247 {
8248 	struct iphdr *ip = lro->iph;
8249 	struct tcphdr *tcp = lro->tcph;
8250 	struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8251 
8252 	DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8253 
8254 	/* Update L3 header */
8255 	csum_replace2(&ip->check, ip->tot_len, htons(lro->total_len));
8256 	ip->tot_len = htons(lro->total_len);
8257 
8258 	/* Update L4 header */
8259 	tcp->ack_seq = lro->tcp_ack;
8260 	tcp->window = lro->window;
8261 
8262 	/* Update tsecr field if this session has timestamps enabled */
8263 	if (lro->saw_ts) {
8264 		__be32 *ptr = (__be32 *)(tcp + 1);
8265 		*(ptr+2) = lro->cur_tsecr;
8266 	}
8267 
8268 	/* Update counters required for calculation of
8269 	 * average no. of packets aggregated.
8270 	 */
8271 	swstats->sum_avg_pkts_aggregated += lro->sg_num;
8272 	swstats->num_aggregations++;
8273 }
8274 
aggregate_new_rx(struct lro * lro,struct iphdr * ip,struct tcphdr * tcp,u32 l4_pyld)8275 static void aggregate_new_rx(struct lro *lro, struct iphdr *ip,
8276 			     struct tcphdr *tcp, u32 l4_pyld)
8277 {
8278 	DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8279 	lro->total_len += l4_pyld;
8280 	lro->frags_len += l4_pyld;
8281 	lro->tcp_next_seq += l4_pyld;
8282 	lro->sg_num++;
8283 
8284 	/* Update ack seq no. and window ad(from this pkt) in LRO object */
8285 	lro->tcp_ack = tcp->ack_seq;
8286 	lro->window = tcp->window;
8287 
8288 	if (lro->saw_ts) {
8289 		__be32 *ptr;
8290 		/* Update tsecr and tsval from this packet */
8291 		ptr = (__be32 *)(tcp+1);
8292 		lro->cur_tsval = ntohl(*(ptr+1));
8293 		lro->cur_tsecr = *(ptr + 2);
8294 	}
8295 }
8296 
verify_l3_l4_lro_capable(struct lro * l_lro,struct iphdr * ip,struct tcphdr * tcp,u32 tcp_pyld_len)8297 static int verify_l3_l4_lro_capable(struct lro *l_lro, struct iphdr *ip,
8298 				    struct tcphdr *tcp, u32 tcp_pyld_len)
8299 {
8300 	u8 *ptr;
8301 
8302 	DBG_PRINT(INFO_DBG, "%s: Been here...\n", __func__);
8303 
8304 	if (!tcp_pyld_len) {
8305 		/* Runt frame or a pure ack */
8306 		return -1;
8307 	}
8308 
8309 	if (ip->ihl != 5) /* IP has options */
8310 		return -1;
8311 
8312 	/* If we see CE codepoint in IP header, packet is not mergeable */
8313 	if (INET_ECN_is_ce(ipv4_get_dsfield(ip)))
8314 		return -1;
8315 
8316 	/* If we see ECE or CWR flags in TCP header, packet is not mergeable */
8317 	if (tcp->urg || tcp->psh || tcp->rst ||
8318 	    tcp->syn || tcp->fin ||
8319 	    tcp->ece || tcp->cwr || !tcp->ack) {
8320 		/*
8321 		 * Currently recognize only the ack control word and
8322 		 * any other control field being set would result in
8323 		 * flushing the LRO session
8324 		 */
8325 		return -1;
8326 	}
8327 
8328 	/*
8329 	 * Allow only one TCP timestamp option. Don't aggregate if
8330 	 * any other options are detected.
8331 	 */
8332 	if (tcp->doff != 5 && tcp->doff != 8)
8333 		return -1;
8334 
8335 	if (tcp->doff == 8) {
8336 		ptr = (u8 *)(tcp + 1);
8337 		while (*ptr == TCPOPT_NOP)
8338 			ptr++;
8339 		if (*ptr != TCPOPT_TIMESTAMP || *(ptr+1) != TCPOLEN_TIMESTAMP)
8340 			return -1;
8341 
8342 		/* Ensure timestamp value increases monotonically */
8343 		if (l_lro)
8344 			if (l_lro->cur_tsval > ntohl(*((__be32 *)(ptr+2))))
8345 				return -1;
8346 
8347 		/* timestamp echo reply should be non-zero */
8348 		if (*((__be32 *)(ptr+6)) == 0)
8349 			return -1;
8350 	}
8351 
8352 	return 0;
8353 }
8354 
s2io_club_tcp_session(struct ring_info * ring_data,u8 * buffer,u8 ** tcp,u32 * tcp_len,struct lro ** lro,struct RxD_t * rxdp,struct s2io_nic * sp)8355 static int s2io_club_tcp_session(struct ring_info *ring_data, u8 *buffer,
8356 				 u8 **tcp, u32 *tcp_len, struct lro **lro,
8357 				 struct RxD_t *rxdp, struct s2io_nic *sp)
8358 {
8359 	struct iphdr *ip;
8360 	struct tcphdr *tcph;
8361 	int ret = 0, i;
8362 	u16 vlan_tag = 0;
8363 	struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8364 
8365 	ret = check_L2_lro_capable(buffer, &ip, (struct tcphdr **)tcp,
8366 				   rxdp, sp);
8367 	if (ret)
8368 		return ret;
8369 
8370 	DBG_PRINT(INFO_DBG, "IP Saddr: %x Daddr: %x\n", ip->saddr, ip->daddr);
8371 
8372 	vlan_tag = RXD_GET_VLAN_TAG(rxdp->Control_2);
8373 	tcph = (struct tcphdr *)*tcp;
8374 	*tcp_len = get_l4_pyld_length(ip, tcph);
8375 	for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8376 		struct lro *l_lro = &ring_data->lro0_n[i];
8377 		if (l_lro->in_use) {
8378 			if (check_for_socket_match(l_lro, ip, tcph))
8379 				continue;
8380 			/* Sock pair matched */
8381 			*lro = l_lro;
8382 
8383 			if ((*lro)->tcp_next_seq != ntohl(tcph->seq)) {
8384 				DBG_PRINT(INFO_DBG, "%s: Out of sequence. "
8385 					  "expected 0x%x, actual 0x%x\n",
8386 					  __func__,
8387 					  (*lro)->tcp_next_seq,
8388 					  ntohl(tcph->seq));
8389 
8390 				swstats->outof_sequence_pkts++;
8391 				ret = 2;
8392 				break;
8393 			}
8394 
8395 			if (!verify_l3_l4_lro_capable(l_lro, ip, tcph,
8396 						      *tcp_len))
8397 				ret = 1; /* Aggregate */
8398 			else
8399 				ret = 2; /* Flush both */
8400 			break;
8401 		}
8402 	}
8403 
8404 	if (ret == 0) {
8405 		/* Before searching for available LRO objects,
8406 		 * check if the pkt is L3/L4 aggregatable. If not
8407 		 * don't create new LRO session. Just send this
8408 		 * packet up.
8409 		 */
8410 		if (verify_l3_l4_lro_capable(NULL, ip, tcph, *tcp_len))
8411 			return 5;
8412 
8413 		for (i = 0; i < MAX_LRO_SESSIONS; i++) {
8414 			struct lro *l_lro = &ring_data->lro0_n[i];
8415 			if (!(l_lro->in_use)) {
8416 				*lro = l_lro;
8417 				ret = 3; /* Begin anew */
8418 				break;
8419 			}
8420 		}
8421 	}
8422 
8423 	if (ret == 0) { /* sessions exceeded */
8424 		DBG_PRINT(INFO_DBG, "%s: All LRO sessions already in use\n",
8425 			  __func__);
8426 		*lro = NULL;
8427 		return ret;
8428 	}
8429 
8430 	switch (ret) {
8431 	case 3:
8432 		initiate_new_session(*lro, buffer, ip, tcph, *tcp_len,
8433 				     vlan_tag);
8434 		break;
8435 	case 2:
8436 		update_L3L4_header(sp, *lro);
8437 		break;
8438 	case 1:
8439 		aggregate_new_rx(*lro, ip, tcph, *tcp_len);
8440 		if ((*lro)->sg_num == sp->lro_max_aggr_per_sess) {
8441 			update_L3L4_header(sp, *lro);
8442 			ret = 4; /* Flush the LRO */
8443 		}
8444 		break;
8445 	default:
8446 		DBG_PRINT(ERR_DBG, "%s: Don't know, can't say!!\n", __func__);
8447 		break;
8448 	}
8449 
8450 	return ret;
8451 }
8452 
clear_lro_session(struct lro * lro)8453 static void clear_lro_session(struct lro *lro)
8454 {
8455 	static u16 lro_struct_size = sizeof(struct lro);
8456 
8457 	memset(lro, 0, lro_struct_size);
8458 }
8459 
queue_rx_frame(struct sk_buff * skb,u16 vlan_tag)8460 static void queue_rx_frame(struct sk_buff *skb, u16 vlan_tag)
8461 {
8462 	struct net_device *dev = skb->dev;
8463 	struct s2io_nic *sp = netdev_priv(dev);
8464 
8465 	skb->protocol = eth_type_trans(skb, dev);
8466 	if (vlan_tag && sp->vlan_strip_flag)
8467 		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tag);
8468 	if (sp->config.napi)
8469 		netif_receive_skb(skb);
8470 	else
8471 		netif_rx(skb);
8472 }
8473 
lro_append_pkt(struct s2io_nic * sp,struct lro * lro,struct sk_buff * skb,u32 tcp_len)8474 static void lro_append_pkt(struct s2io_nic *sp, struct lro *lro,
8475 			   struct sk_buff *skb, u32 tcp_len)
8476 {
8477 	struct sk_buff *first = lro->parent;
8478 	struct swStat *swstats = &sp->mac_control.stats_info->sw_stat;
8479 
8480 	first->len += tcp_len;
8481 	first->data_len = lro->frags_len;
8482 	skb_pull(skb, (skb->len - tcp_len));
8483 	if (skb_shinfo(first)->frag_list)
8484 		lro->last_frag->next = skb;
8485 	else
8486 		skb_shinfo(first)->frag_list = skb;
8487 	first->truesize += skb->truesize;
8488 	lro->last_frag = skb;
8489 	swstats->clubbed_frms_cnt++;
8490 }
8491 
8492 /**
8493  * s2io_io_error_detected - called when PCI error is detected
8494  * @pdev: Pointer to PCI device
8495  * @state: The current pci connection state
8496  *
8497  * This function is called after a PCI bus error affecting
8498  * this device has been detected.
8499  */
s2io_io_error_detected(struct pci_dev * pdev,pci_channel_state_t state)8500 static pci_ers_result_t s2io_io_error_detected(struct pci_dev *pdev,
8501 					       pci_channel_state_t state)
8502 {
8503 	struct net_device *netdev = pci_get_drvdata(pdev);
8504 	struct s2io_nic *sp = netdev_priv(netdev);
8505 
8506 	netif_device_detach(netdev);
8507 
8508 	if (state == pci_channel_io_perm_failure)
8509 		return PCI_ERS_RESULT_DISCONNECT;
8510 
8511 	if (netif_running(netdev)) {
8512 		/* Bring down the card, while avoiding PCI I/O */
8513 		do_s2io_card_down(sp, 0);
8514 	}
8515 	pci_disable_device(pdev);
8516 
8517 	return PCI_ERS_RESULT_NEED_RESET;
8518 }
8519 
8520 /**
8521  * s2io_io_slot_reset - called after the pci bus has been reset.
8522  * @pdev: Pointer to PCI device
8523  *
8524  * Restart the card from scratch, as if from a cold-boot.
8525  * At this point, the card has exprienced a hard reset,
8526  * followed by fixups by BIOS, and has its config space
8527  * set up identically to what it was at cold boot.
8528  */
s2io_io_slot_reset(struct pci_dev * pdev)8529 static pci_ers_result_t s2io_io_slot_reset(struct pci_dev *pdev)
8530 {
8531 	struct net_device *netdev = pci_get_drvdata(pdev);
8532 	struct s2io_nic *sp = netdev_priv(netdev);
8533 
8534 	if (pci_enable_device(pdev)) {
8535 		pr_err("Cannot re-enable PCI device after reset.\n");
8536 		return PCI_ERS_RESULT_DISCONNECT;
8537 	}
8538 
8539 	pci_set_master(pdev);
8540 	s2io_reset(sp);
8541 
8542 	return PCI_ERS_RESULT_RECOVERED;
8543 }
8544 
8545 /**
8546  * s2io_io_resume - called when traffic can start flowing again.
8547  * @pdev: Pointer to PCI device
8548  *
8549  * This callback is called when the error recovery driver tells
8550  * us that its OK to resume normal operation.
8551  */
s2io_io_resume(struct pci_dev * pdev)8552 static void s2io_io_resume(struct pci_dev *pdev)
8553 {
8554 	struct net_device *netdev = pci_get_drvdata(pdev);
8555 	struct s2io_nic *sp = netdev_priv(netdev);
8556 
8557 	if (netif_running(netdev)) {
8558 		if (s2io_card_up(sp)) {
8559 			pr_err("Can't bring device back up after reset.\n");
8560 			return;
8561 		}
8562 
8563 		if (do_s2io_prog_unicast(netdev, netdev->dev_addr) == FAILURE) {
8564 			s2io_card_down(sp);
8565 			pr_err("Can't restore mac addr after reset.\n");
8566 			return;
8567 		}
8568 	}
8569 
8570 	netif_device_attach(netdev);
8571 	netif_tx_wake_all_queues(netdev);
8572 }
8573