1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
3 // Copyright (c) 2017-2018, Linaro Limited
4
5 #include <linux/module.h>
6 #include <linux/init.h>
7 #include <linux/platform_device.h>
8 #include <linux/device.h>
9 #include <linux/wait.h>
10 #include <linux/bitops.h>
11 #include <linux/regulator/consumer.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/kernel.h>
15 #include <linux/slimbus.h>
16 #include <sound/soc.h>
17 #include <sound/pcm_params.h>
18 #include <sound/soc-dapm.h>
19 #include <linux/gpio/consumer.h>
20 #include <linux/of.h>
21 #include <linux/of_irq.h>
22 #include <sound/tlv.h>
23 #include <sound/info.h>
24 #include "wcd9335.h"
25 #include "wcd-clsh-v2.h"
26
27 #include <dt-bindings/sound/qcom,wcd9335.h>
28
29 #define WCD9335_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
30 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
31 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
32 /* Fractional Rates */
33 #define WCD9335_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100)
34 #define WCD9335_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
35 SNDRV_PCM_FMTBIT_S24_LE)
36
37 /* slave port water mark level
38 * (0: 6bytes, 1: 9bytes, 2: 12 bytes, 3: 15 bytes)
39 */
40 #define SLAVE_PORT_WATER_MARK_6BYTES 0
41 #define SLAVE_PORT_WATER_MARK_9BYTES 1
42 #define SLAVE_PORT_WATER_MARK_12BYTES 2
43 #define SLAVE_PORT_WATER_MARK_15BYTES 3
44 #define SLAVE_PORT_WATER_MARK_SHIFT 1
45 #define SLAVE_PORT_ENABLE 1
46 #define SLAVE_PORT_DISABLE 0
47 #define WCD9335_SLIM_WATER_MARK_VAL \
48 ((SLAVE_PORT_WATER_MARK_12BYTES << SLAVE_PORT_WATER_MARK_SHIFT) | \
49 (SLAVE_PORT_ENABLE))
50
51 #define WCD9335_SLIM_NUM_PORT_REG 3
52 #define WCD9335_SLIM_PGD_PORT_INT_TX_EN0 (WCD9335_SLIM_PGD_PORT_INT_EN0 + 2)
53
54 #define WCD9335_MCLK_CLK_12P288MHZ 12288000
55 #define WCD9335_MCLK_CLK_9P6MHZ 9600000
56
57 #define WCD9335_SLIM_CLOSE_TIMEOUT 1000
58 #define WCD9335_SLIM_IRQ_OVERFLOW (1 << 0)
59 #define WCD9335_SLIM_IRQ_UNDERFLOW (1 << 1)
60 #define WCD9335_SLIM_IRQ_PORT_CLOSED (1 << 2)
61
62 #define WCD9335_NUM_INTERPOLATORS 9
63 #define WCD9335_RX_START 16
64 #define WCD9335_SLIM_CH_START 128
65 #define WCD9335_MAX_MICBIAS 4
66 #define WCD9335_MAX_VALID_ADC_MUX 13
67 #define WCD9335_INVALID_ADC_MUX 9
68
69 #define TX_HPF_CUT_OFF_FREQ_MASK 0x60
70 #define CF_MIN_3DB_4HZ 0x0
71 #define CF_MIN_3DB_75HZ 0x1
72 #define CF_MIN_3DB_150HZ 0x2
73 #define WCD9335_DMIC_CLK_DIV_2 0x0
74 #define WCD9335_DMIC_CLK_DIV_3 0x1
75 #define WCD9335_DMIC_CLK_DIV_4 0x2
76 #define WCD9335_DMIC_CLK_DIV_6 0x3
77 #define WCD9335_DMIC_CLK_DIV_8 0x4
78 #define WCD9335_DMIC_CLK_DIV_16 0x5
79 #define WCD9335_DMIC_CLK_DRIVE_DEFAULT 0x02
80 #define WCD9335_AMIC_PWR_LEVEL_LP 0
81 #define WCD9335_AMIC_PWR_LEVEL_DEFAULT 1
82 #define WCD9335_AMIC_PWR_LEVEL_HP 2
83 #define WCD9335_AMIC_PWR_LVL_MASK 0x60
84 #define WCD9335_AMIC_PWR_LVL_SHIFT 0x5
85
86 #define WCD9335_DEC_PWR_LVL_MASK 0x06
87 #define WCD9335_DEC_PWR_LVL_LP 0x02
88 #define WCD9335_DEC_PWR_LVL_HP 0x04
89 #define WCD9335_DEC_PWR_LVL_DF 0x00
90
91 #define WCD9335_SLIM_RX_CH(p) \
92 {.port = p + WCD9335_RX_START, .shift = p,}
93
94 #define WCD9335_SLIM_TX_CH(p) \
95 {.port = p, .shift = p,}
96
97 /* vout step value */
98 #define WCD9335_CALCULATE_VOUT_D(req_mv) (((req_mv - 650) * 10) / 25)
99
100 #define WCD9335_INTERPOLATOR_PATH(id) \
101 {"RX INT" #id "_1 MIX1 INP0", "RX0", "SLIM RX0"}, \
102 {"RX INT" #id "_1 MIX1 INP0", "RX1", "SLIM RX1"}, \
103 {"RX INT" #id "_1 MIX1 INP0", "RX2", "SLIM RX2"}, \
104 {"RX INT" #id "_1 MIX1 INP0", "RX3", "SLIM RX3"}, \
105 {"RX INT" #id "_1 MIX1 INP0", "RX4", "SLIM RX4"}, \
106 {"RX INT" #id "_1 MIX1 INP0", "RX5", "SLIM RX5"}, \
107 {"RX INT" #id "_1 MIX1 INP0", "RX6", "SLIM RX6"}, \
108 {"RX INT" #id "_1 MIX1 INP0", "RX7", "SLIM RX7"}, \
109 {"RX INT" #id "_1 MIX1 INP1", "RX0", "SLIM RX0"}, \
110 {"RX INT" #id "_1 MIX1 INP1", "RX1", "SLIM RX1"}, \
111 {"RX INT" #id "_1 MIX1 INP1", "RX2", "SLIM RX2"}, \
112 {"RX INT" #id "_1 MIX1 INP1", "RX3", "SLIM RX3"}, \
113 {"RX INT" #id "_1 MIX1 INP1", "RX4", "SLIM RX4"}, \
114 {"RX INT" #id "_1 MIX1 INP1", "RX5", "SLIM RX5"}, \
115 {"RX INT" #id "_1 MIX1 INP1", "RX6", "SLIM RX6"}, \
116 {"RX INT" #id "_1 MIX1 INP1", "RX7", "SLIM RX7"}, \
117 {"RX INT" #id "_1 MIX1 INP2", "RX0", "SLIM RX0"}, \
118 {"RX INT" #id "_1 MIX1 INP2", "RX1", "SLIM RX1"}, \
119 {"RX INT" #id "_1 MIX1 INP2", "RX2", "SLIM RX2"}, \
120 {"RX INT" #id "_1 MIX1 INP2", "RX3", "SLIM RX3"}, \
121 {"RX INT" #id "_1 MIX1 INP2", "RX4", "SLIM RX4"}, \
122 {"RX INT" #id "_1 MIX1 INP2", "RX5", "SLIM RX5"}, \
123 {"RX INT" #id "_1 MIX1 INP2", "RX6", "SLIM RX6"}, \
124 {"RX INT" #id "_1 MIX1 INP2", "RX7", "SLIM RX7"}, \
125 {"RX INT" #id "_2 MUX", "RX0", "SLIM RX0"}, \
126 {"RX INT" #id "_2 MUX", "RX1", "SLIM RX1"}, \
127 {"RX INT" #id "_2 MUX", "RX2", "SLIM RX2"}, \
128 {"RX INT" #id "_2 MUX", "RX3", "SLIM RX3"}, \
129 {"RX INT" #id "_2 MUX", "RX4", "SLIM RX4"}, \
130 {"RX INT" #id "_2 MUX", "RX5", "SLIM RX5"}, \
131 {"RX INT" #id "_2 MUX", "RX6", "SLIM RX6"}, \
132 {"RX INT" #id "_2 MUX", "RX7", "SLIM RX7"}, \
133 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP0"}, \
134 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP1"}, \
135 {"RX INT" #id "_1 MIX1", NULL, "RX INT" #id "_1 MIX1 INP2"}, \
136 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_2 MUX"}, \
137 {"RX INT" #id " SEC MIX", NULL, "RX INT" #id "_1 MIX1"}, \
138 {"RX INT" #id " MIX2", NULL, "RX INT" #id " SEC MIX"}, \
139 {"RX INT" #id " INTERP", NULL, "RX INT" #id " MIX2"}
140
141 #define WCD9335_ADC_MUX_PATH(id) \
142 {"AIF1_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
143 {"AIF2_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
144 {"AIF3_CAP Mixer", "SLIM TX" #id, "SLIM TX" #id " MUX"}, \
145 {"SLIM TX" #id " MUX", "DEC" #id, "ADC MUX" #id}, \
146 {"ADC MUX" #id, "DMIC", "DMIC MUX" #id}, \
147 {"ADC MUX" #id, "AMIC", "AMIC MUX" #id}, \
148 {"DMIC MUX" #id, "DMIC0", "DMIC0"}, \
149 {"DMIC MUX" #id, "DMIC1", "DMIC1"}, \
150 {"DMIC MUX" #id, "DMIC2", "DMIC2"}, \
151 {"DMIC MUX" #id, "DMIC3", "DMIC3"}, \
152 {"DMIC MUX" #id, "DMIC4", "DMIC4"}, \
153 {"DMIC MUX" #id, "DMIC5", "DMIC5"}, \
154 {"AMIC MUX" #id, "ADC1", "ADC1"}, \
155 {"AMIC MUX" #id, "ADC2", "ADC2"}, \
156 {"AMIC MUX" #id, "ADC3", "ADC3"}, \
157 {"AMIC MUX" #id, "ADC4", "ADC4"}, \
158 {"AMIC MUX" #id, "ADC5", "ADC5"}, \
159 {"AMIC MUX" #id, "ADC6", "ADC6"}
160
161 enum {
162 WCD9335_RX0 = 0,
163 WCD9335_RX1,
164 WCD9335_RX2,
165 WCD9335_RX3,
166 WCD9335_RX4,
167 WCD9335_RX5,
168 WCD9335_RX6,
169 WCD9335_RX7,
170 WCD9335_RX8,
171 WCD9335_RX9,
172 WCD9335_RX10,
173 WCD9335_RX11,
174 WCD9335_RX12,
175 WCD9335_RX_MAX,
176 };
177
178 enum {
179 WCD9335_TX0 = 0,
180 WCD9335_TX1,
181 WCD9335_TX2,
182 WCD9335_TX3,
183 WCD9335_TX4,
184 WCD9335_TX5,
185 WCD9335_TX6,
186 WCD9335_TX7,
187 WCD9335_TX8,
188 WCD9335_TX9,
189 WCD9335_TX10,
190 WCD9335_TX11,
191 WCD9335_TX12,
192 WCD9335_TX13,
193 WCD9335_TX14,
194 WCD9335_TX15,
195 WCD9335_TX_MAX,
196 };
197
198 enum {
199 SIDO_SOURCE_INTERNAL = 0,
200 SIDO_SOURCE_RCO_BG,
201 };
202
203 enum wcd9335_sido_voltage {
204 SIDO_VOLTAGE_SVS_MV = 950,
205 SIDO_VOLTAGE_NOMINAL_MV = 1100,
206 };
207
208 enum {
209 COMPANDER_1, /* HPH_L */
210 COMPANDER_2, /* HPH_R */
211 COMPANDER_3, /* LO1_DIFF */
212 COMPANDER_4, /* LO2_DIFF */
213 COMPANDER_5, /* LO3_SE */
214 COMPANDER_6, /* LO4_SE */
215 COMPANDER_7, /* SWR SPK CH1 */
216 COMPANDER_8, /* SWR SPK CH2 */
217 COMPANDER_MAX,
218 };
219
220 enum {
221 INTn_2_INP_SEL_ZERO = 0,
222 INTn_2_INP_SEL_RX0,
223 INTn_2_INP_SEL_RX1,
224 INTn_2_INP_SEL_RX2,
225 INTn_2_INP_SEL_RX3,
226 INTn_2_INP_SEL_RX4,
227 INTn_2_INP_SEL_RX5,
228 INTn_2_INP_SEL_RX6,
229 INTn_2_INP_SEL_RX7,
230 INTn_2_INP_SEL_PROXIMITY,
231 };
232
233 enum {
234 INTn_1_MIX_INP_SEL_ZERO = 0,
235 INTn_1_MIX_INP_SEL_DEC0,
236 INTn_1_MIX_INP_SEL_DEC1,
237 INTn_1_MIX_INP_SEL_IIR0,
238 INTn_1_MIX_INP_SEL_IIR1,
239 INTn_1_MIX_INP_SEL_RX0,
240 INTn_1_MIX_INP_SEL_RX1,
241 INTn_1_MIX_INP_SEL_RX2,
242 INTn_1_MIX_INP_SEL_RX3,
243 INTn_1_MIX_INP_SEL_RX4,
244 INTn_1_MIX_INP_SEL_RX5,
245 INTn_1_MIX_INP_SEL_RX6,
246 INTn_1_MIX_INP_SEL_RX7,
247
248 };
249
250 enum {
251 INTERP_EAR = 0,
252 INTERP_HPHL,
253 INTERP_HPHR,
254 INTERP_LO1,
255 INTERP_LO2,
256 INTERP_LO3,
257 INTERP_LO4,
258 INTERP_SPKR1,
259 INTERP_SPKR2,
260 };
261
262 enum wcd_clock_type {
263 WCD_CLK_OFF,
264 WCD_CLK_RCO,
265 WCD_CLK_MCLK,
266 };
267
268 enum {
269 MIC_BIAS_1 = 1,
270 MIC_BIAS_2,
271 MIC_BIAS_3,
272 MIC_BIAS_4
273 };
274
275 enum {
276 MICB_PULLUP_ENABLE,
277 MICB_PULLUP_DISABLE,
278 MICB_ENABLE,
279 MICB_DISABLE,
280 };
281
282 struct wcd9335_slim_ch {
283 u32 ch_num;
284 u16 port;
285 u16 shift;
286 struct list_head list;
287 };
288
289 struct wcd_slim_codec_dai_data {
290 struct list_head slim_ch_list;
291 struct slim_stream_config sconfig;
292 struct slim_stream_runtime *sruntime;
293 };
294
295 struct wcd9335_codec {
296 struct device *dev;
297 struct clk *mclk;
298 struct clk *native_clk;
299 u32 mclk_rate;
300 u8 version;
301
302 struct slim_device *slim;
303 struct slim_device *slim_ifc_dev;
304 struct regmap *regmap;
305 struct regmap *if_regmap;
306 struct regmap_irq_chip_data *irq_data;
307
308 struct wcd9335_slim_ch rx_chs[WCD9335_RX_MAX];
309 struct wcd9335_slim_ch tx_chs[WCD9335_TX_MAX];
310 u32 num_rx_port;
311 u32 num_tx_port;
312
313 int sido_input_src;
314 enum wcd9335_sido_voltage sido_voltage;
315
316 struct wcd_slim_codec_dai_data dai[NUM_CODEC_DAIS];
317 struct snd_soc_component *component;
318
319 int master_bias_users;
320 int clk_mclk_users;
321 int clk_rco_users;
322 int sido_ccl_cnt;
323 enum wcd_clock_type clk_type;
324
325 struct wcd_clsh_ctrl *clsh_ctrl;
326 u32 hph_mode;
327 int prim_int_users[WCD9335_NUM_INTERPOLATORS];
328
329 int comp_enabled[COMPANDER_MAX];
330
331 int intr1;
332 struct gpio_desc *reset_gpio;
333
334 unsigned int rx_port_value[WCD9335_RX_MAX];
335 unsigned int tx_port_value[WCD9335_TX_MAX];
336 int hph_l_gain;
337 int hph_r_gain;
338 u32 rx_bias_count;
339
340 /*TX*/
341 int micb_ref[WCD9335_MAX_MICBIAS];
342 int pullup_ref[WCD9335_MAX_MICBIAS];
343
344 int dmic_0_1_clk_cnt;
345 int dmic_2_3_clk_cnt;
346 int dmic_4_5_clk_cnt;
347 int dmic_sample_rate;
348 int mad_dmic_sample_rate;
349
350 int native_clk_users;
351 };
352
353 struct wcd9335_irq {
354 int irq;
355 irqreturn_t (*handler)(int irq, void *data);
356 char *name;
357 };
358
359 static const char * const wcd9335_supplies[] = {
360 "vdd-buck", "vdd-buck-sido", "vdd-tx", "vdd-rx", "vdd-io",
361 };
362
363 static const struct wcd9335_slim_ch wcd9335_tx_chs[WCD9335_TX_MAX] = {
364 WCD9335_SLIM_TX_CH(0),
365 WCD9335_SLIM_TX_CH(1),
366 WCD9335_SLIM_TX_CH(2),
367 WCD9335_SLIM_TX_CH(3),
368 WCD9335_SLIM_TX_CH(4),
369 WCD9335_SLIM_TX_CH(5),
370 WCD9335_SLIM_TX_CH(6),
371 WCD9335_SLIM_TX_CH(7),
372 WCD9335_SLIM_TX_CH(8),
373 WCD9335_SLIM_TX_CH(9),
374 WCD9335_SLIM_TX_CH(10),
375 WCD9335_SLIM_TX_CH(11),
376 WCD9335_SLIM_TX_CH(12),
377 WCD9335_SLIM_TX_CH(13),
378 WCD9335_SLIM_TX_CH(14),
379 WCD9335_SLIM_TX_CH(15),
380 };
381
382 static const struct wcd9335_slim_ch wcd9335_rx_chs[WCD9335_RX_MAX] = {
383 WCD9335_SLIM_RX_CH(0), /* 16 */
384 WCD9335_SLIM_RX_CH(1), /* 17 */
385 WCD9335_SLIM_RX_CH(2),
386 WCD9335_SLIM_RX_CH(3),
387 WCD9335_SLIM_RX_CH(4),
388 WCD9335_SLIM_RX_CH(5),
389 WCD9335_SLIM_RX_CH(6),
390 WCD9335_SLIM_RX_CH(7),
391 WCD9335_SLIM_RX_CH(8),
392 WCD9335_SLIM_RX_CH(9),
393 WCD9335_SLIM_RX_CH(10),
394 WCD9335_SLIM_RX_CH(11),
395 WCD9335_SLIM_RX_CH(12),
396 };
397
398 struct interp_sample_rate {
399 int rate;
400 int rate_val;
401 };
402
403 static struct interp_sample_rate int_mix_rate_val[] = {
404 {48000, 0x4}, /* 48K */
405 {96000, 0x5}, /* 96K */
406 {192000, 0x6}, /* 192K */
407 };
408
409 static struct interp_sample_rate int_prim_rate_val[] = {
410 {8000, 0x0}, /* 8K */
411 {16000, 0x1}, /* 16K */
412 {24000, -EINVAL},/* 24K */
413 {32000, 0x3}, /* 32K */
414 {48000, 0x4}, /* 48K */
415 {96000, 0x5}, /* 96K */
416 {192000, 0x6}, /* 192K */
417 {384000, 0x7}, /* 384K */
418 {44100, 0x8}, /* 44.1K */
419 };
420
421 struct wcd9335_reg_mask_val {
422 u16 reg;
423 u8 mask;
424 u8 val;
425 };
426
427 static const struct wcd9335_reg_mask_val wcd9335_codec_reg_init[] = {
428 /* Rbuckfly/R_EAR(32) */
429 {WCD9335_CDC_CLSH_K2_MSB, 0x0F, 0x00},
430 {WCD9335_CDC_CLSH_K2_LSB, 0xFF, 0x60},
431 {WCD9335_CPE_SS_DMIC_CFG, 0x80, 0x00},
432 {WCD9335_CDC_BOOST0_BOOST_CTL, 0x70, 0x50},
433 {WCD9335_CDC_BOOST1_BOOST_CTL, 0x70, 0x50},
434 {WCD9335_CDC_RX7_RX_PATH_CFG1, 0x08, 0x08},
435 {WCD9335_CDC_RX8_RX_PATH_CFG1, 0x08, 0x08},
436 {WCD9335_ANA_LO_1_2, 0x3C, 0X3C},
437 {WCD9335_DIFF_LO_COM_SWCAP_REFBUF_FREQ, 0x70, 0x00},
438 {WCD9335_DIFF_LO_COM_PA_FREQ, 0x70, 0x40},
439 {WCD9335_SOC_MAD_AUDIO_CTL_2, 0x03, 0x03},
440 {WCD9335_CDC_TOP_TOP_CFG1, 0x02, 0x02},
441 {WCD9335_CDC_TOP_TOP_CFG1, 0x01, 0x01},
442 {WCD9335_EAR_CMBUFF, 0x08, 0x00},
443 {WCD9335_CDC_TX9_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
444 {WCD9335_CDC_TX10_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
445 {WCD9335_CDC_TX11_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
446 {WCD9335_CDC_TX12_SPKR_PROT_PATH_CFG0, 0x01, 0x01},
447 {WCD9335_CDC_COMPANDER7_CTL3, 0x80, 0x80},
448 {WCD9335_CDC_COMPANDER8_CTL3, 0x80, 0x80},
449 {WCD9335_CDC_COMPANDER7_CTL7, 0x01, 0x01},
450 {WCD9335_CDC_COMPANDER8_CTL7, 0x01, 0x01},
451 {WCD9335_CDC_RX0_RX_PATH_CFG0, 0x01, 0x01},
452 {WCD9335_CDC_RX1_RX_PATH_CFG0, 0x01, 0x01},
453 {WCD9335_CDC_RX2_RX_PATH_CFG0, 0x01, 0x01},
454 {WCD9335_CDC_RX3_RX_PATH_CFG0, 0x01, 0x01},
455 {WCD9335_CDC_RX4_RX_PATH_CFG0, 0x01, 0x01},
456 {WCD9335_CDC_RX5_RX_PATH_CFG0, 0x01, 0x01},
457 {WCD9335_CDC_RX6_RX_PATH_CFG0, 0x01, 0x01},
458 {WCD9335_CDC_RX7_RX_PATH_CFG0, 0x01, 0x01},
459 {WCD9335_CDC_RX8_RX_PATH_CFG0, 0x01, 0x01},
460 {WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 0x01, 0x01},
461 {WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 0x01, 0x01},
462 {WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 0x01, 0x01},
463 {WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 0x01, 0x01},
464 {WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 0x01, 0x01},
465 {WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 0x01, 0x01},
466 {WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 0x01, 0x01},
467 {WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 0x01, 0x01},
468 {WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 0x01, 0x01},
469 {WCD9335_VBADC_IBIAS_FE, 0x0C, 0x08},
470 {WCD9335_RCO_CTRL_2, 0x0F, 0x08},
471 {WCD9335_RX_BIAS_FLYB_MID_RST, 0xF0, 0x10},
472 {WCD9335_FLYBACK_CTRL_1, 0x20, 0x20},
473 {WCD9335_HPH_OCP_CTL, 0xFF, 0x5A},
474 {WCD9335_HPH_L_TEST, 0x01, 0x01},
475 {WCD9335_HPH_R_TEST, 0x01, 0x01},
476 {WCD9335_CDC_BOOST0_BOOST_CFG1, 0x3F, 0x12},
477 {WCD9335_CDC_BOOST0_BOOST_CFG2, 0x1C, 0x08},
478 {WCD9335_CDC_COMPANDER7_CTL7, 0x1E, 0x18},
479 {WCD9335_CDC_BOOST1_BOOST_CFG1, 0x3F, 0x12},
480 {WCD9335_CDC_BOOST1_BOOST_CFG2, 0x1C, 0x08},
481 {WCD9335_CDC_COMPANDER8_CTL7, 0x1E, 0x18},
482 {WCD9335_CDC_TX0_TX_PATH_SEC7, 0xFF, 0x45},
483 {WCD9335_CDC_RX0_RX_PATH_SEC0, 0xFC, 0xF4},
484 {WCD9335_HPH_REFBUFF_LP_CTL, 0x08, 0x08},
485 {WCD9335_HPH_REFBUFF_LP_CTL, 0x06, 0x02},
486 };
487
488 /* Cutoff frequency for high pass filter */
489 static const char * const cf_text[] = {
490 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ"
491 };
492
493 static const char * const rx_cf_text[] = {
494 "CF_NEG_3DB_4HZ", "CF_NEG_3DB_75HZ", "CF_NEG_3DB_150HZ",
495 "CF_NEG_3DB_0P48HZ"
496 };
497
498 static const char * const rx_int0_7_mix_mux_text[] = {
499 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
500 "RX6", "RX7", "PROXIMITY"
501 };
502
503 static const char * const rx_int_mix_mux_text[] = {
504 "ZERO", "RX0", "RX1", "RX2", "RX3", "RX4", "RX5",
505 "RX6", "RX7"
506 };
507
508 static const char * const rx_prim_mix_text[] = {
509 "ZERO", "DEC0", "DEC1", "IIR0", "IIR1", "RX0", "RX1", "RX2",
510 "RX3", "RX4", "RX5", "RX6", "RX7"
511 };
512
513 static const char * const rx_int_dem_inp_mux_text[] = {
514 "NORMAL_DSM_OUT", "CLSH_DSM_OUT",
515 };
516
517 static const char * const rx_int0_interp_mux_text[] = {
518 "ZERO", "RX INT0 MIX2",
519 };
520
521 static const char * const rx_int1_interp_mux_text[] = {
522 "ZERO", "RX INT1 MIX2",
523 };
524
525 static const char * const rx_int2_interp_mux_text[] = {
526 "ZERO", "RX INT2 MIX2",
527 };
528
529 static const char * const rx_int3_interp_mux_text[] = {
530 "ZERO", "RX INT3 MIX2",
531 };
532
533 static const char * const rx_int4_interp_mux_text[] = {
534 "ZERO", "RX INT4 MIX2",
535 };
536
537 static const char * const rx_int5_interp_mux_text[] = {
538 "ZERO", "RX INT5 MIX2",
539 };
540
541 static const char * const rx_int6_interp_mux_text[] = {
542 "ZERO", "RX INT6 MIX2",
543 };
544
545 static const char * const rx_int7_interp_mux_text[] = {
546 "ZERO", "RX INT7 MIX2",
547 };
548
549 static const char * const rx_int8_interp_mux_text[] = {
550 "ZERO", "RX INT8 SEC MIX"
551 };
552
553 static const char * const rx_hph_mode_mux_text[] = {
554 "Class H Invalid", "Class-H Hi-Fi", "Class-H Low Power", "Class-AB",
555 "Class-H Hi-Fi Low Power"
556 };
557
558 static const char *const slim_rx_mux_text[] = {
559 "ZERO", "AIF1_PB", "AIF2_PB", "AIF3_PB", "AIF4_PB",
560 };
561
562 static const char * const adc_mux_text[] = {
563 "DMIC", "AMIC", "ANC_FB_TUNE1", "ANC_FB_TUNE2"
564 };
565
566 static const char * const dmic_mux_text[] = {
567 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
568 "SMIC0", "SMIC1", "SMIC2", "SMIC3"
569 };
570
571 static const char * const dmic_mux_alt_text[] = {
572 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", "DMIC4", "DMIC5",
573 };
574
575 static const char * const amic_mux_text[] = {
576 "ZERO", "ADC1", "ADC2", "ADC3", "ADC4", "ADC5", "ADC6"
577 };
578
579 static const char * const sb_tx0_mux_text[] = {
580 "ZERO", "RX_MIX_TX0", "DEC0", "DEC0_192"
581 };
582
583 static const char * const sb_tx1_mux_text[] = {
584 "ZERO", "RX_MIX_TX1", "DEC1", "DEC1_192"
585 };
586
587 static const char * const sb_tx2_mux_text[] = {
588 "ZERO", "RX_MIX_TX2", "DEC2", "DEC2_192"
589 };
590
591 static const char * const sb_tx3_mux_text[] = {
592 "ZERO", "RX_MIX_TX3", "DEC3", "DEC3_192"
593 };
594
595 static const char * const sb_tx4_mux_text[] = {
596 "ZERO", "RX_MIX_TX4", "DEC4", "DEC4_192"
597 };
598
599 static const char * const sb_tx5_mux_text[] = {
600 "ZERO", "RX_MIX_TX5", "DEC5", "DEC5_192"
601 };
602
603 static const char * const sb_tx6_mux_text[] = {
604 "ZERO", "RX_MIX_TX6", "DEC6", "DEC6_192"
605 };
606
607 static const char * const sb_tx7_mux_text[] = {
608 "ZERO", "RX_MIX_TX7", "DEC7", "DEC7_192"
609 };
610
611 static const char * const sb_tx8_mux_text[] = {
612 "ZERO", "RX_MIX_TX8", "DEC8", "DEC8_192"
613 };
614
615 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
616 static const DECLARE_TLV_DB_SCALE(line_gain, 0, 7, 1);
617 static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 25, 1);
618 static const DECLARE_TLV_DB_SCALE(ear_pa_gain, 0, 150, 0);
619
620 static const struct soc_enum cf_dec0_enum =
621 SOC_ENUM_SINGLE(WCD9335_CDC_TX0_TX_PATH_CFG0, 5, 3, cf_text);
622
623 static const struct soc_enum cf_dec1_enum =
624 SOC_ENUM_SINGLE(WCD9335_CDC_TX1_TX_PATH_CFG0, 5, 3, cf_text);
625
626 static const struct soc_enum cf_dec2_enum =
627 SOC_ENUM_SINGLE(WCD9335_CDC_TX2_TX_PATH_CFG0, 5, 3, cf_text);
628
629 static const struct soc_enum cf_dec3_enum =
630 SOC_ENUM_SINGLE(WCD9335_CDC_TX3_TX_PATH_CFG0, 5, 3, cf_text);
631
632 static const struct soc_enum cf_dec4_enum =
633 SOC_ENUM_SINGLE(WCD9335_CDC_TX4_TX_PATH_CFG0, 5, 3, cf_text);
634
635 static const struct soc_enum cf_dec5_enum =
636 SOC_ENUM_SINGLE(WCD9335_CDC_TX5_TX_PATH_CFG0, 5, 3, cf_text);
637
638 static const struct soc_enum cf_dec6_enum =
639 SOC_ENUM_SINGLE(WCD9335_CDC_TX6_TX_PATH_CFG0, 5, 3, cf_text);
640
641 static const struct soc_enum cf_dec7_enum =
642 SOC_ENUM_SINGLE(WCD9335_CDC_TX7_TX_PATH_CFG0, 5, 3, cf_text);
643
644 static const struct soc_enum cf_dec8_enum =
645 SOC_ENUM_SINGLE(WCD9335_CDC_TX8_TX_PATH_CFG0, 5, 3, cf_text);
646
647 static const struct soc_enum cf_int0_1_enum =
648 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CFG2, 0, 4, rx_cf_text);
649
650 static SOC_ENUM_SINGLE_DECL(cf_int0_2_enum, WCD9335_CDC_RX0_RX_PATH_MIX_CFG, 2,
651 rx_cf_text);
652
653 static const struct soc_enum cf_int1_1_enum =
654 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CFG2, 0, 4, rx_cf_text);
655
656 static SOC_ENUM_SINGLE_DECL(cf_int1_2_enum, WCD9335_CDC_RX1_RX_PATH_MIX_CFG, 2,
657 rx_cf_text);
658
659 static const struct soc_enum cf_int2_1_enum =
660 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CFG2, 0, 4, rx_cf_text);
661
662 static SOC_ENUM_SINGLE_DECL(cf_int2_2_enum, WCD9335_CDC_RX2_RX_PATH_MIX_CFG, 2,
663 rx_cf_text);
664
665 static const struct soc_enum cf_int3_1_enum =
666 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CFG2, 0, 4, rx_cf_text);
667
668 static SOC_ENUM_SINGLE_DECL(cf_int3_2_enum, WCD9335_CDC_RX3_RX_PATH_MIX_CFG, 2,
669 rx_cf_text);
670
671 static const struct soc_enum cf_int4_1_enum =
672 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CFG2, 0, 4, rx_cf_text);
673
674 static SOC_ENUM_SINGLE_DECL(cf_int4_2_enum, WCD9335_CDC_RX4_RX_PATH_MIX_CFG, 2,
675 rx_cf_text);
676
677 static const struct soc_enum cf_int5_1_enum =
678 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CFG2, 0, 4, rx_cf_text);
679
680 static SOC_ENUM_SINGLE_DECL(cf_int5_2_enum, WCD9335_CDC_RX5_RX_PATH_MIX_CFG, 2,
681 rx_cf_text);
682
683 static const struct soc_enum cf_int6_1_enum =
684 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CFG2, 0, 4, rx_cf_text);
685
686 static SOC_ENUM_SINGLE_DECL(cf_int6_2_enum, WCD9335_CDC_RX6_RX_PATH_MIX_CFG, 2,
687 rx_cf_text);
688
689 static const struct soc_enum cf_int7_1_enum =
690 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CFG2, 0, 4, rx_cf_text);
691
692 static SOC_ENUM_SINGLE_DECL(cf_int7_2_enum, WCD9335_CDC_RX7_RX_PATH_MIX_CFG, 2,
693 rx_cf_text);
694
695 static const struct soc_enum cf_int8_1_enum =
696 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CFG2, 0, 4, rx_cf_text);
697
698 static SOC_ENUM_SINGLE_DECL(cf_int8_2_enum, WCD9335_CDC_RX8_RX_PATH_MIX_CFG, 2,
699 rx_cf_text);
700
701 static const struct soc_enum rx_hph_mode_mux_enum =
702 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
703 rx_hph_mode_mux_text);
704
705 static const struct soc_enum slim_rx_mux_enum =
706 SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(slim_rx_mux_text), slim_rx_mux_text);
707
708 static const struct soc_enum rx_int0_2_mux_chain_enum =
709 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 0, 10,
710 rx_int0_7_mix_mux_text);
711
712 static const struct soc_enum rx_int1_2_mux_chain_enum =
713 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 0, 9,
714 rx_int_mix_mux_text);
715
716 static const struct soc_enum rx_int2_2_mux_chain_enum =
717 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 0, 9,
718 rx_int_mix_mux_text);
719
720 static const struct soc_enum rx_int3_2_mux_chain_enum =
721 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 0, 9,
722 rx_int_mix_mux_text);
723
724 static const struct soc_enum rx_int4_2_mux_chain_enum =
725 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 0, 9,
726 rx_int_mix_mux_text);
727
728 static const struct soc_enum rx_int5_2_mux_chain_enum =
729 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 0, 9,
730 rx_int_mix_mux_text);
731
732 static const struct soc_enum rx_int6_2_mux_chain_enum =
733 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 0, 9,
734 rx_int_mix_mux_text);
735
736 static const struct soc_enum rx_int7_2_mux_chain_enum =
737 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 0, 10,
738 rx_int0_7_mix_mux_text);
739
740 static const struct soc_enum rx_int8_2_mux_chain_enum =
741 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 0, 9,
742 rx_int_mix_mux_text);
743
744 static const struct soc_enum rx_int0_1_mix_inp0_chain_enum =
745 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 0, 13,
746 rx_prim_mix_text);
747
748 static const struct soc_enum rx_int0_1_mix_inp1_chain_enum =
749 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG0, 4, 13,
750 rx_prim_mix_text);
751
752 static const struct soc_enum rx_int0_1_mix_inp2_chain_enum =
753 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT0_CFG1, 4, 13,
754 rx_prim_mix_text);
755
756 static const struct soc_enum rx_int1_1_mix_inp0_chain_enum =
757 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 0, 13,
758 rx_prim_mix_text);
759
760 static const struct soc_enum rx_int1_1_mix_inp1_chain_enum =
761 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG0, 4, 13,
762 rx_prim_mix_text);
763
764 static const struct soc_enum rx_int1_1_mix_inp2_chain_enum =
765 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT1_CFG1, 4, 13,
766 rx_prim_mix_text);
767
768 static const struct soc_enum rx_int2_1_mix_inp0_chain_enum =
769 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 0, 13,
770 rx_prim_mix_text);
771
772 static const struct soc_enum rx_int2_1_mix_inp1_chain_enum =
773 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG0, 4, 13,
774 rx_prim_mix_text);
775
776 static const struct soc_enum rx_int2_1_mix_inp2_chain_enum =
777 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT2_CFG1, 4, 13,
778 rx_prim_mix_text);
779
780 static const struct soc_enum rx_int3_1_mix_inp0_chain_enum =
781 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 0, 13,
782 rx_prim_mix_text);
783
784 static const struct soc_enum rx_int3_1_mix_inp1_chain_enum =
785 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG0, 4, 13,
786 rx_prim_mix_text);
787
788 static const struct soc_enum rx_int3_1_mix_inp2_chain_enum =
789 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT3_CFG1, 4, 13,
790 rx_prim_mix_text);
791
792 static const struct soc_enum rx_int4_1_mix_inp0_chain_enum =
793 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 0, 13,
794 rx_prim_mix_text);
795
796 static const struct soc_enum rx_int4_1_mix_inp1_chain_enum =
797 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG0, 4, 13,
798 rx_prim_mix_text);
799
800 static const struct soc_enum rx_int4_1_mix_inp2_chain_enum =
801 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT4_CFG1, 4, 13,
802 rx_prim_mix_text);
803
804 static const struct soc_enum rx_int5_1_mix_inp0_chain_enum =
805 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 0, 13,
806 rx_prim_mix_text);
807
808 static const struct soc_enum rx_int5_1_mix_inp1_chain_enum =
809 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG0, 4, 13,
810 rx_prim_mix_text);
811
812 static const struct soc_enum rx_int5_1_mix_inp2_chain_enum =
813 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT5_CFG1, 4, 13,
814 rx_prim_mix_text);
815
816 static const struct soc_enum rx_int6_1_mix_inp0_chain_enum =
817 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 0, 13,
818 rx_prim_mix_text);
819
820 static const struct soc_enum rx_int6_1_mix_inp1_chain_enum =
821 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG0, 4, 13,
822 rx_prim_mix_text);
823
824 static const struct soc_enum rx_int6_1_mix_inp2_chain_enum =
825 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT6_CFG1, 4, 13,
826 rx_prim_mix_text);
827
828 static const struct soc_enum rx_int7_1_mix_inp0_chain_enum =
829 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 0, 13,
830 rx_prim_mix_text);
831
832 static const struct soc_enum rx_int7_1_mix_inp1_chain_enum =
833 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG0, 4, 13,
834 rx_prim_mix_text);
835
836 static const struct soc_enum rx_int7_1_mix_inp2_chain_enum =
837 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT7_CFG1, 4, 13,
838 rx_prim_mix_text);
839
840 static const struct soc_enum rx_int8_1_mix_inp0_chain_enum =
841 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 0, 13,
842 rx_prim_mix_text);
843
844 static const struct soc_enum rx_int8_1_mix_inp1_chain_enum =
845 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG0, 4, 13,
846 rx_prim_mix_text);
847
848 static const struct soc_enum rx_int8_1_mix_inp2_chain_enum =
849 SOC_ENUM_SINGLE(WCD9335_CDC_RX_INP_MUX_RX_INT8_CFG1, 4, 13,
850 rx_prim_mix_text);
851
852 static const struct soc_enum rx_int0_dem_inp_mux_enum =
853 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_SEC0, 0,
854 ARRAY_SIZE(rx_int_dem_inp_mux_text),
855 rx_int_dem_inp_mux_text);
856
857 static const struct soc_enum rx_int1_dem_inp_mux_enum =
858 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_SEC0, 0,
859 ARRAY_SIZE(rx_int_dem_inp_mux_text),
860 rx_int_dem_inp_mux_text);
861
862 static const struct soc_enum rx_int2_dem_inp_mux_enum =
863 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_SEC0, 0,
864 ARRAY_SIZE(rx_int_dem_inp_mux_text),
865 rx_int_dem_inp_mux_text);
866
867 static const struct soc_enum rx_int0_interp_mux_enum =
868 SOC_ENUM_SINGLE(WCD9335_CDC_RX0_RX_PATH_CTL, 5, 2,
869 rx_int0_interp_mux_text);
870
871 static const struct soc_enum rx_int1_interp_mux_enum =
872 SOC_ENUM_SINGLE(WCD9335_CDC_RX1_RX_PATH_CTL, 5, 2,
873 rx_int1_interp_mux_text);
874
875 static const struct soc_enum rx_int2_interp_mux_enum =
876 SOC_ENUM_SINGLE(WCD9335_CDC_RX2_RX_PATH_CTL, 5, 2,
877 rx_int2_interp_mux_text);
878
879 static const struct soc_enum rx_int3_interp_mux_enum =
880 SOC_ENUM_SINGLE(WCD9335_CDC_RX3_RX_PATH_CTL, 5, 2,
881 rx_int3_interp_mux_text);
882
883 static const struct soc_enum rx_int4_interp_mux_enum =
884 SOC_ENUM_SINGLE(WCD9335_CDC_RX4_RX_PATH_CTL, 5, 2,
885 rx_int4_interp_mux_text);
886
887 static const struct soc_enum rx_int5_interp_mux_enum =
888 SOC_ENUM_SINGLE(WCD9335_CDC_RX5_RX_PATH_CTL, 5, 2,
889 rx_int5_interp_mux_text);
890
891 static const struct soc_enum rx_int6_interp_mux_enum =
892 SOC_ENUM_SINGLE(WCD9335_CDC_RX6_RX_PATH_CTL, 5, 2,
893 rx_int6_interp_mux_text);
894
895 static const struct soc_enum rx_int7_interp_mux_enum =
896 SOC_ENUM_SINGLE(WCD9335_CDC_RX7_RX_PATH_CTL, 5, 2,
897 rx_int7_interp_mux_text);
898
899 static const struct soc_enum rx_int8_interp_mux_enum =
900 SOC_ENUM_SINGLE(WCD9335_CDC_RX8_RX_PATH_CTL, 5, 2,
901 rx_int8_interp_mux_text);
902
903 static const struct soc_enum tx_adc_mux0_chain_enum =
904 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0, 4,
905 adc_mux_text);
906
907 static const struct soc_enum tx_adc_mux1_chain_enum =
908 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0, 4,
909 adc_mux_text);
910
911 static const struct soc_enum tx_adc_mux2_chain_enum =
912 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0, 4,
913 adc_mux_text);
914
915 static const struct soc_enum tx_adc_mux3_chain_enum =
916 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0, 4,
917 adc_mux_text);
918
919 static const struct soc_enum tx_adc_mux4_chain_enum =
920 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 6, 4,
921 adc_mux_text);
922
923 static const struct soc_enum tx_adc_mux5_chain_enum =
924 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 6, 4,
925 adc_mux_text);
926
927 static const struct soc_enum tx_adc_mux6_chain_enum =
928 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 6, 4,
929 adc_mux_text);
930
931 static const struct soc_enum tx_adc_mux7_chain_enum =
932 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 6, 4,
933 adc_mux_text);
934
935 static const struct soc_enum tx_adc_mux8_chain_enum =
936 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 6, 4,
937 adc_mux_text);
938
939 static const struct soc_enum tx_dmic_mux0_enum =
940 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 3, 11,
941 dmic_mux_text);
942
943 static const struct soc_enum tx_dmic_mux1_enum =
944 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 3, 11,
945 dmic_mux_text);
946
947 static const struct soc_enum tx_dmic_mux2_enum =
948 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 3, 11,
949 dmic_mux_text);
950
951 static const struct soc_enum tx_dmic_mux3_enum =
952 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 3, 11,
953 dmic_mux_text);
954
955 static const struct soc_enum tx_dmic_mux4_enum =
956 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 3, 7,
957 dmic_mux_alt_text);
958
959 static const struct soc_enum tx_dmic_mux5_enum =
960 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 3, 7,
961 dmic_mux_alt_text);
962
963 static const struct soc_enum tx_dmic_mux6_enum =
964 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 3, 7,
965 dmic_mux_alt_text);
966
967 static const struct soc_enum tx_dmic_mux7_enum =
968 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 3, 7,
969 dmic_mux_alt_text);
970
971 static const struct soc_enum tx_dmic_mux8_enum =
972 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 3, 7,
973 dmic_mux_alt_text);
974
975 static const struct soc_enum tx_amic_mux0_enum =
976 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0, 7,
977 amic_mux_text);
978
979 static const struct soc_enum tx_amic_mux1_enum =
980 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0, 7,
981 amic_mux_text);
982
983 static const struct soc_enum tx_amic_mux2_enum =
984 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0, 7,
985 amic_mux_text);
986
987 static const struct soc_enum tx_amic_mux3_enum =
988 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0, 7,
989 amic_mux_text);
990
991 static const struct soc_enum tx_amic_mux4_enum =
992 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0, 7,
993 amic_mux_text);
994
995 static const struct soc_enum tx_amic_mux5_enum =
996 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0, 7,
997 amic_mux_text);
998
999 static const struct soc_enum tx_amic_mux6_enum =
1000 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0, 7,
1001 amic_mux_text);
1002
1003 static const struct soc_enum tx_amic_mux7_enum =
1004 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0, 7,
1005 amic_mux_text);
1006
1007 static const struct soc_enum tx_amic_mux8_enum =
1008 SOC_ENUM_SINGLE(WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0, 0, 7,
1009 amic_mux_text);
1010
1011 static const struct soc_enum sb_tx0_mux_enum =
1012 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 0, 4,
1013 sb_tx0_mux_text);
1014
1015 static const struct soc_enum sb_tx1_mux_enum =
1016 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 2, 4,
1017 sb_tx1_mux_text);
1018
1019 static const struct soc_enum sb_tx2_mux_enum =
1020 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 4, 4,
1021 sb_tx2_mux_text);
1022
1023 static const struct soc_enum sb_tx3_mux_enum =
1024 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0, 6, 4,
1025 sb_tx3_mux_text);
1026
1027 static const struct soc_enum sb_tx4_mux_enum =
1028 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 0, 4,
1029 sb_tx4_mux_text);
1030
1031 static const struct soc_enum sb_tx5_mux_enum =
1032 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 2, 4,
1033 sb_tx5_mux_text);
1034
1035 static const struct soc_enum sb_tx6_mux_enum =
1036 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 4, 4,
1037 sb_tx6_mux_text);
1038
1039 static const struct soc_enum sb_tx7_mux_enum =
1040 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1, 6, 4,
1041 sb_tx7_mux_text);
1042
1043 static const struct soc_enum sb_tx8_mux_enum =
1044 SOC_ENUM_SINGLE(WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2, 0, 4,
1045 sb_tx8_mux_text);
1046
1047 static const struct snd_kcontrol_new rx_int0_2_mux =
1048 SOC_DAPM_ENUM("RX INT0_2 MUX Mux", rx_int0_2_mux_chain_enum);
1049
1050 static const struct snd_kcontrol_new rx_int1_2_mux =
1051 SOC_DAPM_ENUM("RX INT1_2 MUX Mux", rx_int1_2_mux_chain_enum);
1052
1053 static const struct snd_kcontrol_new rx_int2_2_mux =
1054 SOC_DAPM_ENUM("RX INT2_2 MUX Mux", rx_int2_2_mux_chain_enum);
1055
1056 static const struct snd_kcontrol_new rx_int3_2_mux =
1057 SOC_DAPM_ENUM("RX INT3_2 MUX Mux", rx_int3_2_mux_chain_enum);
1058
1059 static const struct snd_kcontrol_new rx_int4_2_mux =
1060 SOC_DAPM_ENUM("RX INT4_2 MUX Mux", rx_int4_2_mux_chain_enum);
1061
1062 static const struct snd_kcontrol_new rx_int5_2_mux =
1063 SOC_DAPM_ENUM("RX INT5_2 MUX Mux", rx_int5_2_mux_chain_enum);
1064
1065 static const struct snd_kcontrol_new rx_int6_2_mux =
1066 SOC_DAPM_ENUM("RX INT6_2 MUX Mux", rx_int6_2_mux_chain_enum);
1067
1068 static const struct snd_kcontrol_new rx_int7_2_mux =
1069 SOC_DAPM_ENUM("RX INT7_2 MUX Mux", rx_int7_2_mux_chain_enum);
1070
1071 static const struct snd_kcontrol_new rx_int8_2_mux =
1072 SOC_DAPM_ENUM("RX INT8_2 MUX Mux", rx_int8_2_mux_chain_enum);
1073
1074 static const struct snd_kcontrol_new rx_int0_1_mix_inp0_mux =
1075 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP0 Mux", rx_int0_1_mix_inp0_chain_enum);
1076
1077 static const struct snd_kcontrol_new rx_int0_1_mix_inp1_mux =
1078 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP1 Mux", rx_int0_1_mix_inp1_chain_enum);
1079
1080 static const struct snd_kcontrol_new rx_int0_1_mix_inp2_mux =
1081 SOC_DAPM_ENUM("RX INT0_1 MIX1 INP2 Mux", rx_int0_1_mix_inp2_chain_enum);
1082
1083 static const struct snd_kcontrol_new rx_int1_1_mix_inp0_mux =
1084 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP0 Mux", rx_int1_1_mix_inp0_chain_enum);
1085
1086 static const struct snd_kcontrol_new rx_int1_1_mix_inp1_mux =
1087 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP1 Mux", rx_int1_1_mix_inp1_chain_enum);
1088
1089 static const struct snd_kcontrol_new rx_int1_1_mix_inp2_mux =
1090 SOC_DAPM_ENUM("RX INT1_1 MIX1 INP2 Mux", rx_int1_1_mix_inp2_chain_enum);
1091
1092 static const struct snd_kcontrol_new rx_int2_1_mix_inp0_mux =
1093 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP0 Mux", rx_int2_1_mix_inp0_chain_enum);
1094
1095 static const struct snd_kcontrol_new rx_int2_1_mix_inp1_mux =
1096 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP1 Mux", rx_int2_1_mix_inp1_chain_enum);
1097
1098 static const struct snd_kcontrol_new rx_int2_1_mix_inp2_mux =
1099 SOC_DAPM_ENUM("RX INT2_1 MIX1 INP2 Mux", rx_int2_1_mix_inp2_chain_enum);
1100
1101 static const struct snd_kcontrol_new rx_int3_1_mix_inp0_mux =
1102 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP0 Mux", rx_int3_1_mix_inp0_chain_enum);
1103
1104 static const struct snd_kcontrol_new rx_int3_1_mix_inp1_mux =
1105 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP1 Mux", rx_int3_1_mix_inp1_chain_enum);
1106
1107 static const struct snd_kcontrol_new rx_int3_1_mix_inp2_mux =
1108 SOC_DAPM_ENUM("RX INT3_1 MIX1 INP2 Mux", rx_int3_1_mix_inp2_chain_enum);
1109
1110 static const struct snd_kcontrol_new rx_int4_1_mix_inp0_mux =
1111 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP0 Mux", rx_int4_1_mix_inp0_chain_enum);
1112
1113 static const struct snd_kcontrol_new rx_int4_1_mix_inp1_mux =
1114 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP1 Mux", rx_int4_1_mix_inp1_chain_enum);
1115
1116 static const struct snd_kcontrol_new rx_int4_1_mix_inp2_mux =
1117 SOC_DAPM_ENUM("RX INT4_1 MIX1 INP2 Mux", rx_int4_1_mix_inp2_chain_enum);
1118
1119 static const struct snd_kcontrol_new rx_int5_1_mix_inp0_mux =
1120 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP0 Mux", rx_int5_1_mix_inp0_chain_enum);
1121
1122 static const struct snd_kcontrol_new rx_int5_1_mix_inp1_mux =
1123 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP1 Mux", rx_int5_1_mix_inp1_chain_enum);
1124
1125 static const struct snd_kcontrol_new rx_int5_1_mix_inp2_mux =
1126 SOC_DAPM_ENUM("RX INT5_1 MIX1 INP2 Mux", rx_int5_1_mix_inp2_chain_enum);
1127
1128 static const struct snd_kcontrol_new rx_int6_1_mix_inp0_mux =
1129 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP0 Mux", rx_int6_1_mix_inp0_chain_enum);
1130
1131 static const struct snd_kcontrol_new rx_int6_1_mix_inp1_mux =
1132 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP1 Mux", rx_int6_1_mix_inp1_chain_enum);
1133
1134 static const struct snd_kcontrol_new rx_int6_1_mix_inp2_mux =
1135 SOC_DAPM_ENUM("RX INT6_1 MIX1 INP2 Mux", rx_int6_1_mix_inp2_chain_enum);
1136
1137 static const struct snd_kcontrol_new rx_int7_1_mix_inp0_mux =
1138 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP0 Mux", rx_int7_1_mix_inp0_chain_enum);
1139
1140 static const struct snd_kcontrol_new rx_int7_1_mix_inp1_mux =
1141 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP1 Mux", rx_int7_1_mix_inp1_chain_enum);
1142
1143 static const struct snd_kcontrol_new rx_int7_1_mix_inp2_mux =
1144 SOC_DAPM_ENUM("RX INT7_1 MIX1 INP2 Mux", rx_int7_1_mix_inp2_chain_enum);
1145
1146 static const struct snd_kcontrol_new rx_int8_1_mix_inp0_mux =
1147 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP0 Mux", rx_int8_1_mix_inp0_chain_enum);
1148
1149 static const struct snd_kcontrol_new rx_int8_1_mix_inp1_mux =
1150 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP1 Mux", rx_int8_1_mix_inp1_chain_enum);
1151
1152 static const struct snd_kcontrol_new rx_int8_1_mix_inp2_mux =
1153 SOC_DAPM_ENUM("RX INT8_1 MIX1 INP2 Mux", rx_int8_1_mix_inp2_chain_enum);
1154
1155 static const struct snd_kcontrol_new rx_int0_interp_mux =
1156 SOC_DAPM_ENUM("RX INT0 INTERP Mux", rx_int0_interp_mux_enum);
1157
1158 static const struct snd_kcontrol_new rx_int1_interp_mux =
1159 SOC_DAPM_ENUM("RX INT1 INTERP Mux", rx_int1_interp_mux_enum);
1160
1161 static const struct snd_kcontrol_new rx_int2_interp_mux =
1162 SOC_DAPM_ENUM("RX INT2 INTERP Mux", rx_int2_interp_mux_enum);
1163
1164 static const struct snd_kcontrol_new rx_int3_interp_mux =
1165 SOC_DAPM_ENUM("RX INT3 INTERP Mux", rx_int3_interp_mux_enum);
1166
1167 static const struct snd_kcontrol_new rx_int4_interp_mux =
1168 SOC_DAPM_ENUM("RX INT4 INTERP Mux", rx_int4_interp_mux_enum);
1169
1170 static const struct snd_kcontrol_new rx_int5_interp_mux =
1171 SOC_DAPM_ENUM("RX INT5 INTERP Mux", rx_int5_interp_mux_enum);
1172
1173 static const struct snd_kcontrol_new rx_int6_interp_mux =
1174 SOC_DAPM_ENUM("RX INT6 INTERP Mux", rx_int6_interp_mux_enum);
1175
1176 static const struct snd_kcontrol_new rx_int7_interp_mux =
1177 SOC_DAPM_ENUM("RX INT7 INTERP Mux", rx_int7_interp_mux_enum);
1178
1179 static const struct snd_kcontrol_new rx_int8_interp_mux =
1180 SOC_DAPM_ENUM("RX INT8 INTERP Mux", rx_int8_interp_mux_enum);
1181
1182 static const struct snd_kcontrol_new tx_dmic_mux0 =
1183 SOC_DAPM_ENUM("DMIC MUX0 Mux", tx_dmic_mux0_enum);
1184
1185 static const struct snd_kcontrol_new tx_dmic_mux1 =
1186 SOC_DAPM_ENUM("DMIC MUX1 Mux", tx_dmic_mux1_enum);
1187
1188 static const struct snd_kcontrol_new tx_dmic_mux2 =
1189 SOC_DAPM_ENUM("DMIC MUX2 Mux", tx_dmic_mux2_enum);
1190
1191 static const struct snd_kcontrol_new tx_dmic_mux3 =
1192 SOC_DAPM_ENUM("DMIC MUX3 Mux", tx_dmic_mux3_enum);
1193
1194 static const struct snd_kcontrol_new tx_dmic_mux4 =
1195 SOC_DAPM_ENUM("DMIC MUX4 Mux", tx_dmic_mux4_enum);
1196
1197 static const struct snd_kcontrol_new tx_dmic_mux5 =
1198 SOC_DAPM_ENUM("DMIC MUX5 Mux", tx_dmic_mux5_enum);
1199
1200 static const struct snd_kcontrol_new tx_dmic_mux6 =
1201 SOC_DAPM_ENUM("DMIC MUX6 Mux", tx_dmic_mux6_enum);
1202
1203 static const struct snd_kcontrol_new tx_dmic_mux7 =
1204 SOC_DAPM_ENUM("DMIC MUX7 Mux", tx_dmic_mux7_enum);
1205
1206 static const struct snd_kcontrol_new tx_dmic_mux8 =
1207 SOC_DAPM_ENUM("DMIC MUX8 Mux", tx_dmic_mux8_enum);
1208
1209 static const struct snd_kcontrol_new tx_amic_mux0 =
1210 SOC_DAPM_ENUM("AMIC MUX0 Mux", tx_amic_mux0_enum);
1211
1212 static const struct snd_kcontrol_new tx_amic_mux1 =
1213 SOC_DAPM_ENUM("AMIC MUX1 Mux", tx_amic_mux1_enum);
1214
1215 static const struct snd_kcontrol_new tx_amic_mux2 =
1216 SOC_DAPM_ENUM("AMIC MUX2 Mux", tx_amic_mux2_enum);
1217
1218 static const struct snd_kcontrol_new tx_amic_mux3 =
1219 SOC_DAPM_ENUM("AMIC MUX3 Mux", tx_amic_mux3_enum);
1220
1221 static const struct snd_kcontrol_new tx_amic_mux4 =
1222 SOC_DAPM_ENUM("AMIC MUX4 Mux", tx_amic_mux4_enum);
1223
1224 static const struct snd_kcontrol_new tx_amic_mux5 =
1225 SOC_DAPM_ENUM("AMIC MUX5 Mux", tx_amic_mux5_enum);
1226
1227 static const struct snd_kcontrol_new tx_amic_mux6 =
1228 SOC_DAPM_ENUM("AMIC MUX6 Mux", tx_amic_mux6_enum);
1229
1230 static const struct snd_kcontrol_new tx_amic_mux7 =
1231 SOC_DAPM_ENUM("AMIC MUX7 Mux", tx_amic_mux7_enum);
1232
1233 static const struct snd_kcontrol_new tx_amic_mux8 =
1234 SOC_DAPM_ENUM("AMIC MUX8 Mux", tx_amic_mux8_enum);
1235
1236 static const struct snd_kcontrol_new sb_tx0_mux =
1237 SOC_DAPM_ENUM("SLIM TX0 MUX Mux", sb_tx0_mux_enum);
1238
1239 static const struct snd_kcontrol_new sb_tx1_mux =
1240 SOC_DAPM_ENUM("SLIM TX1 MUX Mux", sb_tx1_mux_enum);
1241
1242 static const struct snd_kcontrol_new sb_tx2_mux =
1243 SOC_DAPM_ENUM("SLIM TX2 MUX Mux", sb_tx2_mux_enum);
1244
1245 static const struct snd_kcontrol_new sb_tx3_mux =
1246 SOC_DAPM_ENUM("SLIM TX3 MUX Mux", sb_tx3_mux_enum);
1247
1248 static const struct snd_kcontrol_new sb_tx4_mux =
1249 SOC_DAPM_ENUM("SLIM TX4 MUX Mux", sb_tx4_mux_enum);
1250
1251 static const struct snd_kcontrol_new sb_tx5_mux =
1252 SOC_DAPM_ENUM("SLIM TX5 MUX Mux", sb_tx5_mux_enum);
1253
1254 static const struct snd_kcontrol_new sb_tx6_mux =
1255 SOC_DAPM_ENUM("SLIM TX6 MUX Mux", sb_tx6_mux_enum);
1256
1257 static const struct snd_kcontrol_new sb_tx7_mux =
1258 SOC_DAPM_ENUM("SLIM TX7 MUX Mux", sb_tx7_mux_enum);
1259
1260 static const struct snd_kcontrol_new sb_tx8_mux =
1261 SOC_DAPM_ENUM("SLIM TX8 MUX Mux", sb_tx8_mux_enum);
1262
slim_rx_mux_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1263 static int slim_rx_mux_get(struct snd_kcontrol *kc,
1264 struct snd_ctl_elem_value *ucontrol)
1265 {
1266 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1267 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1268 u32 port_id = w->shift;
1269
1270 ucontrol->value.enumerated.item[0] = wcd->rx_port_value[port_id];
1271
1272 return 0;
1273 }
1274
slim_rx_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1275 static int slim_rx_mux_put(struct snd_kcontrol *kc,
1276 struct snd_ctl_elem_value *ucontrol)
1277 {
1278 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kc);
1279 struct wcd9335_codec *wcd = dev_get_drvdata(w->dapm->dev);
1280 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1281 struct snd_soc_dapm_update *update = NULL;
1282 u32 port_id = w->shift;
1283
1284 if (wcd->rx_port_value[port_id] == ucontrol->value.enumerated.item[0])
1285 return 0;
1286
1287 wcd->rx_port_value[port_id] = ucontrol->value.enumerated.item[0];
1288
1289 /* Remove channel from any list it's in before adding it to a new one */
1290 list_del_init(&wcd->rx_chs[port_id].list);
1291
1292 switch (wcd->rx_port_value[port_id]) {
1293 case 0:
1294 /* Channel already removed from lists. Nothing to do here */
1295 break;
1296 case 1:
1297 list_add_tail(&wcd->rx_chs[port_id].list,
1298 &wcd->dai[AIF1_PB].slim_ch_list);
1299 break;
1300 case 2:
1301 list_add_tail(&wcd->rx_chs[port_id].list,
1302 &wcd->dai[AIF2_PB].slim_ch_list);
1303 break;
1304 case 3:
1305 list_add_tail(&wcd->rx_chs[port_id].list,
1306 &wcd->dai[AIF3_PB].slim_ch_list);
1307 break;
1308 case 4:
1309 list_add_tail(&wcd->rx_chs[port_id].list,
1310 &wcd->dai[AIF4_PB].slim_ch_list);
1311 break;
1312 default:
1313 dev_err(wcd->dev, "Unknown AIF %d\n", wcd->rx_port_value[port_id]);
1314 goto err;
1315 }
1316
1317 snd_soc_dapm_mux_update_power(w->dapm, kc, wcd->rx_port_value[port_id],
1318 e, update);
1319
1320 return 0;
1321 err:
1322 return -EINVAL;
1323 }
1324
slim_tx_mixer_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1325 static int slim_tx_mixer_get(struct snd_kcontrol *kc,
1326 struct snd_ctl_elem_value *ucontrol)
1327 {
1328
1329 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1330 struct wcd9335_codec *wcd = dev_get_drvdata(dapm->dev);
1331 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1332 struct soc_mixer_control *mixer =
1333 (struct soc_mixer_control *)kc->private_value;
1334 int dai_id = widget->shift;
1335 int port_id = mixer->shift;
1336
1337 ucontrol->value.integer.value[0] = wcd->tx_port_value[port_id] == dai_id;
1338
1339 return 0;
1340 }
1341
slim_tx_mixer_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1342 static int slim_tx_mixer_put(struct snd_kcontrol *kc,
1343 struct snd_ctl_elem_value *ucontrol)
1344 {
1345
1346 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kc);
1347 struct wcd9335_codec *wcd = dev_get_drvdata(widget->dapm->dev);
1348 struct snd_soc_dapm_update *update = NULL;
1349 struct soc_mixer_control *mixer =
1350 (struct soc_mixer_control *)kc->private_value;
1351 int enable = ucontrol->value.integer.value[0];
1352 int dai_id = widget->shift;
1353 int port_id = mixer->shift;
1354
1355 switch (dai_id) {
1356 case AIF1_CAP:
1357 case AIF2_CAP:
1358 case AIF3_CAP:
1359 /* only add to the list if value not set */
1360 if (enable && wcd->tx_port_value[port_id] != dai_id) {
1361 wcd->tx_port_value[port_id] = dai_id;
1362 list_add_tail(&wcd->tx_chs[port_id].list,
1363 &wcd->dai[dai_id].slim_ch_list);
1364 } else if (!enable && wcd->tx_port_value[port_id] == dai_id) {
1365 wcd->tx_port_value[port_id] = -1;
1366 list_del_init(&wcd->tx_chs[port_id].list);
1367 }
1368 break;
1369 default:
1370 dev_err(wcd->dev, "Unknown AIF %d\n", dai_id);
1371 return -EINVAL;
1372 }
1373
1374 snd_soc_dapm_mixer_update_power(widget->dapm, kc, enable, update);
1375
1376 return 0;
1377 }
1378
1379 static const struct snd_kcontrol_new slim_rx_mux[WCD9335_RX_MAX] = {
1380 SOC_DAPM_ENUM_EXT("SLIM RX0 Mux", slim_rx_mux_enum,
1381 slim_rx_mux_get, slim_rx_mux_put),
1382 SOC_DAPM_ENUM_EXT("SLIM RX1 Mux", slim_rx_mux_enum,
1383 slim_rx_mux_get, slim_rx_mux_put),
1384 SOC_DAPM_ENUM_EXT("SLIM RX2 Mux", slim_rx_mux_enum,
1385 slim_rx_mux_get, slim_rx_mux_put),
1386 SOC_DAPM_ENUM_EXT("SLIM RX3 Mux", slim_rx_mux_enum,
1387 slim_rx_mux_get, slim_rx_mux_put),
1388 SOC_DAPM_ENUM_EXT("SLIM RX4 Mux", slim_rx_mux_enum,
1389 slim_rx_mux_get, slim_rx_mux_put),
1390 SOC_DAPM_ENUM_EXT("SLIM RX5 Mux", slim_rx_mux_enum,
1391 slim_rx_mux_get, slim_rx_mux_put),
1392 SOC_DAPM_ENUM_EXT("SLIM RX6 Mux", slim_rx_mux_enum,
1393 slim_rx_mux_get, slim_rx_mux_put),
1394 SOC_DAPM_ENUM_EXT("SLIM RX7 Mux", slim_rx_mux_enum,
1395 slim_rx_mux_get, slim_rx_mux_put),
1396 };
1397
1398 static const struct snd_kcontrol_new aif1_cap_mixer[] = {
1399 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1400 slim_tx_mixer_get, slim_tx_mixer_put),
1401 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1402 slim_tx_mixer_get, slim_tx_mixer_put),
1403 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1404 slim_tx_mixer_get, slim_tx_mixer_put),
1405 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1406 slim_tx_mixer_get, slim_tx_mixer_put),
1407 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1408 slim_tx_mixer_get, slim_tx_mixer_put),
1409 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1410 slim_tx_mixer_get, slim_tx_mixer_put),
1411 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1412 slim_tx_mixer_get, slim_tx_mixer_put),
1413 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1414 slim_tx_mixer_get, slim_tx_mixer_put),
1415 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1416 slim_tx_mixer_get, slim_tx_mixer_put),
1417 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1418 slim_tx_mixer_get, slim_tx_mixer_put),
1419 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1420 slim_tx_mixer_get, slim_tx_mixer_put),
1421 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1422 slim_tx_mixer_get, slim_tx_mixer_put),
1423 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1424 slim_tx_mixer_get, slim_tx_mixer_put),
1425 };
1426
1427 static const struct snd_kcontrol_new aif2_cap_mixer[] = {
1428 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1429 slim_tx_mixer_get, slim_tx_mixer_put),
1430 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1431 slim_tx_mixer_get, slim_tx_mixer_put),
1432 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1433 slim_tx_mixer_get, slim_tx_mixer_put),
1434 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1435 slim_tx_mixer_get, slim_tx_mixer_put),
1436 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1437 slim_tx_mixer_get, slim_tx_mixer_put),
1438 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1439 slim_tx_mixer_get, slim_tx_mixer_put),
1440 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1441 slim_tx_mixer_get, slim_tx_mixer_put),
1442 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1443 slim_tx_mixer_get, slim_tx_mixer_put),
1444 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1445 slim_tx_mixer_get, slim_tx_mixer_put),
1446 SOC_SINGLE_EXT("SLIM TX9", SND_SOC_NOPM, WCD9335_TX9, 1, 0,
1447 slim_tx_mixer_get, slim_tx_mixer_put),
1448 SOC_SINGLE_EXT("SLIM TX10", SND_SOC_NOPM, WCD9335_TX10, 1, 0,
1449 slim_tx_mixer_get, slim_tx_mixer_put),
1450 SOC_SINGLE_EXT("SLIM TX11", SND_SOC_NOPM, WCD9335_TX11, 1, 0,
1451 slim_tx_mixer_get, slim_tx_mixer_put),
1452 SOC_SINGLE_EXT("SLIM TX13", SND_SOC_NOPM, WCD9335_TX13, 1, 0,
1453 slim_tx_mixer_get, slim_tx_mixer_put),
1454 };
1455
1456 static const struct snd_kcontrol_new aif3_cap_mixer[] = {
1457 SOC_SINGLE_EXT("SLIM TX0", SND_SOC_NOPM, WCD9335_TX0, 1, 0,
1458 slim_tx_mixer_get, slim_tx_mixer_put),
1459 SOC_SINGLE_EXT("SLIM TX1", SND_SOC_NOPM, WCD9335_TX1, 1, 0,
1460 slim_tx_mixer_get, slim_tx_mixer_put),
1461 SOC_SINGLE_EXT("SLIM TX2", SND_SOC_NOPM, WCD9335_TX2, 1, 0,
1462 slim_tx_mixer_get, slim_tx_mixer_put),
1463 SOC_SINGLE_EXT("SLIM TX3", SND_SOC_NOPM, WCD9335_TX3, 1, 0,
1464 slim_tx_mixer_get, slim_tx_mixer_put),
1465 SOC_SINGLE_EXT("SLIM TX4", SND_SOC_NOPM, WCD9335_TX4, 1, 0,
1466 slim_tx_mixer_get, slim_tx_mixer_put),
1467 SOC_SINGLE_EXT("SLIM TX5", SND_SOC_NOPM, WCD9335_TX5, 1, 0,
1468 slim_tx_mixer_get, slim_tx_mixer_put),
1469 SOC_SINGLE_EXT("SLIM TX6", SND_SOC_NOPM, WCD9335_TX6, 1, 0,
1470 slim_tx_mixer_get, slim_tx_mixer_put),
1471 SOC_SINGLE_EXT("SLIM TX7", SND_SOC_NOPM, WCD9335_TX7, 1, 0,
1472 slim_tx_mixer_get, slim_tx_mixer_put),
1473 SOC_SINGLE_EXT("SLIM TX8", SND_SOC_NOPM, WCD9335_TX8, 1, 0,
1474 slim_tx_mixer_get, slim_tx_mixer_put),
1475 };
1476
wcd9335_put_dec_enum(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1477 static int wcd9335_put_dec_enum(struct snd_kcontrol *kc,
1478 struct snd_ctl_elem_value *ucontrol)
1479 {
1480 struct snd_soc_dapm_context *dapm = snd_soc_dapm_kcontrol_dapm(kc);
1481 struct snd_soc_component *component = snd_soc_dapm_to_component(dapm);
1482 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1483 unsigned int val, reg, sel;
1484
1485 val = ucontrol->value.enumerated.item[0];
1486
1487 switch (e->reg) {
1488 case WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1:
1489 reg = WCD9335_CDC_TX0_TX_PATH_CFG0;
1490 break;
1491 case WCD9335_CDC_TX_INP_MUX_ADC_MUX1_CFG1:
1492 reg = WCD9335_CDC_TX1_TX_PATH_CFG0;
1493 break;
1494 case WCD9335_CDC_TX_INP_MUX_ADC_MUX2_CFG1:
1495 reg = WCD9335_CDC_TX2_TX_PATH_CFG0;
1496 break;
1497 case WCD9335_CDC_TX_INP_MUX_ADC_MUX3_CFG1:
1498 reg = WCD9335_CDC_TX3_TX_PATH_CFG0;
1499 break;
1500 case WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0:
1501 reg = WCD9335_CDC_TX4_TX_PATH_CFG0;
1502 break;
1503 case WCD9335_CDC_TX_INP_MUX_ADC_MUX5_CFG0:
1504 reg = WCD9335_CDC_TX5_TX_PATH_CFG0;
1505 break;
1506 case WCD9335_CDC_TX_INP_MUX_ADC_MUX6_CFG0:
1507 reg = WCD9335_CDC_TX6_TX_PATH_CFG0;
1508 break;
1509 case WCD9335_CDC_TX_INP_MUX_ADC_MUX7_CFG0:
1510 reg = WCD9335_CDC_TX7_TX_PATH_CFG0;
1511 break;
1512 case WCD9335_CDC_TX_INP_MUX_ADC_MUX8_CFG0:
1513 reg = WCD9335_CDC_TX8_TX_PATH_CFG0;
1514 break;
1515 default:
1516 return -EINVAL;
1517 }
1518
1519 /* AMIC: 0, DMIC: 1 */
1520 sel = val ? WCD9335_CDC_TX_ADC_AMIC_SEL : WCD9335_CDC_TX_ADC_DMIC_SEL;
1521 snd_soc_component_update_bits(component, reg,
1522 WCD9335_CDC_TX_ADC_AMIC_DMIC_SEL_MASK,
1523 sel);
1524
1525 return snd_soc_dapm_put_enum_double(kc, ucontrol);
1526 }
1527
wcd9335_int_dem_inp_mux_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)1528 static int wcd9335_int_dem_inp_mux_put(struct snd_kcontrol *kc,
1529 struct snd_ctl_elem_value *ucontrol)
1530 {
1531 struct soc_enum *e = (struct soc_enum *)kc->private_value;
1532 struct snd_soc_component *component;
1533 int reg, val;
1534
1535 component = snd_soc_dapm_kcontrol_component(kc);
1536 val = ucontrol->value.enumerated.item[0];
1537
1538 if (e->reg == WCD9335_CDC_RX0_RX_PATH_SEC0)
1539 reg = WCD9335_CDC_RX0_RX_PATH_CFG0;
1540 else if (e->reg == WCD9335_CDC_RX1_RX_PATH_SEC0)
1541 reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
1542 else if (e->reg == WCD9335_CDC_RX2_RX_PATH_SEC0)
1543 reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
1544 else
1545 return -EINVAL;
1546
1547 /* Set Look Ahead Delay */
1548 snd_soc_component_update_bits(component, reg,
1549 WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN_MASK,
1550 val ? WCD9335_CDC_RX_PATH_CFG0_DLY_ZN_EN : 0);
1551 /* Set DEM INP Select */
1552 return snd_soc_dapm_put_enum_double(kc, ucontrol);
1553 }
1554
1555 static const struct snd_kcontrol_new rx_int0_dem_inp_mux =
1556 SOC_DAPM_ENUM_EXT("RX INT0 DEM MUX Mux", rx_int0_dem_inp_mux_enum,
1557 snd_soc_dapm_get_enum_double,
1558 wcd9335_int_dem_inp_mux_put);
1559
1560 static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
1561 SOC_DAPM_ENUM_EXT("RX INT1 DEM MUX Mux", rx_int1_dem_inp_mux_enum,
1562 snd_soc_dapm_get_enum_double,
1563 wcd9335_int_dem_inp_mux_put);
1564
1565 static const struct snd_kcontrol_new rx_int2_dem_inp_mux =
1566 SOC_DAPM_ENUM_EXT("RX INT2 DEM MUX Mux", rx_int2_dem_inp_mux_enum,
1567 snd_soc_dapm_get_enum_double,
1568 wcd9335_int_dem_inp_mux_put);
1569
1570 static const struct snd_kcontrol_new tx_adc_mux0 =
1571 SOC_DAPM_ENUM_EXT("ADC MUX0 Mux", tx_adc_mux0_chain_enum,
1572 snd_soc_dapm_get_enum_double,
1573 wcd9335_put_dec_enum);
1574
1575 static const struct snd_kcontrol_new tx_adc_mux1 =
1576 SOC_DAPM_ENUM_EXT("ADC MUX1 Mux", tx_adc_mux1_chain_enum,
1577 snd_soc_dapm_get_enum_double,
1578 wcd9335_put_dec_enum);
1579
1580 static const struct snd_kcontrol_new tx_adc_mux2 =
1581 SOC_DAPM_ENUM_EXT("ADC MUX2 Mux", tx_adc_mux2_chain_enum,
1582 snd_soc_dapm_get_enum_double,
1583 wcd9335_put_dec_enum);
1584
1585 static const struct snd_kcontrol_new tx_adc_mux3 =
1586 SOC_DAPM_ENUM_EXT("ADC MUX3 Mux", tx_adc_mux3_chain_enum,
1587 snd_soc_dapm_get_enum_double,
1588 wcd9335_put_dec_enum);
1589
1590 static const struct snd_kcontrol_new tx_adc_mux4 =
1591 SOC_DAPM_ENUM_EXT("ADC MUX4 Mux", tx_adc_mux4_chain_enum,
1592 snd_soc_dapm_get_enum_double,
1593 wcd9335_put_dec_enum);
1594
1595 static const struct snd_kcontrol_new tx_adc_mux5 =
1596 SOC_DAPM_ENUM_EXT("ADC MUX5 Mux", tx_adc_mux5_chain_enum,
1597 snd_soc_dapm_get_enum_double,
1598 wcd9335_put_dec_enum);
1599
1600 static const struct snd_kcontrol_new tx_adc_mux6 =
1601 SOC_DAPM_ENUM_EXT("ADC MUX6 Mux", tx_adc_mux6_chain_enum,
1602 snd_soc_dapm_get_enum_double,
1603 wcd9335_put_dec_enum);
1604
1605 static const struct snd_kcontrol_new tx_adc_mux7 =
1606 SOC_DAPM_ENUM_EXT("ADC MUX7 Mux", tx_adc_mux7_chain_enum,
1607 snd_soc_dapm_get_enum_double,
1608 wcd9335_put_dec_enum);
1609
1610 static const struct snd_kcontrol_new tx_adc_mux8 =
1611 SOC_DAPM_ENUM_EXT("ADC MUX8 Mux", tx_adc_mux8_chain_enum,
1612 snd_soc_dapm_get_enum_double,
1613 wcd9335_put_dec_enum);
1614
wcd9335_set_mix_interpolator_rate(struct snd_soc_dai * dai,int rate_val,u32 rate)1615 static int wcd9335_set_mix_interpolator_rate(struct snd_soc_dai *dai,
1616 int rate_val,
1617 u32 rate)
1618 {
1619 struct snd_soc_component *component = dai->component;
1620 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
1621 struct wcd9335_slim_ch *ch;
1622 int val, j;
1623
1624 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1625 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1626 val = snd_soc_component_read(component,
1627 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j)) &
1628 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1629
1630 if (val == (ch->shift + INTn_2_INP_SEL_RX0))
1631 snd_soc_component_update_bits(component,
1632 WCD9335_CDC_RX_PATH_MIX_CTL(j),
1633 WCD9335_CDC_MIX_PCM_RATE_MASK,
1634 rate_val);
1635 }
1636 }
1637
1638 return 0;
1639 }
1640
wcd9335_set_prim_interpolator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1641 static int wcd9335_set_prim_interpolator_rate(struct snd_soc_dai *dai,
1642 u8 rate_val,
1643 u32 rate)
1644 {
1645 struct snd_soc_component *comp = dai->component;
1646 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
1647 struct wcd9335_slim_ch *ch;
1648 u8 cfg0, cfg1, inp0_sel, inp1_sel, inp2_sel;
1649 int inp, j;
1650
1651 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1652 inp = ch->shift + INTn_1_MIX_INP_SEL_RX0;
1653 /*
1654 * Loop through all interpolator MUX inputs and find out
1655 * to which interpolator input, the slim rx port
1656 * is connected
1657 */
1658 for (j = 0; j < WCD9335_NUM_INTERPOLATORS; j++) {
1659 cfg0 = snd_soc_component_read(comp,
1660 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG0(j));
1661 cfg1 = snd_soc_component_read(comp,
1662 WCD9335_CDC_RX_INP_MUX_RX_INT_CFG1(j));
1663
1664 inp0_sel = cfg0 &
1665 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1666 inp1_sel = (cfg0 >> 4) &
1667 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1668 inp2_sel = (cfg1 >> 4) &
1669 WCD9335_CDC_RX_INP_MUX_RX_INT_SEL_MASK;
1670
1671 if ((inp0_sel == inp) || (inp1_sel == inp) ||
1672 (inp2_sel == inp)) {
1673 /* rate is in Hz */
1674 if ((j == 0) && (rate == 44100))
1675 dev_info(wcd->dev,
1676 "Cannot set 44.1KHz on INT0\n");
1677 else
1678 snd_soc_component_update_bits(comp,
1679 WCD9335_CDC_RX_PATH_CTL(j),
1680 WCD9335_CDC_MIX_PCM_RATE_MASK,
1681 rate_val);
1682 }
1683 }
1684 }
1685
1686 return 0;
1687 }
1688
wcd9335_set_interpolator_rate(struct snd_soc_dai * dai,u32 rate)1689 static int wcd9335_set_interpolator_rate(struct snd_soc_dai *dai, u32 rate)
1690 {
1691 int i;
1692
1693 /* set mixing path rate */
1694 for (i = 0; i < ARRAY_SIZE(int_mix_rate_val); i++) {
1695 if (rate == int_mix_rate_val[i].rate) {
1696 wcd9335_set_mix_interpolator_rate(dai,
1697 int_mix_rate_val[i].rate_val, rate);
1698 break;
1699 }
1700 }
1701
1702 /* set primary path sample rate */
1703 for (i = 0; i < ARRAY_SIZE(int_prim_rate_val); i++) {
1704 if (rate == int_prim_rate_val[i].rate) {
1705 wcd9335_set_prim_interpolator_rate(dai,
1706 int_prim_rate_val[i].rate_val, rate);
1707 break;
1708 }
1709 }
1710
1711 return 0;
1712 }
1713
wcd9335_slim_set_hw_params(struct wcd9335_codec * wcd,struct wcd_slim_codec_dai_data * dai_data,int direction)1714 static int wcd9335_slim_set_hw_params(struct wcd9335_codec *wcd,
1715 struct wcd_slim_codec_dai_data *dai_data,
1716 int direction)
1717 {
1718 struct list_head *slim_ch_list = &dai_data->slim_ch_list;
1719 struct slim_stream_config *cfg = &dai_data->sconfig;
1720 struct wcd9335_slim_ch *ch;
1721 u16 payload = 0;
1722 int ret, i;
1723
1724 cfg->ch_count = 0;
1725 cfg->direction = direction;
1726 cfg->port_mask = 0;
1727
1728 /* Configure slave interface device */
1729 list_for_each_entry(ch, slim_ch_list, list) {
1730 cfg->ch_count++;
1731 payload |= 1 << ch->shift;
1732 cfg->port_mask |= BIT(ch->port);
1733 }
1734
1735 cfg->chs = kcalloc(cfg->ch_count, sizeof(unsigned int), GFP_KERNEL);
1736 if (!cfg->chs)
1737 return -ENOMEM;
1738
1739 i = 0;
1740 list_for_each_entry(ch, slim_ch_list, list) {
1741 cfg->chs[i++] = ch->ch_num;
1742 if (direction == SNDRV_PCM_STREAM_PLAYBACK) {
1743 /* write to interface device */
1744 ret = regmap_write(wcd->if_regmap,
1745 WCD9335_SLIM_PGD_RX_PORT_MULTI_CHNL_0(ch->port),
1746 payload);
1747
1748 if (ret < 0)
1749 goto err;
1750
1751 /* configure the slave port for water mark and enable*/
1752 ret = regmap_write(wcd->if_regmap,
1753 WCD9335_SLIM_PGD_RX_PORT_CFG(ch->port),
1754 WCD9335_SLIM_WATER_MARK_VAL);
1755 if (ret < 0)
1756 goto err;
1757 } else {
1758 ret = regmap_write(wcd->if_regmap,
1759 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_0(ch->port),
1760 payload & 0x00FF);
1761 if (ret < 0)
1762 goto err;
1763
1764 /* ports 8,9 */
1765 ret = regmap_write(wcd->if_regmap,
1766 WCD9335_SLIM_PGD_TX_PORT_MULTI_CHNL_1(ch->port),
1767 (payload & 0xFF00)>>8);
1768 if (ret < 0)
1769 goto err;
1770
1771 /* configure the slave port for water mark and enable*/
1772 ret = regmap_write(wcd->if_regmap,
1773 WCD9335_SLIM_PGD_TX_PORT_CFG(ch->port),
1774 WCD9335_SLIM_WATER_MARK_VAL);
1775
1776 if (ret < 0)
1777 goto err;
1778 }
1779 }
1780
1781 dai_data->sruntime = slim_stream_allocate(wcd->slim, "WCD9335-SLIM");
1782
1783 return 0;
1784
1785 err:
1786 dev_err(wcd->dev, "Error Setting slim hw params\n");
1787 kfree(cfg->chs);
1788 cfg->chs = NULL;
1789
1790 return ret;
1791 }
1792
wcd9335_set_decimator_rate(struct snd_soc_dai * dai,u8 rate_val,u32 rate)1793 static int wcd9335_set_decimator_rate(struct snd_soc_dai *dai,
1794 u8 rate_val, u32 rate)
1795 {
1796 struct snd_soc_component *comp = dai->component;
1797 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
1798 u8 shift = 0, shift_val = 0, tx_mux_sel;
1799 struct wcd9335_slim_ch *ch;
1800 int tx_port, tx_port_reg;
1801 int decimator = -1;
1802
1803 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list) {
1804 tx_port = ch->port;
1805 if ((tx_port == 12) || (tx_port >= 14)) {
1806 dev_err(wcd->dev, "Invalid SLIM TX%u port DAI ID:%d\n",
1807 tx_port, dai->id);
1808 return -EINVAL;
1809 }
1810 /* Find the SB TX MUX input - which decimator is connected */
1811 if (tx_port < 4) {
1812 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG0;
1813 shift = (tx_port << 1);
1814 shift_val = 0x03;
1815 } else if (tx_port < 8) {
1816 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG1;
1817 shift = ((tx_port - 4) << 1);
1818 shift_val = 0x03;
1819 } else if (tx_port < 11) {
1820 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG2;
1821 shift = ((tx_port - 8) << 1);
1822 shift_val = 0x03;
1823 } else if (tx_port == 11) {
1824 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1825 shift = 0;
1826 shift_val = 0x0F;
1827 } else /* (tx_port == 13) */ {
1828 tx_port_reg = WCD9335_CDC_IF_ROUTER_TX_MUX_CFG3;
1829 shift = 4;
1830 shift_val = 0x03;
1831 }
1832
1833 tx_mux_sel = snd_soc_component_read(comp, tx_port_reg) &
1834 (shift_val << shift);
1835
1836 tx_mux_sel = tx_mux_sel >> shift;
1837 if (tx_port <= 8) {
1838 if ((tx_mux_sel == 0x2) || (tx_mux_sel == 0x3))
1839 decimator = tx_port;
1840 } else if (tx_port <= 10) {
1841 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1842 decimator = ((tx_port == 9) ? 7 : 6);
1843 } else if (tx_port == 11) {
1844 if ((tx_mux_sel >= 1) && (tx_mux_sel < 7))
1845 decimator = tx_mux_sel - 1;
1846 } else if (tx_port == 13) {
1847 if ((tx_mux_sel == 0x1) || (tx_mux_sel == 0x2))
1848 decimator = 5;
1849 }
1850
1851 if (decimator >= 0) {
1852 snd_soc_component_update_bits(comp,
1853 WCD9335_CDC_TX_PATH_CTL(decimator),
1854 WCD9335_CDC_TX_PATH_CTL_PCM_RATE_MASK,
1855 rate_val);
1856 } else if ((tx_port <= 8) && (tx_mux_sel == 0x01)) {
1857 /* Check if the TX Mux input is RX MIX TXn */
1858 dev_err(wcd->dev, "RX_MIX_TX%u going to SLIM TX%u\n",
1859 tx_port, tx_port);
1860 } else {
1861 dev_err(wcd->dev, "ERROR: Invalid decimator: %d\n",
1862 decimator);
1863 return -EINVAL;
1864 }
1865 }
1866
1867 return 0;
1868 }
1869
wcd9335_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1870 static int wcd9335_hw_params(struct snd_pcm_substream *substream,
1871 struct snd_pcm_hw_params *params,
1872 struct snd_soc_dai *dai)
1873 {
1874 struct wcd9335_codec *wcd;
1875 int ret, tx_fs_rate = 0;
1876
1877 wcd = snd_soc_component_get_drvdata(dai->component);
1878
1879 switch (substream->stream) {
1880 case SNDRV_PCM_STREAM_PLAYBACK:
1881 ret = wcd9335_set_interpolator_rate(dai, params_rate(params));
1882 if (ret) {
1883 dev_err(wcd->dev, "cannot set sample rate: %u\n",
1884 params_rate(params));
1885 return ret;
1886 }
1887 switch (params_width(params)) {
1888 case 16 ... 24:
1889 wcd->dai[dai->id].sconfig.bps = params_width(params);
1890 break;
1891 default:
1892 dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1893 __func__, params_width(params));
1894 return -EINVAL;
1895 }
1896 break;
1897
1898 case SNDRV_PCM_STREAM_CAPTURE:
1899 switch (params_rate(params)) {
1900 case 8000:
1901 tx_fs_rate = 0;
1902 break;
1903 case 16000:
1904 tx_fs_rate = 1;
1905 break;
1906 case 32000:
1907 tx_fs_rate = 3;
1908 break;
1909 case 48000:
1910 tx_fs_rate = 4;
1911 break;
1912 case 96000:
1913 tx_fs_rate = 5;
1914 break;
1915 case 192000:
1916 tx_fs_rate = 6;
1917 break;
1918 case 384000:
1919 tx_fs_rate = 7;
1920 break;
1921 default:
1922 dev_err(wcd->dev, "%s: Invalid TX sample rate: %d\n",
1923 __func__, params_rate(params));
1924 return -EINVAL;
1925
1926 }
1927
1928 ret = wcd9335_set_decimator_rate(dai, tx_fs_rate,
1929 params_rate(params));
1930 if (ret < 0) {
1931 dev_err(wcd->dev, "Cannot set TX Decimator rate\n");
1932 return ret;
1933 }
1934 switch (params_width(params)) {
1935 case 16 ... 32:
1936 wcd->dai[dai->id].sconfig.bps = params_width(params);
1937 break;
1938 default:
1939 dev_err(wcd->dev, "%s: Invalid format 0x%x\n",
1940 __func__, params_width(params));
1941 return -EINVAL;
1942 }
1943 break;
1944 default:
1945 dev_err(wcd->dev, "Invalid stream type %d\n",
1946 substream->stream);
1947 return -EINVAL;
1948 }
1949
1950 wcd->dai[dai->id].sconfig.rate = params_rate(params);
1951 wcd9335_slim_set_hw_params(wcd, &wcd->dai[dai->id], substream->stream);
1952
1953 return 0;
1954 }
1955
wcd9335_trigger(struct snd_pcm_substream * substream,int cmd,struct snd_soc_dai * dai)1956 static int wcd9335_trigger(struct snd_pcm_substream *substream, int cmd,
1957 struct snd_soc_dai *dai)
1958 {
1959 struct wcd_slim_codec_dai_data *dai_data;
1960 struct wcd9335_codec *wcd;
1961 struct slim_stream_config *cfg;
1962
1963 wcd = snd_soc_component_get_drvdata(dai->component);
1964
1965 dai_data = &wcd->dai[dai->id];
1966
1967 switch (cmd) {
1968 case SNDRV_PCM_TRIGGER_START:
1969 case SNDRV_PCM_TRIGGER_RESUME:
1970 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1971 cfg = &dai_data->sconfig;
1972 slim_stream_prepare(dai_data->sruntime, cfg);
1973 slim_stream_enable(dai_data->sruntime);
1974 break;
1975 case SNDRV_PCM_TRIGGER_STOP:
1976 case SNDRV_PCM_TRIGGER_SUSPEND:
1977 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1978 slim_stream_disable(dai_data->sruntime);
1979 slim_stream_unprepare(dai_data->sruntime);
1980 break;
1981 default:
1982 break;
1983 }
1984
1985 return 0;
1986 }
1987
wcd9335_set_channel_map(struct snd_soc_dai * dai,unsigned int tx_num,unsigned int * tx_slot,unsigned int rx_num,unsigned int * rx_slot)1988 static int wcd9335_set_channel_map(struct snd_soc_dai *dai,
1989 unsigned int tx_num, unsigned int *tx_slot,
1990 unsigned int rx_num, unsigned int *rx_slot)
1991 {
1992 struct wcd9335_codec *wcd;
1993 int i;
1994
1995 wcd = snd_soc_component_get_drvdata(dai->component);
1996
1997 if (!tx_slot || !rx_slot) {
1998 dev_err(wcd->dev, "Invalid tx_slot=%p, rx_slot=%p\n",
1999 tx_slot, rx_slot);
2000 return -EINVAL;
2001 }
2002
2003 wcd->num_rx_port = rx_num;
2004 for (i = 0; i < rx_num; i++) {
2005 wcd->rx_chs[i].ch_num = rx_slot[i];
2006 INIT_LIST_HEAD(&wcd->rx_chs[i].list);
2007 }
2008
2009 wcd->num_tx_port = tx_num;
2010 for (i = 0; i < tx_num; i++) {
2011 wcd->tx_chs[i].ch_num = tx_slot[i];
2012 INIT_LIST_HEAD(&wcd->tx_chs[i].list);
2013 }
2014
2015 return 0;
2016 }
2017
wcd9335_get_channel_map(struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)2018 static int wcd9335_get_channel_map(struct snd_soc_dai *dai,
2019 unsigned int *tx_num, unsigned int *tx_slot,
2020 unsigned int *rx_num, unsigned int *rx_slot)
2021 {
2022 struct wcd9335_slim_ch *ch;
2023 struct wcd9335_codec *wcd;
2024 int i = 0;
2025
2026 wcd = snd_soc_component_get_drvdata(dai->component);
2027
2028 switch (dai->id) {
2029 case AIF1_PB:
2030 case AIF2_PB:
2031 case AIF3_PB:
2032 case AIF4_PB:
2033 if (!rx_slot || !rx_num) {
2034 dev_err(wcd->dev, "Invalid rx_slot %p or rx_num %p\n",
2035 rx_slot, rx_num);
2036 return -EINVAL;
2037 }
2038
2039 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2040 rx_slot[i++] = ch->ch_num;
2041
2042 *rx_num = i;
2043 break;
2044 case AIF1_CAP:
2045 case AIF2_CAP:
2046 case AIF3_CAP:
2047 if (!tx_slot || !tx_num) {
2048 dev_err(wcd->dev, "Invalid tx_slot %p or tx_num %p\n",
2049 tx_slot, tx_num);
2050 return -EINVAL;
2051 }
2052 list_for_each_entry(ch, &wcd->dai[dai->id].slim_ch_list, list)
2053 tx_slot[i++] = ch->ch_num;
2054
2055 *tx_num = i;
2056 break;
2057 default:
2058 dev_err(wcd->dev, "Invalid DAI ID %x\n", dai->id);
2059 break;
2060 }
2061
2062 return 0;
2063 }
2064
2065 static const struct snd_soc_dai_ops wcd9335_dai_ops = {
2066 .hw_params = wcd9335_hw_params,
2067 .trigger = wcd9335_trigger,
2068 .set_channel_map = wcd9335_set_channel_map,
2069 .get_channel_map = wcd9335_get_channel_map,
2070 };
2071
2072 static struct snd_soc_dai_driver wcd9335_slim_dais[] = {
2073 [0] = {
2074 .name = "wcd9335_rx1",
2075 .id = AIF1_PB,
2076 .playback = {
2077 .stream_name = "AIF1 Playback",
2078 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2079 SNDRV_PCM_RATE_384000,
2080 .formats = WCD9335_FORMATS_S16_S24_LE,
2081 .rate_max = 384000,
2082 .rate_min = 8000,
2083 .channels_min = 1,
2084 .channels_max = 2,
2085 },
2086 .ops = &wcd9335_dai_ops,
2087 },
2088 [1] = {
2089 .name = "wcd9335_tx1",
2090 .id = AIF1_CAP,
2091 .capture = {
2092 .stream_name = "AIF1 Capture",
2093 .rates = WCD9335_RATES_MASK,
2094 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2095 .rate_min = 8000,
2096 .rate_max = 192000,
2097 .channels_min = 1,
2098 .channels_max = 4,
2099 },
2100 .ops = &wcd9335_dai_ops,
2101 },
2102 [2] = {
2103 .name = "wcd9335_rx2",
2104 .id = AIF2_PB,
2105 .playback = {
2106 .stream_name = "AIF2 Playback",
2107 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2108 SNDRV_PCM_RATE_384000,
2109 .formats = WCD9335_FORMATS_S16_S24_LE,
2110 .rate_min = 8000,
2111 .rate_max = 384000,
2112 .channels_min = 1,
2113 .channels_max = 2,
2114 },
2115 .ops = &wcd9335_dai_ops,
2116 },
2117 [3] = {
2118 .name = "wcd9335_tx2",
2119 .id = AIF2_CAP,
2120 .capture = {
2121 .stream_name = "AIF2 Capture",
2122 .rates = WCD9335_RATES_MASK,
2123 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2124 .rate_min = 8000,
2125 .rate_max = 192000,
2126 .channels_min = 1,
2127 .channels_max = 4,
2128 },
2129 .ops = &wcd9335_dai_ops,
2130 },
2131 [4] = {
2132 .name = "wcd9335_rx3",
2133 .id = AIF3_PB,
2134 .playback = {
2135 .stream_name = "AIF3 Playback",
2136 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2137 SNDRV_PCM_RATE_384000,
2138 .formats = WCD9335_FORMATS_S16_S24_LE,
2139 .rate_min = 8000,
2140 .rate_max = 384000,
2141 .channels_min = 1,
2142 .channels_max = 2,
2143 },
2144 .ops = &wcd9335_dai_ops,
2145 },
2146 [5] = {
2147 .name = "wcd9335_tx3",
2148 .id = AIF3_CAP,
2149 .capture = {
2150 .stream_name = "AIF3 Capture",
2151 .rates = WCD9335_RATES_MASK,
2152 .formats = SNDRV_PCM_FMTBIT_S16_LE,
2153 .rate_min = 8000,
2154 .rate_max = 192000,
2155 .channels_min = 1,
2156 .channels_max = 4,
2157 },
2158 .ops = &wcd9335_dai_ops,
2159 },
2160 [6] = {
2161 .name = "wcd9335_rx4",
2162 .id = AIF4_PB,
2163 .playback = {
2164 .stream_name = "AIF4 Playback",
2165 .rates = WCD9335_RATES_MASK | WCD9335_FRAC_RATES_MASK |
2166 SNDRV_PCM_RATE_384000,
2167 .formats = WCD9335_FORMATS_S16_S24_LE,
2168 .rate_min = 8000,
2169 .rate_max = 384000,
2170 .channels_min = 1,
2171 .channels_max = 2,
2172 },
2173 .ops = &wcd9335_dai_ops,
2174 },
2175 };
2176
wcd9335_get_compander(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2177 static int wcd9335_get_compander(struct snd_kcontrol *kc,
2178 struct snd_ctl_elem_value *ucontrol)
2179 {
2180
2181 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2182 int comp = ((struct soc_mixer_control *)kc->private_value)->shift;
2183 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2184
2185 ucontrol->value.integer.value[0] = wcd->comp_enabled[comp];
2186 return 0;
2187 }
2188
wcd9335_set_compander(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2189 static int wcd9335_set_compander(struct snd_kcontrol *kc,
2190 struct snd_ctl_elem_value *ucontrol)
2191 {
2192 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2193 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2194 int comp = ((struct soc_mixer_control *) kc->private_value)->shift;
2195 int value = ucontrol->value.integer.value[0];
2196 int sel;
2197
2198 wcd->comp_enabled[comp] = value;
2199 sel = value ? WCD9335_HPH_GAIN_SRC_SEL_COMPANDER :
2200 WCD9335_HPH_GAIN_SRC_SEL_REGISTER;
2201
2202 /* Any specific register configuration for compander */
2203 switch (comp) {
2204 case COMPANDER_1:
2205 /* Set Gain Source Select based on compander enable/disable */
2206 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
2207 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2208 break;
2209 case COMPANDER_2:
2210 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
2211 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2212 break;
2213 case COMPANDER_5:
2214 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO3_GAIN,
2215 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2216 break;
2217 case COMPANDER_6:
2218 snd_soc_component_update_bits(component, WCD9335_SE_LO_LO4_GAIN,
2219 WCD9335_HPH_GAIN_SRC_SEL_MASK, sel);
2220 break;
2221 default:
2222 break;
2223 }
2224
2225 return 0;
2226 }
2227
wcd9335_rx_hph_mode_get(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2228 static int wcd9335_rx_hph_mode_get(struct snd_kcontrol *kc,
2229 struct snd_ctl_elem_value *ucontrol)
2230 {
2231 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2232 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2233
2234 ucontrol->value.enumerated.item[0] = wcd->hph_mode;
2235
2236 return 0;
2237 }
2238
wcd9335_rx_hph_mode_put(struct snd_kcontrol * kc,struct snd_ctl_elem_value * ucontrol)2239 static int wcd9335_rx_hph_mode_put(struct snd_kcontrol *kc,
2240 struct snd_ctl_elem_value *ucontrol)
2241 {
2242 struct snd_soc_component *component = snd_soc_kcontrol_component(kc);
2243 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2244 u32 mode_val;
2245
2246 mode_val = ucontrol->value.enumerated.item[0];
2247
2248 if (mode_val == 0) {
2249 dev_err(wcd->dev, "Invalid HPH Mode, default to ClSH HiFi\n");
2250 mode_val = CLS_H_HIFI;
2251 }
2252 wcd->hph_mode = mode_val;
2253
2254 return 0;
2255 }
2256
2257 static const struct snd_kcontrol_new wcd9335_snd_controls[] = {
2258 /* -84dB min - 40dB max */
2259 SOC_SINGLE_S8_TLV("RX0 Digital Volume", WCD9335_CDC_RX0_RX_VOL_CTL,
2260 -84, 40, digital_gain),
2261 SOC_SINGLE_S8_TLV("RX1 Digital Volume", WCD9335_CDC_RX1_RX_VOL_CTL,
2262 -84, 40, digital_gain),
2263 SOC_SINGLE_S8_TLV("RX2 Digital Volume", WCD9335_CDC_RX2_RX_VOL_CTL,
2264 -84, 40, digital_gain),
2265 SOC_SINGLE_S8_TLV("RX3 Digital Volume", WCD9335_CDC_RX3_RX_VOL_CTL,
2266 -84, 40, digital_gain),
2267 SOC_SINGLE_S8_TLV("RX4 Digital Volume", WCD9335_CDC_RX4_RX_VOL_CTL,
2268 -84, 40, digital_gain),
2269 SOC_SINGLE_S8_TLV("RX5 Digital Volume", WCD9335_CDC_RX5_RX_VOL_CTL,
2270 -84, 40, digital_gain),
2271 SOC_SINGLE_S8_TLV("RX6 Digital Volume", WCD9335_CDC_RX6_RX_VOL_CTL,
2272 -84, 40, digital_gain),
2273 SOC_SINGLE_S8_TLV("RX7 Digital Volume", WCD9335_CDC_RX7_RX_VOL_CTL,
2274 -84, 40, digital_gain),
2275 SOC_SINGLE_S8_TLV("RX8 Digital Volume", WCD9335_CDC_RX8_RX_VOL_CTL,
2276 -84, 40, digital_gain),
2277 SOC_SINGLE_S8_TLV("RX0 Mix Digital Volume", WCD9335_CDC_RX0_RX_VOL_MIX_CTL,
2278 -84, 40, digital_gain),
2279 SOC_SINGLE_S8_TLV("RX1 Mix Digital Volume", WCD9335_CDC_RX1_RX_VOL_MIX_CTL,
2280 -84, 40, digital_gain),
2281 SOC_SINGLE_S8_TLV("RX2 Mix Digital Volume", WCD9335_CDC_RX2_RX_VOL_MIX_CTL,
2282 -84, 40, digital_gain),
2283 SOC_SINGLE_S8_TLV("RX3 Mix Digital Volume", WCD9335_CDC_RX3_RX_VOL_MIX_CTL,
2284 -84, 40, digital_gain),
2285 SOC_SINGLE_S8_TLV("RX4 Mix Digital Volume", WCD9335_CDC_RX4_RX_VOL_MIX_CTL,
2286 -84, 40, digital_gain),
2287 SOC_SINGLE_S8_TLV("RX5 Mix Digital Volume", WCD9335_CDC_RX5_RX_VOL_MIX_CTL,
2288 -84, 40, digital_gain),
2289 SOC_SINGLE_S8_TLV("RX6 Mix Digital Volume", WCD9335_CDC_RX6_RX_VOL_MIX_CTL,
2290 -84, 40, digital_gain),
2291 SOC_SINGLE_S8_TLV("RX7 Mix Digital Volume", WCD9335_CDC_RX7_RX_VOL_MIX_CTL,
2292 -84, 40, digital_gain),
2293 SOC_SINGLE_S8_TLV("RX8 Mix Digital Volume", WCD9335_CDC_RX8_RX_VOL_MIX_CTL,
2294 -84, 40, digital_gain),
2295 SOC_ENUM("RX INT0_1 HPF cut off", cf_int0_1_enum),
2296 SOC_ENUM("RX INT0_2 HPF cut off", cf_int0_2_enum),
2297 SOC_ENUM("RX INT1_1 HPF cut off", cf_int1_1_enum),
2298 SOC_ENUM("RX INT1_2 HPF cut off", cf_int1_2_enum),
2299 SOC_ENUM("RX INT2_1 HPF cut off", cf_int2_1_enum),
2300 SOC_ENUM("RX INT2_2 HPF cut off", cf_int2_2_enum),
2301 SOC_ENUM("RX INT3_1 HPF cut off", cf_int3_1_enum),
2302 SOC_ENUM("RX INT3_2 HPF cut off", cf_int3_2_enum),
2303 SOC_ENUM("RX INT4_1 HPF cut off", cf_int4_1_enum),
2304 SOC_ENUM("RX INT4_2 HPF cut off", cf_int4_2_enum),
2305 SOC_ENUM("RX INT5_1 HPF cut off", cf_int5_1_enum),
2306 SOC_ENUM("RX INT5_2 HPF cut off", cf_int5_2_enum),
2307 SOC_ENUM("RX INT6_1 HPF cut off", cf_int6_1_enum),
2308 SOC_ENUM("RX INT6_2 HPF cut off", cf_int6_2_enum),
2309 SOC_ENUM("RX INT7_1 HPF cut off", cf_int7_1_enum),
2310 SOC_ENUM("RX INT7_2 HPF cut off", cf_int7_2_enum),
2311 SOC_ENUM("RX INT8_1 HPF cut off", cf_int8_1_enum),
2312 SOC_ENUM("RX INT8_2 HPF cut off", cf_int8_2_enum),
2313 SOC_SINGLE_EXT("COMP1 Switch", SND_SOC_NOPM, COMPANDER_1, 1, 0,
2314 wcd9335_get_compander, wcd9335_set_compander),
2315 SOC_SINGLE_EXT("COMP2 Switch", SND_SOC_NOPM, COMPANDER_2, 1, 0,
2316 wcd9335_get_compander, wcd9335_set_compander),
2317 SOC_SINGLE_EXT("COMP3 Switch", SND_SOC_NOPM, COMPANDER_3, 1, 0,
2318 wcd9335_get_compander, wcd9335_set_compander),
2319 SOC_SINGLE_EXT("COMP4 Switch", SND_SOC_NOPM, COMPANDER_4, 1, 0,
2320 wcd9335_get_compander, wcd9335_set_compander),
2321 SOC_SINGLE_EXT("COMP5 Switch", SND_SOC_NOPM, COMPANDER_5, 1, 0,
2322 wcd9335_get_compander, wcd9335_set_compander),
2323 SOC_SINGLE_EXT("COMP6 Switch", SND_SOC_NOPM, COMPANDER_6, 1, 0,
2324 wcd9335_get_compander, wcd9335_set_compander),
2325 SOC_SINGLE_EXT("COMP7 Switch", SND_SOC_NOPM, COMPANDER_7, 1, 0,
2326 wcd9335_get_compander, wcd9335_set_compander),
2327 SOC_SINGLE_EXT("COMP8 Switch", SND_SOC_NOPM, COMPANDER_8, 1, 0,
2328 wcd9335_get_compander, wcd9335_set_compander),
2329 SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2330 wcd9335_rx_hph_mode_get, wcd9335_rx_hph_mode_put),
2331
2332 /* Gain Controls */
2333 SOC_SINGLE_TLV("EAR PA Volume", WCD9335_ANA_EAR, 4, 4, 1,
2334 ear_pa_gain),
2335 SOC_SINGLE_TLV("HPHL Volume", WCD9335_HPH_L_EN, 0, 20, 1,
2336 line_gain),
2337 SOC_SINGLE_TLV("HPHR Volume", WCD9335_HPH_R_EN, 0, 20, 1,
2338 line_gain),
2339 SOC_SINGLE_TLV("LINEOUT1 Volume", WCD9335_DIFF_LO_LO1_COMPANDER,
2340 3, 16, 1, line_gain),
2341 SOC_SINGLE_TLV("LINEOUT2 Volume", WCD9335_DIFF_LO_LO2_COMPANDER,
2342 3, 16, 1, line_gain),
2343 SOC_SINGLE_TLV("LINEOUT3 Volume", WCD9335_SE_LO_LO3_GAIN, 0, 20, 1,
2344 line_gain),
2345 SOC_SINGLE_TLV("LINEOUT4 Volume", WCD9335_SE_LO_LO4_GAIN, 0, 20, 1,
2346 line_gain),
2347
2348 SOC_SINGLE_TLV("ADC1 Volume", WCD9335_ANA_AMIC1, 0, 20, 0,
2349 analog_gain),
2350 SOC_SINGLE_TLV("ADC2 Volume", WCD9335_ANA_AMIC2, 0, 20, 0,
2351 analog_gain),
2352 SOC_SINGLE_TLV("ADC3 Volume", WCD9335_ANA_AMIC3, 0, 20, 0,
2353 analog_gain),
2354 SOC_SINGLE_TLV("ADC4 Volume", WCD9335_ANA_AMIC4, 0, 20, 0,
2355 analog_gain),
2356 SOC_SINGLE_TLV("ADC5 Volume", WCD9335_ANA_AMIC5, 0, 20, 0,
2357 analog_gain),
2358 SOC_SINGLE_TLV("ADC6 Volume", WCD9335_ANA_AMIC6, 0, 20, 0,
2359 analog_gain),
2360
2361 SOC_ENUM("TX0 HPF cut off", cf_dec0_enum),
2362 SOC_ENUM("TX1 HPF cut off", cf_dec1_enum),
2363 SOC_ENUM("TX2 HPF cut off", cf_dec2_enum),
2364 SOC_ENUM("TX3 HPF cut off", cf_dec3_enum),
2365 SOC_ENUM("TX4 HPF cut off", cf_dec4_enum),
2366 SOC_ENUM("TX5 HPF cut off", cf_dec5_enum),
2367 SOC_ENUM("TX6 HPF cut off", cf_dec6_enum),
2368 SOC_ENUM("TX7 HPF cut off", cf_dec7_enum),
2369 SOC_ENUM("TX8 HPF cut off", cf_dec8_enum),
2370 };
2371
2372 static const struct snd_soc_dapm_route wcd9335_audio_map[] = {
2373 {"SLIM RX0 MUX", "AIF1_PB", "AIF1 PB"},
2374 {"SLIM RX1 MUX", "AIF1_PB", "AIF1 PB"},
2375 {"SLIM RX2 MUX", "AIF1_PB", "AIF1 PB"},
2376 {"SLIM RX3 MUX", "AIF1_PB", "AIF1 PB"},
2377 {"SLIM RX4 MUX", "AIF1_PB", "AIF1 PB"},
2378 {"SLIM RX5 MUX", "AIF1_PB", "AIF1 PB"},
2379 {"SLIM RX6 MUX", "AIF1_PB", "AIF1 PB"},
2380 {"SLIM RX7 MUX", "AIF1_PB", "AIF1 PB"},
2381
2382 {"SLIM RX0 MUX", "AIF2_PB", "AIF2 PB"},
2383 {"SLIM RX1 MUX", "AIF2_PB", "AIF2 PB"},
2384 {"SLIM RX2 MUX", "AIF2_PB", "AIF2 PB"},
2385 {"SLIM RX3 MUX", "AIF2_PB", "AIF2 PB"},
2386 {"SLIM RX4 MUX", "AIF2_PB", "AIF2 PB"},
2387 {"SLIM RX5 MUX", "AIF2_PB", "AIF2 PB"},
2388 {"SLIM RX6 MUX", "AIF2_PB", "AIF2 PB"},
2389 {"SLIM RX7 MUX", "AIF2_PB", "AIF2 PB"},
2390
2391 {"SLIM RX0 MUX", "AIF3_PB", "AIF3 PB"},
2392 {"SLIM RX1 MUX", "AIF3_PB", "AIF3 PB"},
2393 {"SLIM RX2 MUX", "AIF3_PB", "AIF3 PB"},
2394 {"SLIM RX3 MUX", "AIF3_PB", "AIF3 PB"},
2395 {"SLIM RX4 MUX", "AIF3_PB", "AIF3 PB"},
2396 {"SLIM RX5 MUX", "AIF3_PB", "AIF3 PB"},
2397 {"SLIM RX6 MUX", "AIF3_PB", "AIF3 PB"},
2398 {"SLIM RX7 MUX", "AIF3_PB", "AIF3 PB"},
2399
2400 {"SLIM RX0 MUX", "AIF4_PB", "AIF4 PB"},
2401 {"SLIM RX1 MUX", "AIF4_PB", "AIF4 PB"},
2402 {"SLIM RX2 MUX", "AIF4_PB", "AIF4 PB"},
2403 {"SLIM RX3 MUX", "AIF4_PB", "AIF4 PB"},
2404 {"SLIM RX4 MUX", "AIF4_PB", "AIF4 PB"},
2405 {"SLIM RX5 MUX", "AIF4_PB", "AIF4 PB"},
2406 {"SLIM RX6 MUX", "AIF4_PB", "AIF4 PB"},
2407 {"SLIM RX7 MUX", "AIF4_PB", "AIF4 PB"},
2408
2409 {"SLIM RX0", NULL, "SLIM RX0 MUX"},
2410 {"SLIM RX1", NULL, "SLIM RX1 MUX"},
2411 {"SLIM RX2", NULL, "SLIM RX2 MUX"},
2412 {"SLIM RX3", NULL, "SLIM RX3 MUX"},
2413 {"SLIM RX4", NULL, "SLIM RX4 MUX"},
2414 {"SLIM RX5", NULL, "SLIM RX5 MUX"},
2415 {"SLIM RX6", NULL, "SLIM RX6 MUX"},
2416 {"SLIM RX7", NULL, "SLIM RX7 MUX"},
2417
2418 WCD9335_INTERPOLATOR_PATH(0),
2419 WCD9335_INTERPOLATOR_PATH(1),
2420 WCD9335_INTERPOLATOR_PATH(2),
2421 WCD9335_INTERPOLATOR_PATH(3),
2422 WCD9335_INTERPOLATOR_PATH(4),
2423 WCD9335_INTERPOLATOR_PATH(5),
2424 WCD9335_INTERPOLATOR_PATH(6),
2425 WCD9335_INTERPOLATOR_PATH(7),
2426 WCD9335_INTERPOLATOR_PATH(8),
2427
2428 /* EAR PA */
2429 {"RX INT0 DEM MUX", "CLSH_DSM_OUT", "RX INT0 INTERP"},
2430 {"RX INT0 DAC", NULL, "RX INT0 DEM MUX"},
2431 {"RX INT0 DAC", NULL, "RX_BIAS"},
2432 {"EAR PA", NULL, "RX INT0 DAC"},
2433 {"EAR", NULL, "EAR PA"},
2434
2435 /* HPHL */
2436 {"RX INT1 DEM MUX", "CLSH_DSM_OUT", "RX INT1 INTERP"},
2437 {"RX INT1 DAC", NULL, "RX INT1 DEM MUX"},
2438 {"RX INT1 DAC", NULL, "RX_BIAS"},
2439 {"HPHL PA", NULL, "RX INT1 DAC"},
2440 {"HPHL", NULL, "HPHL PA"},
2441
2442 /* HPHR */
2443 {"RX INT2 DEM MUX", "CLSH_DSM_OUT", "RX INT2 INTERP"},
2444 {"RX INT2 DAC", NULL, "RX INT2 DEM MUX"},
2445 {"RX INT2 DAC", NULL, "RX_BIAS"},
2446 {"HPHR PA", NULL, "RX INT2 DAC"},
2447 {"HPHR", NULL, "HPHR PA"},
2448
2449 /* LINEOUT1 */
2450 {"RX INT3 DAC", NULL, "RX INT3 INTERP"},
2451 {"RX INT3 DAC", NULL, "RX_BIAS"},
2452 {"LINEOUT1 PA", NULL, "RX INT3 DAC"},
2453 {"LINEOUT1", NULL, "LINEOUT1 PA"},
2454
2455 /* LINEOUT2 */
2456 {"RX INT4 DAC", NULL, "RX INT4 INTERP"},
2457 {"RX INT4 DAC", NULL, "RX_BIAS"},
2458 {"LINEOUT2 PA", NULL, "RX INT4 DAC"},
2459 {"LINEOUT2", NULL, "LINEOUT2 PA"},
2460
2461 /* LINEOUT3 */
2462 {"RX INT5 DAC", NULL, "RX INT5 INTERP"},
2463 {"RX INT5 DAC", NULL, "RX_BIAS"},
2464 {"LINEOUT3 PA", NULL, "RX INT5 DAC"},
2465 {"LINEOUT3", NULL, "LINEOUT3 PA"},
2466
2467 /* LINEOUT4 */
2468 {"RX INT6 DAC", NULL, "RX INT6 INTERP"},
2469 {"RX INT6 DAC", NULL, "RX_BIAS"},
2470 {"LINEOUT4 PA", NULL, "RX INT6 DAC"},
2471 {"LINEOUT4", NULL, "LINEOUT4 PA"},
2472
2473 /* SLIMBUS Connections */
2474 {"AIF1 CAP", NULL, "AIF1_CAP Mixer"},
2475 {"AIF2 CAP", NULL, "AIF2_CAP Mixer"},
2476 {"AIF3 CAP", NULL, "AIF3_CAP Mixer"},
2477
2478 /* ADC Mux */
2479 WCD9335_ADC_MUX_PATH(0),
2480 WCD9335_ADC_MUX_PATH(1),
2481 WCD9335_ADC_MUX_PATH(2),
2482 WCD9335_ADC_MUX_PATH(3),
2483 WCD9335_ADC_MUX_PATH(4),
2484 WCD9335_ADC_MUX_PATH(5),
2485 WCD9335_ADC_MUX_PATH(6),
2486 WCD9335_ADC_MUX_PATH(7),
2487 WCD9335_ADC_MUX_PATH(8),
2488
2489 /* ADC Connections */
2490 {"ADC1", NULL, "AMIC1"},
2491 {"ADC2", NULL, "AMIC2"},
2492 {"ADC3", NULL, "AMIC3"},
2493 {"ADC4", NULL, "AMIC4"},
2494 {"ADC5", NULL, "AMIC5"},
2495 {"ADC6", NULL, "AMIC6"},
2496 };
2497
wcd9335_micbias_control(struct snd_soc_component * component,int micb_num,int req,bool is_dapm)2498 static int wcd9335_micbias_control(struct snd_soc_component *component,
2499 int micb_num, int req, bool is_dapm)
2500 {
2501 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(component);
2502 int micb_index = micb_num - 1;
2503 u16 micb_reg;
2504
2505 if ((micb_index < 0) || (micb_index > WCD9335_MAX_MICBIAS - 1)) {
2506 dev_err(wcd->dev, "Invalid micbias index, micb_ind:%d\n",
2507 micb_index);
2508 return -EINVAL;
2509 }
2510
2511 switch (micb_num) {
2512 case MIC_BIAS_1:
2513 micb_reg = WCD9335_ANA_MICB1;
2514 break;
2515 case MIC_BIAS_2:
2516 micb_reg = WCD9335_ANA_MICB2;
2517 break;
2518 case MIC_BIAS_3:
2519 micb_reg = WCD9335_ANA_MICB3;
2520 break;
2521 case MIC_BIAS_4:
2522 micb_reg = WCD9335_ANA_MICB4;
2523 break;
2524 default:
2525 dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2526 __func__, micb_num);
2527 return -EINVAL;
2528 }
2529
2530 switch (req) {
2531 case MICB_PULLUP_ENABLE:
2532 wcd->pullup_ref[micb_index]++;
2533 if ((wcd->pullup_ref[micb_index] == 1) &&
2534 (wcd->micb_ref[micb_index] == 0))
2535 snd_soc_component_update_bits(component, micb_reg,
2536 0xC0, 0x80);
2537 break;
2538 case MICB_PULLUP_DISABLE:
2539 wcd->pullup_ref[micb_index]--;
2540 if ((wcd->pullup_ref[micb_index] == 0) &&
2541 (wcd->micb_ref[micb_index] == 0))
2542 snd_soc_component_update_bits(component, micb_reg,
2543 0xC0, 0x00);
2544 break;
2545 case MICB_ENABLE:
2546 wcd->micb_ref[micb_index]++;
2547 if (wcd->micb_ref[micb_index] == 1)
2548 snd_soc_component_update_bits(component, micb_reg,
2549 0xC0, 0x40);
2550 break;
2551 case MICB_DISABLE:
2552 wcd->micb_ref[micb_index]--;
2553 if ((wcd->micb_ref[micb_index] == 0) &&
2554 (wcd->pullup_ref[micb_index] > 0))
2555 snd_soc_component_update_bits(component, micb_reg,
2556 0xC0, 0x80);
2557 else if ((wcd->micb_ref[micb_index] == 0) &&
2558 (wcd->pullup_ref[micb_index] == 0)) {
2559 snd_soc_component_update_bits(component, micb_reg,
2560 0xC0, 0x00);
2561 }
2562 break;
2563 }
2564
2565 return 0;
2566 }
2567
__wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget * w,int event)2568 static int __wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2569 int event)
2570 {
2571 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2572 int micb_num;
2573
2574 if (strnstr(w->name, "MIC BIAS1", sizeof("MIC BIAS1")))
2575 micb_num = MIC_BIAS_1;
2576 else if (strnstr(w->name, "MIC BIAS2", sizeof("MIC BIAS2")))
2577 micb_num = MIC_BIAS_2;
2578 else if (strnstr(w->name, "MIC BIAS3", sizeof("MIC BIAS3")))
2579 micb_num = MIC_BIAS_3;
2580 else if (strnstr(w->name, "MIC BIAS4", sizeof("MIC BIAS4")))
2581 micb_num = MIC_BIAS_4;
2582 else
2583 return -EINVAL;
2584
2585 switch (event) {
2586 case SND_SOC_DAPM_PRE_PMU:
2587 /*
2588 * MIC BIAS can also be requested by MBHC,
2589 * so use ref count to handle micbias pullup
2590 * and enable requests
2591 */
2592 wcd9335_micbias_control(comp, micb_num, MICB_ENABLE, true);
2593 break;
2594 case SND_SOC_DAPM_POST_PMU:
2595 /* wait for cnp time */
2596 usleep_range(1000, 1100);
2597 break;
2598 case SND_SOC_DAPM_POST_PMD:
2599 wcd9335_micbias_control(comp, micb_num, MICB_DISABLE, true);
2600 break;
2601 }
2602
2603 return 0;
2604 }
2605
wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2606 static int wcd9335_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2607 struct snd_kcontrol *kc, int event)
2608 {
2609 return __wcd9335_codec_enable_micbias(w, event);
2610 }
2611
wcd9335_codec_set_tx_hold(struct snd_soc_component * comp,u16 amic_reg,bool set)2612 static void wcd9335_codec_set_tx_hold(struct snd_soc_component *comp,
2613 u16 amic_reg, bool set)
2614 {
2615 u8 mask = 0x20;
2616 u8 val;
2617
2618 if (amic_reg == WCD9335_ANA_AMIC1 || amic_reg == WCD9335_ANA_AMIC3 ||
2619 amic_reg == WCD9335_ANA_AMIC5)
2620 mask = 0x40;
2621
2622 val = set ? mask : 0x00;
2623
2624 switch (amic_reg) {
2625 case WCD9335_ANA_AMIC1:
2626 case WCD9335_ANA_AMIC2:
2627 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC2, mask,
2628 val);
2629 break;
2630 case WCD9335_ANA_AMIC3:
2631 case WCD9335_ANA_AMIC4:
2632 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC4, mask,
2633 val);
2634 break;
2635 case WCD9335_ANA_AMIC5:
2636 case WCD9335_ANA_AMIC6:
2637 snd_soc_component_update_bits(comp, WCD9335_ANA_AMIC6, mask,
2638 val);
2639 break;
2640 default:
2641 dev_err(comp->dev, "%s: invalid amic: %d\n",
2642 __func__, amic_reg);
2643 break;
2644 }
2645 }
2646
wcd9335_codec_enable_adc(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2647 static int wcd9335_codec_enable_adc(struct snd_soc_dapm_widget *w,
2648 struct snd_kcontrol *kc, int event)
2649 {
2650 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2651
2652 switch (event) {
2653 case SND_SOC_DAPM_PRE_PMU:
2654 wcd9335_codec_set_tx_hold(comp, w->reg, true);
2655 break;
2656 default:
2657 break;
2658 }
2659
2660 return 0;
2661 }
2662
wcd9335_codec_find_amic_input(struct snd_soc_component * comp,int adc_mux_n)2663 static int wcd9335_codec_find_amic_input(struct snd_soc_component *comp,
2664 int adc_mux_n)
2665 {
2666 int mux_sel, reg, mreg;
2667
2668 if (adc_mux_n < 0 || adc_mux_n > WCD9335_MAX_VALID_ADC_MUX ||
2669 adc_mux_n == WCD9335_INVALID_ADC_MUX)
2670 return 0;
2671
2672 /* Check whether adc mux input is AMIC or DMIC */
2673 if (adc_mux_n < 4) {
2674 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + 2 * adc_mux_n;
2675 mreg = WCD9335_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + 2 * adc_mux_n;
2676 mux_sel = snd_soc_component_read(comp, reg) & 0x3;
2677 } else {
2678 reg = WCD9335_CDC_TX_INP_MUX_ADC_MUX4_CFG0 + adc_mux_n - 4;
2679 mreg = reg;
2680 mux_sel = snd_soc_component_read(comp, reg) >> 6;
2681 }
2682
2683 if (mux_sel != WCD9335_CDC_TX_INP_MUX_SEL_AMIC)
2684 return 0;
2685
2686 return snd_soc_component_read(comp, mreg) & 0x07;
2687 }
2688
wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component * comp,int amic)2689 static u16 wcd9335_codec_get_amic_pwlvl_reg(struct snd_soc_component *comp,
2690 int amic)
2691 {
2692 u16 pwr_level_reg = 0;
2693
2694 switch (amic) {
2695 case 1:
2696 case 2:
2697 pwr_level_reg = WCD9335_ANA_AMIC1;
2698 break;
2699
2700 case 3:
2701 case 4:
2702 pwr_level_reg = WCD9335_ANA_AMIC3;
2703 break;
2704
2705 case 5:
2706 case 6:
2707 pwr_level_reg = WCD9335_ANA_AMIC5;
2708 break;
2709 default:
2710 dev_err(comp->dev, "invalid amic: %d\n", amic);
2711 break;
2712 }
2713
2714 return pwr_level_reg;
2715 }
2716
wcd9335_codec_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2717 static int wcd9335_codec_enable_dec(struct snd_soc_dapm_widget *w,
2718 struct snd_kcontrol *kc, int event)
2719 {
2720 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2721 unsigned int decimator;
2722 char *dec_adc_mux_name = NULL;
2723 char *widget_name = NULL;
2724 char *wname;
2725 int ret = 0, amic_n;
2726 u16 tx_vol_ctl_reg, pwr_level_reg = 0, dec_cfg_reg, hpf_gate_reg;
2727 u16 tx_gain_ctl_reg;
2728 char *dec;
2729 u8 hpf_coff_freq;
2730
2731 widget_name = kmemdup_nul(w->name, 15, GFP_KERNEL);
2732 if (!widget_name)
2733 return -ENOMEM;
2734
2735 wname = widget_name;
2736 dec_adc_mux_name = strsep(&widget_name, " ");
2737 if (!dec_adc_mux_name) {
2738 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2739 __func__, w->name);
2740 ret = -EINVAL;
2741 goto out;
2742 }
2743 dec_adc_mux_name = widget_name;
2744
2745 dec = strpbrk(dec_adc_mux_name, "012345678");
2746 if (!dec) {
2747 dev_err(comp->dev, "%s: decimator index not found\n",
2748 __func__);
2749 ret = -EINVAL;
2750 goto out;
2751 }
2752
2753 ret = kstrtouint(dec, 10, &decimator);
2754 if (ret < 0) {
2755 dev_err(comp->dev, "%s: Invalid decimator = %s\n",
2756 __func__, wname);
2757 ret = -EINVAL;
2758 goto out;
2759 }
2760
2761 tx_vol_ctl_reg = WCD9335_CDC_TX0_TX_PATH_CTL + 16 * decimator;
2762 hpf_gate_reg = WCD9335_CDC_TX0_TX_PATH_SEC2 + 16 * decimator;
2763 dec_cfg_reg = WCD9335_CDC_TX0_TX_PATH_CFG0 + 16 * decimator;
2764 tx_gain_ctl_reg = WCD9335_CDC_TX0_TX_VOL_CTL + 16 * decimator;
2765
2766 switch (event) {
2767 case SND_SOC_DAPM_PRE_PMU:
2768 amic_n = wcd9335_codec_find_amic_input(comp, decimator);
2769 if (amic_n)
2770 pwr_level_reg = wcd9335_codec_get_amic_pwlvl_reg(comp,
2771 amic_n);
2772
2773 if (pwr_level_reg) {
2774 switch ((snd_soc_component_read(comp, pwr_level_reg) &
2775 WCD9335_AMIC_PWR_LVL_MASK) >>
2776 WCD9335_AMIC_PWR_LVL_SHIFT) {
2777 case WCD9335_AMIC_PWR_LEVEL_LP:
2778 snd_soc_component_update_bits(comp, dec_cfg_reg,
2779 WCD9335_DEC_PWR_LVL_MASK,
2780 WCD9335_DEC_PWR_LVL_LP);
2781 break;
2782
2783 case WCD9335_AMIC_PWR_LEVEL_HP:
2784 snd_soc_component_update_bits(comp, dec_cfg_reg,
2785 WCD9335_DEC_PWR_LVL_MASK,
2786 WCD9335_DEC_PWR_LVL_HP);
2787 break;
2788 case WCD9335_AMIC_PWR_LEVEL_DEFAULT:
2789 default:
2790 snd_soc_component_update_bits(comp, dec_cfg_reg,
2791 WCD9335_DEC_PWR_LVL_MASK,
2792 WCD9335_DEC_PWR_LVL_DF);
2793 break;
2794 }
2795 }
2796 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2797 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2798
2799 if (hpf_coff_freq != CF_MIN_3DB_150HZ)
2800 snd_soc_component_update_bits(comp, dec_cfg_reg,
2801 TX_HPF_CUT_OFF_FREQ_MASK,
2802 CF_MIN_3DB_150HZ << 5);
2803 /* Enable TX PGA Mute */
2804 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2805 0x10, 0x10);
2806 /* Enable APC */
2807 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x08);
2808 break;
2809 case SND_SOC_DAPM_POST_PMU:
2810 snd_soc_component_update_bits(comp, hpf_gate_reg, 0x01, 0x00);
2811
2812 if (decimator == 0) {
2813 snd_soc_component_write(comp,
2814 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2815 snd_soc_component_write(comp,
2816 WCD9335_MBHC_ZDET_RAMP_CTL, 0xA3);
2817 snd_soc_component_write(comp,
2818 WCD9335_MBHC_ZDET_RAMP_CTL, 0x83);
2819 snd_soc_component_write(comp,
2820 WCD9335_MBHC_ZDET_RAMP_CTL, 0x03);
2821 }
2822
2823 snd_soc_component_update_bits(comp, hpf_gate_reg,
2824 0x01, 0x01);
2825 snd_soc_component_update_bits(comp, tx_vol_ctl_reg,
2826 0x10, 0x00);
2827 snd_soc_component_write(comp, tx_gain_ctl_reg,
2828 snd_soc_component_read(comp, tx_gain_ctl_reg));
2829 break;
2830 case SND_SOC_DAPM_PRE_PMD:
2831 hpf_coff_freq = (snd_soc_component_read(comp, dec_cfg_reg) &
2832 TX_HPF_CUT_OFF_FREQ_MASK) >> 5;
2833 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x10);
2834 snd_soc_component_update_bits(comp, dec_cfg_reg, 0x08, 0x00);
2835 if (hpf_coff_freq != CF_MIN_3DB_150HZ) {
2836 snd_soc_component_update_bits(comp, dec_cfg_reg,
2837 TX_HPF_CUT_OFF_FREQ_MASK,
2838 hpf_coff_freq << 5);
2839 }
2840 break;
2841 case SND_SOC_DAPM_POST_PMD:
2842 snd_soc_component_update_bits(comp, tx_vol_ctl_reg, 0x10, 0x00);
2843 break;
2844 }
2845 out:
2846 kfree(wname);
2847 return ret;
2848 }
2849
wcd9335_get_dmic_clk_val(struct snd_soc_component * component,u32 mclk_rate,u32 dmic_clk_rate)2850 static u8 wcd9335_get_dmic_clk_val(struct snd_soc_component *component,
2851 u32 mclk_rate, u32 dmic_clk_rate)
2852 {
2853 u32 div_factor;
2854 u8 dmic_ctl_val;
2855
2856 dev_err(component->dev,
2857 "%s: mclk_rate = %d, dmic_sample_rate = %d\n",
2858 __func__, mclk_rate, dmic_clk_rate);
2859
2860 /* Default value to return in case of error */
2861 if (mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
2862 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2863 else
2864 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2865
2866 if (dmic_clk_rate == 0) {
2867 dev_err(component->dev,
2868 "%s: dmic_sample_rate cannot be 0\n",
2869 __func__);
2870 goto done;
2871 }
2872
2873 div_factor = mclk_rate / dmic_clk_rate;
2874 switch (div_factor) {
2875 case 2:
2876 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_2;
2877 break;
2878 case 3:
2879 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_3;
2880 break;
2881 case 4:
2882 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_4;
2883 break;
2884 case 6:
2885 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_6;
2886 break;
2887 case 8:
2888 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_8;
2889 break;
2890 case 16:
2891 dmic_ctl_val = WCD9335_DMIC_CLK_DIV_16;
2892 break;
2893 default:
2894 dev_err(component->dev,
2895 "%s: Invalid div_factor %u, clk_rate(%u), dmic_rate(%u)\n",
2896 __func__, div_factor, mclk_rate, dmic_clk_rate);
2897 break;
2898 }
2899
2900 done:
2901 return dmic_ctl_val;
2902 }
2903
wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)2904 static int wcd9335_codec_enable_dmic(struct snd_soc_dapm_widget *w,
2905 struct snd_kcontrol *kc, int event)
2906 {
2907 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
2908 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
2909 u8 dmic_clk_en = 0x01;
2910 u16 dmic_clk_reg;
2911 s32 *dmic_clk_cnt;
2912 u8 dmic_rate_val, dmic_rate_shift = 1;
2913 unsigned int dmic;
2914 int ret;
2915 char *wname;
2916
2917 wname = strpbrk(w->name, "012345");
2918 if (!wname) {
2919 dev_err(comp->dev, "%s: widget not found\n", __func__);
2920 return -EINVAL;
2921 }
2922
2923 ret = kstrtouint(wname, 10, &dmic);
2924 if (ret < 0) {
2925 dev_err(comp->dev, "%s: Invalid DMIC line on the codec\n",
2926 __func__);
2927 return -EINVAL;
2928 }
2929
2930 switch (dmic) {
2931 case 0:
2932 case 1:
2933 dmic_clk_cnt = &(wcd->dmic_0_1_clk_cnt);
2934 dmic_clk_reg = WCD9335_CPE_SS_DMIC0_CTL;
2935 break;
2936 case 2:
2937 case 3:
2938 dmic_clk_cnt = &(wcd->dmic_2_3_clk_cnt);
2939 dmic_clk_reg = WCD9335_CPE_SS_DMIC1_CTL;
2940 break;
2941 case 4:
2942 case 5:
2943 dmic_clk_cnt = &(wcd->dmic_4_5_clk_cnt);
2944 dmic_clk_reg = WCD9335_CPE_SS_DMIC2_CTL;
2945 break;
2946 default:
2947 dev_err(comp->dev, "%s: Invalid DMIC Selection\n",
2948 __func__);
2949 return -EINVAL;
2950 }
2951
2952 switch (event) {
2953 case SND_SOC_DAPM_PRE_PMU:
2954 dmic_rate_val =
2955 wcd9335_get_dmic_clk_val(comp,
2956 wcd->mclk_rate,
2957 wcd->dmic_sample_rate);
2958
2959 (*dmic_clk_cnt)++;
2960 if (*dmic_clk_cnt == 1) {
2961 snd_soc_component_update_bits(comp, dmic_clk_reg,
2962 0x07 << dmic_rate_shift,
2963 dmic_rate_val << dmic_rate_shift);
2964 snd_soc_component_update_bits(comp, dmic_clk_reg,
2965 dmic_clk_en, dmic_clk_en);
2966 }
2967
2968 break;
2969 case SND_SOC_DAPM_POST_PMD:
2970 dmic_rate_val =
2971 wcd9335_get_dmic_clk_val(comp,
2972 wcd->mclk_rate,
2973 wcd->mad_dmic_sample_rate);
2974 (*dmic_clk_cnt)--;
2975 if (*dmic_clk_cnt == 0) {
2976 snd_soc_component_update_bits(comp, dmic_clk_reg,
2977 dmic_clk_en, 0);
2978 snd_soc_component_update_bits(comp, dmic_clk_reg,
2979 0x07 << dmic_rate_shift,
2980 dmic_rate_val << dmic_rate_shift);
2981 }
2982 break;
2983 }
2984
2985 return 0;
2986 }
2987
wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data * dai,struct snd_soc_component * component)2988 static void wcd9335_codec_enable_int_port(struct wcd_slim_codec_dai_data *dai,
2989 struct snd_soc_component *component)
2990 {
2991 int port_num = 0;
2992 unsigned short reg = 0;
2993 unsigned int val = 0;
2994 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
2995 struct wcd9335_slim_ch *ch;
2996
2997 list_for_each_entry(ch, &dai->slim_ch_list, list) {
2998 if (ch->port >= WCD9335_RX_START) {
2999 port_num = ch->port - WCD9335_RX_START;
3000 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 + (port_num / 8);
3001 } else {
3002 port_num = ch->port;
3003 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 + (port_num / 8);
3004 }
3005
3006 regmap_read(wcd->if_regmap, reg, &val);
3007 if (!(val & BIT(port_num % 8)))
3008 regmap_write(wcd->if_regmap, reg,
3009 val | BIT(port_num % 8));
3010 }
3011 }
3012
wcd9335_codec_enable_slim(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3013 static int wcd9335_codec_enable_slim(struct snd_soc_dapm_widget *w,
3014 struct snd_kcontrol *kc,
3015 int event)
3016 {
3017 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3018 struct wcd9335_codec *wcd = snd_soc_component_get_drvdata(comp);
3019 struct wcd_slim_codec_dai_data *dai = &wcd->dai[w->shift];
3020
3021 switch (event) {
3022 case SND_SOC_DAPM_POST_PMU:
3023 wcd9335_codec_enable_int_port(dai, comp);
3024 break;
3025 case SND_SOC_DAPM_POST_PMD:
3026 kfree(dai->sconfig.chs);
3027
3028 break;
3029 }
3030
3031 return 0;
3032 }
3033
wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3034 static int wcd9335_codec_enable_mix_path(struct snd_soc_dapm_widget *w,
3035 struct snd_kcontrol *kc, int event)
3036 {
3037 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3038 u16 gain_reg;
3039 int offset_val = 0;
3040 int val = 0;
3041
3042 switch (w->reg) {
3043 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3044 gain_reg = WCD9335_CDC_RX0_RX_VOL_MIX_CTL;
3045 break;
3046 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3047 gain_reg = WCD9335_CDC_RX1_RX_VOL_MIX_CTL;
3048 break;
3049 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3050 gain_reg = WCD9335_CDC_RX2_RX_VOL_MIX_CTL;
3051 break;
3052 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3053 gain_reg = WCD9335_CDC_RX3_RX_VOL_MIX_CTL;
3054 break;
3055 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3056 gain_reg = WCD9335_CDC_RX4_RX_VOL_MIX_CTL;
3057 break;
3058 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3059 gain_reg = WCD9335_CDC_RX5_RX_VOL_MIX_CTL;
3060 break;
3061 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3062 gain_reg = WCD9335_CDC_RX6_RX_VOL_MIX_CTL;
3063 break;
3064 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3065 gain_reg = WCD9335_CDC_RX7_RX_VOL_MIX_CTL;
3066 break;
3067 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3068 gain_reg = WCD9335_CDC_RX8_RX_VOL_MIX_CTL;
3069 break;
3070 default:
3071 dev_err(comp->dev, "%s: No gain register avail for %s\n",
3072 __func__, w->name);
3073 return 0;
3074 }
3075
3076 switch (event) {
3077 case SND_SOC_DAPM_POST_PMU:
3078 val = snd_soc_component_read(comp, gain_reg);
3079 val += offset_val;
3080 snd_soc_component_write(comp, gain_reg, val);
3081 break;
3082 case SND_SOC_DAPM_POST_PMD:
3083 break;
3084 }
3085
3086 return 0;
3087 }
3088
wcd9335_interp_get_primary_reg(u16 reg,u16 * ind)3089 static u16 wcd9335_interp_get_primary_reg(u16 reg, u16 *ind)
3090 {
3091 u16 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3092
3093 switch (reg) {
3094 case WCD9335_CDC_RX0_RX_PATH_CTL:
3095 case WCD9335_CDC_RX0_RX_PATH_MIX_CTL:
3096 prim_int_reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3097 *ind = 0;
3098 break;
3099 case WCD9335_CDC_RX1_RX_PATH_CTL:
3100 case WCD9335_CDC_RX1_RX_PATH_MIX_CTL:
3101 prim_int_reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3102 *ind = 1;
3103 break;
3104 case WCD9335_CDC_RX2_RX_PATH_CTL:
3105 case WCD9335_CDC_RX2_RX_PATH_MIX_CTL:
3106 prim_int_reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3107 *ind = 2;
3108 break;
3109 case WCD9335_CDC_RX3_RX_PATH_CTL:
3110 case WCD9335_CDC_RX3_RX_PATH_MIX_CTL:
3111 prim_int_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3112 *ind = 3;
3113 break;
3114 case WCD9335_CDC_RX4_RX_PATH_CTL:
3115 case WCD9335_CDC_RX4_RX_PATH_MIX_CTL:
3116 prim_int_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3117 *ind = 4;
3118 break;
3119 case WCD9335_CDC_RX5_RX_PATH_CTL:
3120 case WCD9335_CDC_RX5_RX_PATH_MIX_CTL:
3121 prim_int_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3122 *ind = 5;
3123 break;
3124 case WCD9335_CDC_RX6_RX_PATH_CTL:
3125 case WCD9335_CDC_RX6_RX_PATH_MIX_CTL:
3126 prim_int_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3127 *ind = 6;
3128 break;
3129 case WCD9335_CDC_RX7_RX_PATH_CTL:
3130 case WCD9335_CDC_RX7_RX_PATH_MIX_CTL:
3131 prim_int_reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3132 *ind = 7;
3133 break;
3134 case WCD9335_CDC_RX8_RX_PATH_CTL:
3135 case WCD9335_CDC_RX8_RX_PATH_MIX_CTL:
3136 prim_int_reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3137 *ind = 8;
3138 break;
3139 }
3140
3141 return prim_int_reg;
3142 }
3143
wcd9335_codec_hd2_control(struct snd_soc_component * component,u16 prim_int_reg,int event)3144 static void wcd9335_codec_hd2_control(struct snd_soc_component *component,
3145 u16 prim_int_reg, int event)
3146 {
3147 u16 hd2_scale_reg;
3148 u16 hd2_enable_reg = 0;
3149
3150 if (prim_int_reg == WCD9335_CDC_RX1_RX_PATH_CTL) {
3151 hd2_scale_reg = WCD9335_CDC_RX1_RX_PATH_SEC3;
3152 hd2_enable_reg = WCD9335_CDC_RX1_RX_PATH_CFG0;
3153 }
3154 if (prim_int_reg == WCD9335_CDC_RX2_RX_PATH_CTL) {
3155 hd2_scale_reg = WCD9335_CDC_RX2_RX_PATH_SEC3;
3156 hd2_enable_reg = WCD9335_CDC_RX2_RX_PATH_CFG0;
3157 }
3158
3159 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_ON(event)) {
3160 snd_soc_component_update_bits(component, hd2_scale_reg,
3161 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3162 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P2500);
3163 snd_soc_component_update_bits(component, hd2_scale_reg,
3164 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3165 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_2);
3166 snd_soc_component_update_bits(component, hd2_enable_reg,
3167 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3168 WCD9335_CDC_RX_PATH_CFG_HD2_ENABLE);
3169 }
3170
3171 if (hd2_enable_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
3172 snd_soc_component_update_bits(component, hd2_enable_reg,
3173 WCD9335_CDC_RX_PATH_CFG_HD2_EN_MASK,
3174 WCD9335_CDC_RX_PATH_CFG_HD2_DISABLE);
3175 snd_soc_component_update_bits(component, hd2_scale_reg,
3176 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_MASK,
3177 WCD9335_CDC_RX_PATH_SEC_HD2_SCALE_1);
3178 snd_soc_component_update_bits(component, hd2_scale_reg,
3179 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_MASK,
3180 WCD9335_CDC_RX_PATH_SEC_HD2_ALPHA_0P0000);
3181 }
3182 }
3183
wcd9335_codec_enable_prim_interpolator(struct snd_soc_component * comp,u16 reg,int event)3184 static int wcd9335_codec_enable_prim_interpolator(
3185 struct snd_soc_component *comp,
3186 u16 reg, int event)
3187 {
3188 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3189 u16 ind = 0;
3190 int prim_int_reg = wcd9335_interp_get_primary_reg(reg, &ind);
3191
3192 switch (event) {
3193 case SND_SOC_DAPM_PRE_PMU:
3194 wcd->prim_int_users[ind]++;
3195 if (wcd->prim_int_users[ind] == 1) {
3196 snd_soc_component_update_bits(comp, prim_int_reg,
3197 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3198 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3199 wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3200 snd_soc_component_update_bits(comp, prim_int_reg,
3201 WCD9335_CDC_RX_CLK_EN_MASK,
3202 WCD9335_CDC_RX_CLK_ENABLE);
3203 }
3204
3205 if ((reg != prim_int_reg) &&
3206 ((snd_soc_component_read(comp, prim_int_reg)) &
3207 WCD9335_CDC_RX_PGA_MUTE_EN_MASK))
3208 snd_soc_component_update_bits(comp, reg,
3209 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3210 WCD9335_CDC_RX_PGA_MUTE_ENABLE);
3211 break;
3212 case SND_SOC_DAPM_POST_PMD:
3213 wcd->prim_int_users[ind]--;
3214 if (wcd->prim_int_users[ind] == 0) {
3215 snd_soc_component_update_bits(comp, prim_int_reg,
3216 WCD9335_CDC_RX_CLK_EN_MASK,
3217 WCD9335_CDC_RX_CLK_DISABLE);
3218 snd_soc_component_update_bits(comp, prim_int_reg,
3219 WCD9335_CDC_RX_RESET_MASK,
3220 WCD9335_CDC_RX_RESET_ENABLE);
3221 snd_soc_component_update_bits(comp, prim_int_reg,
3222 WCD9335_CDC_RX_RESET_MASK,
3223 WCD9335_CDC_RX_RESET_DISABLE);
3224 wcd9335_codec_hd2_control(comp, prim_int_reg, event);
3225 }
3226 break;
3227 }
3228
3229 return 0;
3230 }
3231
wcd9335_config_compander(struct snd_soc_component * component,int interp_n,int event)3232 static int wcd9335_config_compander(struct snd_soc_component *component,
3233 int interp_n, int event)
3234 {
3235 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3236 int comp;
3237 u16 comp_ctl0_reg, rx_path_cfg0_reg;
3238
3239 /* EAR does not have compander */
3240 if (!interp_n)
3241 return 0;
3242
3243 comp = interp_n - 1;
3244 if (!wcd->comp_enabled[comp])
3245 return 0;
3246
3247 comp_ctl0_reg = WCD9335_CDC_COMPANDER1_CTL(comp);
3248 rx_path_cfg0_reg = WCD9335_CDC_RX1_RX_PATH_CFG(comp);
3249
3250 if (SND_SOC_DAPM_EVENT_ON(event)) {
3251 /* Enable Compander Clock */
3252 snd_soc_component_update_bits(component, comp_ctl0_reg,
3253 WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3254 WCD9335_CDC_COMPANDER_CLK_ENABLE);
3255 /* Reset comander */
3256 snd_soc_component_update_bits(component, comp_ctl0_reg,
3257 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3258 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3259 snd_soc_component_update_bits(component, comp_ctl0_reg,
3260 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3261 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3262 /* Enables DRE in this path */
3263 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3264 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3265 WCD9335_CDC_RX_PATH_CFG_CMP_ENABLE);
3266 }
3267
3268 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3269 snd_soc_component_update_bits(component, comp_ctl0_reg,
3270 WCD9335_CDC_COMPANDER_HALT_MASK,
3271 WCD9335_CDC_COMPANDER_HALT);
3272 snd_soc_component_update_bits(component, rx_path_cfg0_reg,
3273 WCD9335_CDC_RX_PATH_CFG_CMP_EN_MASK,
3274 WCD9335_CDC_RX_PATH_CFG_CMP_DISABLE);
3275
3276 snd_soc_component_update_bits(component, comp_ctl0_reg,
3277 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3278 WCD9335_CDC_COMPANDER_SOFT_RST_ENABLE);
3279 snd_soc_component_update_bits(component, comp_ctl0_reg,
3280 WCD9335_CDC_COMPANDER_SOFT_RST_MASK,
3281 WCD9335_CDC_COMPANDER_SOFT_RST_DISABLE);
3282 snd_soc_component_update_bits(component, comp_ctl0_reg,
3283 WCD9335_CDC_COMPANDER_CLK_EN_MASK,
3284 WCD9335_CDC_COMPANDER_CLK_DISABLE);
3285 snd_soc_component_update_bits(component, comp_ctl0_reg,
3286 WCD9335_CDC_COMPANDER_HALT_MASK,
3287 WCD9335_CDC_COMPANDER_NOHALT);
3288 }
3289
3290 return 0;
3291 }
3292
wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3293 static int wcd9335_codec_enable_interpolator(struct snd_soc_dapm_widget *w,
3294 struct snd_kcontrol *kc, int event)
3295 {
3296 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3297 u16 gain_reg;
3298 u16 reg;
3299 int val;
3300 int offset_val = 0;
3301
3302 if (!(strcmp(w->name, "RX INT0 INTERP"))) {
3303 reg = WCD9335_CDC_RX0_RX_PATH_CTL;
3304 gain_reg = WCD9335_CDC_RX0_RX_VOL_CTL;
3305 } else if (!(strcmp(w->name, "RX INT1 INTERP"))) {
3306 reg = WCD9335_CDC_RX1_RX_PATH_CTL;
3307 gain_reg = WCD9335_CDC_RX1_RX_VOL_CTL;
3308 } else if (!(strcmp(w->name, "RX INT2 INTERP"))) {
3309 reg = WCD9335_CDC_RX2_RX_PATH_CTL;
3310 gain_reg = WCD9335_CDC_RX2_RX_VOL_CTL;
3311 } else if (!(strcmp(w->name, "RX INT3 INTERP"))) {
3312 reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3313 gain_reg = WCD9335_CDC_RX3_RX_VOL_CTL;
3314 } else if (!(strcmp(w->name, "RX INT4 INTERP"))) {
3315 reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3316 gain_reg = WCD9335_CDC_RX4_RX_VOL_CTL;
3317 } else if (!(strcmp(w->name, "RX INT5 INTERP"))) {
3318 reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3319 gain_reg = WCD9335_CDC_RX5_RX_VOL_CTL;
3320 } else if (!(strcmp(w->name, "RX INT6 INTERP"))) {
3321 reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3322 gain_reg = WCD9335_CDC_RX6_RX_VOL_CTL;
3323 } else if (!(strcmp(w->name, "RX INT7 INTERP"))) {
3324 reg = WCD9335_CDC_RX7_RX_PATH_CTL;
3325 gain_reg = WCD9335_CDC_RX7_RX_VOL_CTL;
3326 } else if (!(strcmp(w->name, "RX INT8 INTERP"))) {
3327 reg = WCD9335_CDC_RX8_RX_PATH_CTL;
3328 gain_reg = WCD9335_CDC_RX8_RX_VOL_CTL;
3329 } else {
3330 dev_err(comp->dev, "%s: Interpolator reg not found\n",
3331 __func__);
3332 return -EINVAL;
3333 }
3334
3335 switch (event) {
3336 case SND_SOC_DAPM_PRE_PMU:
3337 /* Reset if needed */
3338 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3339 break;
3340 case SND_SOC_DAPM_POST_PMU:
3341 wcd9335_config_compander(comp, w->shift, event);
3342 val = snd_soc_component_read(comp, gain_reg);
3343 val += offset_val;
3344 snd_soc_component_write(comp, gain_reg, val);
3345 break;
3346 case SND_SOC_DAPM_POST_PMD:
3347 wcd9335_config_compander(comp, w->shift, event);
3348 wcd9335_codec_enable_prim_interpolator(comp, reg, event);
3349 break;
3350 }
3351
3352 return 0;
3353 }
3354
wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component * component,u8 gain)3355 static void wcd9335_codec_hph_mode_gain_opt(struct snd_soc_component *component,
3356 u8 gain)
3357 {
3358 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
3359 u8 hph_l_en, hph_r_en;
3360 u8 l_val, r_val;
3361 u8 hph_pa_status;
3362 bool is_hphl_pa, is_hphr_pa;
3363
3364 hph_pa_status = snd_soc_component_read(component, WCD9335_ANA_HPH);
3365 is_hphl_pa = hph_pa_status >> 7;
3366 is_hphr_pa = (hph_pa_status & 0x40) >> 6;
3367
3368 hph_l_en = snd_soc_component_read(component, WCD9335_HPH_L_EN);
3369 hph_r_en = snd_soc_component_read(component, WCD9335_HPH_R_EN);
3370
3371 l_val = (hph_l_en & 0xC0) | 0x20 | gain;
3372 r_val = (hph_r_en & 0xC0) | 0x20 | gain;
3373
3374 /*
3375 * Set HPH_L & HPH_R gain source selection to REGISTER
3376 * for better click and pop only if corresponding PAs are
3377 * not enabled. Also cache the values of the HPHL/R
3378 * PA gains to be applied after PAs are enabled
3379 */
3380 if ((l_val != hph_l_en) && !is_hphl_pa) {
3381 snd_soc_component_write(component, WCD9335_HPH_L_EN, l_val);
3382 wcd->hph_l_gain = hph_l_en & 0x1F;
3383 }
3384
3385 if ((r_val != hph_r_en) && !is_hphr_pa) {
3386 snd_soc_component_write(component, WCD9335_HPH_R_EN, r_val);
3387 wcd->hph_r_gain = hph_r_en & 0x1F;
3388 }
3389 }
3390
wcd9335_codec_hph_lohifi_config(struct snd_soc_component * comp,int event)3391 static void wcd9335_codec_hph_lohifi_config(struct snd_soc_component *comp,
3392 int event)
3393 {
3394 if (SND_SOC_DAPM_EVENT_ON(event)) {
3395 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3396 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3397 0x06);
3398 snd_soc_component_update_bits(comp,
3399 WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3400 0xF0, 0x40);
3401 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3402 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3403 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3404 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3405 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3406 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3407 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3408 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3409 0x0C);
3410 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3411 }
3412
3413 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3414 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3415 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3416 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3417 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3418 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3419 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3420 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDACBUFF_CNP2,
3421 0x8A);
3422 snd_soc_component_update_bits(comp, WCD9335_RX_BIAS_HPH_PA,
3423 WCD9335_RX_BIAS_HPH_PA_AMP_5_UA_MASK,
3424 0x0A);
3425 }
3426 }
3427
wcd9335_codec_hph_lp_config(struct snd_soc_component * comp,int event)3428 static void wcd9335_codec_hph_lp_config(struct snd_soc_component *comp,
3429 int event)
3430 {
3431 if (SND_SOC_DAPM_EVENT_ON(event)) {
3432 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3433 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3434 0x0C);
3435 wcd9335_codec_hph_mode_gain_opt(comp, 0x10);
3436 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3437 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3438 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3439 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3440 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3441 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3442 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3443 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3444 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_ENABLE);
3445 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3446 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3447 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENABLE);
3448 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3449 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_MASK,
3450 WCD9335_HPH_RDAC_N1P65_LD_OUTCTL_V_N1P60);
3451 snd_soc_component_update_bits(comp, WCD9335_HPH_RDAC_LDO_CTL,
3452 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_MASK,
3453 WCD9335_HPH_RDAC_1P65_LD_OUTCTL_V_N1P60);
3454 snd_soc_component_update_bits(comp,
3455 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0x0F, 0x01);
3456 snd_soc_component_update_bits(comp,
3457 WCD9335_RX_BIAS_HPH_RDAC_LDO, 0xF0, 0x10);
3458 }
3459
3460 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3461 snd_soc_component_write(comp, WCD9335_RX_BIAS_HPH_RDAC_LDO,
3462 0x88);
3463 snd_soc_component_write(comp, WCD9335_HPH_RDAC_LDO_CTL,
3464 0x33);
3465 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3466 WCD9335_HPH_PA_CTL2_HPH_PSRR_ENH_MASK,
3467 WCD9335_HPH_PA_CTL2_HPH_PSRR_DISABLE);
3468 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3469 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_MASK,
3470 WCD9335_HPH_PA_CTL2_FORCE_PSRREH_DISABLE);
3471 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3472 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3473 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3474 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3475 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3476 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3477 snd_soc_component_update_bits(comp, WCD9335_HPH_R_EN,
3478 WCD9335_HPH_CONST_SEL_L_MASK,
3479 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3480 snd_soc_component_update_bits(comp, WCD9335_HPH_L_EN,
3481 WCD9335_HPH_CONST_SEL_L_MASK,
3482 WCD9335_HPH_CONST_SEL_L_HQ_PATH);
3483 }
3484 }
3485
wcd9335_codec_hph_hifi_config(struct snd_soc_component * comp,int event)3486 static void wcd9335_codec_hph_hifi_config(struct snd_soc_component *comp,
3487 int event)
3488 {
3489 if (SND_SOC_DAPM_EVENT_ON(event)) {
3490 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3491 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3492 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_1000);
3493 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3494 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3495 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_ENABLE);
3496 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL1,
3497 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3498 0x0C);
3499 wcd9335_codec_hph_mode_gain_opt(comp, 0x11);
3500 }
3501
3502 if (SND_SOC_DAPM_EVENT_OFF(event)) {
3503 snd_soc_component_update_bits(comp, WCD9335_HPH_PA_CTL2,
3504 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_MASK,
3505 WCD9335_HPH_PA_CTL2_FORCE_IQCTRL_DISABLE);
3506 snd_soc_component_update_bits(comp, WCD9335_HPH_CNP_WG_CTL,
3507 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_MASK,
3508 WCD9335_HPH_CNP_WG_CTL_CURR_LDIV_RATIO_500);
3509 }
3510 }
3511
wcd9335_codec_hph_mode_config(struct snd_soc_component * component,int event,int mode)3512 static void wcd9335_codec_hph_mode_config(struct snd_soc_component *component,
3513 int event, int mode)
3514 {
3515 switch (mode) {
3516 case CLS_H_LP:
3517 wcd9335_codec_hph_lp_config(component, event);
3518 break;
3519 case CLS_H_LOHIFI:
3520 wcd9335_codec_hph_lohifi_config(component, event);
3521 break;
3522 case CLS_H_HIFI:
3523 wcd9335_codec_hph_hifi_config(component, event);
3524 break;
3525 }
3526 }
3527
wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3528 static int wcd9335_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
3529 struct snd_kcontrol *kc,
3530 int event)
3531 {
3532 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3533 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3534 int hph_mode = wcd->hph_mode;
3535 u8 dem_inp;
3536
3537 switch (event) {
3538 case SND_SOC_DAPM_PRE_PMU:
3539 /* Read DEM INP Select */
3540 dem_inp = snd_soc_component_read(comp,
3541 WCD9335_CDC_RX1_RX_PATH_SEC0) & 0x03;
3542 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3543 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3544 dev_err(comp->dev, "Incorrect DEM Input\n");
3545 return -EINVAL;
3546 }
3547 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3548 WCD_CLSH_STATE_HPHL,
3549 ((hph_mode == CLS_H_LOHIFI) ?
3550 CLS_H_HIFI : hph_mode));
3551
3552 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3553
3554 break;
3555 case SND_SOC_DAPM_POST_PMU:
3556 usleep_range(1000, 1100);
3557 break;
3558 case SND_SOC_DAPM_PRE_PMD:
3559 break;
3560 case SND_SOC_DAPM_POST_PMD:
3561 /* 1000us required as per HW requirement */
3562 usleep_range(1000, 1100);
3563
3564 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3565 WCD_CLSH_STATE_HPHR))
3566 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3567
3568 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3569 WCD_CLSH_STATE_HPHL,
3570 ((hph_mode == CLS_H_LOHIFI) ?
3571 CLS_H_HIFI : hph_mode));
3572 break;
3573 }
3574
3575 return 0;
3576 }
3577
wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3578 static int wcd9335_codec_lineout_dac_event(struct snd_soc_dapm_widget *w,
3579 struct snd_kcontrol *kc, int event)
3580 {
3581 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3582 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3583
3584 switch (event) {
3585 case SND_SOC_DAPM_PRE_PMU:
3586 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3587 WCD_CLSH_STATE_LO, CLS_AB);
3588 break;
3589 case SND_SOC_DAPM_POST_PMD:
3590 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3591 WCD_CLSH_STATE_LO, CLS_AB);
3592 break;
3593 }
3594
3595 return 0;
3596 }
3597
wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3598 static int wcd9335_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
3599 struct snd_kcontrol *kc, int event)
3600 {
3601 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3602 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3603
3604 switch (event) {
3605 case SND_SOC_DAPM_PRE_PMU:
3606 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_PRE_DAC,
3607 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3608
3609 break;
3610 case SND_SOC_DAPM_POST_PMD:
3611 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3612 WCD_CLSH_STATE_EAR, CLS_H_NORMAL);
3613 break;
3614 }
3615
3616 return 0;
3617 }
3618
wcd9335_codec_hph_post_pa_config(struct wcd9335_codec * wcd,int mode,int event)3619 static void wcd9335_codec_hph_post_pa_config(struct wcd9335_codec *wcd,
3620 int mode, int event)
3621 {
3622 u8 scale_val = 0;
3623
3624 switch (event) {
3625 case SND_SOC_DAPM_POST_PMU:
3626 switch (mode) {
3627 case CLS_H_HIFI:
3628 scale_val = 0x3;
3629 break;
3630 case CLS_H_LOHIFI:
3631 scale_val = 0x1;
3632 break;
3633 }
3634 break;
3635 case SND_SOC_DAPM_PRE_PMD:
3636 scale_val = 0x6;
3637 break;
3638 }
3639
3640 if (scale_val)
3641 snd_soc_component_update_bits(wcd->component,
3642 WCD9335_HPH_PA_CTL1,
3643 WCD9335_HPH_PA_GM3_IB_SCALE_MASK,
3644 scale_val << 1);
3645 if (SND_SOC_DAPM_EVENT_ON(event)) {
3646 if (wcd->comp_enabled[COMPANDER_1] ||
3647 wcd->comp_enabled[COMPANDER_2]) {
3648 /* GAIN Source Selection */
3649 snd_soc_component_update_bits(wcd->component,
3650 WCD9335_HPH_L_EN,
3651 WCD9335_HPH_GAIN_SRC_SEL_MASK,
3652 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3653 snd_soc_component_update_bits(wcd->component,
3654 WCD9335_HPH_R_EN,
3655 WCD9335_HPH_GAIN_SRC_SEL_MASK,
3656 WCD9335_HPH_GAIN_SRC_SEL_COMPANDER);
3657 snd_soc_component_update_bits(wcd->component,
3658 WCD9335_HPH_AUTO_CHOP,
3659 WCD9335_HPH_AUTO_CHOP_MASK,
3660 WCD9335_HPH_AUTO_CHOP_FORCE_ENABLE);
3661 }
3662 snd_soc_component_update_bits(wcd->component,
3663 WCD9335_HPH_L_EN,
3664 WCD9335_HPH_PA_GAIN_MASK,
3665 wcd->hph_l_gain);
3666 snd_soc_component_update_bits(wcd->component,
3667 WCD9335_HPH_R_EN,
3668 WCD9335_HPH_PA_GAIN_MASK,
3669 wcd->hph_r_gain);
3670 }
3671
3672 if (SND_SOC_DAPM_EVENT_OFF(event))
3673 snd_soc_component_update_bits(wcd->component,
3674 WCD9335_HPH_AUTO_CHOP,
3675 WCD9335_HPH_AUTO_CHOP_MASK,
3676 WCD9335_HPH_AUTO_CHOP_ENABLE_BY_CMPDR_GAIN);
3677 }
3678
wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3679 static int wcd9335_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
3680 struct snd_kcontrol *kc,
3681 int event)
3682 {
3683 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3684 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3685 int hph_mode = wcd->hph_mode;
3686 u8 dem_inp;
3687
3688 switch (event) {
3689 case SND_SOC_DAPM_PRE_PMU:
3690
3691 /* Read DEM INP Select */
3692 dem_inp = snd_soc_component_read(comp,
3693 WCD9335_CDC_RX2_RX_PATH_SEC0) &
3694 WCD9335_CDC_RX_PATH_DEM_INP_SEL_MASK;
3695 if (((hph_mode == CLS_H_HIFI) || (hph_mode == CLS_H_LOHIFI) ||
3696 (hph_mode == CLS_H_LP)) && (dem_inp != 0x01)) {
3697 dev_err(comp->dev, "DEM Input not set correctly, hph_mode: %d\n",
3698 hph_mode);
3699 return -EINVAL;
3700 }
3701
3702 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl,
3703 WCD_CLSH_EVENT_PRE_DAC,
3704 WCD_CLSH_STATE_HPHR,
3705 ((hph_mode == CLS_H_LOHIFI) ?
3706 CLS_H_HIFI : hph_mode));
3707
3708 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3709
3710 break;
3711 case SND_SOC_DAPM_POST_PMD:
3712 /* 1000us required as per HW requirement */
3713 usleep_range(1000, 1100);
3714
3715 if (!(wcd_clsh_ctrl_get_state(wcd->clsh_ctrl) &
3716 WCD_CLSH_STATE_HPHL))
3717 wcd9335_codec_hph_mode_config(comp, event, hph_mode);
3718
3719 wcd_clsh_ctrl_set_state(wcd->clsh_ctrl, WCD_CLSH_EVENT_POST_PA,
3720 WCD_CLSH_STATE_HPHR, ((hph_mode == CLS_H_LOHIFI) ?
3721 CLS_H_HIFI : hph_mode));
3722 break;
3723 }
3724
3725 return 0;
3726 }
3727
wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3728 static int wcd9335_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
3729 struct snd_kcontrol *kc,
3730 int event)
3731 {
3732 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3733 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3734 int hph_mode = wcd->hph_mode;
3735
3736 switch (event) {
3737 case SND_SOC_DAPM_PRE_PMU:
3738 break;
3739 case SND_SOC_DAPM_POST_PMU:
3740 /*
3741 * 7ms sleep is required after PA is enabled as per
3742 * HW requirement
3743 */
3744 usleep_range(7000, 7100);
3745
3746 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3747 snd_soc_component_update_bits(comp,
3748 WCD9335_CDC_RX1_RX_PATH_CTL,
3749 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3750 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3751
3752 /* Remove mix path mute if it is enabled */
3753 if ((snd_soc_component_read(comp,
3754 WCD9335_CDC_RX1_RX_PATH_MIX_CTL)) &
3755 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3756 snd_soc_component_update_bits(comp,
3757 WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
3758 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3759 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3760
3761 break;
3762 case SND_SOC_DAPM_PRE_PMD:
3763 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3764 break;
3765 case SND_SOC_DAPM_POST_PMD:
3766 /* 5ms sleep is required after PA is disabled as per
3767 * HW requirement
3768 */
3769 usleep_range(5000, 5500);
3770 break;
3771 }
3772
3773 return 0;
3774 }
3775
wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3776 static int wcd9335_codec_enable_lineout_pa(struct snd_soc_dapm_widget *w,
3777 struct snd_kcontrol *kc,
3778 int event)
3779 {
3780 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3781 int vol_reg = 0, mix_vol_reg = 0;
3782
3783 if (w->reg == WCD9335_ANA_LO_1_2) {
3784 if (w->shift == 7) {
3785 vol_reg = WCD9335_CDC_RX3_RX_PATH_CTL;
3786 mix_vol_reg = WCD9335_CDC_RX3_RX_PATH_MIX_CTL;
3787 } else if (w->shift == 6) {
3788 vol_reg = WCD9335_CDC_RX4_RX_PATH_CTL;
3789 mix_vol_reg = WCD9335_CDC_RX4_RX_PATH_MIX_CTL;
3790 }
3791 } else if (w->reg == WCD9335_ANA_LO_3_4) {
3792 if (w->shift == 7) {
3793 vol_reg = WCD9335_CDC_RX5_RX_PATH_CTL;
3794 mix_vol_reg = WCD9335_CDC_RX5_RX_PATH_MIX_CTL;
3795 } else if (w->shift == 6) {
3796 vol_reg = WCD9335_CDC_RX6_RX_PATH_CTL;
3797 mix_vol_reg = WCD9335_CDC_RX6_RX_PATH_MIX_CTL;
3798 }
3799 } else {
3800 dev_err(comp->dev, "Error enabling lineout PA\n");
3801 return -EINVAL;
3802 }
3803
3804 switch (event) {
3805 case SND_SOC_DAPM_POST_PMU:
3806 /* 5ms sleep is required after PA is enabled as per
3807 * HW requirement
3808 */
3809 usleep_range(5000, 5500);
3810 snd_soc_component_update_bits(comp, vol_reg,
3811 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3812 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3813
3814 /* Remove mix path mute if it is enabled */
3815 if ((snd_soc_component_read(comp, mix_vol_reg)) &
3816 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3817 snd_soc_component_update_bits(comp, mix_vol_reg,
3818 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3819 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3820 break;
3821 case SND_SOC_DAPM_POST_PMD:
3822 /* 5ms sleep is required after PA is disabled as per
3823 * HW requirement
3824 */
3825 usleep_range(5000, 5500);
3826 break;
3827 }
3828
3829 return 0;
3830 }
3831
wcd9335_codec_init_flyback(struct snd_soc_component * component)3832 static void wcd9335_codec_init_flyback(struct snd_soc_component *component)
3833 {
3834 snd_soc_component_update_bits(component, WCD9335_HPH_L_EN,
3835 WCD9335_HPH_CONST_SEL_L_MASK,
3836 WCD9335_HPH_CONST_SEL_L_BYPASS);
3837 snd_soc_component_update_bits(component, WCD9335_HPH_R_EN,
3838 WCD9335_HPH_CONST_SEL_L_MASK,
3839 WCD9335_HPH_CONST_SEL_L_BYPASS);
3840 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3841 WCD9335_RX_BIAS_FLYB_VPOS_5_UA_MASK,
3842 WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3843 snd_soc_component_update_bits(component, WCD9335_RX_BIAS_FLYB_BUFF,
3844 WCD9335_RX_BIAS_FLYB_VNEG_5_UA_MASK,
3845 WCD9335_RX_BIAS_FLYB_I_0P0_UA);
3846 }
3847
wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3848 static int wcd9335_codec_enable_rx_bias(struct snd_soc_dapm_widget *w,
3849 struct snd_kcontrol *kc, int event)
3850 {
3851 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3852 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3853
3854 switch (event) {
3855 case SND_SOC_DAPM_PRE_PMU:
3856 wcd->rx_bias_count++;
3857 if (wcd->rx_bias_count == 1) {
3858 wcd9335_codec_init_flyback(comp);
3859 snd_soc_component_update_bits(comp,
3860 WCD9335_ANA_RX_SUPPLIES,
3861 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3862 WCD9335_ANA_RX_BIAS_ENABLE);
3863 }
3864 break;
3865 case SND_SOC_DAPM_POST_PMD:
3866 wcd->rx_bias_count--;
3867 if (!wcd->rx_bias_count)
3868 snd_soc_component_update_bits(comp,
3869 WCD9335_ANA_RX_SUPPLIES,
3870 WCD9335_ANA_RX_BIAS_ENABLE_MASK,
3871 WCD9335_ANA_RX_BIAS_DISABLE);
3872 break;
3873 }
3874
3875 return 0;
3876 }
3877
wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3878 static int wcd9335_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
3879 struct snd_kcontrol *kc, int event)
3880 {
3881 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3882 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
3883 int hph_mode = wcd->hph_mode;
3884
3885 switch (event) {
3886 case SND_SOC_DAPM_PRE_PMU:
3887 break;
3888 case SND_SOC_DAPM_POST_PMU:
3889 /*
3890 * 7ms sleep is required after PA is enabled as per
3891 * HW requirement
3892 */
3893 usleep_range(7000, 7100);
3894 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3895 snd_soc_component_update_bits(comp,
3896 WCD9335_CDC_RX2_RX_PATH_CTL,
3897 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3898 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3899 /* Remove mix path mute if it is enabled */
3900 if ((snd_soc_component_read(comp,
3901 WCD9335_CDC_RX2_RX_PATH_MIX_CTL)) &
3902 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3903 snd_soc_component_update_bits(comp,
3904 WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
3905 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3906 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3907
3908 break;
3909
3910 case SND_SOC_DAPM_PRE_PMD:
3911 wcd9335_codec_hph_post_pa_config(wcd, hph_mode, event);
3912 break;
3913 case SND_SOC_DAPM_POST_PMD:
3914 /* 5ms sleep is required after PA is disabled as per
3915 * HW requirement
3916 */
3917 usleep_range(5000, 5500);
3918 break;
3919 }
3920
3921 return 0;
3922 }
3923
wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)3924 static int wcd9335_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
3925 struct snd_kcontrol *kc, int event)
3926 {
3927 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
3928
3929 switch (event) {
3930 case SND_SOC_DAPM_POST_PMU:
3931 /* 5ms sleep is required after PA is enabled as per
3932 * HW requirement
3933 */
3934 usleep_range(5000, 5500);
3935 snd_soc_component_update_bits(comp,
3936 WCD9335_CDC_RX0_RX_PATH_CTL,
3937 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3938 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3939 /* Remove mix path mute if it is enabled */
3940 if ((snd_soc_component_read(comp,
3941 WCD9335_CDC_RX0_RX_PATH_MIX_CTL)) &
3942 WCD9335_CDC_RX_PGA_MUTE_EN_MASK)
3943 snd_soc_component_update_bits(comp,
3944 WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
3945 WCD9335_CDC_RX_PGA_MUTE_EN_MASK,
3946 WCD9335_CDC_RX_PGA_MUTE_DISABLE);
3947 break;
3948 case SND_SOC_DAPM_POST_PMD:
3949 /* 5ms sleep is required after PA is disabled as per
3950 * HW requirement
3951 */
3952 usleep_range(5000, 5500);
3953
3954 break;
3955 }
3956
3957 return 0;
3958 }
3959
wcd9335_slimbus_irq(int irq,void * data)3960 static irqreturn_t wcd9335_slimbus_irq(int irq, void *data)
3961 {
3962 struct wcd9335_codec *wcd = data;
3963 unsigned long status = 0;
3964 int i, j, port_id;
3965 unsigned int val, int_val = 0;
3966 irqreturn_t ret = IRQ_NONE;
3967 bool tx;
3968 unsigned short reg = 0;
3969
3970 for (i = WCD9335_SLIM_PGD_PORT_INT_STATUS_RX_0, j = 0;
3971 i <= WCD9335_SLIM_PGD_PORT_INT_STATUS_TX_1; i++, j++) {
3972 regmap_read(wcd->if_regmap, i, &val);
3973 status |= ((u32)val << (8 * j));
3974 }
3975
3976 for_each_set_bit(j, &status, 32) {
3977 tx = (j >= 16);
3978 port_id = (tx ? j - 16 : j);
3979 regmap_read(wcd->if_regmap,
3980 WCD9335_SLIM_PGD_PORT_INT_RX_SOURCE0 + j, &val);
3981 if (val) {
3982 if (!tx)
3983 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
3984 (port_id / 8);
3985 else
3986 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
3987 (port_id / 8);
3988 regmap_read(
3989 wcd->if_regmap, reg, &int_val);
3990 /*
3991 * Ignore interrupts for ports for which the
3992 * interrupts are not specifically enabled.
3993 */
3994 if (!(int_val & (1 << (port_id % 8))))
3995 continue;
3996 }
3997
3998 if (val & WCD9335_SLIM_IRQ_OVERFLOW)
3999 dev_err_ratelimited(wcd->dev,
4000 "%s: overflow error on %s port %d, value %x\n",
4001 __func__, (tx ? "TX" : "RX"), port_id, val);
4002
4003 if (val & WCD9335_SLIM_IRQ_UNDERFLOW)
4004 dev_err_ratelimited(wcd->dev,
4005 "%s: underflow error on %s port %d, value %x\n",
4006 __func__, (tx ? "TX" : "RX"), port_id, val);
4007
4008 if ((val & WCD9335_SLIM_IRQ_OVERFLOW) ||
4009 (val & WCD9335_SLIM_IRQ_UNDERFLOW)) {
4010 if (!tx)
4011 reg = WCD9335_SLIM_PGD_PORT_INT_EN0 +
4012 (port_id / 8);
4013 else
4014 reg = WCD9335_SLIM_PGD_PORT_INT_TX_EN0 +
4015 (port_id / 8);
4016 regmap_read(
4017 wcd->if_regmap, reg, &int_val);
4018 if (int_val & (1 << (port_id % 8))) {
4019 int_val = int_val ^ (1 << (port_id % 8));
4020 regmap_write(wcd->if_regmap,
4021 reg, int_val);
4022 }
4023 }
4024
4025 regmap_write(wcd->if_regmap,
4026 WCD9335_SLIM_PGD_PORT_INT_CLR_RX_0 + (j / 8),
4027 BIT(j % 8));
4028 ret = IRQ_HANDLED;
4029 }
4030
4031 return ret;
4032 }
4033
4034 static struct wcd9335_irq wcd9335_irqs[] = {
4035 {
4036 .irq = WCD9335_IRQ_SLIMBUS,
4037 .handler = wcd9335_slimbus_irq,
4038 .name = "SLIM Slave",
4039 },
4040 };
4041
wcd9335_setup_irqs(struct wcd9335_codec * wcd)4042 static int wcd9335_setup_irqs(struct wcd9335_codec *wcd)
4043 {
4044 int irq, ret, i;
4045
4046 for (i = 0; i < ARRAY_SIZE(wcd9335_irqs); i++) {
4047 irq = regmap_irq_get_virq(wcd->irq_data, wcd9335_irqs[i].irq);
4048 if (irq < 0) {
4049 dev_err(wcd->dev, "Failed to get %s\n",
4050 wcd9335_irqs[i].name);
4051 return irq;
4052 }
4053
4054 ret = devm_request_threaded_irq(wcd->dev, irq, NULL,
4055 wcd9335_irqs[i].handler,
4056 IRQF_TRIGGER_RISING |
4057 IRQF_ONESHOT,
4058 wcd9335_irqs[i].name, wcd);
4059 if (ret) {
4060 dev_err(wcd->dev, "Failed to request %s\n",
4061 wcd9335_irqs[i].name);
4062 return ret;
4063 }
4064 }
4065
4066 /* enable interrupts on all slave ports */
4067 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4068 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4069 0xFF);
4070
4071 return ret;
4072 }
4073
wcd9335_teardown_irqs(struct wcd9335_codec * wcd)4074 static void wcd9335_teardown_irqs(struct wcd9335_codec *wcd)
4075 {
4076 int i;
4077
4078 /* disable interrupts on all slave ports */
4079 for (i = 0; i < WCD9335_SLIM_NUM_PORT_REG; i++)
4080 regmap_write(wcd->if_regmap, WCD9335_SLIM_PGD_PORT_INT_EN0 + i,
4081 0x00);
4082 }
4083
wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec * wcd,bool ccl_flag)4084 static void wcd9335_cdc_sido_ccl_enable(struct wcd9335_codec *wcd,
4085 bool ccl_flag)
4086 {
4087 struct snd_soc_component *comp = wcd->component;
4088
4089 if (ccl_flag) {
4090 if (++wcd->sido_ccl_cnt == 1)
4091 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4092 WCD9335_SIDO_SIDO_CCL_DEF_VALUE);
4093 } else {
4094 if (wcd->sido_ccl_cnt == 0) {
4095 dev_err(wcd->dev, "sido_ccl already disabled\n");
4096 return;
4097 }
4098 if (--wcd->sido_ccl_cnt == 0)
4099 snd_soc_component_write(comp, WCD9335_SIDO_SIDO_CCL_10,
4100 WCD9335_SIDO_SIDO_CCL_10_ICHARG_PWR_SEL_C320FF);
4101 }
4102 }
4103
wcd9335_enable_master_bias(struct wcd9335_codec * wcd)4104 static int wcd9335_enable_master_bias(struct wcd9335_codec *wcd)
4105 {
4106 wcd->master_bias_users++;
4107 if (wcd->master_bias_users == 1) {
4108 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4109 WCD9335_ANA_BIAS_EN_MASK,
4110 WCD9335_ANA_BIAS_ENABLE);
4111 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4112 WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4113 WCD9335_ANA_BIAS_PRECHRG_ENABLE);
4114 /*
4115 * 1ms delay is required after pre-charge is enabled
4116 * as per HW requirement
4117 */
4118 usleep_range(1000, 1100);
4119 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4120 WCD9335_ANA_BIAS_PRECHRG_EN_MASK,
4121 WCD9335_ANA_BIAS_PRECHRG_DISABLE);
4122 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4123 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4124 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4125 }
4126
4127 return 0;
4128 }
4129
wcd9335_enable_mclk(struct wcd9335_codec * wcd)4130 static int wcd9335_enable_mclk(struct wcd9335_codec *wcd)
4131 {
4132 /* Enable mclk requires master bias to be enabled first */
4133 if (wcd->master_bias_users <= 0)
4134 return -EINVAL;
4135
4136 if (((wcd->clk_mclk_users == 0) && (wcd->clk_type == WCD_CLK_MCLK)) ||
4137 ((wcd->clk_mclk_users > 0) && (wcd->clk_type != WCD_CLK_MCLK))) {
4138 dev_err(wcd->dev, "Error enabling MCLK, clk_type: %d\n",
4139 wcd->clk_type);
4140 return -EINVAL;
4141 }
4142
4143 if (++wcd->clk_mclk_users == 1) {
4144 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4145 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4146 WCD9335_ANA_CLK_EXT_CLKBUF_ENABLE);
4147 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4148 WCD9335_ANA_CLK_MCLK_SRC_MASK,
4149 WCD9335_ANA_CLK_MCLK_SRC_EXTERNAL);
4150 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4151 WCD9335_ANA_CLK_MCLK_EN_MASK,
4152 WCD9335_ANA_CLK_MCLK_ENABLE);
4153 regmap_update_bits(wcd->regmap,
4154 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,
4155 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_EN_MASK,
4156 WCD9335_CDC_CLK_RST_CTRL_FS_CNT_ENABLE);
4157 regmap_update_bits(wcd->regmap,
4158 WCD9335_CDC_CLK_RST_CTRL_MCLK_CONTROL,
4159 WCD9335_CDC_CLK_RST_CTRL_MCLK_EN_MASK,
4160 WCD9335_CDC_CLK_RST_CTRL_MCLK_ENABLE);
4161 /*
4162 * 10us sleep is required after clock is enabled
4163 * as per HW requirement
4164 */
4165 usleep_range(10, 15);
4166 }
4167
4168 wcd->clk_type = WCD_CLK_MCLK;
4169
4170 return 0;
4171 }
4172
wcd9335_disable_mclk(struct wcd9335_codec * wcd)4173 static int wcd9335_disable_mclk(struct wcd9335_codec *wcd)
4174 {
4175 if (wcd->clk_mclk_users <= 0)
4176 return -EINVAL;
4177
4178 if (--wcd->clk_mclk_users == 0) {
4179 if (wcd->clk_rco_users > 0) {
4180 /* MCLK to RCO switch */
4181 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4182 WCD9335_ANA_CLK_MCLK_SRC_MASK,
4183 WCD9335_ANA_CLK_MCLK_SRC_RCO);
4184 wcd->clk_type = WCD_CLK_RCO;
4185 } else {
4186 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4187 WCD9335_ANA_CLK_MCLK_EN_MASK,
4188 WCD9335_ANA_CLK_MCLK_DISABLE);
4189 wcd->clk_type = WCD_CLK_OFF;
4190 }
4191
4192 regmap_update_bits(wcd->regmap, WCD9335_ANA_CLK_TOP,
4193 WCD9335_ANA_CLK_EXT_CLKBUF_EN_MASK,
4194 WCD9335_ANA_CLK_EXT_CLKBUF_DISABLE);
4195 }
4196
4197 return 0;
4198 }
4199
wcd9335_disable_master_bias(struct wcd9335_codec * wcd)4200 static int wcd9335_disable_master_bias(struct wcd9335_codec *wcd)
4201 {
4202 if (wcd->master_bias_users <= 0)
4203 return -EINVAL;
4204
4205 wcd->master_bias_users--;
4206 if (wcd->master_bias_users == 0) {
4207 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4208 WCD9335_ANA_BIAS_EN_MASK,
4209 WCD9335_ANA_BIAS_DISABLE);
4210 regmap_update_bits(wcd->regmap, WCD9335_ANA_BIAS,
4211 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE,
4212 WCD9335_ANA_BIAS_PRECHRG_CTL_MODE_MANUAL);
4213 }
4214 return 0;
4215 }
4216
wcd9335_cdc_req_mclk_enable(struct wcd9335_codec * wcd,bool enable)4217 static int wcd9335_cdc_req_mclk_enable(struct wcd9335_codec *wcd,
4218 bool enable)
4219 {
4220 int ret = 0;
4221
4222 if (enable) {
4223 wcd9335_cdc_sido_ccl_enable(wcd, true);
4224 ret = clk_prepare_enable(wcd->mclk);
4225 if (ret) {
4226 dev_err(wcd->dev, "%s: ext clk enable failed\n",
4227 __func__);
4228 goto err;
4229 }
4230 /* get BG */
4231 wcd9335_enable_master_bias(wcd);
4232 /* get MCLK */
4233 wcd9335_enable_mclk(wcd);
4234
4235 } else {
4236 /* put MCLK */
4237 wcd9335_disable_mclk(wcd);
4238 /* put BG */
4239 wcd9335_disable_master_bias(wcd);
4240 clk_disable_unprepare(wcd->mclk);
4241 wcd9335_cdc_sido_ccl_enable(wcd, false);
4242 }
4243 err:
4244 return ret;
4245 }
4246
wcd9335_codec_apply_sido_voltage(struct wcd9335_codec * wcd,enum wcd9335_sido_voltage req_mv)4247 static void wcd9335_codec_apply_sido_voltage(struct wcd9335_codec *wcd,
4248 enum wcd9335_sido_voltage req_mv)
4249 {
4250 struct snd_soc_component *comp = wcd->component;
4251 int vout_d_val;
4252
4253 if (req_mv == wcd->sido_voltage)
4254 return;
4255
4256 /* compute the vout_d step value */
4257 vout_d_val = WCD9335_CALCULATE_VOUT_D(req_mv) &
4258 WCD9335_ANA_BUCK_VOUT_MASK;
4259 snd_soc_component_write(comp, WCD9335_ANA_BUCK_VOUT_D, vout_d_val);
4260 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4261 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4262 WCD9335_ANA_BUCK_CTL_RAMP_START_ENABLE);
4263
4264 /* 1 msec sleep required after SIDO Vout_D voltage change */
4265 usleep_range(1000, 1100);
4266 wcd->sido_voltage = req_mv;
4267 snd_soc_component_update_bits(comp, WCD9335_ANA_BUCK_CTL,
4268 WCD9335_ANA_BUCK_CTL_RAMP_START_MASK,
4269 WCD9335_ANA_BUCK_CTL_RAMP_START_DISABLE);
4270 }
4271
wcd9335_codec_update_sido_voltage(struct wcd9335_codec * wcd,enum wcd9335_sido_voltage req_mv)4272 static int wcd9335_codec_update_sido_voltage(struct wcd9335_codec *wcd,
4273 enum wcd9335_sido_voltage req_mv)
4274 {
4275 int ret = 0;
4276
4277 /* enable mclk before setting SIDO voltage */
4278 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4279 if (ret) {
4280 dev_err(wcd->dev, "Ext clk enable failed\n");
4281 goto err;
4282 }
4283
4284 wcd9335_codec_apply_sido_voltage(wcd, req_mv);
4285 wcd9335_cdc_req_mclk_enable(wcd, false);
4286
4287 err:
4288 return ret;
4289 }
4290
_wcd9335_codec_enable_mclk(struct snd_soc_component * component,int enable)4291 static int _wcd9335_codec_enable_mclk(struct snd_soc_component *component,
4292 int enable)
4293 {
4294 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4295 int ret;
4296
4297 if (enable) {
4298 ret = wcd9335_cdc_req_mclk_enable(wcd, true);
4299 if (ret)
4300 return ret;
4301
4302 wcd9335_codec_apply_sido_voltage(wcd,
4303 SIDO_VOLTAGE_NOMINAL_MV);
4304 } else {
4305 wcd9335_codec_update_sido_voltage(wcd,
4306 wcd->sido_voltage);
4307 wcd9335_cdc_req_mclk_enable(wcd, false);
4308 }
4309
4310 return 0;
4311 }
4312
wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kc,int event)4313 static int wcd9335_codec_enable_mclk(struct snd_soc_dapm_widget *w,
4314 struct snd_kcontrol *kc, int event)
4315 {
4316 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm);
4317
4318 switch (event) {
4319 case SND_SOC_DAPM_PRE_PMU:
4320 return _wcd9335_codec_enable_mclk(comp, true);
4321 case SND_SOC_DAPM_POST_PMD:
4322 return _wcd9335_codec_enable_mclk(comp, false);
4323 }
4324
4325 return 0;
4326 }
4327
4328 static const struct snd_soc_dapm_widget wcd9335_dapm_widgets[] = {
4329 /* TODO SPK1 & SPK2 OUT*/
4330 SND_SOC_DAPM_OUTPUT("EAR"),
4331 SND_SOC_DAPM_OUTPUT("HPHL"),
4332 SND_SOC_DAPM_OUTPUT("HPHR"),
4333 SND_SOC_DAPM_OUTPUT("LINEOUT1"),
4334 SND_SOC_DAPM_OUTPUT("LINEOUT2"),
4335 SND_SOC_DAPM_OUTPUT("LINEOUT3"),
4336 SND_SOC_DAPM_OUTPUT("LINEOUT4"),
4337 SND_SOC_DAPM_AIF_IN_E("AIF1 PB", "AIF1 Playback", 0, SND_SOC_NOPM,
4338 AIF1_PB, 0, wcd9335_codec_enable_slim,
4339 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4340 SND_SOC_DAPM_AIF_IN_E("AIF2 PB", "AIF2 Playback", 0, SND_SOC_NOPM,
4341 AIF2_PB, 0, wcd9335_codec_enable_slim,
4342 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4343 SND_SOC_DAPM_AIF_IN_E("AIF3 PB", "AIF3 Playback", 0, SND_SOC_NOPM,
4344 AIF3_PB, 0, wcd9335_codec_enable_slim,
4345 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4346 SND_SOC_DAPM_AIF_IN_E("AIF4 PB", "AIF4 Playback", 0, SND_SOC_NOPM,
4347 AIF4_PB, 0, wcd9335_codec_enable_slim,
4348 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4349 SND_SOC_DAPM_MUX("SLIM RX0 MUX", SND_SOC_NOPM, WCD9335_RX0, 0,
4350 &slim_rx_mux[WCD9335_RX0]),
4351 SND_SOC_DAPM_MUX("SLIM RX1 MUX", SND_SOC_NOPM, WCD9335_RX1, 0,
4352 &slim_rx_mux[WCD9335_RX1]),
4353 SND_SOC_DAPM_MUX("SLIM RX2 MUX", SND_SOC_NOPM, WCD9335_RX2, 0,
4354 &slim_rx_mux[WCD9335_RX2]),
4355 SND_SOC_DAPM_MUX("SLIM RX3 MUX", SND_SOC_NOPM, WCD9335_RX3, 0,
4356 &slim_rx_mux[WCD9335_RX3]),
4357 SND_SOC_DAPM_MUX("SLIM RX4 MUX", SND_SOC_NOPM, WCD9335_RX4, 0,
4358 &slim_rx_mux[WCD9335_RX4]),
4359 SND_SOC_DAPM_MUX("SLIM RX5 MUX", SND_SOC_NOPM, WCD9335_RX5, 0,
4360 &slim_rx_mux[WCD9335_RX5]),
4361 SND_SOC_DAPM_MUX("SLIM RX6 MUX", SND_SOC_NOPM, WCD9335_RX6, 0,
4362 &slim_rx_mux[WCD9335_RX6]),
4363 SND_SOC_DAPM_MUX("SLIM RX7 MUX", SND_SOC_NOPM, WCD9335_RX7, 0,
4364 &slim_rx_mux[WCD9335_RX7]),
4365 SND_SOC_DAPM_MIXER("SLIM RX0", SND_SOC_NOPM, 0, 0, NULL, 0),
4366 SND_SOC_DAPM_MIXER("SLIM RX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4367 SND_SOC_DAPM_MIXER("SLIM RX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4368 SND_SOC_DAPM_MIXER("SLIM RX3", SND_SOC_NOPM, 0, 0, NULL, 0),
4369 SND_SOC_DAPM_MIXER("SLIM RX4", SND_SOC_NOPM, 0, 0, NULL, 0),
4370 SND_SOC_DAPM_MIXER("SLIM RX5", SND_SOC_NOPM, 0, 0, NULL, 0),
4371 SND_SOC_DAPM_MIXER("SLIM RX6", SND_SOC_NOPM, 0, 0, NULL, 0),
4372 SND_SOC_DAPM_MIXER("SLIM RX7", SND_SOC_NOPM, 0, 0, NULL, 0),
4373 SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", WCD9335_CDC_RX0_RX_PATH_MIX_CTL,
4374 5, 0, &rx_int0_2_mux, wcd9335_codec_enable_mix_path,
4375 SND_SOC_DAPM_POST_PMU),
4376 SND_SOC_DAPM_MUX_E("RX INT1_2 MUX", WCD9335_CDC_RX1_RX_PATH_MIX_CTL,
4377 5, 0, &rx_int1_2_mux, wcd9335_codec_enable_mix_path,
4378 SND_SOC_DAPM_POST_PMU),
4379 SND_SOC_DAPM_MUX_E("RX INT2_2 MUX", WCD9335_CDC_RX2_RX_PATH_MIX_CTL,
4380 5, 0, &rx_int2_2_mux, wcd9335_codec_enable_mix_path,
4381 SND_SOC_DAPM_POST_PMU),
4382 SND_SOC_DAPM_MUX_E("RX INT3_2 MUX", WCD9335_CDC_RX3_RX_PATH_MIX_CTL,
4383 5, 0, &rx_int3_2_mux, wcd9335_codec_enable_mix_path,
4384 SND_SOC_DAPM_POST_PMU),
4385 SND_SOC_DAPM_MUX_E("RX INT4_2 MUX", WCD9335_CDC_RX4_RX_PATH_MIX_CTL,
4386 5, 0, &rx_int4_2_mux, wcd9335_codec_enable_mix_path,
4387 SND_SOC_DAPM_POST_PMU),
4388 SND_SOC_DAPM_MUX_E("RX INT5_2 MUX", WCD9335_CDC_RX5_RX_PATH_MIX_CTL,
4389 5, 0, &rx_int5_2_mux, wcd9335_codec_enable_mix_path,
4390 SND_SOC_DAPM_POST_PMU),
4391 SND_SOC_DAPM_MUX_E("RX INT6_2 MUX", WCD9335_CDC_RX6_RX_PATH_MIX_CTL,
4392 5, 0, &rx_int6_2_mux, wcd9335_codec_enable_mix_path,
4393 SND_SOC_DAPM_POST_PMU),
4394 SND_SOC_DAPM_MUX_E("RX INT7_2 MUX", WCD9335_CDC_RX7_RX_PATH_MIX_CTL,
4395 5, 0, &rx_int7_2_mux, wcd9335_codec_enable_mix_path,
4396 SND_SOC_DAPM_POST_PMU),
4397 SND_SOC_DAPM_MUX_E("RX INT8_2 MUX", WCD9335_CDC_RX8_RX_PATH_MIX_CTL,
4398 5, 0, &rx_int8_2_mux, wcd9335_codec_enable_mix_path,
4399 SND_SOC_DAPM_POST_PMU),
4400 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4401 &rx_int0_1_mix_inp0_mux),
4402 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4403 &rx_int0_1_mix_inp1_mux),
4404 SND_SOC_DAPM_MUX("RX INT0_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4405 &rx_int0_1_mix_inp2_mux),
4406 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4407 &rx_int1_1_mix_inp0_mux),
4408 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4409 &rx_int1_1_mix_inp1_mux),
4410 SND_SOC_DAPM_MUX("RX INT1_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4411 &rx_int1_1_mix_inp2_mux),
4412 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4413 &rx_int2_1_mix_inp0_mux),
4414 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4415 &rx_int2_1_mix_inp1_mux),
4416 SND_SOC_DAPM_MUX("RX INT2_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4417 &rx_int2_1_mix_inp2_mux),
4418 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4419 &rx_int3_1_mix_inp0_mux),
4420 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4421 &rx_int3_1_mix_inp1_mux),
4422 SND_SOC_DAPM_MUX("RX INT3_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4423 &rx_int3_1_mix_inp2_mux),
4424 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4425 &rx_int4_1_mix_inp0_mux),
4426 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4427 &rx_int4_1_mix_inp1_mux),
4428 SND_SOC_DAPM_MUX("RX INT4_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4429 &rx_int4_1_mix_inp2_mux),
4430 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4431 &rx_int5_1_mix_inp0_mux),
4432 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4433 &rx_int5_1_mix_inp1_mux),
4434 SND_SOC_DAPM_MUX("RX INT5_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4435 &rx_int5_1_mix_inp2_mux),
4436 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4437 &rx_int6_1_mix_inp0_mux),
4438 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4439 &rx_int6_1_mix_inp1_mux),
4440 SND_SOC_DAPM_MUX("RX INT6_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4441 &rx_int6_1_mix_inp2_mux),
4442 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4443 &rx_int7_1_mix_inp0_mux),
4444 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4445 &rx_int7_1_mix_inp1_mux),
4446 SND_SOC_DAPM_MUX("RX INT7_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4447 &rx_int7_1_mix_inp2_mux),
4448 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP0", SND_SOC_NOPM, 0, 0,
4449 &rx_int8_1_mix_inp0_mux),
4450 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP1", SND_SOC_NOPM, 0, 0,
4451 &rx_int8_1_mix_inp1_mux),
4452 SND_SOC_DAPM_MUX("RX INT8_1 MIX1 INP2", SND_SOC_NOPM, 0, 0,
4453 &rx_int8_1_mix_inp2_mux),
4454
4455 SND_SOC_DAPM_MIXER("RX INT0_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4456 SND_SOC_DAPM_MIXER("RX INT0 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4457 SND_SOC_DAPM_MIXER("RX INT1_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4458 SND_SOC_DAPM_MIXER("RX INT1 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4459 SND_SOC_DAPM_MIXER("RX INT2_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4460 SND_SOC_DAPM_MIXER("RX INT2 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4461 SND_SOC_DAPM_MIXER("RX INT3_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4462 SND_SOC_DAPM_MIXER("RX INT3 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4463 SND_SOC_DAPM_MIXER("RX INT4_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4464 SND_SOC_DAPM_MIXER("RX INT4 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4465 SND_SOC_DAPM_MIXER("RX INT5_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4466 SND_SOC_DAPM_MIXER("RX INT5 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4467 SND_SOC_DAPM_MIXER("RX INT6_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4468 SND_SOC_DAPM_MIXER("RX INT6 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4469 SND_SOC_DAPM_MIXER("RX INT7_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4470 SND_SOC_DAPM_MIXER("RX INT7 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4471 SND_SOC_DAPM_MIXER("RX INT8_1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0),
4472 SND_SOC_DAPM_MIXER("RX INT8 SEC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
4473
4474 SND_SOC_DAPM_MIXER("RX INT0 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4475 SND_SOC_DAPM_MIXER("RX INT1 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4476 SND_SOC_DAPM_MIXER("RX INT2 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4477 SND_SOC_DAPM_MIXER("RX INT3 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4478 SND_SOC_DAPM_MIXER("RX INT4 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4479 SND_SOC_DAPM_MIXER("RX INT5 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4480 SND_SOC_DAPM_MIXER("RX INT6 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4481 SND_SOC_DAPM_MIXER("RX INT7 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4482 SND_SOC_DAPM_MIXER("RX INT8 MIX2", SND_SOC_NOPM, 0, 0, NULL, 0),
4483
4484 SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
4485 &rx_int0_dem_inp_mux),
4486 SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
4487 &rx_int1_dem_inp_mux),
4488 SND_SOC_DAPM_MUX("RX INT2 DEM MUX", SND_SOC_NOPM, 0, 0,
4489 &rx_int2_dem_inp_mux),
4490
4491 SND_SOC_DAPM_MUX_E("RX INT0 INTERP", SND_SOC_NOPM,
4492 INTERP_EAR, 0, &rx_int0_interp_mux,
4493 wcd9335_codec_enable_interpolator,
4494 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4495 SND_SOC_DAPM_POST_PMD),
4496 SND_SOC_DAPM_MUX_E("RX INT1 INTERP", SND_SOC_NOPM,
4497 INTERP_HPHL, 0, &rx_int1_interp_mux,
4498 wcd9335_codec_enable_interpolator,
4499 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4500 SND_SOC_DAPM_POST_PMD),
4501 SND_SOC_DAPM_MUX_E("RX INT2 INTERP", SND_SOC_NOPM,
4502 INTERP_HPHR, 0, &rx_int2_interp_mux,
4503 wcd9335_codec_enable_interpolator,
4504 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4505 SND_SOC_DAPM_POST_PMD),
4506 SND_SOC_DAPM_MUX_E("RX INT3 INTERP", SND_SOC_NOPM,
4507 INTERP_LO1, 0, &rx_int3_interp_mux,
4508 wcd9335_codec_enable_interpolator,
4509 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4510 SND_SOC_DAPM_POST_PMD),
4511 SND_SOC_DAPM_MUX_E("RX INT4 INTERP", SND_SOC_NOPM,
4512 INTERP_LO2, 0, &rx_int4_interp_mux,
4513 wcd9335_codec_enable_interpolator,
4514 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4515 SND_SOC_DAPM_POST_PMD),
4516 SND_SOC_DAPM_MUX_E("RX INT5 INTERP", SND_SOC_NOPM,
4517 INTERP_LO3, 0, &rx_int5_interp_mux,
4518 wcd9335_codec_enable_interpolator,
4519 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4520 SND_SOC_DAPM_POST_PMD),
4521 SND_SOC_DAPM_MUX_E("RX INT6 INTERP", SND_SOC_NOPM,
4522 INTERP_LO4, 0, &rx_int6_interp_mux,
4523 wcd9335_codec_enable_interpolator,
4524 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4525 SND_SOC_DAPM_POST_PMD),
4526 SND_SOC_DAPM_MUX_E("RX INT7 INTERP", SND_SOC_NOPM,
4527 INTERP_SPKR1, 0, &rx_int7_interp_mux,
4528 wcd9335_codec_enable_interpolator,
4529 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4530 SND_SOC_DAPM_POST_PMD),
4531 SND_SOC_DAPM_MUX_E("RX INT8 INTERP", SND_SOC_NOPM,
4532 INTERP_SPKR2, 0, &rx_int8_interp_mux,
4533 wcd9335_codec_enable_interpolator,
4534 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4535 SND_SOC_DAPM_POST_PMD),
4536
4537 SND_SOC_DAPM_DAC_E("RX INT0 DAC", NULL, SND_SOC_NOPM,
4538 0, 0, wcd9335_codec_ear_dac_event,
4539 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4540 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4541 SND_SOC_DAPM_DAC_E("RX INT1 DAC", NULL, WCD9335_ANA_HPH,
4542 5, 0, wcd9335_codec_hphl_dac_event,
4543 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4544 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4545 SND_SOC_DAPM_DAC_E("RX INT2 DAC", NULL, WCD9335_ANA_HPH,
4546 4, 0, wcd9335_codec_hphr_dac_event,
4547 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4548 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4549 SND_SOC_DAPM_DAC_E("RX INT3 DAC", NULL, SND_SOC_NOPM,
4550 0, 0, wcd9335_codec_lineout_dac_event,
4551 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4552 SND_SOC_DAPM_DAC_E("RX INT4 DAC", NULL, SND_SOC_NOPM,
4553 0, 0, wcd9335_codec_lineout_dac_event,
4554 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4555 SND_SOC_DAPM_DAC_E("RX INT5 DAC", NULL, SND_SOC_NOPM,
4556 0, 0, wcd9335_codec_lineout_dac_event,
4557 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4558 SND_SOC_DAPM_DAC_E("RX INT6 DAC", NULL, SND_SOC_NOPM,
4559 0, 0, wcd9335_codec_lineout_dac_event,
4560 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
4561 SND_SOC_DAPM_PGA_E("HPHL PA", WCD9335_ANA_HPH, 7, 0, NULL, 0,
4562 wcd9335_codec_enable_hphl_pa,
4563 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4564 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4565 SND_SOC_DAPM_PGA_E("HPHR PA", WCD9335_ANA_HPH, 6, 0, NULL, 0,
4566 wcd9335_codec_enable_hphr_pa,
4567 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4568 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4569 SND_SOC_DAPM_PGA_E("EAR PA", WCD9335_ANA_EAR, 7, 0, NULL, 0,
4570 wcd9335_codec_enable_ear_pa,
4571 SND_SOC_DAPM_POST_PMU |
4572 SND_SOC_DAPM_POST_PMD),
4573 SND_SOC_DAPM_PGA_E("LINEOUT1 PA", WCD9335_ANA_LO_1_2, 7, 0, NULL, 0,
4574 wcd9335_codec_enable_lineout_pa,
4575 SND_SOC_DAPM_POST_PMU |
4576 SND_SOC_DAPM_POST_PMD),
4577 SND_SOC_DAPM_PGA_E("LINEOUT2 PA", WCD9335_ANA_LO_1_2, 6, 0, NULL, 0,
4578 wcd9335_codec_enable_lineout_pa,
4579 SND_SOC_DAPM_POST_PMU |
4580 SND_SOC_DAPM_POST_PMD),
4581 SND_SOC_DAPM_PGA_E("LINEOUT3 PA", WCD9335_ANA_LO_3_4, 7, 0, NULL, 0,
4582 wcd9335_codec_enable_lineout_pa,
4583 SND_SOC_DAPM_POST_PMU |
4584 SND_SOC_DAPM_POST_PMD),
4585 SND_SOC_DAPM_PGA_E("LINEOUT4 PA", WCD9335_ANA_LO_3_4, 6, 0, NULL, 0,
4586 wcd9335_codec_enable_lineout_pa,
4587 SND_SOC_DAPM_POST_PMU |
4588 SND_SOC_DAPM_POST_PMD),
4589 SND_SOC_DAPM_SUPPLY("RX_BIAS", SND_SOC_NOPM, 0, 0,
4590 wcd9335_codec_enable_rx_bias, SND_SOC_DAPM_PRE_PMU |
4591 SND_SOC_DAPM_POST_PMD),
4592 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
4593 wcd9335_codec_enable_mclk, SND_SOC_DAPM_PRE_PMU |
4594 SND_SOC_DAPM_POST_PMD),
4595
4596 /* TX */
4597 SND_SOC_DAPM_INPUT("AMIC1"),
4598 SND_SOC_DAPM_INPUT("AMIC2"),
4599 SND_SOC_DAPM_INPUT("AMIC3"),
4600 SND_SOC_DAPM_INPUT("AMIC4"),
4601 SND_SOC_DAPM_INPUT("AMIC5"),
4602 SND_SOC_DAPM_INPUT("AMIC6"),
4603
4604 SND_SOC_DAPM_AIF_OUT_E("AIF1 CAP", "AIF1 Capture", 0, SND_SOC_NOPM,
4605 AIF1_CAP, 0, wcd9335_codec_enable_slim,
4606 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4607
4608 SND_SOC_DAPM_AIF_OUT_E("AIF2 CAP", "AIF2 Capture", 0, SND_SOC_NOPM,
4609 AIF2_CAP, 0, wcd9335_codec_enable_slim,
4610 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4611
4612 SND_SOC_DAPM_AIF_OUT_E("AIF3 CAP", "AIF3 Capture", 0, SND_SOC_NOPM,
4613 AIF3_CAP, 0, wcd9335_codec_enable_slim,
4614 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
4615
4616 SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, 0, 0,
4617 wcd9335_codec_enable_micbias,
4618 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4619 SND_SOC_DAPM_POST_PMD),
4620 SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, 0, 0,
4621 wcd9335_codec_enable_micbias,
4622 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4623 SND_SOC_DAPM_POST_PMD),
4624 SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, 0, 0,
4625 wcd9335_codec_enable_micbias,
4626 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4627 SND_SOC_DAPM_POST_PMD),
4628 SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, 0, 0,
4629 wcd9335_codec_enable_micbias,
4630 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4631 SND_SOC_DAPM_POST_PMD),
4632
4633 SND_SOC_DAPM_ADC_E("ADC1", NULL, WCD9335_ANA_AMIC1, 7, 0,
4634 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4635 SND_SOC_DAPM_ADC_E("ADC2", NULL, WCD9335_ANA_AMIC2, 7, 0,
4636 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4637 SND_SOC_DAPM_ADC_E("ADC3", NULL, WCD9335_ANA_AMIC3, 7, 0,
4638 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4639 SND_SOC_DAPM_ADC_E("ADC4", NULL, WCD9335_ANA_AMIC4, 7, 0,
4640 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4641 SND_SOC_DAPM_ADC_E("ADC5", NULL, WCD9335_ANA_AMIC5, 7, 0,
4642 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4643 SND_SOC_DAPM_ADC_E("ADC6", NULL, WCD9335_ANA_AMIC6, 7, 0,
4644 wcd9335_codec_enable_adc, SND_SOC_DAPM_PRE_PMU),
4645
4646 /* Digital Mic Inputs */
4647 SND_SOC_DAPM_ADC_E("DMIC0", NULL, SND_SOC_NOPM, 0, 0,
4648 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4649 SND_SOC_DAPM_POST_PMD),
4650
4651 SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
4652 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4653 SND_SOC_DAPM_POST_PMD),
4654
4655 SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0,
4656 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4657 SND_SOC_DAPM_POST_PMD),
4658
4659 SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 0, 0,
4660 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4661 SND_SOC_DAPM_POST_PMD),
4662
4663 SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 0, 0,
4664 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4665 SND_SOC_DAPM_POST_PMD),
4666
4667 SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 0, 0,
4668 wcd9335_codec_enable_dmic, SND_SOC_DAPM_PRE_PMU |
4669 SND_SOC_DAPM_POST_PMD),
4670
4671 SND_SOC_DAPM_MUX("DMIC MUX0", SND_SOC_NOPM, 0, 0,
4672 &tx_dmic_mux0),
4673 SND_SOC_DAPM_MUX("DMIC MUX1", SND_SOC_NOPM, 0, 0,
4674 &tx_dmic_mux1),
4675 SND_SOC_DAPM_MUX("DMIC MUX2", SND_SOC_NOPM, 0, 0,
4676 &tx_dmic_mux2),
4677 SND_SOC_DAPM_MUX("DMIC MUX3", SND_SOC_NOPM, 0, 0,
4678 &tx_dmic_mux3),
4679 SND_SOC_DAPM_MUX("DMIC MUX4", SND_SOC_NOPM, 0, 0,
4680 &tx_dmic_mux4),
4681 SND_SOC_DAPM_MUX("DMIC MUX5", SND_SOC_NOPM, 0, 0,
4682 &tx_dmic_mux5),
4683 SND_SOC_DAPM_MUX("DMIC MUX6", SND_SOC_NOPM, 0, 0,
4684 &tx_dmic_mux6),
4685 SND_SOC_DAPM_MUX("DMIC MUX7", SND_SOC_NOPM, 0, 0,
4686 &tx_dmic_mux7),
4687 SND_SOC_DAPM_MUX("DMIC MUX8", SND_SOC_NOPM, 0, 0,
4688 &tx_dmic_mux8),
4689
4690 SND_SOC_DAPM_MUX("AMIC MUX0", SND_SOC_NOPM, 0, 0,
4691 &tx_amic_mux0),
4692 SND_SOC_DAPM_MUX("AMIC MUX1", SND_SOC_NOPM, 0, 0,
4693 &tx_amic_mux1),
4694 SND_SOC_DAPM_MUX("AMIC MUX2", SND_SOC_NOPM, 0, 0,
4695 &tx_amic_mux2),
4696 SND_SOC_DAPM_MUX("AMIC MUX3", SND_SOC_NOPM, 0, 0,
4697 &tx_amic_mux3),
4698 SND_SOC_DAPM_MUX("AMIC MUX4", SND_SOC_NOPM, 0, 0,
4699 &tx_amic_mux4),
4700 SND_SOC_DAPM_MUX("AMIC MUX5", SND_SOC_NOPM, 0, 0,
4701 &tx_amic_mux5),
4702 SND_SOC_DAPM_MUX("AMIC MUX6", SND_SOC_NOPM, 0, 0,
4703 &tx_amic_mux6),
4704 SND_SOC_DAPM_MUX("AMIC MUX7", SND_SOC_NOPM, 0, 0,
4705 &tx_amic_mux7),
4706 SND_SOC_DAPM_MUX("AMIC MUX8", SND_SOC_NOPM, 0, 0,
4707 &tx_amic_mux8),
4708
4709 SND_SOC_DAPM_MIXER("AIF1_CAP Mixer", SND_SOC_NOPM, AIF1_CAP, 0,
4710 aif1_cap_mixer, ARRAY_SIZE(aif1_cap_mixer)),
4711
4712 SND_SOC_DAPM_MIXER("AIF2_CAP Mixer", SND_SOC_NOPM, AIF2_CAP, 0,
4713 aif2_cap_mixer, ARRAY_SIZE(aif2_cap_mixer)),
4714
4715 SND_SOC_DAPM_MIXER("AIF3_CAP Mixer", SND_SOC_NOPM, AIF3_CAP, 0,
4716 aif3_cap_mixer, ARRAY_SIZE(aif3_cap_mixer)),
4717
4718 SND_SOC_DAPM_MUX("SLIM TX0 MUX", SND_SOC_NOPM, WCD9335_TX0, 0,
4719 &sb_tx0_mux),
4720 SND_SOC_DAPM_MUX("SLIM TX1 MUX", SND_SOC_NOPM, WCD9335_TX1, 0,
4721 &sb_tx1_mux),
4722 SND_SOC_DAPM_MUX("SLIM TX2 MUX", SND_SOC_NOPM, WCD9335_TX2, 0,
4723 &sb_tx2_mux),
4724 SND_SOC_DAPM_MUX("SLIM TX3 MUX", SND_SOC_NOPM, WCD9335_TX3, 0,
4725 &sb_tx3_mux),
4726 SND_SOC_DAPM_MUX("SLIM TX4 MUX", SND_SOC_NOPM, WCD9335_TX4, 0,
4727 &sb_tx4_mux),
4728 SND_SOC_DAPM_MUX("SLIM TX5 MUX", SND_SOC_NOPM, WCD9335_TX5, 0,
4729 &sb_tx5_mux),
4730 SND_SOC_DAPM_MUX("SLIM TX6 MUX", SND_SOC_NOPM, WCD9335_TX6, 0,
4731 &sb_tx6_mux),
4732 SND_SOC_DAPM_MUX("SLIM TX7 MUX", SND_SOC_NOPM, WCD9335_TX7, 0,
4733 &sb_tx7_mux),
4734 SND_SOC_DAPM_MUX("SLIM TX8 MUX", SND_SOC_NOPM, WCD9335_TX8, 0,
4735 &sb_tx8_mux),
4736
4737 SND_SOC_DAPM_MUX_E("ADC MUX0", WCD9335_CDC_TX0_TX_PATH_CTL, 5, 0,
4738 &tx_adc_mux0, wcd9335_codec_enable_dec,
4739 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4740 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4741
4742 SND_SOC_DAPM_MUX_E("ADC MUX1", WCD9335_CDC_TX1_TX_PATH_CTL, 5, 0,
4743 &tx_adc_mux1, wcd9335_codec_enable_dec,
4744 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4745 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4746
4747 SND_SOC_DAPM_MUX_E("ADC MUX2", WCD9335_CDC_TX2_TX_PATH_CTL, 5, 0,
4748 &tx_adc_mux2, wcd9335_codec_enable_dec,
4749 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4750 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4751
4752 SND_SOC_DAPM_MUX_E("ADC MUX3", WCD9335_CDC_TX3_TX_PATH_CTL, 5, 0,
4753 &tx_adc_mux3, wcd9335_codec_enable_dec,
4754 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4755 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4756
4757 SND_SOC_DAPM_MUX_E("ADC MUX4", WCD9335_CDC_TX4_TX_PATH_CTL, 5, 0,
4758 &tx_adc_mux4, wcd9335_codec_enable_dec,
4759 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4760 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4761
4762 SND_SOC_DAPM_MUX_E("ADC MUX5", WCD9335_CDC_TX5_TX_PATH_CTL, 5, 0,
4763 &tx_adc_mux5, wcd9335_codec_enable_dec,
4764 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4765 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4766
4767 SND_SOC_DAPM_MUX_E("ADC MUX6", WCD9335_CDC_TX6_TX_PATH_CTL, 5, 0,
4768 &tx_adc_mux6, wcd9335_codec_enable_dec,
4769 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4770 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4771
4772 SND_SOC_DAPM_MUX_E("ADC MUX7", WCD9335_CDC_TX7_TX_PATH_CTL, 5, 0,
4773 &tx_adc_mux7, wcd9335_codec_enable_dec,
4774 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4775 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4776
4777 SND_SOC_DAPM_MUX_E("ADC MUX8", WCD9335_CDC_TX8_TX_PATH_CTL, 5, 0,
4778 &tx_adc_mux8, wcd9335_codec_enable_dec,
4779 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
4780 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
4781 };
4782
wcd9335_enable_sido_buck(struct snd_soc_component * component)4783 static void wcd9335_enable_sido_buck(struct snd_soc_component *component)
4784 {
4785 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4786
4787 snd_soc_component_update_bits(component, WCD9335_ANA_RCO,
4788 WCD9335_ANA_RCO_BG_EN_MASK,
4789 WCD9335_ANA_RCO_BG_ENABLE);
4790 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4791 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_MASK,
4792 WCD9335_ANA_BUCK_CTL_VOUT_D_IREF_EXT);
4793 /* 100us sleep needed after IREF settings */
4794 usleep_range(100, 110);
4795 snd_soc_component_update_bits(component, WCD9335_ANA_BUCK_CTL,
4796 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_MASK,
4797 WCD9335_ANA_BUCK_CTL_VOUT_D_VREF_EXT);
4798 /* 100us sleep needed after VREF settings */
4799 usleep_range(100, 110);
4800 wcd->sido_input_src = SIDO_SOURCE_RCO_BG;
4801 }
4802
wcd9335_enable_efuse_sensing(struct snd_soc_component * comp)4803 static int wcd9335_enable_efuse_sensing(struct snd_soc_component *comp)
4804 {
4805 _wcd9335_codec_enable_mclk(comp, true);
4806 snd_soc_component_update_bits(comp,
4807 WCD9335_CHIP_TIER_CTRL_EFUSE_CTL,
4808 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK,
4809 WCD9335_CHIP_TIER_CTRL_EFUSE_ENABLE);
4810 /*
4811 * 5ms sleep required after enabling efuse control
4812 * before checking the status.
4813 */
4814 usleep_range(5000, 5500);
4815
4816 if (!(snd_soc_component_read(comp,
4817 WCD9335_CHIP_TIER_CTRL_EFUSE_STATUS) &
4818 WCD9335_CHIP_TIER_CTRL_EFUSE_EN_MASK))
4819 WARN(1, "%s: Efuse sense is not complete\n", __func__);
4820
4821 wcd9335_enable_sido_buck(comp);
4822 _wcd9335_codec_enable_mclk(comp, false);
4823
4824 return 0;
4825 }
4826
wcd9335_codec_init(struct snd_soc_component * component)4827 static void wcd9335_codec_init(struct snd_soc_component *component)
4828 {
4829 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4830 int i;
4831
4832 /* ungate MCLK and set clk rate */
4833 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_GATE,
4834 WCD9335_CODEC_RPM_CLK_GATE_MCLK_GATE_MASK, 0);
4835
4836 regmap_update_bits(wcd->regmap, WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4837 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4838 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4839
4840 for (i = 0; i < ARRAY_SIZE(wcd9335_codec_reg_init); i++)
4841 snd_soc_component_update_bits(component,
4842 wcd9335_codec_reg_init[i].reg,
4843 wcd9335_codec_reg_init[i].mask,
4844 wcd9335_codec_reg_init[i].val);
4845
4846 wcd9335_enable_efuse_sensing(component);
4847 }
4848
wcd9335_codec_probe(struct snd_soc_component * component)4849 static int wcd9335_codec_probe(struct snd_soc_component *component)
4850 {
4851 struct wcd9335_codec *wcd = dev_get_drvdata(component->dev);
4852 int ret;
4853 int i;
4854
4855 snd_soc_component_init_regmap(component, wcd->regmap);
4856 /* Class-H Init*/
4857 wcd->clsh_ctrl = wcd_clsh_ctrl_alloc(component, WCD9335);
4858 if (IS_ERR(wcd->clsh_ctrl))
4859 return PTR_ERR(wcd->clsh_ctrl);
4860
4861 /* Default HPH Mode to Class-H HiFi */
4862 wcd->hph_mode = CLS_H_HIFI;
4863 wcd->component = component;
4864
4865 wcd9335_codec_init(component);
4866
4867 for (i = 0; i < NUM_CODEC_DAIS; i++)
4868 INIT_LIST_HEAD(&wcd->dai[i].slim_ch_list);
4869
4870 ret = wcd9335_setup_irqs(wcd);
4871 if (ret)
4872 goto free_clsh_ctrl;
4873
4874 return 0;
4875
4876 free_clsh_ctrl:
4877 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4878 return ret;
4879 }
4880
wcd9335_codec_remove(struct snd_soc_component * comp)4881 static void wcd9335_codec_remove(struct snd_soc_component *comp)
4882 {
4883 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4884
4885 wcd_clsh_ctrl_free(wcd->clsh_ctrl);
4886 wcd9335_teardown_irqs(wcd);
4887 }
4888
wcd9335_codec_set_sysclk(struct snd_soc_component * comp,int clk_id,int source,unsigned int freq,int dir)4889 static int wcd9335_codec_set_sysclk(struct snd_soc_component *comp,
4890 int clk_id, int source,
4891 unsigned int freq, int dir)
4892 {
4893 struct wcd9335_codec *wcd = dev_get_drvdata(comp->dev);
4894
4895 wcd->mclk_rate = freq;
4896
4897 if (wcd->mclk_rate == WCD9335_MCLK_CLK_12P288MHZ)
4898 snd_soc_component_update_bits(comp,
4899 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4900 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4901 WCD9335_CODEC_RPM_CLK_MCLK_CFG_12P288MHZ);
4902 else if (wcd->mclk_rate == WCD9335_MCLK_CLK_9P6MHZ)
4903 snd_soc_component_update_bits(comp,
4904 WCD9335_CODEC_RPM_CLK_MCLK_CFG,
4905 WCD9335_CODEC_RPM_CLK_MCLK_CFG_MCLK_MASK,
4906 WCD9335_CODEC_RPM_CLK_MCLK_CFG_9P6MHZ);
4907
4908 return clk_set_rate(wcd->mclk, freq);
4909 }
4910
4911 static const struct snd_soc_component_driver wcd9335_component_drv = {
4912 .probe = wcd9335_codec_probe,
4913 .remove = wcd9335_codec_remove,
4914 .set_sysclk = wcd9335_codec_set_sysclk,
4915 .controls = wcd9335_snd_controls,
4916 .num_controls = ARRAY_SIZE(wcd9335_snd_controls),
4917 .dapm_widgets = wcd9335_dapm_widgets,
4918 .num_dapm_widgets = ARRAY_SIZE(wcd9335_dapm_widgets),
4919 .dapm_routes = wcd9335_audio_map,
4920 .num_dapm_routes = ARRAY_SIZE(wcd9335_audio_map),
4921 .endianness = 1,
4922 };
4923
wcd9335_probe(struct wcd9335_codec * wcd)4924 static int wcd9335_probe(struct wcd9335_codec *wcd)
4925 {
4926 struct device *dev = wcd->dev;
4927
4928 memcpy(wcd->rx_chs, wcd9335_rx_chs, sizeof(wcd9335_rx_chs));
4929 memcpy(wcd->tx_chs, wcd9335_tx_chs, sizeof(wcd9335_tx_chs));
4930
4931 wcd->sido_input_src = SIDO_SOURCE_INTERNAL;
4932 wcd->sido_voltage = SIDO_VOLTAGE_NOMINAL_MV;
4933
4934 return devm_snd_soc_register_component(dev, &wcd9335_component_drv,
4935 wcd9335_slim_dais,
4936 ARRAY_SIZE(wcd9335_slim_dais));
4937 }
4938
4939 static const struct regmap_range_cfg wcd9335_ranges[] = {
4940 {
4941 .name = "WCD9335",
4942 .range_min = 0x0,
4943 .range_max = WCD9335_MAX_REGISTER,
4944 .selector_reg = WCD9335_SEL_REGISTER,
4945 .selector_mask = 0xff,
4946 .selector_shift = 0,
4947 .window_start = 0x800,
4948 .window_len = 0x100,
4949 },
4950 };
4951
wcd9335_is_volatile_register(struct device * dev,unsigned int reg)4952 static bool wcd9335_is_volatile_register(struct device *dev, unsigned int reg)
4953 {
4954 switch (reg) {
4955 case WCD9335_INTR_PIN1_STATUS0...WCD9335_INTR_PIN2_CLEAR3:
4956 case WCD9335_ANA_MBHC_RESULT_3:
4957 case WCD9335_ANA_MBHC_RESULT_2:
4958 case WCD9335_ANA_MBHC_RESULT_1:
4959 case WCD9335_ANA_MBHC_MECH:
4960 case WCD9335_ANA_MBHC_ELECT:
4961 case WCD9335_ANA_MBHC_ZDET:
4962 case WCD9335_ANA_MICB2:
4963 case WCD9335_ANA_RCO:
4964 case WCD9335_ANA_BIAS:
4965 return true;
4966 default:
4967 return false;
4968 }
4969 }
4970
4971 static struct regmap_config wcd9335_regmap_config = {
4972 .reg_bits = 16,
4973 .val_bits = 8,
4974 .cache_type = REGCACHE_MAPLE,
4975 .max_register = WCD9335_MAX_REGISTER,
4976 .can_multi_write = true,
4977 .ranges = wcd9335_ranges,
4978 .num_ranges = ARRAY_SIZE(wcd9335_ranges),
4979 .volatile_reg = wcd9335_is_volatile_register,
4980 };
4981
4982 static const struct regmap_range_cfg wcd9335_ifc_ranges[] = {
4983 {
4984 .name = "WCD9335-IFC-DEV",
4985 .range_min = 0x0,
4986 .range_max = WCD9335_MAX_REGISTER,
4987 .selector_reg = WCD9335_SEL_REGISTER,
4988 .selector_mask = 0xfff,
4989 .selector_shift = 0,
4990 .window_start = 0x800,
4991 .window_len = 0x400,
4992 },
4993 };
4994
4995 static struct regmap_config wcd9335_ifc_regmap_config = {
4996 .reg_bits = 16,
4997 .val_bits = 8,
4998 .can_multi_write = true,
4999 .max_register = WCD9335_MAX_REGISTER,
5000 .ranges = wcd9335_ifc_ranges,
5001 .num_ranges = ARRAY_SIZE(wcd9335_ifc_ranges),
5002 };
5003
5004 static const struct regmap_irq wcd9335_codec_irqs[] = {
5005 /* INTR_REG 0 */
5006 [WCD9335_IRQ_SLIMBUS] = {
5007 .reg_offset = 0,
5008 .mask = BIT(0),
5009 .type = {
5010 .type_reg_offset = 0,
5011 .types_supported = IRQ_TYPE_EDGE_BOTH,
5012 .type_reg_mask = BIT(0),
5013 },
5014 },
5015 };
5016
5017 static const unsigned int wcd9335_config_regs[] = {
5018 WCD9335_INTR_LEVEL0,
5019 };
5020
5021 static const struct regmap_irq_chip wcd9335_regmap_irq1_chip = {
5022 .name = "wcd9335_pin1_irq",
5023 .status_base = WCD9335_INTR_PIN1_STATUS0,
5024 .mask_base = WCD9335_INTR_PIN1_MASK0,
5025 .ack_base = WCD9335_INTR_PIN1_CLEAR0,
5026 .num_regs = 4,
5027 .irqs = wcd9335_codec_irqs,
5028 .num_irqs = ARRAY_SIZE(wcd9335_codec_irqs),
5029 .config_base = wcd9335_config_regs,
5030 .num_config_bases = ARRAY_SIZE(wcd9335_config_regs),
5031 .num_config_regs = 4,
5032 .set_type_config = regmap_irq_set_type_config_simple,
5033 };
5034
wcd9335_parse_dt(struct wcd9335_codec * wcd)5035 static int wcd9335_parse_dt(struct wcd9335_codec *wcd)
5036 {
5037 struct device *dev = wcd->dev;
5038 int ret;
5039
5040 wcd->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
5041 if (IS_ERR(wcd->reset_gpio))
5042 return dev_err_probe(dev, PTR_ERR(wcd->reset_gpio), "Reset GPIO missing from DT\n");
5043
5044 wcd->mclk = devm_clk_get(dev, "mclk");
5045 if (IS_ERR(wcd->mclk))
5046 return dev_err_probe(dev, PTR_ERR(wcd->mclk), "mclk not found\n");
5047
5048 wcd->native_clk = devm_clk_get(dev, "slimbus");
5049 if (IS_ERR(wcd->native_clk))
5050 return dev_err_probe(dev, PTR_ERR(wcd->native_clk), "slimbus clock not found\n");
5051
5052 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(wcd9335_supplies),
5053 wcd9335_supplies);
5054 if (ret)
5055 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n");
5056
5057 return 0;
5058 }
5059
wcd9335_power_on_reset(struct wcd9335_codec * wcd)5060 static int wcd9335_power_on_reset(struct wcd9335_codec *wcd)
5061 {
5062 /*
5063 * For WCD9335, it takes about 600us for the Vout_A and
5064 * Vout_D to be ready after BUCK_SIDO is powered up.
5065 * SYS_RST_N shouldn't be pulled high during this time
5066 * Toggle the reset line to make sure the reset pulse is
5067 * correctly applied
5068 */
5069 usleep_range(600, 650);
5070
5071 gpiod_set_value(wcd->reset_gpio, 1);
5072 msleep(20);
5073 gpiod_set_value(wcd->reset_gpio, 0);
5074 msleep(20);
5075
5076 return 0;
5077 }
5078
wcd9335_bring_up(struct wcd9335_codec * wcd)5079 static int wcd9335_bring_up(struct wcd9335_codec *wcd)
5080 {
5081 struct regmap *rm = wcd->regmap;
5082 int val, byte0;
5083
5084 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_EFUSE_VAL_OUT0, &val);
5085 regmap_read(rm, WCD9335_CHIP_TIER_CTRL_CHIP_ID_BYTE0, &byte0);
5086
5087 if ((val < 0) || (byte0 < 0)) {
5088 dev_err(wcd->dev, "WCD9335 CODEC version detection fail!\n");
5089 return -EINVAL;
5090 }
5091
5092 if (byte0 == 0x1) {
5093 dev_info(wcd->dev, "WCD9335 CODEC version is v2.0\n");
5094 wcd->version = WCD9335_VERSION_2_0;
5095 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x01);
5096 regmap_write(rm, WCD9335_SIDO_SIDO_TEST_2, 0x00);
5097 regmap_write(rm, WCD9335_SIDO_SIDO_CCL_8, 0x6F);
5098 regmap_write(rm, WCD9335_BIAS_VBG_FINE_ADJ, 0x65);
5099 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x5);
5100 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x7);
5101 regmap_write(rm, WCD9335_CODEC_RPM_PWR_CDC_DIG_HM_CTL, 0x3);
5102 regmap_write(rm, WCD9335_CODEC_RPM_RST_CTL, 0x3);
5103 } else {
5104 dev_err(wcd->dev, "WCD9335 CODEC version not supported\n");
5105 return -EINVAL;
5106 }
5107
5108 return 0;
5109 }
5110
wcd9335_irq_init(struct wcd9335_codec * wcd)5111 static int wcd9335_irq_init(struct wcd9335_codec *wcd)
5112 {
5113 int ret;
5114
5115 /*
5116 * INTR1 consists of all possible interrupt sources Ear OCP,
5117 * HPH OCP, MBHC, MAD, VBAT, and SVA
5118 * INTR2 is a subset of first interrupt sources MAD, VBAT, and SVA
5119 */
5120 wcd->intr1 = of_irq_get_byname(wcd->dev->of_node, "intr1");
5121 if (wcd->intr1 < 0)
5122 return dev_err_probe(wcd->dev, wcd->intr1,
5123 "Unable to configure IRQ\n");
5124
5125 ret = devm_regmap_add_irq_chip(wcd->dev, wcd->regmap, wcd->intr1,
5126 IRQF_TRIGGER_HIGH, 0,
5127 &wcd9335_regmap_irq1_chip, &wcd->irq_data);
5128 if (ret)
5129 return dev_err_probe(wcd->dev, ret, "Failed to register IRQ chip\n");
5130
5131 return 0;
5132 }
5133
wcd9335_slim_probe(struct slim_device * slim)5134 static int wcd9335_slim_probe(struct slim_device *slim)
5135 {
5136 struct device *dev = &slim->dev;
5137 struct wcd9335_codec *wcd;
5138 int ret;
5139
5140 wcd = devm_kzalloc(dev, sizeof(*wcd), GFP_KERNEL);
5141 if (!wcd)
5142 return -ENOMEM;
5143
5144 wcd->dev = dev;
5145 ret = wcd9335_parse_dt(wcd);
5146 if (ret)
5147 return ret;
5148
5149 ret = wcd9335_power_on_reset(wcd);
5150 if (ret)
5151 return ret;
5152
5153 dev_set_drvdata(dev, wcd);
5154
5155 return 0;
5156 }
5157
wcd9335_slim_status(struct slim_device * sdev,enum slim_device_status status)5158 static int wcd9335_slim_status(struct slim_device *sdev,
5159 enum slim_device_status status)
5160 {
5161 struct device *dev = &sdev->dev;
5162 struct device_node *ifc_dev_np;
5163 struct wcd9335_codec *wcd;
5164 int ret;
5165
5166 wcd = dev_get_drvdata(dev);
5167
5168 ifc_dev_np = of_parse_phandle(dev->of_node, "slim-ifc-dev", 0);
5169 if (!ifc_dev_np) {
5170 dev_err(dev, "No Interface device found\n");
5171 return -EINVAL;
5172 }
5173
5174 wcd->slim = sdev;
5175 wcd->slim_ifc_dev = of_slim_get_device(sdev->ctrl, ifc_dev_np);
5176 of_node_put(ifc_dev_np);
5177 if (!wcd->slim_ifc_dev) {
5178 dev_err(dev, "Unable to get SLIM Interface device\n");
5179 return -EINVAL;
5180 }
5181
5182 slim_get_logical_addr(wcd->slim_ifc_dev);
5183
5184 wcd->regmap = regmap_init_slimbus(sdev, &wcd9335_regmap_config);
5185 if (IS_ERR(wcd->regmap))
5186 return dev_err_probe(dev, PTR_ERR(wcd->regmap),
5187 "Failed to allocate slim register map\n");
5188
5189 wcd->if_regmap = regmap_init_slimbus(wcd->slim_ifc_dev,
5190 &wcd9335_ifc_regmap_config);
5191 if (IS_ERR(wcd->if_regmap))
5192 return dev_err_probe(dev, PTR_ERR(wcd->if_regmap),
5193 "Failed to allocate ifc register map\n");
5194
5195 ret = wcd9335_bring_up(wcd);
5196 if (ret) {
5197 dev_err(dev, "Failed to bringup WCD9335\n");
5198 return ret;
5199 }
5200
5201 ret = wcd9335_irq_init(wcd);
5202 if (ret)
5203 return ret;
5204
5205 wcd9335_probe(wcd);
5206
5207 return 0;
5208 }
5209
5210 static const struct slim_device_id wcd9335_slim_id[] = {
5211 {SLIM_MANF_ID_QCOM, SLIM_PROD_CODE_WCD9335, 0x1, 0x0},
5212 {}
5213 };
5214 MODULE_DEVICE_TABLE(slim, wcd9335_slim_id);
5215
5216 static struct slim_driver wcd9335_slim_driver = {
5217 .driver = {
5218 .name = "wcd9335-slim",
5219 },
5220 .probe = wcd9335_slim_probe,
5221 .device_status = wcd9335_slim_status,
5222 .id_table = wcd9335_slim_id,
5223 };
5224
5225 module_slim_driver(wcd9335_slim_driver);
5226 MODULE_DESCRIPTION("WCD9335 slim driver");
5227 MODULE_LICENSE("GPL v2");
5228 MODULE_ALIAS("slim:217:1a0:*");
5229