1 /* 2 * RX emulation 3 * 4 * Copyright (c) 2019 Yoshinori Sato 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "qemu/bitops.h" 21 #include "cpu.h" 22 #include "exec/log.h" 23 #include "accel/tcg/cpu-ldst.h" 24 #include "hw/irq.h" 25 #include "qemu/plugin.h" 26 27 void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) 28 { 29 if (env->psw_pm == 0) { 30 env->psw_ipl = FIELD_EX32(psw, PSW, IPL); 31 if (rte) { 32 /* PSW.PM can write RTE and RTFI */ 33 env->psw_pm = FIELD_EX32(psw, PSW, PM); 34 } 35 env->psw_u = FIELD_EX32(psw, PSW, U); 36 env->psw_i = FIELD_EX32(psw, PSW, I); 37 } 38 env->psw_o = FIELD_EX32(psw, PSW, O) << 31; 39 env->psw_s = FIELD_EX32(psw, PSW, S) << 31; 40 env->psw_z = 1 - FIELD_EX32(psw, PSW, Z); 41 env->psw_c = FIELD_EX32(psw, PSW, C); 42 } 43 44 void rx_cpu_do_interrupt(CPUState *cs) 45 { 46 CPURXState *env = cpu_env(cs); 47 uint32_t save_psw; 48 uint64_t last_pc = env->pc; 49 50 env->in_sleep = 0; 51 52 if (env->psw_u) { 53 env->usp = env->regs[0]; 54 } else { 55 env->isp = env->regs[0]; 56 } 57 save_psw = rx_cpu_pack_psw(env); 58 env->psw_pm = env->psw_i = env->psw_u = 0; 59 60 if (cpu_test_interrupt(cs, CPU_INTERRUPT_FIR)) { 61 env->bpc = env->pc; 62 env->bpsw = save_psw; 63 env->pc = env->fintv; 64 env->psw_ipl = 15; 65 cpu_reset_interrupt(cs, CPU_INTERRUPT_FIR); 66 qemu_set_irq(env->ack, env->ack_irq); 67 qemu_plugin_vcpu_interrupt_cb(cs, last_pc); 68 qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); 69 } else if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) { 70 env->isp -= 4; 71 cpu_stl_data(env, env->isp, save_psw); 72 env->isp -= 4; 73 cpu_stl_data(env, env->isp, env->pc); 74 env->pc = cpu_ldl_data(env, env->intb + env->ack_irq * 4); 75 env->psw_ipl = env->ack_ipl; 76 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 77 qemu_set_irq(env->ack, env->ack_irq); 78 qemu_plugin_vcpu_interrupt_cb(cs, last_pc); 79 qemu_log_mask(CPU_LOG_INT, "interrupt 0x%02x raised\n", env->ack_irq); 80 } else { 81 uint32_t vec = cs->exception_index; 82 const char *expname = "unknown exception"; 83 84 env->isp -= 4; 85 cpu_stl_data(env, env->isp, save_psw); 86 env->isp -= 4; 87 cpu_stl_data(env, env->isp, env->pc); 88 89 if (vec < 0x100) { 90 env->pc = cpu_ldl_data(env, 0xffffff80 + vec * 4); 91 } else { 92 env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4); 93 } 94 95 if (vec == 30) { 96 /* Non-maskable interrupt */ 97 qemu_plugin_vcpu_interrupt_cb(cs, last_pc); 98 } else { 99 qemu_plugin_vcpu_exception_cb(cs, last_pc); 100 } 101 102 switch (vec) { 103 case 20: 104 expname = "privilege violation"; 105 break; 106 case 21: 107 expname = "access exception"; 108 break; 109 case 23: 110 expname = "illegal instruction"; 111 break; 112 case 25: 113 expname = "fpu exception"; 114 break; 115 case 30: 116 expname = "non-maskable interrupt"; 117 break; 118 case 0x100 ... 0x1ff: 119 expname = "unconditional trap"; 120 } 121 qemu_log_mask(CPU_LOG_INT, "exception 0x%02x [%s] raised\n", 122 (vec & 0xff), expname); 123 } 124 env->regs[0] = env->isp; 125 } 126 127 bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) 128 { 129 CPURXState *env = cpu_env(cs); 130 int accept = 0; 131 /* hardware interrupt (Normal) */ 132 if ((interrupt_request & CPU_INTERRUPT_HARD) && 133 env->psw_i && (env->psw_ipl < env->req_ipl)) { 134 env->ack_irq = env->req_irq; 135 env->ack_ipl = env->req_ipl; 136 accept = 1; 137 } 138 /* hardware interrupt (FIR) */ 139 if ((interrupt_request & CPU_INTERRUPT_FIR) && 140 env->psw_i && (env->psw_ipl < 15)) { 141 accept = 1; 142 } 143 if (accept) { 144 rx_cpu_do_interrupt(cs); 145 return true; 146 } 147 return false; 148 } 149 150 hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) 151 { 152 return addr; 153 } 154