1 /*
2  * Copyright 2012-16 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: AMD
23  *
24  */
25 
26 #include "core_types.h"
27 #include "clk_mgr_internal.h"
28 #include "reg_helper.h"
29 #include <linux/delay.h>
30 
31 #include "rv1_clk_mgr_vbios_smu.h"
32 
33 #define MAX_INSTANCE	5
34 #define MAX_SEGMENT		5
35 
36 struct IP_BASE_INSTANCE {
37 	unsigned int segment[MAX_SEGMENT];
38 };
39 
40 struct IP_BASE {
41 	struct IP_BASE_INSTANCE instance[MAX_INSTANCE];
42 };
43 
44 
45 static const struct IP_BASE MP1_BASE  = { { { { 0x00016000, 0, 0, 0, 0 } },
46 											 { { 0, 0, 0, 0, 0 } },
47 											 { { 0, 0, 0, 0, 0 } },
48 											 { { 0, 0, 0, 0, 0 } },
49 											 { { 0, 0, 0, 0, 0 } } } };
50 
51 #define mmMP1_SMN_C2PMSG_91            0x29B
52 #define mmMP1_SMN_C2PMSG_83            0x293
53 #define mmMP1_SMN_C2PMSG_67            0x283
54 #define mmMP1_SMN_C2PMSG_91_BASE_IDX   0
55 #define mmMP1_SMN_C2PMSG_83_BASE_IDX   0
56 #define mmMP1_SMN_C2PMSG_67_BASE_IDX   0
57 
58 #define MP1_SMN_C2PMSG_91__CONTENT_MASK                    0xffffffffL
59 #define MP1_SMN_C2PMSG_83__CONTENT_MASK                    0xffffffffL
60 #define MP1_SMN_C2PMSG_67__CONTENT_MASK                    0xffffffffL
61 #define MP1_SMN_C2PMSG_91__CONTENT__SHIFT                  0x00000000
62 #define MP1_SMN_C2PMSG_83__CONTENT__SHIFT                  0x00000000
63 #define MP1_SMN_C2PMSG_67__CONTENT__SHIFT                  0x00000000
64 
65 #define REG(reg_name) \
66 	(MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
67 
68 #define FN(reg_name, field) \
69 	FD(reg_name##__##field)
70 
71 #define VBIOSSMC_MSG_SetDispclkFreq           0x4
72 #define VBIOSSMC_MSG_SetDprefclkFreq          0x5
73 
74 #define VBIOSSMC_Status_BUSY                      0x0
75 #define VBIOSSMC_Result_OK                        0x1
76 #define VBIOSSMC_Result_Failed                    0xFF
77 #define VBIOSSMC_Result_UnknownCmd                0xFE
78 #define VBIOSSMC_Result_CmdRejectedPrereq         0xFD
79 #define VBIOSSMC_Result_CmdRejectedBusy           0xFC
80 
81 /*
82  * Function to be used instead of REG_WAIT macro because the wait ends when
83  * the register is NOT EQUAL to zero, and because the translation in msg_if.h
84  * won't work with REG_WAIT.
85  */
rv1_smu_wait_for_response(struct clk_mgr_internal * clk_mgr,unsigned int delay_us,unsigned int max_retries)86 static uint32_t rv1_smu_wait_for_response(struct clk_mgr_internal *clk_mgr, unsigned int delay_us, unsigned int max_retries)
87 {
88 	uint32_t res_val = VBIOSSMC_Status_BUSY;
89 
90 	do {
91 		res_val = REG_READ(MP1_SMN_C2PMSG_91);
92 		if (res_val != VBIOSSMC_Status_BUSY)
93 			break;
94 
95 		if (delay_us >= 1000)
96 			msleep(delay_us/1000);
97 		else if (delay_us > 0)
98 			udelay(delay_us);
99 	} while (max_retries--);
100 
101 	return res_val;
102 }
103 
rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal * clk_mgr,unsigned int msg_id,unsigned int param)104 static int rv1_vbios_smu_send_msg_with_param(struct clk_mgr_internal *clk_mgr,
105 		unsigned int msg_id, unsigned int param)
106 {
107 	uint32_t result;
108 
109 	/* First clear response register */
110 	REG_WRITE(MP1_SMN_C2PMSG_91, VBIOSSMC_Status_BUSY);
111 
112 	/* Set the parameter register for the SMU message, unit is Mhz */
113 	REG_WRITE(MP1_SMN_C2PMSG_83, param);
114 
115 	/* Trigger the message transaction by writing the message ID */
116 	REG_WRITE(MP1_SMN_C2PMSG_67, msg_id);
117 
118 	result = rv1_smu_wait_for_response(clk_mgr, 10, 1000);
119 
120 	ASSERT(result == VBIOSSMC_Result_OK);
121 
122 	/* Actual dispclk set is returned in the parameter register */
123 	return REG_READ(MP1_SMN_C2PMSG_83);
124 }
125 
rv1_vbios_smu_set_dispclk(struct clk_mgr_internal * clk_mgr,int requested_dispclk_khz)126 int rv1_vbios_smu_set_dispclk(struct clk_mgr_internal *clk_mgr, int requested_dispclk_khz)
127 {
128 	int actual_dispclk_set_mhz = -1;
129 	struct dc *dc = clk_mgr->base.ctx->dc;
130 	struct dmcu *dmcu = dc->res_pool->dmcu;
131 
132 	/*  Unit of SMU msg parameter is Mhz */
133 	actual_dispclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
134 			clk_mgr,
135 			VBIOSSMC_MSG_SetDispclkFreq,
136 			khz_to_mhz_ceil(requested_dispclk_khz));
137 
138 	if (dmcu && dmcu->funcs->is_dmcu_initialized(dmcu)) {
139 		if (clk_mgr->dfs_bypass_disp_clk != actual_dispclk_set_mhz)
140 			dmcu->funcs->set_psr_wait_loop(dmcu,
141 					actual_dispclk_set_mhz / 7);
142 	}
143 
144 	return actual_dispclk_set_mhz * 1000;
145 }
146 
rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal * clk_mgr)147 int rv1_vbios_smu_set_dprefclk(struct clk_mgr_internal *clk_mgr)
148 {
149 	int actual_dprefclk_set_mhz = -1;
150 
151 	actual_dprefclk_set_mhz = rv1_vbios_smu_send_msg_with_param(
152 			clk_mgr,
153 			VBIOSSMC_MSG_SetDprefclkFreq,
154 			khz_to_mhz_ceil(clk_mgr->base.dprefclk_khz));
155 
156 	/* TODO: add code for programing DP DTO, currently this is down by command table */
157 
158 	return actual_dprefclk_set_mhz * 1000;
159 }
160