xref: /openbmc/linux/drivers/hwmon/fam15h_power.c (revision e104d530)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * fam15h_power.c - AMD Family 15h processor power monitoring
4  *
5  * Copyright (c) 2011-2016 Advanced Micro Devices, Inc.
6  * Author: Andreas Herrmann <herrmann.der.user@googlemail.com>
7  */
8 
9 #include <linux/err.h>
10 #include <linux/hwmon.h>
11 #include <linux/hwmon-sysfs.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/pci.h>
15 #include <linux/bitops.h>
16 #include <linux/cpu.h>
17 #include <linux/cpumask.h>
18 #include <linux/time.h>
19 #include <linux/sched.h>
20 #include <asm/processor.h>
21 #include <asm/msr.h>
22 
23 MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
24 MODULE_AUTHOR("Andreas Herrmann <herrmann.der.user@googlemail.com>");
25 MODULE_LICENSE("GPL");
26 
27 /* D18F3 */
28 #define REG_NORTHBRIDGE_CAP		0xe8
29 
30 /* D18F4 */
31 #define REG_PROCESSOR_TDP		0x1b8
32 
33 /* D18F5 */
34 #define REG_TDP_RUNNING_AVERAGE		0xe0
35 #define REG_TDP_LIMIT3			0xe8
36 
37 #define FAM15H_MIN_NUM_ATTRS		2
38 #define FAM15H_NUM_GROUPS		2
39 #define MAX_CUS				8
40 
41 /* set maximum interval as 1 second */
42 #define MAX_INTERVAL			1000
43 
44 #define PCI_DEVICE_ID_AMD_15H_M70H_NB_F4 0x15b4
45 
46 struct fam15h_power_data {
47 	struct pci_dev *pdev;
48 	unsigned int tdp_to_watts;
49 	unsigned int base_tdp;
50 	unsigned int processor_pwr_watts;
51 	unsigned int cpu_pwr_sample_ratio;
52 	const struct attribute_group *groups[FAM15H_NUM_GROUPS];
53 	struct attribute_group group;
54 	/* maximum accumulated power of a compute unit */
55 	u64 max_cu_acc_power;
56 	/* accumulated power of the compute units */
57 	u64 cu_acc_power[MAX_CUS];
58 	/* performance timestamp counter */
59 	u64 cpu_sw_pwr_ptsc[MAX_CUS];
60 	/* online/offline status of current compute unit */
61 	int cu_on[MAX_CUS];
62 	unsigned long power_period;
63 };
64 
is_carrizo_or_later(void)65 static bool is_carrizo_or_later(void)
66 {
67 	return boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model >= 0x60;
68 }
69 
power1_input_show(struct device * dev,struct device_attribute * attr,char * buf)70 static ssize_t power1_input_show(struct device *dev,
71 				 struct device_attribute *attr, char *buf)
72 {
73 	u32 val, tdp_limit, running_avg_range;
74 	s32 running_avg_capture;
75 	u64 curr_pwr_watts;
76 	struct fam15h_power_data *data = dev_get_drvdata(dev);
77 	struct pci_dev *f4 = data->pdev;
78 
79 	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
80 				  REG_TDP_RUNNING_AVERAGE, &val);
81 
82 	/*
83 	 * On Carrizo and later platforms, TdpRunAvgAccCap bit field
84 	 * is extended to 4:31 from 4:25.
85 	 */
86 	if (is_carrizo_or_later()) {
87 		running_avg_capture = val >> 4;
88 		running_avg_capture = sign_extend32(running_avg_capture, 27);
89 	} else {
90 		running_avg_capture = (val >> 4) & 0x3fffff;
91 		running_avg_capture = sign_extend32(running_avg_capture, 21);
92 	}
93 
94 	running_avg_range = (val & 0xf) + 1;
95 
96 	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
97 				  REG_TDP_LIMIT3, &val);
98 
99 	/*
100 	 * On Carrizo and later platforms, ApmTdpLimit bit field
101 	 * is extended to 16:31 from 16:28.
102 	 */
103 	if (is_carrizo_or_later())
104 		tdp_limit = val >> 16;
105 	else
106 		tdp_limit = (val >> 16) & 0x1fff;
107 
108 	curr_pwr_watts = ((u64)(tdp_limit +
109 				data->base_tdp)) << running_avg_range;
110 	curr_pwr_watts -= running_avg_capture;
111 	curr_pwr_watts *= data->tdp_to_watts;
112 
113 	/*
114 	 * Convert to microWatt
115 	 *
116 	 * power is in Watt provided as fixed point integer with
117 	 * scaling factor 1/(2^16).  For conversion we use
118 	 * (10^6)/(2^16) = 15625/(2^10)
119 	 */
120 	curr_pwr_watts = (curr_pwr_watts * 15625) >> (10 + running_avg_range);
121 	return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts);
122 }
123 static DEVICE_ATTR_RO(power1_input);
124 
power1_crit_show(struct device * dev,struct device_attribute * attr,char * buf)125 static ssize_t power1_crit_show(struct device *dev,
126 				struct device_attribute *attr, char *buf)
127 {
128 	struct fam15h_power_data *data = dev_get_drvdata(dev);
129 
130 	return sprintf(buf, "%u\n", data->processor_pwr_watts);
131 }
132 static DEVICE_ATTR_RO(power1_crit);
133 
do_read_registers_on_cu(void * _data)134 static void do_read_registers_on_cu(void *_data)
135 {
136 	struct fam15h_power_data *data = _data;
137 	int cpu, cu;
138 
139 	cpu = smp_processor_id();
140 
141 	/*
142 	 * With the new x86 topology modelling, cpu core id actually
143 	 * is compute unit id.
144 	 */
145 	cu = cpu_data(cpu).cpu_core_id;
146 
147 	rdmsrl_safe(MSR_F15H_CU_PWR_ACCUMULATOR, &data->cu_acc_power[cu]);
148 	rdmsrl_safe(MSR_F15H_PTSC, &data->cpu_sw_pwr_ptsc[cu]);
149 
150 	data->cu_on[cu] = 1;
151 }
152 
153 /*
154  * This function is only able to be called when CPUID
155  * Fn8000_0007:EDX[12] is set.
156  */
read_registers(struct fam15h_power_data * data)157 static int read_registers(struct fam15h_power_data *data)
158 {
159 	int core, this_core;
160 	cpumask_var_t mask;
161 	int ret, cpu;
162 
163 	ret = zalloc_cpumask_var(&mask, GFP_KERNEL);
164 	if (!ret)
165 		return -ENOMEM;
166 
167 	memset(data->cu_on, 0, sizeof(int) * MAX_CUS);
168 
169 	cpus_read_lock();
170 
171 	/*
172 	 * Choose the first online core of each compute unit, and then
173 	 * read their MSR value of power and ptsc in a single IPI,
174 	 * because the MSR value of CPU core represent the compute
175 	 * unit's.
176 	 */
177 	core = -1;
178 
179 	for_each_online_cpu(cpu) {
180 		this_core = topology_core_id(cpu);
181 
182 		if (this_core == core)
183 			continue;
184 
185 		core = this_core;
186 
187 		/* get any CPU on this compute unit */
188 		cpumask_set_cpu(cpumask_any(topology_sibling_cpumask(cpu)), mask);
189 	}
190 
191 	on_each_cpu_mask(mask, do_read_registers_on_cu, data, true);
192 
193 	cpus_read_unlock();
194 	free_cpumask_var(mask);
195 
196 	return 0;
197 }
198 
power1_average_show(struct device * dev,struct device_attribute * attr,char * buf)199 static ssize_t power1_average_show(struct device *dev,
200 				   struct device_attribute *attr, char *buf)
201 {
202 	struct fam15h_power_data *data = dev_get_drvdata(dev);
203 	u64 prev_cu_acc_power[MAX_CUS], prev_ptsc[MAX_CUS],
204 	    jdelta[MAX_CUS];
205 	u64 tdelta, avg_acc;
206 	int cu, cu_num, ret;
207 	signed long leftover;
208 
209 	/*
210 	 * With the new x86 topology modelling, x86_max_cores is the
211 	 * compute unit number.
212 	 */
213 	cu_num = boot_cpu_data.x86_max_cores;
214 
215 	ret = read_registers(data);
216 	if (ret)
217 		return 0;
218 
219 	for (cu = 0; cu < cu_num; cu++) {
220 		prev_cu_acc_power[cu] = data->cu_acc_power[cu];
221 		prev_ptsc[cu] = data->cpu_sw_pwr_ptsc[cu];
222 	}
223 
224 	leftover = schedule_timeout_interruptible(msecs_to_jiffies(data->power_period));
225 	if (leftover)
226 		return 0;
227 
228 	ret = read_registers(data);
229 	if (ret)
230 		return 0;
231 
232 	for (cu = 0, avg_acc = 0; cu < cu_num; cu++) {
233 		/* check if current compute unit is online */
234 		if (data->cu_on[cu] == 0)
235 			continue;
236 
237 		if (data->cu_acc_power[cu] < prev_cu_acc_power[cu]) {
238 			jdelta[cu] = data->max_cu_acc_power + data->cu_acc_power[cu];
239 			jdelta[cu] -= prev_cu_acc_power[cu];
240 		} else {
241 			jdelta[cu] = data->cu_acc_power[cu] - prev_cu_acc_power[cu];
242 		}
243 		tdelta = data->cpu_sw_pwr_ptsc[cu] - prev_ptsc[cu];
244 		jdelta[cu] *= data->cpu_pwr_sample_ratio * 1000;
245 		do_div(jdelta[cu], tdelta);
246 
247 		/* the unit is microWatt */
248 		avg_acc += jdelta[cu];
249 	}
250 
251 	return sprintf(buf, "%llu\n", (unsigned long long)avg_acc);
252 }
253 static DEVICE_ATTR_RO(power1_average);
254 
power1_average_interval_show(struct device * dev,struct device_attribute * attr,char * buf)255 static ssize_t power1_average_interval_show(struct device *dev,
256 					    struct device_attribute *attr,
257 					    char *buf)
258 {
259 	struct fam15h_power_data *data = dev_get_drvdata(dev);
260 
261 	return sprintf(buf, "%lu\n", data->power_period);
262 }
263 
power1_average_interval_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)264 static ssize_t power1_average_interval_store(struct device *dev,
265 					     struct device_attribute *attr,
266 					     const char *buf, size_t count)
267 {
268 	struct fam15h_power_data *data = dev_get_drvdata(dev);
269 	unsigned long temp;
270 	int ret;
271 
272 	ret = kstrtoul(buf, 10, &temp);
273 	if (ret)
274 		return ret;
275 
276 	if (temp > MAX_INTERVAL)
277 		return -EINVAL;
278 
279 	/* the interval value should be greater than 0 */
280 	if (temp <= 0)
281 		return -EINVAL;
282 
283 	data->power_period = temp;
284 
285 	return count;
286 }
287 static DEVICE_ATTR_RW(power1_average_interval);
288 
fam15h_power_init_attrs(struct pci_dev * pdev,struct fam15h_power_data * data)289 static int fam15h_power_init_attrs(struct pci_dev *pdev,
290 				   struct fam15h_power_data *data)
291 {
292 	int n = FAM15H_MIN_NUM_ATTRS;
293 	struct attribute **fam15h_power_attrs;
294 	struct cpuinfo_x86 *c = &boot_cpu_data;
295 
296 	if (c->x86 == 0x15 &&
297 	    (c->x86_model <= 0xf ||
298 	     (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
299 		n += 1;
300 
301 	/* check if processor supports accumulated power */
302 	if (boot_cpu_has(X86_FEATURE_ACC_POWER))
303 		n += 2;
304 
305 	fam15h_power_attrs = devm_kcalloc(&pdev->dev, n,
306 					  sizeof(*fam15h_power_attrs),
307 					  GFP_KERNEL);
308 
309 	if (!fam15h_power_attrs)
310 		return -ENOMEM;
311 
312 	n = 0;
313 	fam15h_power_attrs[n++] = &dev_attr_power1_crit.attr;
314 	if (c->x86 == 0x15 &&
315 	    (c->x86_model <= 0xf ||
316 	     (c->x86_model >= 0x60 && c->x86_model <= 0x7f)))
317 		fam15h_power_attrs[n++] = &dev_attr_power1_input.attr;
318 
319 	if (boot_cpu_has(X86_FEATURE_ACC_POWER)) {
320 		fam15h_power_attrs[n++] = &dev_attr_power1_average.attr;
321 		fam15h_power_attrs[n++] = &dev_attr_power1_average_interval.attr;
322 	}
323 
324 	data->group.attrs = fam15h_power_attrs;
325 
326 	return 0;
327 }
328 
should_load_on_this_node(struct pci_dev * f4)329 static bool should_load_on_this_node(struct pci_dev *f4)
330 {
331 	u32 val;
332 
333 	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3),
334 				  REG_NORTHBRIDGE_CAP, &val);
335 	if ((val & BIT(29)) && ((val >> 30) & 3))
336 		return false;
337 
338 	return true;
339 }
340 
341 /*
342  * Newer BKDG versions have an updated recommendation on how to properly
343  * initialize the running average range (was: 0xE, now: 0x9). This avoids
344  * counter saturations resulting in bogus power readings.
345  * We correct this value ourselves to cope with older BIOSes.
346  */
347 static const struct pci_device_id affected_device[] = {
348 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
349 	{ 0 }
350 };
351 
tweak_runavg_range(struct pci_dev * pdev)352 static void tweak_runavg_range(struct pci_dev *pdev)
353 {
354 	u32 val;
355 
356 	/*
357 	 * let this quirk apply only to the current version of the
358 	 * northbridge, since future versions may change the behavior
359 	 */
360 	if (!pci_match_id(affected_device, pdev))
361 		return;
362 
363 	pci_bus_read_config_dword(pdev->bus,
364 		PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
365 		REG_TDP_RUNNING_AVERAGE, &val);
366 	if ((val & 0xf) != 0xe)
367 		return;
368 
369 	val &= ~0xf;
370 	val |=  0x9;
371 	pci_bus_write_config_dword(pdev->bus,
372 		PCI_DEVFN(PCI_SLOT(pdev->devfn), 5),
373 		REG_TDP_RUNNING_AVERAGE, val);
374 }
375 
376 #ifdef CONFIG_PM
fam15h_power_resume(struct pci_dev * pdev)377 static int fam15h_power_resume(struct pci_dev *pdev)
378 {
379 	tweak_runavg_range(pdev);
380 	return 0;
381 }
382 #else
383 #define fam15h_power_resume NULL
384 #endif
385 
fam15h_power_init_data(struct pci_dev * f4,struct fam15h_power_data * data)386 static int fam15h_power_init_data(struct pci_dev *f4,
387 				  struct fam15h_power_data *data)
388 {
389 	u32 val;
390 	u64 tmp;
391 	int ret;
392 
393 	pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val);
394 	data->base_tdp = val >> 16;
395 	tmp = val & 0xffff;
396 
397 	pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
398 				  REG_TDP_LIMIT3, &val);
399 
400 	data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f);
401 	tmp *= data->tdp_to_watts;
402 
403 	/* result not allowed to be >= 256W */
404 	if ((tmp >> 16) >= 256)
405 		dev_warn(&f4->dev,
406 			 "Bogus value for ProcessorPwrWatts (processor_pwr_watts>=%u)\n",
407 			 (unsigned int) (tmp >> 16));
408 
409 	/* convert to microWatt */
410 	data->processor_pwr_watts = (tmp * 15625) >> 10;
411 
412 	ret = fam15h_power_init_attrs(f4, data);
413 	if (ret)
414 		return ret;
415 
416 
417 	/* CPUID Fn8000_0007:EDX[12] indicates to support accumulated power */
418 	if (!boot_cpu_has(X86_FEATURE_ACC_POWER))
419 		return 0;
420 
421 	/*
422 	 * determine the ratio of the compute unit power accumulator
423 	 * sample period to the PTSC counter period by executing CPUID
424 	 * Fn8000_0007:ECX
425 	 */
426 	data->cpu_pwr_sample_ratio = cpuid_ecx(0x80000007);
427 
428 	if (rdmsrl_safe(MSR_F15H_CU_MAX_PWR_ACCUMULATOR, &tmp)) {
429 		pr_err("Failed to read max compute unit power accumulator MSR\n");
430 		return -ENODEV;
431 	}
432 
433 	data->max_cu_acc_power = tmp;
434 
435 	/*
436 	 * Milliseconds are a reasonable interval for the measurement.
437 	 * But it shouldn't set too long here, because several seconds
438 	 * would cause the read function to hang. So set default
439 	 * interval as 10 ms.
440 	 */
441 	data->power_period = 10;
442 
443 	return read_registers(data);
444 }
445 
fam15h_power_probe(struct pci_dev * pdev,const struct pci_device_id * id)446 static int fam15h_power_probe(struct pci_dev *pdev,
447 			      const struct pci_device_id *id)
448 {
449 	struct fam15h_power_data *data;
450 	struct device *dev = &pdev->dev;
451 	struct device *hwmon_dev;
452 	int ret;
453 
454 	/*
455 	 * though we ignore every other northbridge, we still have to
456 	 * do the tweaking on _each_ node in MCM processors as the counters
457 	 * are working hand-in-hand
458 	 */
459 	tweak_runavg_range(pdev);
460 
461 	if (!should_load_on_this_node(pdev))
462 		return -ENODEV;
463 
464 	data = devm_kzalloc(dev, sizeof(struct fam15h_power_data), GFP_KERNEL);
465 	if (!data)
466 		return -ENOMEM;
467 
468 	ret = fam15h_power_init_data(pdev, data);
469 	if (ret)
470 		return ret;
471 
472 	data->pdev = pdev;
473 
474 	data->groups[0] = &data->group;
475 
476 	hwmon_dev = devm_hwmon_device_register_with_groups(dev, "fam15h_power",
477 							   data,
478 							   &data->groups[0]);
479 	return PTR_ERR_OR_ZERO(hwmon_dev);
480 }
481 
482 static const struct pci_device_id fam15h_power_id_table[] = {
483 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
484 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },
485 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M60H_NB_F4) },
486 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_M70H_NB_F4) },
487 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },
488 	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_16H_M30H_NB_F4) },
489 	{}
490 };
491 MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);
492 
493 static struct pci_driver fam15h_power_driver = {
494 	.name = "fam15h_power",
495 	.id_table = fam15h_power_id_table,
496 	.probe = fam15h_power_probe,
497 	.resume = fam15h_power_resume,
498 };
499 
500 module_pci_driver(fam15h_power_driver);
501